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-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_default.h272
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_offset.h514
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_sh_mask.h2264
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h33
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h38
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h17535
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h68024
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h18
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h6028
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h11339
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h43963
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h31
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_offset.h217
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h659
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h927
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h1799
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h7567
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h429
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_default.h18521
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h14663
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h120339
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h3
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h3
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h3
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h353
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h1305
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h323
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h689
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h1008
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h3815
30 files changed, 322682 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_default.h
new file mode 100644
index 000000000000..5a998c75caf0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_default.h
@@ -0,0 +1,272 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _athub_2_0_0_DEFAULT_HEADER
+#define _athub_2_0_0_DEFAULT_HEADER
+
+
+// addressBlock: athub_atsdec
+#define mmATC_ATS_CNTL_DEFAULT 0x009a0c00
+#define mmATC_ATS_STATUS_DEFAULT 0x00000000
+#define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff
+#define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000
+#define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000
+#define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000
+#define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff
+#define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000
+#define mmATHUB_MISC_CNTL_DEFAULT 0x001c0200
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000
+#define mmATC_VMID0_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID1_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID2_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID3_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID4_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID5_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID6_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID7_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID8_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID9_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID10_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID11_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID12_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID13_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID14_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID15_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_ATS_VMID_STATUS_DEFAULT 0x00000000
+#define mmATC_ATS_GFX_ATCL2_STATUS_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmATC_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmATC_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define mmATHUB_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define mmATHUB_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define mmATHUB_COMMAND_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_16_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_17_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_18_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_19_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_20_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_21_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_22_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_23_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_24_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_25_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_26_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_27_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_28_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_29_DEFAULT 0x00000000
+#define mmATHUB_PCIE_ATS_CNTL_VF_30_DEFAULT 0x00000000
+#define mmATHUB_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmATS_IH_CREDIT_DEFAULT 0x00150002
+#define mmATHUB_IH_CREDIT_DEFAULT 0x00020002
+#define mmATC_VMID16_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID17_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID18_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID19_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID20_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID21_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID22_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID23_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID24_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID25_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID26_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID27_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID28_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID29_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID30_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_VMID31_PASID_MAPPING_DEFAULT 0x00000000
+#define mmATC_ATS_MMHUB_ATCL2_STATUS_DEFAULT 0x00000000
+#define mmATHUB_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmATHUB_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmATC_ATS_SDPPORT_CNTL_DEFAULT 0x03ffa210
+#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_DEFAULT 0x00000000
+#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_DEFAULT 0x00000000
+
+
+// addressBlock: athub_xpbdec
+#define mmXPB_RTR_SRC_APRTR0_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR1_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR2_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR3_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR4_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR5_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR6_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR7_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR8_DEFAULT 0x00000000
+#define mmXPB_RTR_SRC_APRTR9_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_SRC_APRTR0_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_SRC_APRTR1_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_SRC_APRTR2_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_SRC_APRTR3_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP0_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP1_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP2_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP3_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP4_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP5_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP6_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP7_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP8_DEFAULT 0x00000000
+#define mmXPB_RTR_DEST_MAP9_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_DEST_MAP0_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_DEST_MAP1_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_DEST_MAP2_DEFAULT 0x00000000
+#define mmXPB_XDMA_RTR_DEST_MAP3_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG0_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG1_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG2_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG3_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG4_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG5_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG6_DEFAULT 0x00000000
+#define mmXPB_CLG_CFG7_DEFAULT 0x00000000
+#define mmXPB_CLG_EXTRA_DEFAULT 0x00000000
+#define mmXPB_CLG_EXTRA_MSK_DEFAULT 0x00000000
+#define mmXPB_LB_ADDR_DEFAULT 0x00000000
+#define mmXPB_WCB_STS_DEFAULT 0x00000000
+#define mmXPB_HST_CFG_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR_CFG_DEFAULT 0x0000000f
+#define mmXPB_P2P_BAR0_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR1_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR2_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR3_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR4_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR5_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR6_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR7_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR_SETUP_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR_DELTA_ABOVE_DEFAULT 0x00000000
+#define mmXPB_P2P_BAR_DELTA_BELOW_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR0_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR1_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR2_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR3_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR4_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR5_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR6_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR7_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR8_DEFAULT 0x00000000
+#define mmXPB_PEER_SYS_BAR9_DEFAULT 0x00000000
+#define mmXPB_XDMA_PEER_SYS_BAR0_DEFAULT 0x00000000
+#define mmXPB_XDMA_PEER_SYS_BAR1_DEFAULT 0x00000000
+#define mmXPB_XDMA_PEER_SYS_BAR2_DEFAULT 0x00000000
+#define mmXPB_XDMA_PEER_SYS_BAR3_DEFAULT 0x00000000
+#define mmXPB_CLK_GAT_DEFAULT 0x00040400
+#define mmXPB_INTF_CFG_DEFAULT 0x000f1040
+#define mmXPB_INTF_STS_DEFAULT 0x00000000
+#define mmXPB_PIPE_STS_DEFAULT 0x00000000
+#define mmXPB_SUB_CTRL_DEFAULT 0x00000000
+#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_DEFAULT 0x00000000
+#define mmXPB_PERF_KNOBS_DEFAULT 0x00000000
+#define mmXPB_STICKY_DEFAULT 0x00000000
+#define mmXPB_STICKY_W1C_DEFAULT 0x00000000
+#define mmXPB_MISC_CFG_DEFAULT 0x4d585042
+#define mmXPB_INTF_CFG2_DEFAULT 0x00000040
+#define mmXPB_CLG_EXTRA_RD_DEFAULT 0x00000000
+#define mmXPB_CLG_EXTRA_MSK_RD_DEFAULT 0x00000000
+#define mmXPB_CLG_GFX_MATCH_DEFAULT 0x03000000
+#define mmXPB_CLG_GFX_MATCH_MSK_DEFAULT 0x003cf3cf
+#define mmXPB_CLG_MM_MATCH_DEFAULT 0x00003000
+#define mmXPB_CLG_MM_MATCH_MSK_DEFAULT 0x00000000
+#define mmXPB_CLG_GUS_MATCH_DEFAULT 0x00000040
+#define mmXPB_CLG_GUS_MATCH_MSK_DEFAULT 0x00000000
+#define mmXPB_CLG_GFX_UNITID_MAPPING0_DEFAULT 0x00000000
+#define mmXPB_CLG_GFX_UNITID_MAPPING1_DEFAULT 0x00000040
+#define mmXPB_CLG_GFX_UNITID_MAPPING2_DEFAULT 0x00000080
+#define mmXPB_CLG_GFX_UNITID_MAPPING3_DEFAULT 0x000000c0
+#define mmXPB_CLG_GFX_UNITID_MAPPING4_DEFAULT 0x00000100
+#define mmXPB_CLG_GFX_UNITID_MAPPING5_DEFAULT 0x00000140
+#define mmXPB_CLG_GFX_UNITID_MAPPING6_DEFAULT 0x00000000
+#define mmXPB_CLG_GFX_UNITID_MAPPING7_DEFAULT 0x000001c0
+#define mmXPB_CLG_MM_UNITID_MAPPING0_DEFAULT 0x00000000
+#define mmXPB_CLG_MM_UNITID_MAPPING1_DEFAULT 0x00000040
+#define mmXPB_CLG_MM_UNITID_MAPPING2_DEFAULT 0x00000080
+#define mmXPB_CLG_MM_UNITID_MAPPING3_DEFAULT 0x000000c0
+#define mmXPB_CLG_GUS_UNITID_MAPPING0_DEFAULT 0x00000000
+#define mmXPB_CLG_GUS_UNITID_MAPPING1_DEFAULT 0x00000040
+#define mmXPB_CLG_GUS_UNITID_MAPPING2_DEFAULT 0x00000080
+#define mmXPB_CLG_GUS_UNITID_MAPPING3_DEFAULT 0x000000c0
+#define mmXPB_CLG_GUS_UNITID_MAPPING4_DEFAULT 0x00000100
+#define mmXPB_CLG_GUS_UNITID_MAPPING5_DEFAULT 0x00000140
+#define mmXPB_CLG_GUS_UNITID_MAPPING6_DEFAULT 0x00000180
+#define mmXPB_CLG_GUS_UNITID_MAPPING7_DEFAULT 0x000001c0
+
+
+// addressBlock: athub_rpbdec
+#define mmRPB_PASSPW_CONF_DEFAULT 0x00000230
+#define mmRPB_BLOCKLEVEL_CONF_DEFAULT 0x000000f0
+#define mmRPB_TAG_CONF_DEFAULT 0x08040080
+#define mmRPB_EFF_CNTL_DEFAULT 0x00001010
+#define mmRPB_ARB_CNTL_DEFAULT 0x00040404
+#define mmRPB_ARB_CNTL2_DEFAULT 0x00040104
+#define mmRPB_BIF_CNTL_DEFAULT 0x01000404
+#define mmRPB_WR_SWITCH_CNTL_DEFAULT 0x02040810
+#define mmRPB_WR_COMBINE_CNTL_DEFAULT 0x00000013
+#define mmRPB_RD_SWITCH_CNTL_DEFAULT 0x02040810
+#define mmRPB_CID_QUEUE_WR_DEFAULT 0x00000000
+#define mmRPB_CID_QUEUE_RD_DEFAULT 0x00000000
+#define mmRPB_PERF_COUNTER_CNTL_DEFAULT 0x00000010
+#define mmRPB_PERF_COUNTER_STATUS_DEFAULT 0x00000000
+#define mmRPB_CID_QUEUE_EX_DEFAULT 0x00000000
+#define mmRPB_CID_QUEUE_EX_DATA_DEFAULT 0x00000000
+#define mmRPB_SWITCH_CNTL2_DEFAULT 0x02040810
+#define mmRPB_DEINTRLV_COMBINE_CNTL_DEFAULT 0x00000204
+#define mmRPB_VC_SWITCH_RDWR_DEFAULT 0x00204040
+#define mmRPB_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmRPB_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmRPB_BIF_CNTL2_DEFAULT 0x00000000
+#define mmRPB_RD_QUEUE_CNTL_DEFAULT 0x00000000
+#define mmRPB_RD_QUEUE_CNTL2_DEFAULT 0x00000000
+#define mmRPB_WR_QUEUE_CNTL_DEFAULT 0x00000000
+#define mmRPB_WR_QUEUE_CNTL2_DEFAULT 0x00000000
+#define mmRPB_EA_QUEUE_WR_DEFAULT 0x00000000
+#define mmRPB_ATS_CNTL_DEFAULT 0x58088422
+#define mmRPB_ATS_CNTL2_DEFAULT 0x00050b13
+#define mmRPB_DF_SDPPORT_CNTL_DEFAULT 0x00003820
+#define mmRPB_SDPPORT_CNTL_DEFAULT 0x0fd14010
+#define mmRPB_NBIF_SDPPORT_CNTL_DEFAULT 0x08084020
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_offset.h
new file mode 100644
index 000000000000..f86def814430
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_offset.h
@@ -0,0 +1,514 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _athub_2_0_0_OFFSET_HEADER
+#define _athub_2_0_0_OFFSET_HEADER
+
+
+// addressBlock: athub_atsdec
+// base address: 0x3000
+#define mmATC_ATS_CNTL 0x0000
+#define mmATC_ATS_CNTL_BASE_IDX 0
+#define mmATC_ATS_STATUS 0x0003
+#define mmATC_ATS_STATUS_BASE_IDX 0
+#define mmATC_ATS_FAULT_CNTL 0x0004
+#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0
+#define mmATC_ATS_FAULT_STATUS_INFO 0x0005
+#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
+#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006
+#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
+#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007
+#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
+#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008
+#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
+#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009
+#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
+#define mmATHUB_MISC_CNTL 0x000a
+#define mmATHUB_MISC_CNTL_BASE_IDX 0
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
+#define mmATC_VMID0_PASID_MAPPING 0x000c
+#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID1_PASID_MAPPING 0x000d
+#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID2_PASID_MAPPING 0x000e
+#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID3_PASID_MAPPING 0x000f
+#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID4_PASID_MAPPING 0x0010
+#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID5_PASID_MAPPING 0x0011
+#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID6_PASID_MAPPING 0x0012
+#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID7_PASID_MAPPING 0x0013
+#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID8_PASID_MAPPING 0x0014
+#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID9_PASID_MAPPING 0x0015
+#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID10_PASID_MAPPING 0x0016
+#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID11_PASID_MAPPING 0x0017
+#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID12_PASID_MAPPING 0x0018
+#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID13_PASID_MAPPING 0x0019
+#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID14_PASID_MAPPING 0x001a
+#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID15_PASID_MAPPING 0x001b
+#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0
+#define mmATC_ATS_VMID_STATUS 0x001c
+#define mmATC_ATS_VMID_STATUS_BASE_IDX 0
+#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d
+#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0
+#define mmATC_PERFCOUNTER0_CFG 0x001e
+#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER1_CFG 0x001f
+#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER2_CFG 0x0020
+#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER3_CFG 0x0021
+#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022
+#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmATC_PERFCOUNTER_LO 0x0023
+#define mmATC_PERFCOUNTER_LO_BASE_IDX 0
+#define mmATC_PERFCOUNTER_HI 0x0024
+#define mmATC_PERFCOUNTER_HI_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL 0x0025
+#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0
+#define mmATHUB_PCIE_PASID_CNTL 0x0026
+#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0
+#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027
+#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
+#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028
+#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
+#define mmATHUB_COMMAND 0x0029
+#define mmATHUB_COMMAND_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a
+#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b
+#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c
+#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d
+#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e
+#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f
+#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030
+#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031
+#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032
+#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033
+#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034
+#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035
+#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036
+#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037
+#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038
+#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039
+#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_16 0x003a
+#define mmATHUB_PCIE_ATS_CNTL_VF_16_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_17 0x003b
+#define mmATHUB_PCIE_ATS_CNTL_VF_17_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_18 0x003c
+#define mmATHUB_PCIE_ATS_CNTL_VF_18_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_19 0x003d
+#define mmATHUB_PCIE_ATS_CNTL_VF_19_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_20 0x003e
+#define mmATHUB_PCIE_ATS_CNTL_VF_20_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_21 0x003f
+#define mmATHUB_PCIE_ATS_CNTL_VF_21_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_22 0x0040
+#define mmATHUB_PCIE_ATS_CNTL_VF_22_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_23 0x0041
+#define mmATHUB_PCIE_ATS_CNTL_VF_23_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_24 0x0042
+#define mmATHUB_PCIE_ATS_CNTL_VF_24_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_25 0x0043
+#define mmATHUB_PCIE_ATS_CNTL_VF_25_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_26 0x0044
+#define mmATHUB_PCIE_ATS_CNTL_VF_26_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_27 0x0045
+#define mmATHUB_PCIE_ATS_CNTL_VF_27_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_28 0x0046
+#define mmATHUB_PCIE_ATS_CNTL_VF_28_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_29 0x0047
+#define mmATHUB_PCIE_ATS_CNTL_VF_29_BASE_IDX 0
+#define mmATHUB_PCIE_ATS_CNTL_VF_30 0x0048
+#define mmATHUB_PCIE_ATS_CNTL_VF_30_BASE_IDX 0
+#define mmATHUB_MEM_POWER_LS 0x0049
+#define mmATHUB_MEM_POWER_LS_BASE_IDX 0
+#define mmATS_IH_CREDIT 0x004a
+#define mmATS_IH_CREDIT_BASE_IDX 0
+#define mmATHUB_IH_CREDIT 0x004b
+#define mmATHUB_IH_CREDIT_BASE_IDX 0
+#define mmATC_VMID16_PASID_MAPPING 0x004c
+#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID17_PASID_MAPPING 0x004d
+#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID18_PASID_MAPPING 0x004e
+#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID19_PASID_MAPPING 0x004f
+#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID20_PASID_MAPPING 0x0050
+#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID21_PASID_MAPPING 0x0051
+#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID22_PASID_MAPPING 0x0052
+#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID23_PASID_MAPPING 0x0053
+#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID24_PASID_MAPPING 0x0054
+#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID25_PASID_MAPPING 0x0055
+#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID26_PASID_MAPPING 0x0056
+#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID27_PASID_MAPPING 0x0057
+#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID28_PASID_MAPPING 0x0058
+#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID29_PASID_MAPPING 0x0059
+#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID30_PASID_MAPPING 0x005a
+#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0
+#define mmATC_VMID31_PASID_MAPPING 0x005b
+#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0
+#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x005c
+#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0
+#define mmATHUB_SHARED_VIRT_RESET_REQ 0x005d
+#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
+#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x005e
+#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmATC_ATS_SDPPORT_CNTL 0x005f
+#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
+#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0061
+#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0
+#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0062
+#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0
+
+
+// addressBlock: athub_xpbdec
+// base address: 0x3190
+#define mmXPB_RTR_SRC_APRTR0 0x0064
+#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR1 0x0065
+#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR2 0x0066
+#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR3 0x0067
+#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR4 0x0068
+#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR5 0x0069
+#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR6 0x006a
+#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR7 0x006b
+#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR8 0x006c
+#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0
+#define mmXPB_RTR_SRC_APRTR9 0x006d
+#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR0 0x006e
+#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR1 0x006f
+#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0070
+#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0
+#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0071
+#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP0 0x0072
+#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP1 0x0073
+#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP2 0x0074
+#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP3 0x0075
+#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP4 0x0076
+#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP5 0x0077
+#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP6 0x0078
+#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP7 0x0079
+#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP8 0x007a
+#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0
+#define mmXPB_RTR_DEST_MAP9 0x007b
+#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP0 0x007c
+#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP1 0x007d
+#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP2 0x007e
+#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0
+#define mmXPB_XDMA_RTR_DEST_MAP3 0x007f
+#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0
+#define mmXPB_CLG_CFG0 0x0080
+#define mmXPB_CLG_CFG0_BASE_IDX 0
+#define mmXPB_CLG_CFG1 0x0081
+#define mmXPB_CLG_CFG1_BASE_IDX 0
+#define mmXPB_CLG_CFG2 0x0082
+#define mmXPB_CLG_CFG2_BASE_IDX 0
+#define mmXPB_CLG_CFG3 0x0083
+#define mmXPB_CLG_CFG3_BASE_IDX 0
+#define mmXPB_CLG_CFG4 0x0084
+#define mmXPB_CLG_CFG4_BASE_IDX 0
+#define mmXPB_CLG_CFG5 0x0085
+#define mmXPB_CLG_CFG5_BASE_IDX 0
+#define mmXPB_CLG_CFG6 0x0086
+#define mmXPB_CLG_CFG6_BASE_IDX 0
+#define mmXPB_CLG_CFG7 0x0087
+#define mmXPB_CLG_CFG7_BASE_IDX 0
+#define mmXPB_CLG_EXTRA 0x0088
+#define mmXPB_CLG_EXTRA_BASE_IDX 0
+#define mmXPB_CLG_EXTRA_MSK 0x0089
+#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0
+#define mmXPB_LB_ADDR 0x008a
+#define mmXPB_LB_ADDR_BASE_IDX 0
+#define mmXPB_WCB_STS 0x008b
+#define mmXPB_WCB_STS_BASE_IDX 0
+#define mmXPB_HST_CFG 0x008c
+#define mmXPB_HST_CFG_BASE_IDX 0
+#define mmXPB_P2P_BAR_CFG 0x008d
+#define mmXPB_P2P_BAR_CFG_BASE_IDX 0
+#define mmXPB_P2P_BAR0 0x008e
+#define mmXPB_P2P_BAR0_BASE_IDX 0
+#define mmXPB_P2P_BAR1 0x008f
+#define mmXPB_P2P_BAR1_BASE_IDX 0
+#define mmXPB_P2P_BAR2 0x0090
+#define mmXPB_P2P_BAR2_BASE_IDX 0
+#define mmXPB_P2P_BAR3 0x0091
+#define mmXPB_P2P_BAR3_BASE_IDX 0
+#define mmXPB_P2P_BAR4 0x0092
+#define mmXPB_P2P_BAR4_BASE_IDX 0
+#define mmXPB_P2P_BAR5 0x0093
+#define mmXPB_P2P_BAR5_BASE_IDX 0
+#define mmXPB_P2P_BAR6 0x0094
+#define mmXPB_P2P_BAR6_BASE_IDX 0
+#define mmXPB_P2P_BAR7 0x0095
+#define mmXPB_P2P_BAR7_BASE_IDX 0
+#define mmXPB_P2P_BAR_SETUP 0x0096
+#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0
+#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0098
+#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
+#define mmXPB_P2P_BAR_DELTA_BELOW 0x0099
+#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR0 0x009a
+#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR1 0x009b
+#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR2 0x009c
+#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR3 0x009d
+#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR4 0x009e
+#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR5 0x009f
+#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR6 0x00a0
+#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR7 0x00a1
+#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR8 0x00a2
+#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0
+#define mmXPB_PEER_SYS_BAR9 0x00a3
+#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR0 0x00a4
+#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR1 0x00a5
+#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR2 0x00a6
+#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0
+#define mmXPB_XDMA_PEER_SYS_BAR3 0x00a7
+#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0
+#define mmXPB_CLK_GAT 0x00a8
+#define mmXPB_CLK_GAT_BASE_IDX 0
+#define mmXPB_INTF_CFG 0x00a9
+#define mmXPB_INTF_CFG_BASE_IDX 0
+#define mmXPB_INTF_STS 0x00aa
+#define mmXPB_INTF_STS_BASE_IDX 0
+#define mmXPB_PIPE_STS 0x00ab
+#define mmXPB_PIPE_STS_BASE_IDX 0
+#define mmXPB_SUB_CTRL 0x00ac
+#define mmXPB_SUB_CTRL_BASE_IDX 0
+#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00ad
+#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
+#define mmXPB_PERF_KNOBS 0x00ae
+#define mmXPB_PERF_KNOBS_BASE_IDX 0
+#define mmXPB_STICKY 0x00af
+#define mmXPB_STICKY_BASE_IDX 0
+#define mmXPB_STICKY_W1C 0x00b0
+#define mmXPB_STICKY_W1C_BASE_IDX 0
+#define mmXPB_MISC_CFG 0x00b1
+#define mmXPB_MISC_CFG_BASE_IDX 0
+#define mmXPB_INTF_CFG2 0x00b2
+#define mmXPB_INTF_CFG2_BASE_IDX 0
+#define mmXPB_CLG_EXTRA_RD 0x00b3
+#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0
+#define mmXPB_CLG_EXTRA_MSK_RD 0x00b4
+#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
+#define mmXPB_CLG_GFX_MATCH 0x00b5
+#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0
+#define mmXPB_CLG_GFX_MATCH_MSK 0x00b6
+#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
+#define mmXPB_CLG_MM_MATCH 0x00b7
+#define mmXPB_CLG_MM_MATCH_BASE_IDX 0
+#define mmXPB_CLG_MM_MATCH_MSK 0x00b8
+#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
+#define mmXPB_CLG_GUS_MATCH 0x00b9
+#define mmXPB_CLG_GUS_MATCH_BASE_IDX 0
+#define mmXPB_CLG_GUS_MATCH_MSK 0x00ba
+#define mmXPB_CLG_GUS_MATCH_MSK_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00bb
+#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00bc
+#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00bd
+#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00be
+#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00bf
+#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00c0
+#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00c1
+#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0
+#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00c2
+#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00c3
+#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00c4
+#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00c5
+#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0
+#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00c6
+#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0
+#define mmXPB_CLG_GUS_UNITID_MAPPING0 0x00c7
+#define mmXPB_CLG_GUS_UNITID_MAPPING0_BASE_IDX 0
+#define mmXPB_CLG_GUS_UNITID_MAPPING1 0x00c8
+#define mmXPB_CLG_GUS_UNITID_MAPPING1_BASE_IDX 0
+#define mmXPB_CLG_GUS_UNITID_MAPPING2 0x00c9
+#define mmXPB_CLG_GUS_UNITID_MAPPING2_BASE_IDX 0
+#define mmXPB_CLG_GUS_UNITID_MAPPING3 0x00ca
+#define mmXPB_CLG_GUS_UNITID_MAPPING3_BASE_IDX 0
+#define mmXPB_CLG_GUS_UNITID_MAPPING4 0x00cb
+#define mmXPB_CLG_GUS_UNITID_MAPPING4_BASE_IDX 0
+#define mmXPB_CLG_GUS_UNITID_MAPPING5 0x00cc
+#define mmXPB_CLG_GUS_UNITID_MAPPING5_BASE_IDX 0
+#define mmXPB_CLG_GUS_UNITID_MAPPING6 0x00cd
+#define mmXPB_CLG_GUS_UNITID_MAPPING6_BASE_IDX 0
+#define mmXPB_CLG_GUS_UNITID_MAPPING7 0x00ce
+#define mmXPB_CLG_GUS_UNITID_MAPPING7_BASE_IDX 0
+
+
+// addressBlock: athub_rpbdec
+// base address: 0x3350
+#define mmRPB_PASSPW_CONF 0x00d4
+#define mmRPB_PASSPW_CONF_BASE_IDX 0
+#define mmRPB_BLOCKLEVEL_CONF 0x00d5
+#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0
+#define mmRPB_TAG_CONF 0x00d7
+#define mmRPB_TAG_CONF_BASE_IDX 0
+#define mmRPB_EFF_CNTL 0x00d9
+#define mmRPB_EFF_CNTL_BASE_IDX 0
+#define mmRPB_ARB_CNTL 0x00da
+#define mmRPB_ARB_CNTL_BASE_IDX 0
+#define mmRPB_ARB_CNTL2 0x00db
+#define mmRPB_ARB_CNTL2_BASE_IDX 0
+#define mmRPB_BIF_CNTL 0x00dc
+#define mmRPB_BIF_CNTL_BASE_IDX 0
+#define mmRPB_WR_SWITCH_CNTL 0x00dd
+#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0
+#define mmRPB_WR_COMBINE_CNTL 0x00de
+#define mmRPB_WR_COMBINE_CNTL_BASE_IDX 0
+#define mmRPB_RD_SWITCH_CNTL 0x00df
+#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0
+#define mmRPB_CID_QUEUE_WR 0x00e0
+#define mmRPB_CID_QUEUE_WR_BASE_IDX 0
+#define mmRPB_CID_QUEUE_RD 0x00e1
+#define mmRPB_CID_QUEUE_RD_BASE_IDX 0
+#define mmRPB_PERF_COUNTER_CNTL 0x00e2
+#define mmRPB_PERF_COUNTER_CNTL_BASE_IDX 0
+#define mmRPB_PERF_COUNTER_STATUS 0x00e3
+#define mmRPB_PERF_COUNTER_STATUS_BASE_IDX 0
+#define mmRPB_CID_QUEUE_EX 0x00e4
+#define mmRPB_CID_QUEUE_EX_BASE_IDX 0
+#define mmRPB_CID_QUEUE_EX_DATA 0x00e5
+#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0
+#define mmRPB_SWITCH_CNTL2 0x00e6
+#define mmRPB_SWITCH_CNTL2_BASE_IDX 0
+#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00e7
+#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
+#define mmRPB_VC_SWITCH_RDWR 0x00e8
+#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0
+#define mmRPB_PERFCOUNTER_LO 0x00e9
+#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0
+#define mmRPB_PERFCOUNTER_HI 0x00ea
+#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0
+#define mmRPB_PERFCOUNTER0_CFG 0x00eb
+#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER1_CFG 0x00ec
+#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER2_CFG 0x00ed
+#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER3_CFG 0x00ee
+#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00ef
+#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmRPB_BIF_CNTL2 0x00f0
+#define mmRPB_BIF_CNTL2_BASE_IDX 0
+#define mmRPB_RD_QUEUE_CNTL 0x00f1
+#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0
+#define mmRPB_RD_QUEUE_CNTL2 0x00f2
+#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0
+#define mmRPB_WR_QUEUE_CNTL 0x00f3
+#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0
+#define mmRPB_WR_QUEUE_CNTL2 0x00f4
+#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0
+#define mmRPB_EA_QUEUE_WR 0x00f5
+#define mmRPB_EA_QUEUE_WR_BASE_IDX 0
+#define mmRPB_ATS_CNTL 0x00f6
+#define mmRPB_ATS_CNTL_BASE_IDX 0
+#define mmRPB_ATS_CNTL2 0x00f7
+#define mmRPB_ATS_CNTL2_BASE_IDX 0
+#define mmRPB_DF_SDPPORT_CNTL 0x00f8
+#define mmRPB_DF_SDPPORT_CNTL_BASE_IDX 0
+#define mmRPB_SDPPORT_CNTL 0x00f9
+#define mmRPB_SDPPORT_CNTL_BASE_IDX 0
+#define mmRPB_NBIF_SDPPORT_CNTL 0x00fa
+#define mmRPB_NBIF_SDPPORT_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_sh_mask.h
new file mode 100644
index 000000000000..88f77e90c5cb
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_sh_mask.h
@@ -0,0 +1,2264 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _athub_2_0_0_SH_MASK_HEADER
+#define _athub_2_0_0_SH_MASK_HEADER
+
+
+// addressBlock: athub_atsdec
+//ATC_ATS_CNTL
+#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
+#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
+#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
+#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
+#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
+#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
+#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
+#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L
+#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L
+#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L
+#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L
+//ATC_ATS_STATUS
+#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
+#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
+#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3
+#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6
+#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L
+#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L
+#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L
+#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L
+//ATC_ATS_FAULT_CNTL
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L
+//ATC_ATS_FAULT_STATUS_INFO
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL
+#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L
+//ATC_ATS_FAULT_STATUS_ADDR
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL
+//ATC_ATS_DEFAULT_PAGE_LOW
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL
+//ATC_TRANS_FAULT_RSPCNTRL
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L
+#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L
+//ATC_ATS_FAULT_STATUS_INFO2
+#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
+#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9
+#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000003EL
+#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L
+//ATHUB_MISC_CNTL
+#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6
+#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12
+#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13
+#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14
+#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15
+#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b
+#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c
+#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L
+#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L
+#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L
+#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L
+#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L
+#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L
+#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L
+//ATC_VMID_PASID_MAPPING_UPDATE_STATUS
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L
+//ATC_VMID0_PASID_MAPPING
+#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID1_PASID_MAPPING
+#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID2_PASID_MAPPING
+#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID3_PASID_MAPPING
+#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID4_PASID_MAPPING
+#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID5_PASID_MAPPING
+#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID6_PASID_MAPPING
+#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID7_PASID_MAPPING
+#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID8_PASID_MAPPING
+#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID9_PASID_MAPPING
+#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID10_PASID_MAPPING
+#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID11_PASID_MAPPING
+#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID12_PASID_MAPPING
+#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID13_PASID_MAPPING
+#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID14_PASID_MAPPING
+#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID15_PASID_MAPPING
+#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_ATS_VMID_STATUS
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
+#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10
+#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11
+#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12
+#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13
+#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14
+#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15
+#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16
+#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17
+#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18
+#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19
+#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a
+#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b
+#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c
+#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d
+#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e
+#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L
+#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L
+#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L
+#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L
+#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L
+#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L
+#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L
+#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L
+#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L
+#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L
+#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L
+#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L
+#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L
+#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L
+#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L
+#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L
+#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L
+//ATC_ATS_GFX_ATCL2_STATUS
+#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0
+#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L
+//ATC_PERFCOUNTER0_CFG
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER1_CFG
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER2_CFG
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER3_CFG
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//ATC_PERFCOUNTER_RSLT_CNTL
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//ATC_PERFCOUNTER_LO
+#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//ATC_PERFCOUNTER_HI
+#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//ATHUB_PCIE_ATS_CNTL
+#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_PASID_CNTL
+#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10
+#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11
+#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12
+#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L
+#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L
+#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L
+//ATHUB_PCIE_PAGE_REQ_CNTL
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L
+#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L
+//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//ATHUB_COMMAND
+#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L
+//ATHUB_PCIE_ATS_CNTL_VF_0
+#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_1
+#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_2
+#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_3
+#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_4
+#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_5
+#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_6
+#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_7
+#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_8
+#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_9
+#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_10
+#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_11
+#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_12
+#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_13
+#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_14
+#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_15
+#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_16
+#define ATHUB_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_17
+#define ATHUB_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_18
+#define ATHUB_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_19
+#define ATHUB_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_20
+#define ATHUB_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_21
+#define ATHUB_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_22
+#define ATHUB_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_23
+#define ATHUB_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_24
+#define ATHUB_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_25
+#define ATHUB_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_26
+#define ATHUB_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_27
+#define ATHUB_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_28
+#define ATHUB_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_29
+#define ATHUB_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_PCIE_ATS_CNTL_VF_30
+#define ATHUB_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f
+#define ATHUB_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L
+//ATHUB_MEM_POWER_LS
+#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//ATS_IH_CREDIT
+#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
+#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
+//ATHUB_IH_CREDIT
+#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
+#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
+//ATC_VMID16_PASID_MAPPING
+#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID17_PASID_MAPPING
+#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID18_PASID_MAPPING
+#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID19_PASID_MAPPING
+#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID20_PASID_MAPPING
+#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID21_PASID_MAPPING
+#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID22_PASID_MAPPING
+#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID23_PASID_MAPPING
+#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID24_PASID_MAPPING
+#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID25_PASID_MAPPING
+#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID26_PASID_MAPPING
+#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID27_PASID_MAPPING
+#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID28_PASID_MAPPING
+#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID29_PASID_MAPPING
+#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID30_PASID_MAPPING
+#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_VMID31_PASID_MAPPING
+#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL
+#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
+#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L
+//ATC_ATS_MMHUB_ATCL2_STATUS
+#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0
+#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L
+//ATHUB_SHARED_VIRT_RESET_REQ
+#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
+#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//ATHUB_SHARED_ACTIVE_FCN_ID
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
+#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//ATC_ATS_SDPPORT_CNTL
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L
+#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L
+#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L
+//ATC_ATS_VMID_SNAPSHOT_GFX_STAT
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L
+#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L
+//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L
+#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L
+
+
+// addressBlock: athub_xpbdec
+//XPB_RTR_SRC_APRTR0
+#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR1
+#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR2
+#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR3
+#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR4
+#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR5
+#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR6
+#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR7
+#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR8
+#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_SRC_APRTR9
+#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
+#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR0
+#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR1
+#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR2
+#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_XDMA_RTR_SRC_APRTR3
+#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
+//XPB_RTR_DEST_MAP0
+#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP1
+#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP2
+#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP3
+#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP4
+#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP5
+#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP6
+#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP7
+#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP8
+#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L
+//XPB_RTR_DEST_MAP9
+#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
+#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
+#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
+#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
+#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
+#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L
+#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L
+#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L
+#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP0
+#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L
+#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP1
+#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L
+#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP2
+#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L
+#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
+//XPB_XDMA_RTR_DEST_MAP3
+#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
+#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
+#define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L
+#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
+//XPB_CLG_CFG0
+#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
+#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
+#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L
+#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L
+#define XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003C000L
+//XPB_CLG_CFG1
+#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
+#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
+#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L
+#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L
+#define XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003C000L
+//XPB_CLG_CFG2
+#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
+#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
+#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L
+#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L
+#define XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003C000L
+//XPB_CLG_CFG3
+#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
+#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
+#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L
+#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L
+#define XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003C000L
+//XPB_CLG_CFG4
+#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
+#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
+#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L
+#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L
+#define XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003C000L
+//XPB_CLG_CFG5
+#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
+#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
+#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L
+#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L
+#define XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003C000L
+//XPB_CLG_CFG6
+#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
+#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
+#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L
+#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L
+#define XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003C000L
+//XPB_CLG_CFG7
+#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
+#define XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
+#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
+#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
+#define XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
+#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL
+#define XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L
+#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L
+#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L
+#define XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003C000L
+//XPB_CLG_EXTRA
+#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb
+#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc
+#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf
+#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15
+#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a
+#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b
+#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L
+#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L
+#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L
+#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L
+#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L
+#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L
+//XPB_CLG_EXTRA_MSK
+#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb
+#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11
+#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L
+#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L
+//XPB_LB_ADDR
+#define XPB_LB_ADDR__CMP0__SHIFT 0x0
+#define XPB_LB_ADDR__MASK0__SHIFT 0xa
+#define XPB_LB_ADDR__CMP1__SHIFT 0x14
+#define XPB_LB_ADDR__MASK1__SHIFT 0x1a
+#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL
+#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L
+#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L
+#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L
+//XPB_WCB_STS
+#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
+#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
+#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
+#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL
+#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L
+#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L
+//XPB_HST_CFG
+#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0
+#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L
+//XPB_P2P_BAR_CFG
+#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
+#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
+#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
+#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
+#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
+#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
+#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
+#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
+#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
+#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL
+#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L
+#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L
+#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L
+#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L
+#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L
+#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L
+#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L
+#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L
+//XPB_P2P_BAR0
+#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR0__VALID__SHIFT 0xc
+#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR0__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR1
+#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR1__VALID__SHIFT 0xc
+#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR1__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR2
+#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR2__VALID__SHIFT 0xc
+#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR2__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR3
+#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR3__VALID__SHIFT 0xc
+#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR3__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR4
+#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR4__VALID__SHIFT 0xc
+#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR4__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR5
+#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR5__VALID__SHIFT 0xc
+#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR5__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR6
+#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR6__VALID__SHIFT 0xc
+#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR6__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR7
+#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
+#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
+#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR7__VALID__SHIFT 0xc
+#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL
+#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L
+#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR7__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR_SETUP
+#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
+#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
+#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
+#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
+#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
+#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
+#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
+#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL
+#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L
+#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L
+#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L
+#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L
+#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L
+#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L
+//XPB_P2P_BAR_DELTA_ABOVE
+#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
+#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
+#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL
+#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L
+//XPB_P2P_BAR_DELTA_BELOW
+#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
+#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
+#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL
+#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L
+//XPB_PEER_SYS_BAR0
+#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR1
+#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR2
+#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR3
+#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR4
+#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR5
+#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR6
+#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR7
+#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR8
+#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL
+//XPB_PEER_SYS_BAR9
+#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
+#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1
+#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L
+#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR0
+#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR1
+#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR2
+#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
+//XPB_XDMA_PEER_SYS_BAR3
+#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1
+#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L
+#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
+//XPB_CLK_GAT
+#define XPB_CLK_GAT__ONDLY__SHIFT 0x0
+#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6
+#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc
+#define XPB_CLK_GAT__ENABLE__SHIFT 0x12
+#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
+#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL
+#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L
+#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L
+#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L
+#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L
+//XPB_INTF_CFG
+#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
+#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
+#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
+#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
+#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
+#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
+#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
+#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
+#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
+#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL
+#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L
+#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L
+#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L
+#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L
+#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L
+#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L
+#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L
+#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L
+#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L
+//XPB_INTF_STS
+#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
+#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
+#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
+#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
+#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
+#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
+#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
+#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL
+#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L
+#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L
+#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L
+#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L
+#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L
+#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L
+//XPB_PIPE_STS
+#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
+#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
+#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
+#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
+#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
+#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
+#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
+#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
+#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
+#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
+#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
+#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
+#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
+#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L
+#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL
+#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L
+#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L
+#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L
+#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L
+#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L
+#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L
+#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L
+#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L
+#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L
+#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L
+#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L
+//XPB_SUB_CTRL
+#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
+#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
+#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
+#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
+#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
+#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
+#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
+#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
+#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
+#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
+#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
+#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
+#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
+#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
+#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
+#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
+#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
+#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
+#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
+#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
+#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L
+#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L
+#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L
+#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L
+#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L
+#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L
+#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L
+#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L
+#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L
+#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L
+#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L
+#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L
+#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L
+#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L
+#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L
+#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L
+#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L
+#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L
+#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L
+#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L
+//XPB_MAP_INVERT_FLUSH_NUM_LSB
+#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
+#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL
+//XPB_PERF_KNOBS
+#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
+#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
+#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
+#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL
+#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L
+#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L
+//XPB_STICKY
+#define XPB_STICKY__BITS__SHIFT 0x0
+#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL
+//XPB_STICKY_W1C
+#define XPB_STICKY_W1C__BITS__SHIFT 0x0
+#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL
+//XPB_MISC_CFG
+#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
+#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
+#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
+#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
+#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
+#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL
+#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L
+#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L
+#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L
+#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L
+//XPB_INTF_CFG2
+#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
+#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL
+//XPB_CLG_EXTRA_RD
+#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb
+#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc
+#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf
+#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15
+#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a
+#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b
+#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L
+#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L
+#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L
+#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L
+#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L
+#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L
+//XPB_CLG_EXTRA_MSK_RD
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL
+#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L
+#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L
+//XPB_CLG_GFX_MATCH
+#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0
+#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6
+#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc
+#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12
+#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18
+#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19
+#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a
+#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b
+#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL
+#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L
+#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L
+#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L
+#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L
+#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L
+#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L
+#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L
+//XPB_CLG_GFX_MATCH_MSK
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L
+#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L
+//XPB_CLG_MM_MATCH
+#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0
+#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6
+#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0xc
+#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0xd
+#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL
+#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L
+#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x00001000L
+#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x00002000L
+//XPB_CLG_MM_MATCH_MSK
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL
+#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L
+//XPB_CLG_GUS_MATCH
+#define XPB_CLG_GUS_MATCH__FARBIRC0_ID__SHIFT 0x0
+#define XPB_CLG_GUS_MATCH__FARBIRC0_VLD__SHIFT 0x6
+#define XPB_CLG_GUS_MATCH__FARBIRC0_ID_MASK 0x0000003FL
+#define XPB_CLG_GUS_MATCH__FARBIRC0_VLD_MASK 0x00000040L
+//XPB_CLG_GUS_MATCH_MSK
+#define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
+#define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL
+//XPB_CLG_GFX_UNITID_MAPPING0
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING1
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING2
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING3
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING4
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING5
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING6
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GFX_UNITID_MAPPING7
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING0
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING1
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING2
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_MM_UNITID_MAPPING3
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GUS_UNITID_MAPPING0
+#define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GUS_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GUS_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GUS_UNITID_MAPPING1
+#define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GUS_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GUS_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GUS_UNITID_MAPPING2
+#define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GUS_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GUS_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GUS_UNITID_MAPPING3
+#define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GUS_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GUS_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GUS_UNITID_MAPPING4
+#define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GUS_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GUS_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GUS_UNITID_MAPPING5
+#define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GUS_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GUS_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GUS_UNITID_MAPPING6
+#define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GUS_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GUS_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L
+//XPB_CLG_GUS_UNITID_MAPPING7
+#define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0
+#define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5
+#define XPB_CLG_GUS_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6
+#define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL
+#define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L
+#define XPB_CLG_GUS_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L
+
+
+// addressBlock: athub_rpbdec
+//RPB_PASSPW_CONF
+#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0
+#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3
+#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4
+#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5
+#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6
+#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8
+#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9
+#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11
+#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L
+#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L
+#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L
+#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L
+#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L
+#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L
+#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L
+#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L
+#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L
+#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L
+#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L
+#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L
+#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L
+//RPB_BLOCKLEVEL_CONF
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0
+#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2
+#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4
+#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L
+#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL
+#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L
+#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L
+#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L
+#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L
+#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L
+#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L
+//RPB_TAG_CONF
+#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0
+#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0xa
+#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x14
+#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000003FFL
+#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x000FFC00L
+#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x3FF00000L
+//RPB_EFF_CNTL
+#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
+#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
+#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL
+#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L
+//RPB_ARB_CNTL
+#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0
+#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8
+#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10
+#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18
+#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19
+#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL
+#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L
+#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L
+#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L
+#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L
+//RPB_ARB_CNTL2
+#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0
+#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8
+#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10
+#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL
+#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L
+#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L
+//RPB_BIF_CNTL
+#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0
+#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8
+#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10
+#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11
+#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12
+#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13
+#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b
+#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c
+#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d
+#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e
+#define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN__SHIFT 0x1f
+#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL
+#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L
+#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L
+#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L
+#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L
+#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L
+#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L
+#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L
+#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L
+#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L
+#define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN_MASK 0x80000000L
+//RPB_WR_SWITCH_CNTL
+#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7
+#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe
+#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15
+#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c
+#define RPB_WR_SWITCH_CNTL__WORKLOAD_ADJUST_EN__SHIFT 0x1d
+#define RPB_WR_SWITCH_CNTL__WEIGHT_ADJUST_STEP__SHIFT 0x1e
+#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL
+#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L
+#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L
+#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L
+#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L
+#define RPB_WR_SWITCH_CNTL__WORKLOAD_ADJUST_EN_MASK 0x20000000L
+#define RPB_WR_SWITCH_CNTL__WEIGHT_ADJUST_STEP_MASK 0xC0000000L
+//RPB_WR_COMBINE_CNTL
+#define RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x0
+#define RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x2
+#define RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x6
+#define RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x00000003L
+#define RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x0000003CL
+#define RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x00000040L
+//RPB_RD_SWITCH_CNTL
+#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7
+#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe
+#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15
+#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c
+#define RPB_RD_SWITCH_CNTL__WORKLOAD_ADJUST_EN__SHIFT 0x1d
+#define RPB_RD_SWITCH_CNTL__WEIGHT_ADJUST_STEP__SHIFT 0x1e
+#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL
+#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L
+#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L
+#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L
+#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L
+#define RPB_RD_SWITCH_CNTL__WORKLOAD_ADJUST_EN_MASK 0x20000000L
+#define RPB_RD_SWITCH_CNTL__WEIGHT_ADJUST_STEP_MASK 0xC0000000L
+//RPB_CID_QUEUE_WR
+#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0
+#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5
+#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb
+#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc
+#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf
+#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12
+#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL
+#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L
+#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L
+#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L
+#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L
+#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L
+//RPB_CID_QUEUE_RD
+#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0
+#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5
+#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb
+#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe
+#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL
+#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L
+#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L
+#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L
+//RPB_PERF_COUNTER_CNTL
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
+#define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
+#define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
+#define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L
+#define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L
+#define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L
+#define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L
+#define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001E0L
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003E00L
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007C000L
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00F80000L
+#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1F000000L
+//RPB_PERF_COUNTER_STATUS
+#define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
+#define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xFFFFFFFFL
+//RPB_CID_QUEUE_EX
+#define RPB_CID_QUEUE_EX__START__SHIFT 0x0
+#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
+#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L
+#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL
+//RPB_CID_QUEUE_EX_DATA
+#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
+#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
+#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL
+#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L
+//RPB_SWITCH_CNTL2
+#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0
+#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7
+#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe
+#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15
+#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL
+#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L
+#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L
+#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L
+//RPB_DEINTRLV_COMBINE_CNTL
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5
+#define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD__SHIFT 0x6
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L
+#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L
+#define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD_MASK 0x00003FC0L
+//RPB_VC_SWITCH_RDWR
+#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0
+#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2
+#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa
+#define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD__SHIFT 0x12
+#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L
+#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL
+#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L
+#define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD_MASK 0x03FC0000L
+//RPB_PERFCOUNTER_LO
+#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//RPB_PERFCOUNTER_HI
+#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//RPB_PERFCOUNTER0_CFG
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER1_CFG
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER2_CFG
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER3_CFG
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//RPB_PERFCOUNTER_RSLT_CNTL
+#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//RPB_BIF_CNTL2
+#define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN__SHIFT 0x0
+#define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN_MASK 0x00000001L
+//RPB_RD_QUEUE_CNTL
+#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0
+#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1
+#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2
+#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3
+#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15
+#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L
+#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L
+#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L
+#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L
+#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L
+#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L
+#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L
+//RPB_RD_QUEUE_CNTL2
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL
+#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L
+#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L
+//RPB_WR_QUEUE_CNTL
+#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0
+#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1
+#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2
+#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3
+#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15
+#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L
+#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L
+#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L
+#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L
+#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L
+#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L
+#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L
+//RPB_WR_QUEUE_CNTL2
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL
+#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L
+#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L
+//RPB_EA_QUEUE_WR
+#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0
+#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5
+#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8
+#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb
+#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL
+#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L
+#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L
+#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L
+//RPB_ATS_CNTL
+#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0
+#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1
+#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2
+#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7
+#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf
+#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13
+#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17
+#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19
+#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L
+#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L
+#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL
+#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L
+#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L
+#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L
+#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L
+#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L
+//RPB_ATS_CNTL2
+#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0
+#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6
+#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc
+#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf
+#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12
+#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL
+#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L
+#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L
+#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L
+#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L
+//RPB_DF_SDPPORT_CNTL
+#define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD__SHIFT 0x0
+#define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD__SHIFT 0x6
+#define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD__SHIFT 0xc
+#define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD_MASK 0x0000003FL
+#define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD_MASK 0x00000FC0L
+#define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD_MASK 0x0000F000L
+//RPB_SDPPORT_CNTL
+#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0
+#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5
+#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6
+#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa
+#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf
+#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10
+#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14
+#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b
+#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L
+#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L
+#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L
+#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L
+#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L
+#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L
+//RPB_NBIF_SDPPORT_CNTL
+#define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD__SHIFT 0x0
+#define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD__SHIFT 0x8
+#define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD__SHIFT 0x10
+#define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD__SHIFT 0x18
+#define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD_MASK 0x000000FFL
+#define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD_MASK 0x0000FF00L
+#define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD_MASK 0x00FF0000L
+#define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD_MASK 0xFF000000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h
new file mode 100644
index 000000000000..63759f8c0fa2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_0_0_OFFSET_HEADER
+#define _clk_11_0_0_OFFSET_HEADER
+
+
+// addressBlock: clk_clk3_0_SmuClkDec
+// base address: 0x5c800
+#define mmCLK3_0_CLK3_CLK_PLL_REQ 0x000e
+#define mmCLK3_0_CLK3_CLK_PLL_REQ_BASE_IDX 3
+#define mmCLK3_0_CLK3_CLK2_DFS_CNTL 0x0054
+#define mmCLK3_0_CLK3_CLK2_DFS_CNTL_BASE_IDX 3
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h
new file mode 100644
index 000000000000..e3d954434fcc
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_0_0_SH_MASK_HEADER
+#define _clk_11_0_0_SH_MASK_HEADER
+
+
+// addressBlock: clk_clk3_0_SmuClkDec
+//CLK3_0_CLK3_CLK_PLL_REQ
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
+//CLK3_0_CLK3_CLK2_DFS_CNTL
+#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER__SHIFT 0x0
+#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER_MASK 0x0000007FL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
new file mode 100644
index 000000000000..cff8f91555d3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
@@ -0,0 +1,17535 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_2_0_0_OFFSET_HEADER
+#define _dcn_2_0_0_OFFSET_HEADER
+
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+// base address: 0x0
+#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
+#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
+#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
+#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
+#define mmVGA_RENDER_CONTROL 0x0000
+#define mmVGA_RENDER_CONTROL_BASE_IDX 1
+#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
+#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
+#define mmVGA_MODE_CONTROL 0x0002
+#define mmVGA_MODE_CONTROL_BASE_IDX 1
+#define mmVGA_SURFACE_PITCH_SELECT 0x0003
+#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
+#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
+#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
+#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
+#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
+#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
+#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
+#define mmVGA_HDP_CONTROL 0x000a
+#define mmVGA_HDP_CONTROL_BASE_IDX 1
+#define mmVGA_CACHE_CONTROL 0x000b
+#define mmVGA_CACHE_CONTROL_BASE_IDX 1
+#define mmD1VGA_CONTROL 0x000c
+#define mmD1VGA_CONTROL_BASE_IDX 1
+#define mmD2VGA_CONTROL 0x000e
+#define mmD2VGA_CONTROL_BASE_IDX 1
+#define mmVGA_STATUS 0x0010
+#define mmVGA_STATUS_BASE_IDX 1
+#define mmVGA_INTERRUPT_CONTROL 0x0011
+#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
+#define mmVGA_STATUS_CLEAR 0x0012
+#define mmVGA_STATUS_CLEAR_BASE_IDX 1
+#define mmVGA_INTERRUPT_STATUS 0x0013
+#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
+#define mmVGA_MAIN_CONTROL 0x0014
+#define mmVGA_MAIN_CONTROL_BASE_IDX 1
+#define mmVGA_TEST_CONTROL 0x0015
+#define mmVGA_TEST_CONTROL_BASE_IDX 1
+#define mmVGA_QOS_CTRL 0x0018
+#define mmVGA_QOS_CTRL_BASE_IDX 1
+#define mmCRTC8_IDX 0x002d
+#define mmCRTC8_IDX_BASE_IDX 1
+#define mmCRTC8_DATA 0x002d
+#define mmCRTC8_DATA_BASE_IDX 1
+#define mmGENFC_WT 0x002e
+#define mmGENFC_WT_BASE_IDX 1
+#define mmGENS1 0x002e
+#define mmGENS1_BASE_IDX 1
+#define mmATTRDW 0x0030
+#define mmATTRDW_BASE_IDX 1
+#define mmATTRX 0x0030
+#define mmATTRX_BASE_IDX 1
+#define mmATTRDR 0x0030
+#define mmATTRDR_BASE_IDX 1
+#define mmGENMO_WT 0x0030
+#define mmGENMO_WT_BASE_IDX 1
+#define mmGENS0 0x0030
+#define mmGENS0_BASE_IDX 1
+#define mmGENENB 0x0030
+#define mmGENENB_BASE_IDX 1
+#define mmSEQ8_IDX 0x0031
+#define mmSEQ8_IDX_BASE_IDX 1
+#define mmSEQ8_DATA 0x0031
+#define mmSEQ8_DATA_BASE_IDX 1
+#define mmDAC_MASK 0x0031
+#define mmDAC_MASK_BASE_IDX 1
+#define mmDAC_R_INDEX 0x0031
+#define mmDAC_R_INDEX_BASE_IDX 1
+#define mmDAC_W_INDEX 0x0032
+#define mmDAC_W_INDEX_BASE_IDX 1
+#define mmDAC_DATA 0x0032
+#define mmDAC_DATA_BASE_IDX 1
+#define mmGENFC_RD 0x0032
+#define mmGENFC_RD_BASE_IDX 1
+#define mmGENMO_RD 0x0033
+#define mmGENMO_RD_BASE_IDX 1
+#define mmGRPH8_IDX 0x0033
+#define mmGRPH8_IDX_BASE_IDX 1
+#define mmGRPH8_DATA 0x0033
+#define mmGRPH8_DATA_BASE_IDX 1
+#define mmCRTC8_IDX_1 0x0035
+#define mmCRTC8_IDX_1_BASE_IDX 1
+#define mmCRTC8_DATA_1 0x0035
+#define mmCRTC8_DATA_1_BASE_IDX 1
+#define mmGENFC_WT_1 0x0036
+#define mmGENFC_WT_1_BASE_IDX 1
+#define mmGENS1_1 0x0036
+#define mmGENS1_1_BASE_IDX 1
+#define mmD3VGA_CONTROL 0x0038
+#define mmD3VGA_CONTROL_BASE_IDX 1
+#define mmD4VGA_CONTROL 0x0039
+#define mmD4VGA_CONTROL_BASE_IDX 1
+#define mmD5VGA_CONTROL 0x003a
+#define mmD5VGA_CONTROL_BASE_IDX 1
+#define mmD6VGA_CONTROL 0x003b
+#define mmD6VGA_CONTROL_BASE_IDX 1
+#define mmVGA_SOURCE_SELECT 0x003c
+#define mmVGA_SOURCE_SELECT_BASE_IDX 1
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+// base address: 0x0
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmDP_DTO_DBUF_EN 0x0044
+#define mmDP_DTO_DBUF_EN_BASE_IDX 1
+#define mmDSCCLK3_DTO_PARAM 0x0045
+#define mmDSCCLK3_DTO_PARAM_BASE_IDX 1
+#define mmDSCCLK4_DTO_PARAM 0x0046
+#define mmDSCCLK4_DTO_PARAM_BASE_IDX 1
+#define mmDSCCLK5_DTO_PARAM 0x0047
+#define mmDSCCLK5_DTO_PARAM_BASE_IDX 1
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmREFCLK_CNTL 0x0049
+#define mmREFCLK_CNTL_BASE_IDX 1
+#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
+#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmDCCG_PERFMON_CNTL2 0x004e
+#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
+#define mmDCCG_DS_DTO_INCR 0x0053
+#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
+#define mmDCCG_DS_DTO_MODULO 0x0054
+#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
+#define mmDCCG_DS_CNTL 0x0055
+#define mmDCCG_DS_CNTL_BASE_IDX 1
+#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
+#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
+#define mmDPREFCLK_CNTL 0x0058
+#define mmDPREFCLK_CNTL_BASE_IDX 1
+#define mmDCE_VERSION 0x005e
+#define mmDCE_VERSION_BASE_IDX 1
+#define mmDCCG_GTC_CNTL 0x0060
+#define mmDCCG_GTC_CNTL_BASE_IDX 1
+#define mmDCCG_GTC_DTO_INCR 0x0061
+#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
+#define mmDCCG_GTC_DTO_MODULO 0x0062
+#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
+#define mmDCCG_GTC_CURRENT 0x0063
+#define mmDCCG_GTC_CURRENT_BASE_IDX 1
+#define mmDSCCLK0_DTO_PARAM 0x006c
+#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1
+#define mmDSCCLK1_DTO_PARAM 0x006d
+#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1
+#define mmDSCCLK2_DTO_PARAM 0x006e
+#define mmDSCCLK2_DTO_PARAM_BASE_IDX 1
+#define mmMILLISECOND_TIME_BASE_DIV 0x0070
+#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
+#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
+#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
+#define mmDCCG_PERFMON_CNTL 0x0073
+#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
+#define mmDCCG_GATE_DISABLE_CNTL 0x0074
+#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
+#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
+#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
+#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmDCCG_CAC_STATUS 0x0077
+#define mmDCCG_CAC_STATUS_BASE_IDX 1
+#define mmMICROSECOND_TIME_BASE_DIV 0x007b
+#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
+#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
+#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
+#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
+#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
+#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
+#define mmDCCG_DISP_CNTL_REG 0x007f
+#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
+#define mmOTG0_PIXEL_RATE_CNTL 0x0080
+#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO0_PHASE 0x0081
+#define mmDP_DTO0_PHASE_BASE_IDX 1
+#define mmDP_DTO0_MODULO 0x0082
+#define mmDP_DTO0_MODULO_BASE_IDX 1
+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmOTG1_PIXEL_RATE_CNTL 0x0084
+#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO1_PHASE 0x0085
+#define mmDP_DTO1_PHASE_BASE_IDX 1
+#define mmDP_DTO1_MODULO 0x0086
+#define mmDP_DTO1_MODULO_BASE_IDX 1
+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmOTG2_PIXEL_RATE_CNTL 0x0088
+#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO2_PHASE 0x0089
+#define mmDP_DTO2_PHASE_BASE_IDX 1
+#define mmDP_DTO2_MODULO 0x008a
+#define mmDP_DTO2_MODULO_BASE_IDX 1
+#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
+#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmOTG3_PIXEL_RATE_CNTL 0x008c
+#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO3_PHASE 0x008d
+#define mmDP_DTO3_PHASE_BASE_IDX 1
+#define mmDP_DTO3_MODULO 0x008e
+#define mmDP_DTO3_MODULO_BASE_IDX 1
+#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
+#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmOTG4_PIXEL_RATE_CNTL 0x0090
+#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO4_PHASE 0x0091
+#define mmDP_DTO4_PHASE_BASE_IDX 1
+#define mmDP_DTO4_MODULO 0x0092
+#define mmDP_DTO4_MODULO_BASE_IDX 1
+#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093
+#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmOTG5_PIXEL_RATE_CNTL 0x0094
+#define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDP_DTO5_PHASE 0x0095
+#define mmDP_DTO5_PHASE_BASE_IDX 1
+#define mmDP_DTO5_MODULO 0x0096
+#define mmDP_DTO5_MODULO_BASE_IDX 1
+#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097
+#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
+#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
+#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
+#define mmDPPCLK0_DTO_PARAM 0x0099
+#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1
+#define mmDPPCLK1_DTO_PARAM 0x009a
+#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1
+#define mmDPPCLK2_DTO_PARAM 0x009b
+#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1
+#define mmDPPCLK3_DTO_PARAM 0x009c
+#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1
+#define mmDPPCLK4_DTO_PARAM 0x009d
+#define mmDPPCLK4_DTO_PARAM_BASE_IDX 1
+#define mmDPPCLK5_DTO_PARAM 0x009e
+#define mmDPPCLK5_DTO_PARAM_BASE_IDX 1
+#define mmDCCG_CAC_STATUS2 0x009f
+#define mmDCCG_CAC_STATUS2_BASE_IDX 1
+#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
+#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
+#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
+#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
+#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
+#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
+#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
+#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
+#define mmDCCG_SOFT_RESET 0x00a6
+#define mmDCCG_SOFT_RESET_BASE_IDX 1
+#define mmDSCCLK_DTO_CTRL 0x00a7
+#define mmDSCCLK_DTO_CTRL_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
+#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
+#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
+#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
+#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
+#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
+#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
+#define mmDPPCLK_DTO_CTRL 0x00b6
+#define mmDPPCLK_DTO_CTRL_BASE_IDX 1
+#define mmDCCG_VSYNC_CNT_CTRL 0x00b8
+#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
+#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
+#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
+#define mmFORCE_SYMCLK_DISABLE 0x00ba
+#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1
+#define mmDCCG_TEST_CLK_SEL 0x00be
+#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+// base address: 0x0
+#define mmDENTIST_DISPCLK_CNTL 0x0064
+#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+// base address: 0x0
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002
+#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_CNTL 0x0003
+#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004
+#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_HI 0x0007
+#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON0_PERFMON_LOW 0x0008
+#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
+// base address: 0x30
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e
+#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_CNTL 0x000f
+#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010
+#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_HI 0x0013
+#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON1_PERFMON_LOW 0x0014
+#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dccg_dccg_pll_dispdec
+// base address: 0x0
+#define mmPLL_MACRO_CNTL_RESERVED0 0x0018
+#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED1 0x0019
+#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED2 0x001a
+#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED3 0x001b
+#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED4 0x001c
+#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED5 0x001d
+#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED6 0x001e
+#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED7 0x001f
+#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED8 0x0020
+#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED9 0x0021
+#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED10 0x0022
+#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED11 0x0023
+#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED12 0x0024
+#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED13 0x0025
+#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED14 0x0026
+#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED15 0x0027
+#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED16 0x0028
+#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED17 0x0029
+#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED18 0x002a
+#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED19 0x002b
+#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED20 0x002c
+#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED21 0x002d
+#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED22 0x002e
+#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED23 0x002f
+#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED24 0x0030
+#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED25 0x0031
+#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED26 0x0032
+#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED27 0x0033
+#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED28 0x0034
+#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED29 0x0035
+#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED30 0x0036
+#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED31 0x0037
+#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED32 0x0038
+#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED33 0x0039
+#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED34 0x003a
+#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED35 0x003b
+#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED36 0x003c
+#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED37 0x003d
+#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED38 0x003e
+#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED39 0x003f
+#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED40 0x0040
+#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmPLL_MACRO_CNTL_RESERVED41 0x0041
+#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+// base address: 0x0
+#define mmRBBMIF_TIMEOUT 0x005b
+#define mmRBBMIF_TIMEOUT_BASE_IDX 2
+#define mmRBBMIF_STATUS 0x005c
+#define mmRBBMIF_STATUS_BASE_IDX 2
+#define mmRBBMIF_STATUS_2 0x005d
+#define mmRBBMIF_STATUS_2_BASE_IDX 2
+#define mmRBBMIF_INT_STATUS 0x005e
+#define mmRBBMIF_INT_STATUS_BASE_IDX 2
+#define mmRBBMIF_TIMEOUT_DIS 0x005f
+#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
+#define mmRBBMIF_TIMEOUT_DIS_2 0x0060
+#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2
+#define mmRBBMIF_STATUS_FLAG 0x0061
+#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+// base address: 0x0
+#define mmDOMAIN0_PG_CONFIG 0x0080
+#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN0_PG_STATUS 0x0081
+#define mmDOMAIN0_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN1_PG_CONFIG 0x0082
+#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN1_PG_STATUS 0x0083
+#define mmDOMAIN1_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN2_PG_CONFIG 0x0084
+#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN2_PG_STATUS 0x0085
+#define mmDOMAIN2_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN3_PG_CONFIG 0x0086
+#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN3_PG_STATUS 0x0087
+#define mmDOMAIN3_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN4_PG_CONFIG 0x0088
+#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN4_PG_STATUS 0x0089
+#define mmDOMAIN4_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN5_PG_CONFIG 0x008a
+#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN5_PG_STATUS 0x008b
+#define mmDOMAIN5_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN6_PG_CONFIG 0x008c
+#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN6_PG_STATUS 0x008d
+#define mmDOMAIN6_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN7_PG_CONFIG 0x008e
+#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN7_PG_STATUS 0x008f
+#define mmDOMAIN7_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN8_PG_CONFIG 0x0090
+#define mmDOMAIN8_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN8_PG_STATUS 0x0091
+#define mmDOMAIN8_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN9_PG_CONFIG 0x0092
+#define mmDOMAIN9_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN9_PG_STATUS 0x0093
+#define mmDOMAIN9_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN10_PG_CONFIG 0x0094
+#define mmDOMAIN10_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN10_PG_STATUS 0x0095
+#define mmDOMAIN10_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN11_PG_CONFIG 0x0096
+#define mmDOMAIN11_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN11_PG_STATUS 0x0097
+#define mmDOMAIN11_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN16_PG_CONFIG 0x00a1
+#define mmDOMAIN16_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN16_PG_STATUS 0x00a2
+#define mmDOMAIN16_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN17_PG_CONFIG 0x00a3
+#define mmDOMAIN17_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN17_PG_STATUS 0x00a4
+#define mmDOMAIN17_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN18_PG_CONFIG 0x00a5
+#define mmDOMAIN18_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN18_PG_STATUS 0x00a6
+#define mmDOMAIN18_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN19_PG_CONFIG 0x00a7
+#define mmDOMAIN19_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN19_PG_STATUS 0x00a8
+#define mmDOMAIN19_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN20_PG_CONFIG 0x00a9
+#define mmDOMAIN20_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN20_PG_STATUS 0x00aa
+#define mmDOMAIN20_PG_STATUS_BASE_IDX 2
+#define mmDOMAIN21_PG_CONFIG 0x00ab
+#define mmDOMAIN21_PG_CONFIG_BASE_IDX 2
+#define mmDOMAIN21_PG_STATUS 0x00ac
+#define mmDOMAIN21_PG_STATUS_BASE_IDX 2
+#define mmDCPG_INTERRUPT_STATUS 0x00ad
+#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCPG_INTERRUPT_STATUS_2 0x00ae
+#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2
+#define mmDCPG_INTERRUPT_CONTROL_1 0x00af
+#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
+#define mmDCPG_INTERRUPT_CONTROL_2 0x00b0
+#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
+#define mmDCPG_INTERRUPT_CONTROL_3 0x00b1
+#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2
+#define mmDC_IP_REQUEST_CNTL 0x00b2
+#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2f8
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0
+#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1
+#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2
+#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_HI 0x00c5
+#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON2_PERFMON_LOW 0x00c6
+#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+// base address: 0x0
+#define mmCC_DC_PIPE_DIS 0x00ca
+#define mmCC_DC_PIPE_DIS_BASE_IDX 2
+#define mmDMU_CLK_CNTL 0x00cb
+#define mmDMU_CLK_CNTL_BASE_IDX 2
+#define mmDMU_MEM_PWR_CNTL 0x00cc
+#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2
+#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd
+#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2
+#define mmSMU_INTERRUPT_CONTROL 0x00ce
+#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6
+#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+// base address: 0x0
+#define mmDMCU_CTRL 0x00da
+#define mmDMCU_CTRL_BASE_IDX 2
+#define mmDMCU_STATUS 0x00db
+#define mmDMCU_STATUS_BASE_IDX 2
+#define mmDMCU_PC_START_ADDR 0x00dc
+#define mmDMCU_PC_START_ADDR_BASE_IDX 2
+#define mmDMCU_FW_START_ADDR 0x00dd
+#define mmDMCU_FW_START_ADDR_BASE_IDX 2
+#define mmDMCU_FW_END_ADDR 0x00de
+#define mmDMCU_FW_END_ADDR_BASE_IDX 2
+#define mmDMCU_FW_ISR_START_ADDR 0x00df
+#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
+#define mmDMCU_FW_CS_HI 0x00e0
+#define mmDMCU_FW_CS_HI_BASE_IDX 2
+#define mmDMCU_FW_CS_LO 0x00e1
+#define mmDMCU_FW_CS_LO_BASE_IDX 2
+#define mmDMCU_RAM_ACCESS_CTRL 0x00e2
+#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
+#define mmDMCU_ERAM_WR_CTRL 0x00e3
+#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
+#define mmDMCU_ERAM_WR_DATA 0x00e4
+#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
+#define mmDMCU_ERAM_RD_CTRL 0x00e5
+#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
+#define mmDMCU_ERAM_RD_DATA 0x00e6
+#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
+#define mmDMCU_IRAM_WR_CTRL 0x00e7
+#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
+#define mmDMCU_IRAM_WR_DATA 0x00e8
+#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
+#define mmDMCU_IRAM_RD_CTRL 0x00e9
+#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
+#define mmDMCU_IRAM_RD_DATA 0x00ea
+#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
+#define mmDMCU_EVENT_TRIGGER 0x00eb
+#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
+#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec
+#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
+#define mmDMCU_INTERRUPT_STATUS 0x00ee
+#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDMCU_INTERRUPT_STATUS_1 0x00ef
+#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
+#define mmDC_DMCU_SCRATCH 0x00f5
+#define mmDC_DMCU_SCRATCH_BASE_IDX 2
+#define mmDMCU_INT_CNT 0x00f6
+#define mmDMCU_INT_CNT_BASE_IDX 2
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
+#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
+#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
+#define mmMASTER_COMM_DATA_REG1 0x00f9
+#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
+#define mmMASTER_COMM_DATA_REG2 0x00fa
+#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
+#define mmMASTER_COMM_DATA_REG3 0x00fb
+#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
+#define mmMASTER_COMM_CMD_REG 0x00fc
+#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
+#define mmMASTER_COMM_CNTL_REG 0x00fd
+#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
+#define mmSLAVE_COMM_DATA_REG1 0x00fe
+#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
+#define mmSLAVE_COMM_DATA_REG2 0x00ff
+#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
+#define mmSLAVE_COMM_DATA_REG3 0x0100
+#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
+#define mmSLAVE_COMM_CMD_REG 0x0101
+#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
+#define mmSLAVE_COMM_CNTL_REG 0x0102
+#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
+#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114
+#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
+#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119
+#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2
+#define mmDMCU_INT_CNT_CONTINUE 0x011c
+#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2
+#define mmDMCU_INTERRUPT_STATUS_2 0x011e
+#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+// base address: 0x0
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
+#define mmDC_GPU_TIMER_READ 0x0128
+#define mmDC_GPU_TIMER_READ_BASE_IDX 2
+#define mmDC_GPU_TIMER_READ_CNTL 0x0129
+#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS 0x012a
+#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b
+#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
+#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
+#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
+#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
+#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
+#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
+#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
+#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
+#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
+#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
+#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
+#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
+#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
+#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141
+#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
+#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142
+#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145
+#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146
+#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2
+#define mmDCCG_INTERRUPT_DEST 0x0147
+#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2
+#define mmDMU_INTERRUPT_DEST 0x0148
+#define mmDMU_INTERRUPT_DEST_BASE_IDX 2
+#define mmDCPG_INTERRUPT_DEST 0x0149
+#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2
+#define mmDCPG_INTERRUPT_DEST2 0x014a
+#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2
+#define mmMMHUBBUB_INTERRUPT_DEST 0x014b
+#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2
+#define mmWB_INTERRUPT_DEST 0x014c
+#define mmWB_INTERRUPT_DEST_BASE_IDX 2
+#define mmDCHUB_INTERRUPT_DEST 0x014d
+#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2
+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x014e
+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
+#define mmDCHUB_INTERRUPT_DEST2 0x014f
+#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2
+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0150
+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
+#define mmMPC_INTERRUPT_DEST 0x0151
+#define mmMPC_INTERRUPT_DEST_BASE_IDX 2
+#define mmOPP_INTERRUPT_DEST 0x0152
+#define mmOPP_INTERRUPT_DEST_BASE_IDX 2
+#define mmOPTC_INTERRUPT_DEST 0x0153
+#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2
+#define mmOTG0_INTERRUPT_DEST 0x0154
+#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2
+#define mmOTG1_INTERRUPT_DEST 0x0155
+#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2
+#define mmOTG2_INTERRUPT_DEST 0x0156
+#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2
+#define mmOTG3_INTERRUPT_DEST 0x0157
+#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2
+#define mmOTG4_INTERRUPT_DEST 0x0158
+#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2
+#define mmOTG5_INTERRUPT_DEST 0x0159
+#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2
+#define mmDIG_INTERRUPT_DEST 0x015a
+#define mmDIG_INTERRUPT_DEST_BASE_IDX 2
+#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015b
+#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2
+#define mmDIO_INTERRUPT_DEST 0x015d
+#define mmDIO_INTERRUPT_DEST_BASE_IDX 2
+#define mmDCIO_INTERRUPT_DEST 0x015e
+#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2
+#define mmHPD_INTERRUPT_DEST 0x015f
+#define mmHPD_INTERRUPT_DEST_BASE_IDX 2
+#define mmAZ_INTERRUPT_DEST 0x0160
+#define mmAZ_INTERRUPT_DEST_BASE_IDX 2
+#define mmAUX_INTERRUPT_DEST 0x0161
+#define mmAUX_INTERRUPT_DEST_BASE_IDX 2
+#define mmDSC_INTERRUPT_DEST 0x0162
+#define mmDSC_INTERRUPT_DEST_BASE_IDX 2
+
+
+// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
+// base address: 0x0
+#define mmWB_ENABLE 0x01da
+#define mmWB_ENABLE_BASE_IDX 2
+#define mmWB_EC_CONFIG 0x01db
+#define mmWB_EC_CONFIG_BASE_IDX 2
+#define mmCNV_MODE 0x01dc
+#define mmCNV_MODE_BASE_IDX 2
+#define mmCNV_WINDOW_START 0x01dd
+#define mmCNV_WINDOW_START_BASE_IDX 2
+#define mmCNV_WINDOW_SIZE 0x01de
+#define mmCNV_WINDOW_SIZE_BASE_IDX 2
+#define mmCNV_UPDATE 0x01df
+#define mmCNV_UPDATE_BASE_IDX 2
+#define mmCNV_SOURCE_SIZE 0x01e0
+#define mmCNV_SOURCE_SIZE_BASE_IDX 2
+#define mmCNV_TEST_CNTL 0x01ee
+#define mmCNV_TEST_CNTL_BASE_IDX 2
+#define mmCNV_TEST_CRC_RED 0x01ef
+#define mmCNV_TEST_CRC_RED_BASE_IDX 2
+#define mmCNV_TEST_CRC_GREEN 0x01f0
+#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2
+#define mmCNV_TEST_CRC_BLUE 0x01f1
+#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
+#define mmWB_DEBUG_CTRL 0x01f2
+#define mmWB_DEBUG_CTRL_BASE_IDX 2
+#define mmWB_DBG_MODE 0x01f3
+#define mmWB_DBG_MODE_BASE_IDX 2
+#define mmWB_HW_DEBUG 0x01f4
+#define mmWB_HW_DEBUG_BASE_IDX 2
+#define mmWB_SOFT_RESET 0x01f5
+#define mmWB_SOFT_RESET_BASE_IDX 2
+#define mmWB_WARM_UP_MODE_CTL1 0x01f6
+#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2
+#define mmWB_WARM_UP_MODE_CTL2 0x01f7
+#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2
+#define mmCNV_TEST_DEBUG_INDEX 0x01f8
+#define mmCNV_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCNV_TEST_DEBUG_DATA 0x01f9
+#define mmCNV_TEST_DEBUG_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
+// base address: 0x0
+#define mmWBSCL_COEF_RAM_SELECT 0x020a
+#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2
+#define mmWBSCL_COEF_RAM_TAP_DATA 0x020b
+#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmWBSCL_MODE 0x020c
+#define mmWBSCL_MODE_BASE_IDX 2
+#define mmWBSCL_TAP_CONTROL 0x020d
+#define mmWBSCL_TAP_CONTROL_BASE_IDX 2
+#define mmWBSCL_DEST_SIZE 0x020e
+#define mmWBSCL_DEST_SIZE_BASE_IDX 2
+#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x020f
+#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210
+#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
+#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0211
+#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
+#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x0212
+#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x0213
+#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
+#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x0214
+#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
+#define mmWBSCL_ROUND_OFFSET 0x0215
+#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2
+#define mmWBSCL_OVERFLOW_STATUS 0x0216
+#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2
+#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0217
+#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
+#define mmWBSCL_TEST_CNTL 0x0218
+#define mmWBSCL_TEST_CNTL_BASE_IDX 2
+#define mmWBSCL_TEST_CRC_RED 0x0219
+#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2
+#define mmWBSCL_TEST_CRC_GREEN 0x021a
+#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2
+#define mmWBSCL_TEST_CRC_BLUE 0x021b
+#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2
+#define mmWBSCL_BACKPRESSURE_CNT_EN 0x021c
+#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
+#define mmWB_MCIF_BACKPRESSURE_CNT 0x021d
+#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
+#define mmWBSCL_CLAMP_Y_RGB 0x021e
+#define mmWBSCL_CLAMP_Y_RGB_BASE_IDX 2
+#define mmWBSCL_CLAMP_CBCR 0x021f
+#define mmWBSCL_CLAMP_CBCR_BASE_IDX 2
+#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0220
+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR 0x0221
+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR_BASE_IDX 2
+#define mmWBSCL_DEBUG 0x0222
+#define mmWBSCL_DEBUG_BASE_IDX 2
+#define mmWBSCL_TEST_DEBUG_INDEX 0x0223
+#define mmWBSCL_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmWBSCL_TEST_DEBUG_DATA 0x0224
+#define mmWBSCL_TEST_DEBUG_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+// base address: 0x8e8
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c
+#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_CNTL 0x023d
+#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_CNTL2 0x023e
+#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_HI 0x0241
+#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON3_PERFMON_LOW 0x0242
+#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+// base address: 0x0
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5
+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be
+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf
+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x02c0
+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x02c1
+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5
+#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7
+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9
+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL 0x02da
+#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db
+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x02dd
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH 0x02de
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x02df
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH 0x02e0
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x02e1
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH 0x02e2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x02e3
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH 0x02e4
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION 0x02e5
+#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION 0x02e6
+#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION 0x02e7
+#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION 0x02e8
+#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
+// base address: 0x100
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5
+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe
+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff
+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x0300
+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x0301
+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315
+#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317
+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319
+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b
+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c
+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x031d
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH 0x031e
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x031f
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH 0x0320
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x0321
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH 0x0322
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x0323
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH 0x0324
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION 0x0325
+#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION 0x0326
+#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION 0x0327
+#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
+#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION 0x0328
+#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+// base address: 0x0
+#define mmWBIF0_MISC_CTRL 0x0333
+#define mmWBIF0_MISC_CTRL_BASE_IDX 2
+#define mmWBIF0_SMU_WM_CONTROL 0x0334
+#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2
+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335
+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336
+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
+#define mmVGA_SRC_SPLIT_CNTL 0x033f
+#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2
+#define mmMMHUBBUB_MEM_PWR_STATUS 0x0340
+#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
+#define mmMMHUBBUB_MEM_PWR_CNTL 0x0341
+#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
+#define mmMMHUBBUB_CLOCK_CNTL 0x0342
+#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
+#define mmMMHUBBUB_SOFT_RESET 0x0343
+#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2
+#define mmDMU_IF_ERR_STATUS 0x0347
+#define mmDMU_IF_ERR_STATUS_BASE_IDX 2
+#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0348
+#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+// base address: 0x0
+#define mmMCIF_CONTROL 0x034a
+#define mmMCIF_CONTROL_BASE_IDX 2
+#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b
+#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e
+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f
+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350
+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0xd48
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x0352
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0354
+#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_CNTL 0x0355
+#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_CNTL2 0x0356
+#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_HI 0x0359
+#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON4_PERFMON_LOW 0x035a
+#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+// base address: 0x0
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+// base address: 0x8
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+// base address: 0x10
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+// base address: 0x18
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+// base address: 0x20
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+// base address: 0x28
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+// base address: 0x30
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+// base address: 0x38
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+// base address: 0x0
+#define mmAZ_CLOCK_CNTL 0x0372
+#define mmAZ_CLOCK_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
+// base address: 0xde8
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x037a
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x037c
+#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_CNTL 0x037d
+#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_CNTL2 0x037e
+#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_HI 0x0381
+#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON5_PERFMON_LOW 0x0382
+#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+// base address: 0x0
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+// base address: 0x18
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+// base address: 0x30
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+// base address: 0x48
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+// base address: 0x60
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+// base address: 0x78
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+// base address: 0x90
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+// base address: 0xa8
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+// base address: 0x0
+#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
+#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
+#define mmAZALIA_AUDIO_DTO 0x03c3
+#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
+#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
+#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
+#define mmAZALIA_SOCCLK_CONTROL 0x03c5
+#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
+#define mmAZALIA_DATA_DMA_CONTROL 0x03c7
+#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
+#define mmAZALIA_BDL_DMA_CONTROL 0x03c8
+#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
+#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
+#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
+#define mmAZALIA_CORB_DMA_CONTROL 0x03ca
+#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
+#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
+#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
+#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
+#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
+#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
+#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
+#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
+#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
+#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
+#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
+#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
+#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
+#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
+#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
+#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
+#define mmAZALIA_CRC0_CONTROL0 0x03e3
+#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
+#define mmAZALIA_CRC0_CONTROL1 0x03e4
+#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
+#define mmAZALIA_CRC0_CONTROL2 0x03e5
+#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
+#define mmAZALIA_CRC0_CONTROL3 0x03e6
+#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
+#define mmAZALIA_CRC0_RESULT 0x03e7
+#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
+#define mmAZALIA_CRC1_CONTROL0 0x03e8
+#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
+#define mmAZALIA_CRC1_CONTROL1 0x03e9
+#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
+#define mmAZALIA_CRC1_CONTROL2 0x03ea
+#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
+#define mmAZALIA_CRC1_CONTROL3 0x03eb
+#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
+#define mmAZALIA_CRC1_RESULT 0x03ec
+#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
+#define mmAZALIA_MEM_PWR_CTRL 0x03ee
+#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
+#define mmAZALIA_MEM_PWR_STATUS 0x03ef
+#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+// base address: 0x0
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+// base address: 0x320
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+// base address: 0x328
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+// base address: 0x330
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+// base address: 0x338
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+// base address: 0x340
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+// base address: 0x348
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+// base address: 0x350
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+// base address: 0x358
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
+// base address: 0x0
+#define mmDCHUBBUB_SDPIF_CFG0 0x048f
+#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
+#define mmVM_REQUEST_PHYSICAL 0x0490
+#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2
+#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491
+#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
+#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492
+#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
+#define mmDCN_VM_FB_LOCATION_BASE 0x0493
+#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2
+#define mmDCN_VM_FB_LOCATION_TOP 0x0494
+#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2
+#define mmDCN_VM_FB_OFFSET 0x0495
+#define mmDCN_VM_FB_OFFSET_BASE_IDX 2
+#define mmDCN_VM_AGP_BOT 0x0496
+#define mmDCN_VM_AGP_BOT_BASE_IDX 2
+#define mmDCN_VM_AGP_TOP 0x0497
+#define mmDCN_VM_AGP_TOP_BASE_IDX 2
+#define mmDCN_VM_AGP_BASE 0x0498
+#define mmDCN_VM_AGP_BASE_BASE_IDX 2
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2
+#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8
+#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2
+#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x04b9
+#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2
+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba
+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb
+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCHUBBUB_SDPIF_CFG1 0x04bf
+#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
+// base address: 0x0
+#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
+#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0 0x04e0
+#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1 0x04e1
+#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0 0x04e2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1 0x04e3
+#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG10_0 0x04e4
+#define mmDCHUBBUB_RET_PATH_DCC_CFG10_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG10_1 0x04e5
+#define mmDCHUBBUB_RET_PATH_DCC_CFG10_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG11_0 0x04e6
+#define mmDCHUBBUB_RET_PATH_DCC_CFG11_0_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG11_1 0x04e7
+#define mmDCHUBBUB_RET_PATH_DCC_CFG11_1_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDCHUBBUB_CRC_CTRL 0x04f1
+#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
+#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2
+#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
+#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3
+#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
+#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4
+#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
+#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5
+#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_dispdec
+// base address: 0x0
+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
+#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
+#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
+#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
+#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
+#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a
+#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
+#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f
+#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
+#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514
+#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
+#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519
+#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
+#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520
+#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
+#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521
+#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
+#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522
+#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
+#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523
+#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
+#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524
+#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
+#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525
+#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
+#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526
+#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
+#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527
+#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
+#define mmVTG0_CONTROL 0x0528
+#define mmVTG0_CONTROL_BASE_IDX 2
+#define mmVTG1_CONTROL 0x0529
+#define mmVTG1_CONTROL_BASE_IDX 2
+#define mmVTG2_CONTROL 0x052a
+#define mmVTG2_CONTROL_BASE_IDX 2
+#define mmVTG3_CONTROL 0x052b
+#define mmVTG3_CONTROL_BASE_IDX 2
+#define mmVTG4_CONTROL 0x052c
+#define mmVTG4_CONTROL_BASE_IDX 2
+#define mmVTG5_CONTROL 0x052d
+#define mmVTG5_CONTROL_BASE_IDX 2
+#define mmDCHUBBUB_SOFT_RESET 0x052e
+#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
+#define mmDCHUBBUB_CLOCK_CNTL 0x052f
+#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
+#define mmDCFCLK_CNTL 0x0530
+#define mmDCFCLK_CNTL_BASE_IDX 2
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
+#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
+#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
+#define mmDCHUBBUB_CTRL_STATUS 0x0534
+#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2
+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c
+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d
+#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e
+#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
+#define mmFMON_CTRL 0x0548
+#define mmFMON_CTRL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1534
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x054d
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x054f
+#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_CNTL 0x0550
+#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_CNTL2 0x0551
+#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_HI 0x0554
+#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON6_PERFMON_LOW 0x0555
+#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
+// base address: 0x0
+#define mmDCN_VM_CONTEXT0_CNTL 0x0559
+#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT1_CNTL 0x0560
+#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT2_CNTL 0x0567
+#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT3_CNTL 0x056e
+#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT4_CNTL 0x0575
+#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT5_CNTL 0x057c
+#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT6_CNTL 0x0583
+#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT7_CNTL 0x058a
+#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT8_CNTL 0x0591
+#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT9_CNTL 0x0598
+#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT10_CNTL 0x059f
+#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT11_CNTL 0x05a6
+#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT12_CNTL 0x05ad
+#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT13_CNTL 0x05b4
+#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT14_CNTL 0x05bb
+#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT15_CNTL 0x05c2
+#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
+#define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x05c9
+#define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x05ca
+#define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x05cb
+#define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x05cc
+#define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmDCN_VM_FAULT_CNTL 0x05cd
+#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2
+#define mmDCN_VM_FAULT_STATUS 0x05ce
+#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2
+#define mmDCN_VM_FAULT_ADDR_MSB 0x05cf
+#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2
+#define mmDCN_VM_FAULT_ADDR_LSB 0x05d0
+#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+// base address: 0x0
+#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5
+#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
+#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6
+#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
+#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7
+#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
+#define mmHUBP0_DCHUBP_CNTL 0x05f3
+#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
+#define mmHUBP0_HUBP_CLK_CNTL 0x05f4
+#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
+#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5
+#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
+#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6
+#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
+#define mmHUBP0_HUBPREQ_DEBUG 0x05f7
+#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+// base address: 0x0
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
+#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609
+#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a
+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_QUEUE_CONTROL 0x061d
+#define mmHUBPREQ0_DCSURF_QUEUE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0x061e
+#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
+#define mmHUBPREQ0_SURFACE_CURRENT_PACING_COUNTER 0x061f
+#define mmHUBPREQ0_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620
+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x062c
+#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
+#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062d
+#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062e
+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062f
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x0630
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x0631
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x0632
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0633
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0634
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0635
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0636
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0637
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0638
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0639
+#define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x063a
+#define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x063b
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x063c
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x063d
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x063e
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x063f
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0640
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0641
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0642
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0643
+#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ0_DC_VM_CONTEXT0_CNTL 0x0644
+#define mmHUBPREQ0_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0645
+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
+#define mmHUBPREQ0_BLANK_OFFSET_0 0x0646
+#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
+#define mmHUBPREQ0_BLANK_OFFSET_1 0x0647
+#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
+#define mmHUBPREQ0_DST_DIMENSIONS 0x0648
+#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
+#define mmHUBPREQ0_DST_AFTER_SCALER 0x0649
+#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
+#define mmHUBPREQ0_PREFETCH_SETTINGS 0x064a
+#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x064b
+#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064c
+#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064d
+#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064e
+#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064f
+#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x0650
+#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x0651
+#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0652
+#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0653
+#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0654
+#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0655
+#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0656
+#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0657
+#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0658
+#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0659
+#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
+#define mmHUBPREQ0_NOM_PARAMETERS_6 0x065a
+#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
+#define mmHUBPREQ0_NOM_PARAMETERS_7 0x065b
+#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065c
+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
+#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065d
+#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
+#define mmHUBPREQ0_CURSOR_SETTINGS 0x065e
+#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065f
+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x0660
+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x0661
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0662
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+// base address: 0x0
+#define mmHUBPRET0_HUBPRET_CONTROL 0x066c
+#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d
+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e
+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
+#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671
+#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
+#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672
+#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
+#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673
+#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674
+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675
+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+// base address: 0x0
+#define mmCURSOR0_0_CURSOR_CONTROL 0x0678
+#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_0_CURSOR_SIZE 0x067b
+#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2
+#define mmCURSOR0_0_CURSOR_POSITION 0x067c
+#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2
+#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d
+#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2
+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e
+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2
+#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f
+#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2
+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680
+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681
+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682
+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683
+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2
+#define mmCURSOR0_0_DMDATA_CNTL 0x0684
+#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2
+#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685
+#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2
+#define mmCURSOR0_0_DMDATA_STATUS 0x0686
+#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2
+#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687
+#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2
+#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688
+#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1a74
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x069d
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x069f
+#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_CNTL 0x06a0
+#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_CNTL2 0x06a1
+#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_HI 0x06a4
+#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON7_PERFMON_LOW 0x06a5
+#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpxfc_dispdec
+// base address: 0x0
+#define mmHUBPXFC0_HUBP_XFC_CNTL 0x06a9
+#define mmHUBPXFC0_HUBP_XFC_CNTL_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x06aa
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x06ab
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x06ac
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x06ad
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_PITCH 0x06ae
+#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG0 0x06af
+#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG1 0x06b0
+#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG2 0x06b1
+#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS 0x06b2
+#define mmHUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0 0x06b3
+#define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1 0x06b4
+#define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0 0x06b5
+#define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1 0x06b6
+#define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC0_HUBP_XFC_MPC_CONFIG 0x06b7
+#define mmHUBPXFC0_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+// base address: 0x370
+#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1
+#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
+#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2
+#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
+#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3
+#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
+#define mmHUBP1_DCHUBP_CNTL 0x06cf
+#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
+#define mmHUBP1_HUBP_CLK_CNTL 0x06d0
+#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
+#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1
+#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
+#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2
+#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
+#define mmHUBP1_HUBPREQ_DEBUG 0x06d3
+#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+// base address: 0x370
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
+#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5
+#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6
+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_QUEUE_CONTROL 0x06f9
+#define mmHUBPREQ1_DCSURF_QUEUE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0x06fa
+#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
+#define mmHUBPREQ1_SURFACE_CURRENT_PACING_COUNTER 0x06fb
+#define mmHUBPREQ1_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc
+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0708
+#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
+#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0709
+#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x070a
+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x070b
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x070c
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070d
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070e
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070f
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0710
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x0711
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x0712
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0713
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0714
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0715
+#define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0716
+#define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0717
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0718
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0719
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x071a
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x071b
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x071c
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x071d
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x071e
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x071f
+#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ1_DC_VM_CONTEXT0_CNTL 0x0720
+#define mmHUBPREQ1_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0721
+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
+#define mmHUBPREQ1_BLANK_OFFSET_0 0x0722
+#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
+#define mmHUBPREQ1_BLANK_OFFSET_1 0x0723
+#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
+#define mmHUBPREQ1_DST_DIMENSIONS 0x0724
+#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
+#define mmHUBPREQ1_DST_AFTER_SCALER 0x0725
+#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
+#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0726
+#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0727
+#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0728
+#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0729
+#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x072a
+#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x072b
+#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072c
+#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072d
+#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072e
+#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072f
+#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ1_NOM_PARAMETERS_0 0x0730
+#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ1_NOM_PARAMETERS_1 0x0731
+#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0732
+#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0733
+#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0734
+#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0735
+#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
+#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0736
+#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
+#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0737
+#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0738
+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
+#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0739
+#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
+#define mmHUBPREQ1_CURSOR_SETTINGS 0x073a
+#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x073b
+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073c
+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073d
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073e
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+// base address: 0x370
+#define mmHUBPRET1_HUBPRET_CONTROL 0x0748
+#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749
+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a
+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
+#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d
+#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
+#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e
+#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
+#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f
+#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750
+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751
+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+// base address: 0x370
+#define mmCURSOR0_1_CURSOR_CONTROL 0x0754
+#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_1_CURSOR_SIZE 0x0757
+#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2
+#define mmCURSOR0_1_CURSOR_POSITION 0x0758
+#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2
+#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759
+#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2
+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a
+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2
+#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b
+#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2
+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c
+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d
+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e
+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f
+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2
+#define mmCURSOR0_1_DMDATA_CNTL 0x0760
+#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2
+#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761
+#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2
+#define mmCURSOR0_1_DMDATA_STATUS 0x0762
+#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2
+#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763
+#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2
+#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764
+#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1de4
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0779
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x077b
+#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_CNTL 0x077c
+#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_CNTL2 0x077d
+#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_HI 0x0780
+#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON8_PERFMON_LOW 0x0781
+#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpxfc_dispdec
+// base address: 0x370
+#define mmHUBPXFC1_HUBP_XFC_CNTL 0x0785
+#define mmHUBPXFC1_HUBP_XFC_CNTL_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0786
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0787
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0788
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0789
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_PITCH 0x078a
+#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG0 0x078b
+#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG1 0x078c
+#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG2 0x078d
+#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS 0x078e
+#define mmHUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0 0x078f
+#define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1 0x0790
+#define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0 0x0791
+#define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1 0x0792
+#define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC1_HUBP_XFC_MPC_CONFIG 0x0793
+#define mmHUBPXFC1_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+// base address: 0x6e0
+#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d
+#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
+#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e
+#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
+#define mmHUBP2_DCSURF_TILING_CONFIG 0x079f
+#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9
+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa
+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
+#define mmHUBP2_DCHUBP_CNTL 0x07ab
+#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2
+#define mmHUBP2_HUBP_CLK_CNTL 0x07ac
+#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
+#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x07ad
+#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2
+#define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae
+#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
+#define mmHUBP2_HUBPREQ_DEBUG 0x07af
+#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3
+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4
+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+// base address: 0x6e0
+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf
+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0
+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
+#define mmHUBPREQ2_VMID_SETTINGS_0 0x07c1
+#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2
+#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3
+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4
+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_QUEUE_CONTROL 0x07d5
+#define mmHUBPREQ2_DCSURF_QUEUE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0x07d6
+#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
+#define mmHUBPREQ2_SURFACE_CURRENT_PACING_COUNTER 0x07d7
+#define mmHUBPREQ2_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8
+#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e4
+#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
+#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e5
+#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
+#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e6
+#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e7
+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e8
+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e9
+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07ea
+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07eb
+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07ec
+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ed
+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ee
+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ef
+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07f0
+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x07f1
+#define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x07f2
+#define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x07f3
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x07f4
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x07f5
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x07f6
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x07f7
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x07f8
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x07f9
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x07fa
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x07fb
+#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ2_DC_VM_CONTEXT0_CNTL 0x07fc
+#define mmHUBPREQ2_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
+#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fd
+#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
+#define mmHUBPREQ2_BLANK_OFFSET_0 0x07fe
+#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
+#define mmHUBPREQ2_BLANK_OFFSET_1 0x07ff
+#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
+#define mmHUBPREQ2_DST_DIMENSIONS 0x0800
+#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
+#define mmHUBPREQ2_DST_AFTER_SCALER 0x0801
+#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
+#define mmHUBPREQ2_PREFETCH_SETTINGS 0x0802
+#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0803
+#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0804
+#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0805
+#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0806
+#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0807
+#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0808
+#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0809
+#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ2_FLIP_PARAMETERS_1 0x080a
+#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ2_FLIP_PARAMETERS_2 0x080b
+#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ2_NOM_PARAMETERS_0 0x080c
+#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ2_NOM_PARAMETERS_1 0x080d
+#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ2_NOM_PARAMETERS_2 0x080e
+#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ2_NOM_PARAMETERS_3 0x080f
+#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ2_NOM_PARAMETERS_4 0x0810
+#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ2_NOM_PARAMETERS_5 0x0811
+#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
+#define mmHUBPREQ2_NOM_PARAMETERS_6 0x0812
+#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
+#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0813
+#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
+#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0814
+#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
+#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0815
+#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
+#define mmHUBPREQ2_CURSOR_SETTINGS 0x0816
+#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0817
+#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
+#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0818
+#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0819
+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x081a
+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+// base address: 0x6e0
+#define mmHUBPRET2_HUBPRET_CONTROL 0x0824
+#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
+#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825
+#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826
+#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827
+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828
+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
+#define mmHUBPRET2_HUBPRET_READ_LINE0 0x0829
+#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
+#define mmHUBPRET2_HUBPRET_READ_LINE1 0x082a
+#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
+#define mmHUBPRET2_HUBPRET_INTERRUPT 0x082b
+#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
+#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c
+#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
+#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d
+#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+// base address: 0x6e0
+#define mmCURSOR0_2_CURSOR_CONTROL 0x0830
+#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2
+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831
+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832
+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_2_CURSOR_SIZE 0x0833
+#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2
+#define mmCURSOR0_2_CURSOR_POSITION 0x0834
+#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2
+#define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835
+#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2
+#define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836
+#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2
+#define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837
+#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2
+#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838
+#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839
+#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a
+#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b
+#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2
+#define mmCURSOR0_2_DMDATA_CNTL 0x083c
+#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2
+#define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d
+#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2
+#define mmCURSOR0_2_DMDATA_STATUS 0x083e
+#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2
+#define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f
+#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2
+#define mmCURSOR0_2_DMDATA_SW_DATA 0x0840
+#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2154
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0855
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0857
+#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_CNTL 0x0858
+#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_CNTL2 0x0859
+#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_HI 0x085c
+#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON9_PERFMON_LOW 0x085d
+#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpxfc_dispdec
+// base address: 0x6e0
+#define mmHUBPXFC2_HUBP_XFC_CNTL 0x0861
+#define mmHUBPXFC2_HUBP_XFC_CNTL_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0862
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0863
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0864
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0865
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_PITCH 0x0866
+#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG0 0x0867
+#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG1 0x0868
+#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG2 0x0869
+#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS 0x086a
+#define mmHUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0 0x086b
+#define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1 0x086c
+#define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0 0x086d
+#define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1 0x086e
+#define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC2_HUBP_XFC_MPC_CONFIG 0x086f
+#define mmHUBPXFC2_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+// base address: 0xa50
+#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879
+#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
+#define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a
+#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
+#define mmHUBP3_DCSURF_TILING_CONFIG 0x087b
+#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885
+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886
+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
+#define mmHUBP3_DCHUBP_CNTL 0x0887
+#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2
+#define mmHUBP3_HUBP_CLK_CNTL 0x0888
+#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
+#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x0889
+#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2
+#define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a
+#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
+#define mmHUBP3_HUBPREQ_DEBUG 0x088b
+#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f
+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890
+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+// base address: 0xa50
+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b
+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c
+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
+#define mmHUBPREQ3_VMID_SETTINGS_0 0x089d
+#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae
+#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af
+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0
+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_QUEUE_CONTROL 0x08b1
+#define mmHUBPREQ3_DCSURF_QUEUE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0x08b2
+#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
+#define mmHUBPREQ3_SURFACE_CURRENT_PACING_COUNTER 0x08b3
+#define mmHUBPREQ3_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4
+#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08c0
+#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
+#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08c1
+#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
+#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08c2
+#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c3
+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c4
+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c5
+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c6
+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c7
+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c8
+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c9
+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08ca
+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08cb
+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08cc
+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08cd
+#define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08ce
+#define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x08cf
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x08d0
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x08d1
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x08d2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x08d3
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x08d4
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x08d5
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x08d6
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x08d7
+#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ3_DC_VM_CONTEXT0_CNTL 0x08d8
+#define mmHUBPREQ3_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
+#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d9
+#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
+#define mmHUBPREQ3_BLANK_OFFSET_0 0x08da
+#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
+#define mmHUBPREQ3_BLANK_OFFSET_1 0x08db
+#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
+#define mmHUBPREQ3_DST_DIMENSIONS 0x08dc
+#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
+#define mmHUBPREQ3_DST_AFTER_SCALER 0x08dd
+#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
+#define mmHUBPREQ3_PREFETCH_SETTINGS 0x08de
+#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08df
+#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08e0
+#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08e1
+#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e3
+#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e4
+#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e5
+#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ3_FLIP_PARAMETERS_1 0x08e6
+#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e7
+#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ3_NOM_PARAMETERS_0 0x08e8
+#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ3_NOM_PARAMETERS_1 0x08e9
+#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ3_NOM_PARAMETERS_2 0x08ea
+#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ3_NOM_PARAMETERS_3 0x08eb
+#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ec
+#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ3_NOM_PARAMETERS_5 0x08ed
+#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
+#define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ee
+#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
+#define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ef
+#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
+#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08f0
+#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
+#define mmHUBPREQ3_PER_LINE_DELIVERY 0x08f1
+#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
+#define mmHUBPREQ3_CURSOR_SETTINGS 0x08f2
+#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f3
+#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
+#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f4
+#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f5
+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f6
+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+// base address: 0xa50
+#define mmHUBPRET3_HUBPRET_CONTROL 0x0900
+#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
+#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901
+#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902
+#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903
+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904
+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
+#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0905
+#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
+#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0906
+#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
+#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0907
+#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
+#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908
+#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
+#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909
+#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+// base address: 0xa50
+#define mmCURSOR0_3_CURSOR_CONTROL 0x090c
+#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2
+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d
+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e
+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_3_CURSOR_SIZE 0x090f
+#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2
+#define mmCURSOR0_3_CURSOR_POSITION 0x0910
+#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2
+#define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911
+#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2
+#define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912
+#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2
+#define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913
+#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2
+#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914
+#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915
+#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916
+#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917
+#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2
+#define mmCURSOR0_3_DMDATA_CNTL 0x0918
+#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2
+#define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919
+#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2
+#define mmCURSOR0_3_DMDATA_STATUS 0x091a
+#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2
+#define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b
+#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2
+#define mmCURSOR0_3_DMDATA_SW_DATA 0x091c
+#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x24c4
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0931
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x0933
+#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_CNTL 0x0934
+#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_CNTL2 0x0935
+#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_HI 0x0938
+#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON10_PERFMON_LOW 0x0939
+#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpxfc_dispdec
+// base address: 0xa50
+#define mmHUBPXFC3_HUBP_XFC_CNTL 0x093d
+#define mmHUBPXFC3_HUBP_XFC_CNTL_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x093e
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x093f
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0940
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0941
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_PITCH 0x0942
+#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG0 0x0943
+#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG1 0x0944
+#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG2 0x0945
+#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS 0x0946
+#define mmHUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0 0x0947
+#define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1 0x0948
+#define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0 0x0949
+#define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1 0x094a
+#define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC3_HUBP_XFC_MPC_CONFIG 0x094b
+#define mmHUBPXFC3_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dispdec
+// base address: 0xdc0
+#define mmHUBP4_DCSURF_SURFACE_CONFIG 0x0955
+#define mmHUBP4_DCSURF_SURFACE_CONFIG_BASE_IDX 2
+#define mmHUBP4_DCSURF_ADDR_CONFIG 0x0956
+#define mmHUBP4_DCSURF_ADDR_CONFIG_BASE_IDX 2
+#define mmHUBP4_DCSURF_TILING_CONFIG 0x0957
+#define mmHUBP4_DCSURF_TILING_CONFIG_BASE_IDX 2
+#define mmHUBP4_DCSURF_PRI_VIEWPORT_START 0x0959
+#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION 0x095a
+#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C 0x095b
+#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x095c
+#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP4_DCSURF_SEC_VIEWPORT_START 0x095d
+#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION 0x095e
+#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C 0x095f
+#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0960
+#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG 0x0961
+#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
+#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C 0x0962
+#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
+#define mmHUBP4_DCHUBP_CNTL 0x0963
+#define mmHUBP4_DCHUBP_CNTL_BASE_IDX 2
+#define mmHUBP4_HUBP_CLK_CNTL 0x0964
+#define mmHUBP4_HUBP_CLK_CNTL_BASE_IDX 2
+#define mmHUBP4_DCHUBP_VMPG_CONFIG 0x0965
+#define mmHUBP4_DCHUBP_VMPG_CONFIG_BASE_IDX 2
+#define mmHUBP4_HUBPREQ_DEBUG_DB 0x0966
+#define mmHUBP4_HUBPREQ_DEBUG_DB_BASE_IDX 2
+#define mmHUBP4_HUBPREQ_DEBUG 0x0967
+#define mmHUBP4_HUBPREQ_DEBUG_BASE_IDX 2
+#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x096b
+#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
+#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x096c
+#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubpreq_dispdec
+// base address: 0xdc0
+#define mmHUBPREQ4_DCSURF_SURFACE_PITCH 0x0977
+#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C 0x0978
+#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
+#define mmHUBPREQ4_VMID_SETTINGS_0 0x0979
+#define mmHUBPREQ4_VMID_SETTINGS_0_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS 0x097a
+#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x097b
+#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x097c
+#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x097d
+#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS 0x097e
+#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x097f
+#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0980
+#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0981
+#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0982
+#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0983
+#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0984
+#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0985
+#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0986
+#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0987
+#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0988
+#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0989
+#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL 0x098a
+#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_FLIP_CONTROL 0x098b
+#define mmHUBPREQ4_DCSURF_FLIP_CONTROL_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2 0x098c
+#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_QUEUE_CONTROL 0x098d
+#define mmHUBPREQ4_DCSURF_QUEUE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_FRAME_PACING_TIME 0x098e
+#define mmHUBPREQ4_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
+#define mmHUBPREQ4_SURFACE_CURRENT_PACING_COUNTER 0x098f
+#define mmHUBPREQ4_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT 0x0990
+#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_INUSE 0x0991
+#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH 0x0992
+#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C 0x0993
+#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C 0x0994
+#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE 0x0995
+#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0996
+#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0997
+#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0998
+#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ4_DCN_EXPANSION_MODE 0x099c
+#define mmHUBPREQ4_DCN_EXPANSION_MODE_BASE_IDX 2
+#define mmHUBPREQ4_DCN_TTU_QOS_WM 0x099d
+#define mmHUBPREQ4_DCN_TTU_QOS_WM_BASE_IDX 2
+#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL 0x099e
+#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
+#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0 0x099f
+#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1 0x09a0
+#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0 0x09a1
+#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1 0x09a2
+#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0 0x09a3
+#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1 0x09a4
+#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0 0x09a5
+#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1 0x09a6
+#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x09a7
+#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
+#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x09a8
+#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x09a9
+#define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x09aa
+#define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x09ab
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x09ac
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x09ad
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x09ae
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x09af
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x09b0
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x09b1
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x09b2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x09b3
+#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ4_DC_VM_CONTEXT0_CNTL 0x09b4
+#define mmHUBPREQ4_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
+#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL 0x09b5
+#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
+#define mmHUBPREQ4_BLANK_OFFSET_0 0x09b6
+#define mmHUBPREQ4_BLANK_OFFSET_0_BASE_IDX 2
+#define mmHUBPREQ4_BLANK_OFFSET_1 0x09b7
+#define mmHUBPREQ4_BLANK_OFFSET_1_BASE_IDX 2
+#define mmHUBPREQ4_DST_DIMENSIONS 0x09b8
+#define mmHUBPREQ4_DST_DIMENSIONS_BASE_IDX 2
+#define mmHUBPREQ4_DST_AFTER_SCALER 0x09b9
+#define mmHUBPREQ4_DST_AFTER_SCALER_BASE_IDX 2
+#define mmHUBPREQ4_PREFETCH_SETTINGS 0x09ba
+#define mmHUBPREQ4_PREFETCH_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ4_PREFETCH_SETTINGS_C 0x09bb
+#define mmHUBPREQ4_PREFETCH_SETTINGS_C_BASE_IDX 2
+#define mmHUBPREQ4_VBLANK_PARAMETERS_0 0x09bc
+#define mmHUBPREQ4_VBLANK_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ4_VBLANK_PARAMETERS_1 0x09bd
+#define mmHUBPREQ4_VBLANK_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ4_VBLANK_PARAMETERS_2 0x09be
+#define mmHUBPREQ4_VBLANK_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ4_VBLANK_PARAMETERS_3 0x09bf
+#define mmHUBPREQ4_VBLANK_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ4_VBLANK_PARAMETERS_4 0x09c0
+#define mmHUBPREQ4_VBLANK_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ4_FLIP_PARAMETERS_0 0x09c1
+#define mmHUBPREQ4_FLIP_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ4_FLIP_PARAMETERS_1 0x09c2
+#define mmHUBPREQ4_FLIP_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ4_FLIP_PARAMETERS_2 0x09c3
+#define mmHUBPREQ4_FLIP_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ4_NOM_PARAMETERS_0 0x09c4
+#define mmHUBPREQ4_NOM_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ4_NOM_PARAMETERS_1 0x09c5
+#define mmHUBPREQ4_NOM_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ4_NOM_PARAMETERS_2 0x09c6
+#define mmHUBPREQ4_NOM_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ4_NOM_PARAMETERS_3 0x09c7
+#define mmHUBPREQ4_NOM_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ4_NOM_PARAMETERS_4 0x09c8
+#define mmHUBPREQ4_NOM_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ4_NOM_PARAMETERS_5 0x09c9
+#define mmHUBPREQ4_NOM_PARAMETERS_5_BASE_IDX 2
+#define mmHUBPREQ4_NOM_PARAMETERS_6 0x09ca
+#define mmHUBPREQ4_NOM_PARAMETERS_6_BASE_IDX 2
+#define mmHUBPREQ4_NOM_PARAMETERS_7 0x09cb
+#define mmHUBPREQ4_NOM_PARAMETERS_7_BASE_IDX 2
+#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE 0x09cc
+#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE_BASE_IDX 2
+#define mmHUBPREQ4_PER_LINE_DELIVERY 0x09cd
+#define mmHUBPREQ4_PER_LINE_DELIVERY_BASE_IDX 2
+#define mmHUBPREQ4_CURSOR_SETTINGS 0x09ce
+#define mmHUBPREQ4_CURSOR_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ 0x09cf
+#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
+#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT 0x09d0
+#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
+#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL 0x09d1
+#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS 0x09d2
+#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubpret_dispdec
+// base address: 0xdc0
+#define mmHUBPRET4_HUBPRET_CONTROL 0x09dc
+#define mmHUBPRET4_HUBPRET_CONTROL_BASE_IDX 2
+#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL 0x09dd
+#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS 0x09de
+#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
+#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0 0x09df
+#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
+#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1 0x09e0
+#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
+#define mmHUBPRET4_HUBPRET_READ_LINE0 0x09e1
+#define mmHUBPRET4_HUBPRET_READ_LINE0_BASE_IDX 2
+#define mmHUBPRET4_HUBPRET_READ_LINE1 0x09e2
+#define mmHUBPRET4_HUBPRET_READ_LINE1_BASE_IDX 2
+#define mmHUBPRET4_HUBPRET_INTERRUPT 0x09e3
+#define mmHUBPRET4_HUBPRET_INTERRUPT_BASE_IDX 2
+#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE 0x09e4
+#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
+#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS 0x09e5
+#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_cursor0_dispdec
+// base address: 0xdc0
+#define mmCURSOR0_4_CURSOR_CONTROL 0x09e8
+#define mmCURSOR0_4_CURSOR_CONTROL_BASE_IDX 2
+#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS 0x09e9
+#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH 0x09ea
+#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_4_CURSOR_SIZE 0x09eb
+#define mmCURSOR0_4_CURSOR_SIZE_BASE_IDX 2
+#define mmCURSOR0_4_CURSOR_POSITION 0x09ec
+#define mmCURSOR0_4_CURSOR_POSITION_BASE_IDX 2
+#define mmCURSOR0_4_CURSOR_HOT_SPOT 0x09ed
+#define mmCURSOR0_4_CURSOR_HOT_SPOT_BASE_IDX 2
+#define mmCURSOR0_4_CURSOR_STEREO_CONTROL 0x09ee
+#define mmCURSOR0_4_CURSOR_STEREO_CONTROL_BASE_IDX 2
+#define mmCURSOR0_4_CURSOR_DST_OFFSET 0x09ef
+#define mmCURSOR0_4_CURSOR_DST_OFFSET_BASE_IDX 2
+#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL 0x09f0
+#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS 0x09f1
+#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH 0x09f2
+#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_4_DMDATA_ADDRESS_LOW 0x09f3
+#define mmCURSOR0_4_DMDATA_ADDRESS_LOW_BASE_IDX 2
+#define mmCURSOR0_4_DMDATA_CNTL 0x09f4
+#define mmCURSOR0_4_DMDATA_CNTL_BASE_IDX 2
+#define mmCURSOR0_4_DMDATA_QOS_CNTL 0x09f5
+#define mmCURSOR0_4_DMDATA_QOS_CNTL_BASE_IDX 2
+#define mmCURSOR0_4_DMDATA_STATUS 0x09f6
+#define mmCURSOR0_4_DMDATA_STATUS_BASE_IDX 2
+#define mmCURSOR0_4_DMDATA_SW_CNTL 0x09f7
+#define mmCURSOR0_4_DMDATA_SW_CNTL_BASE_IDX 2
+#define mmCURSOR0_4_DMDATA_SW_DATA 0x09f8
+#define mmCURSOR0_4_DMDATA_SW_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2834
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x0a0d
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x0a0e
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x0a0f
+#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_CNTL 0x0a10
+#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_CNTL2 0x0a11
+#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0a12
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0a13
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_HI 0x0a14
+#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON11_PERFMON_LOW 0x0a15
+#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubpxfc_dispdec
+// base address: 0xdc0
+#define mmHUBPXFC4_HUBP_XFC_CNTL 0x0a19
+#define mmHUBPXFC4_HUBP_XFC_CNTL_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0a1a
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0a1b
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0a1c
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0a1d
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_PITCH 0x0a1e
+#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG0 0x0a1f
+#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG1 0x0a20
+#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG2 0x0a21
+#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS 0x0a22
+#define mmHUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0 0x0a23
+#define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1 0x0a24
+#define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0 0x0a25
+#define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1 0x0a26
+#define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC4_HUBP_XFC_MPC_CONFIG 0x0a27
+#define mmHUBPXFC4_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dispdec
+// base address: 0x1130
+#define mmHUBP5_DCSURF_SURFACE_CONFIG 0x0a31
+#define mmHUBP5_DCSURF_SURFACE_CONFIG_BASE_IDX 2
+#define mmHUBP5_DCSURF_ADDR_CONFIG 0x0a32
+#define mmHUBP5_DCSURF_ADDR_CONFIG_BASE_IDX 2
+#define mmHUBP5_DCSURF_TILING_CONFIG 0x0a33
+#define mmHUBP5_DCSURF_TILING_CONFIG_BASE_IDX 2
+#define mmHUBP5_DCSURF_PRI_VIEWPORT_START 0x0a35
+#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION 0x0a36
+#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C 0x0a37
+#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0a38
+#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP5_DCSURF_SEC_VIEWPORT_START 0x0a39
+#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
+#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION 0x0a3a
+#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
+#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C 0x0a3b
+#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
+#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0a3c
+#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
+#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG 0x0a3d
+#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
+#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C 0x0a3e
+#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
+#define mmHUBP5_DCHUBP_CNTL 0x0a3f
+#define mmHUBP5_DCHUBP_CNTL_BASE_IDX 2
+#define mmHUBP5_HUBP_CLK_CNTL 0x0a40
+#define mmHUBP5_HUBP_CLK_CNTL_BASE_IDX 2
+#define mmHUBP5_DCHUBP_VMPG_CONFIG 0x0a41
+#define mmHUBP5_DCHUBP_VMPG_CONFIG_BASE_IDX 2
+#define mmHUBP5_HUBPREQ_DEBUG_DB 0x0a42
+#define mmHUBP5_HUBPREQ_DEBUG_DB_BASE_IDX 2
+#define mmHUBP5_HUBPREQ_DEBUG 0x0a43
+#define mmHUBP5_HUBPREQ_DEBUG_BASE_IDX 2
+#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0a47
+#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
+#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0a48
+#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubpreq_dispdec
+// base address: 0x1130
+#define mmHUBPREQ5_DCSURF_SURFACE_PITCH 0x0a53
+#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C 0x0a54
+#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
+#define mmHUBPREQ5_VMID_SETTINGS_0 0x0a55
+#define mmHUBPREQ5_VMID_SETTINGS_0_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0a56
+#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0a57
+#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0a58
+#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0a59
+#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0a5a
+#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0a5b
+#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0a5c
+#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0a5d
+#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0a5e
+#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0a5f
+#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0a60
+#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0a61
+#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0a62
+#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0a63
+#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0a64
+#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0a65
+#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL 0x0a66
+#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_FLIP_CONTROL 0x0a67
+#define mmHUBPREQ5_DCSURF_FLIP_CONTROL_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2 0x0a68
+#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_QUEUE_CONTROL 0x0a69
+#define mmHUBPREQ5_DCSURF_QUEUE_CONTROL_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_FRAME_PACING_TIME 0x0a6a
+#define mmHUBPREQ5_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
+#define mmHUBPREQ5_SURFACE_CURRENT_PACING_COUNTER 0x0a6b
+#define mmHUBPREQ5_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT 0x0a6c
+#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_INUSE 0x0a6d
+#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH 0x0a6e
+#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C 0x0a6f
+#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C 0x0a70
+#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE 0x0a71
+#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0a72
+#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0a73
+#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
+#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0a74
+#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
+#define mmHUBPREQ5_DCN_EXPANSION_MODE 0x0a78
+#define mmHUBPREQ5_DCN_EXPANSION_MODE_BASE_IDX 2
+#define mmHUBPREQ5_DCN_TTU_QOS_WM 0x0a79
+#define mmHUBPREQ5_DCN_TTU_QOS_WM_BASE_IDX 2
+#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL 0x0a7a
+#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
+#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0 0x0a7b
+#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1 0x0a7c
+#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0 0x0a7d
+#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1 0x0a7e
+#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0 0x0a7f
+#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1 0x0a80
+#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0 0x0a81
+#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
+#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1 0x0a82
+#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
+#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0a83
+#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
+#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0a84
+#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0a85
+#define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0a86
+#define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0a87
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0a88
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0a89
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0a8a
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0a8b
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0a8c
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0a8d
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0a8e
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0a8f
+#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
+#define mmHUBPREQ5_DC_VM_CONTEXT0_CNTL 0x0a90
+#define mmHUBPREQ5_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
+#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL 0x0a91
+#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
+#define mmHUBPREQ5_BLANK_OFFSET_0 0x0a92
+#define mmHUBPREQ5_BLANK_OFFSET_0_BASE_IDX 2
+#define mmHUBPREQ5_BLANK_OFFSET_1 0x0a93
+#define mmHUBPREQ5_BLANK_OFFSET_1_BASE_IDX 2
+#define mmHUBPREQ5_DST_DIMENSIONS 0x0a94
+#define mmHUBPREQ5_DST_DIMENSIONS_BASE_IDX 2
+#define mmHUBPREQ5_DST_AFTER_SCALER 0x0a95
+#define mmHUBPREQ5_DST_AFTER_SCALER_BASE_IDX 2
+#define mmHUBPREQ5_PREFETCH_SETTINGS 0x0a96
+#define mmHUBPREQ5_PREFETCH_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ5_PREFETCH_SETTINGS_C 0x0a97
+#define mmHUBPREQ5_PREFETCH_SETTINGS_C_BASE_IDX 2
+#define mmHUBPREQ5_VBLANK_PARAMETERS_0 0x0a98
+#define mmHUBPREQ5_VBLANK_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ5_VBLANK_PARAMETERS_1 0x0a99
+#define mmHUBPREQ5_VBLANK_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ5_VBLANK_PARAMETERS_2 0x0a9a
+#define mmHUBPREQ5_VBLANK_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ5_VBLANK_PARAMETERS_3 0x0a9b
+#define mmHUBPREQ5_VBLANK_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ5_VBLANK_PARAMETERS_4 0x0a9c
+#define mmHUBPREQ5_VBLANK_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ5_FLIP_PARAMETERS_0 0x0a9d
+#define mmHUBPREQ5_FLIP_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ5_FLIP_PARAMETERS_1 0x0a9e
+#define mmHUBPREQ5_FLIP_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ5_FLIP_PARAMETERS_2 0x0a9f
+#define mmHUBPREQ5_FLIP_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ5_NOM_PARAMETERS_0 0x0aa0
+#define mmHUBPREQ5_NOM_PARAMETERS_0_BASE_IDX 2
+#define mmHUBPREQ5_NOM_PARAMETERS_1 0x0aa1
+#define mmHUBPREQ5_NOM_PARAMETERS_1_BASE_IDX 2
+#define mmHUBPREQ5_NOM_PARAMETERS_2 0x0aa2
+#define mmHUBPREQ5_NOM_PARAMETERS_2_BASE_IDX 2
+#define mmHUBPREQ5_NOM_PARAMETERS_3 0x0aa3
+#define mmHUBPREQ5_NOM_PARAMETERS_3_BASE_IDX 2
+#define mmHUBPREQ5_NOM_PARAMETERS_4 0x0aa4
+#define mmHUBPREQ5_NOM_PARAMETERS_4_BASE_IDX 2
+#define mmHUBPREQ5_NOM_PARAMETERS_5 0x0aa5
+#define mmHUBPREQ5_NOM_PARAMETERS_5_BASE_IDX 2
+#define mmHUBPREQ5_NOM_PARAMETERS_6 0x0aa6
+#define mmHUBPREQ5_NOM_PARAMETERS_6_BASE_IDX 2
+#define mmHUBPREQ5_NOM_PARAMETERS_7 0x0aa7
+#define mmHUBPREQ5_NOM_PARAMETERS_7_BASE_IDX 2
+#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE 0x0aa8
+#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE_BASE_IDX 2
+#define mmHUBPREQ5_PER_LINE_DELIVERY 0x0aa9
+#define mmHUBPREQ5_PER_LINE_DELIVERY_BASE_IDX 2
+#define mmHUBPREQ5_CURSOR_SETTINGS 0x0aaa
+#define mmHUBPREQ5_CURSOR_SETTINGS_BASE_IDX 2
+#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ 0x0aab
+#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
+#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT 0x0aac
+#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
+#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL 0x0aad
+#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS 0x0aae
+#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubpret_dispdec
+// base address: 0x1130
+#define mmHUBPRET5_HUBPRET_CONTROL 0x0ab8
+#define mmHUBPRET5_HUBPRET_CONTROL_BASE_IDX 2
+#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL 0x0ab9
+#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
+#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS 0x0aba
+#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
+#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0 0x0abb
+#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
+#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1 0x0abc
+#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
+#define mmHUBPRET5_HUBPRET_READ_LINE0 0x0abd
+#define mmHUBPRET5_HUBPRET_READ_LINE0_BASE_IDX 2
+#define mmHUBPRET5_HUBPRET_READ_LINE1 0x0abe
+#define mmHUBPRET5_HUBPRET_READ_LINE1_BASE_IDX 2
+#define mmHUBPRET5_HUBPRET_INTERRUPT 0x0abf
+#define mmHUBPRET5_HUBPRET_INTERRUPT_BASE_IDX 2
+#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE 0x0ac0
+#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
+#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS 0x0ac1
+#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_cursor0_dispdec
+// base address: 0x1130
+#define mmCURSOR0_5_CURSOR_CONTROL 0x0ac4
+#define mmCURSOR0_5_CURSOR_CONTROL_BASE_IDX 2
+#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS 0x0ac5
+#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
+#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH 0x0ac6
+#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_5_CURSOR_SIZE 0x0ac7
+#define mmCURSOR0_5_CURSOR_SIZE_BASE_IDX 2
+#define mmCURSOR0_5_CURSOR_POSITION 0x0ac8
+#define mmCURSOR0_5_CURSOR_POSITION_BASE_IDX 2
+#define mmCURSOR0_5_CURSOR_HOT_SPOT 0x0ac9
+#define mmCURSOR0_5_CURSOR_HOT_SPOT_BASE_IDX 2
+#define mmCURSOR0_5_CURSOR_STEREO_CONTROL 0x0aca
+#define mmCURSOR0_5_CURSOR_STEREO_CONTROL_BASE_IDX 2
+#define mmCURSOR0_5_CURSOR_DST_OFFSET 0x0acb
+#define mmCURSOR0_5_CURSOR_DST_OFFSET_BASE_IDX 2
+#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL 0x0acc
+#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS 0x0acd
+#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH 0x0ace
+#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH_BASE_IDX 2
+#define mmCURSOR0_5_DMDATA_ADDRESS_LOW 0x0acf
+#define mmCURSOR0_5_DMDATA_ADDRESS_LOW_BASE_IDX 2
+#define mmCURSOR0_5_DMDATA_CNTL 0x0ad0
+#define mmCURSOR0_5_DMDATA_CNTL_BASE_IDX 2
+#define mmCURSOR0_5_DMDATA_QOS_CNTL 0x0ad1
+#define mmCURSOR0_5_DMDATA_QOS_CNTL_BASE_IDX 2
+#define mmCURSOR0_5_DMDATA_STATUS 0x0ad2
+#define mmCURSOR0_5_DMDATA_STATUS_BASE_IDX 2
+#define mmCURSOR0_5_DMDATA_SW_CNTL 0x0ad3
+#define mmCURSOR0_5_DMDATA_SW_CNTL_BASE_IDX 2
+#define mmCURSOR0_5_DMDATA_SW_DATA 0x0ad4
+#define mmCURSOR0_5_DMDATA_SW_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2ba4
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0ae9
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0aea
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0aeb
+#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_CNTL 0x0aec
+#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_CNTL2 0x0aed
+#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0aee
+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0aef
+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_HI 0x0af0
+#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON12_PERFMON_LOW 0x0af1
+#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubpxfc_dispdec
+// base address: 0x1130
+#define mmHUBPXFC5_HUBP_XFC_CNTL 0x0af5
+#define mmHUBPXFC5_HUBP_XFC_CNTL_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0af6
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0af7
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0af8
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0af9
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_PITCH 0x0afa
+#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG0 0x0afb
+#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG1 0x0afc
+#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG2 0x0afd
+#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS 0x0afe
+#define mmHUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0 0x0aff
+#define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1 0x0b00
+#define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0 0x0b01
+#define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1 0x0b02
+#define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
+#define mmHUBPXFC5_HUBP_XFC_MPC_CONFIG 0x0b03
+#define mmHUBPXFC5_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+// base address: 0x0
+#define mmDPP_TOP0_DPP_CONTROL 0x0cc5
+#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2
+#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6
+#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
+#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7
+#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
+#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8
+#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
+#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9
+#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
+#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca
+#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+// base address: 0x0
+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf
+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
+#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0
+#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1
+#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3
+#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2
+#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4
+#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2
+#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5
+#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2
+#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6
+#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2
+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7
+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8
+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
+#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9
+#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
+#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda
+#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
+#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb
+#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
+#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd
+#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+// base address: 0x0
+#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0ce0
+#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2
+#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0ce1
+#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2
+#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0ce2
+#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2
+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0ce3
+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+// base address: 0x0
+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cea
+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0ceb
+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmDSCL0_SCL_MODE 0x0cec
+#define mmDSCL0_SCL_MODE_BASE_IDX 2
+#define mmDSCL0_SCL_TAP_CONTROL 0x0ced
+#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmDSCL0_DSCL_CONTROL 0x0cee
+#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2
+#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cef
+#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cf0
+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0cf1
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0cf2
+#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0cf3
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0cf4
+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0cf5
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0cf6
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0cf7
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0cf8
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0cf9
+#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0cfa
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+#define mmDSCL0_SCL_BLACK_OFFSET 0x0cfb
+#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2
+#define mmDSCL0_DSCL_UPDATE 0x0cfc
+#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2
+#define mmDSCL0_DSCL_AUTOCAL 0x0cfd
+#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2
+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0cfe
+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0cff
+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmDSCL0_OTG_H_BLANK 0x0d00
+#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2
+#define mmDSCL0_OTG_V_BLANK 0x0d01
+#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2
+#define mmDSCL0_RECOUT_START 0x0d02
+#define mmDSCL0_RECOUT_START_BASE_IDX 2
+#define mmDSCL0_RECOUT_SIZE 0x0d03
+#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2
+#define mmDSCL0_MPC_SIZE 0x0d04
+#define mmDSCL0_MPC_SIZE_BASE_IDX 2
+#define mmDSCL0_LB_DATA_FORMAT 0x0d05
+#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2
+#define mmDSCL0_LB_MEMORY_CTRL 0x0d06
+#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmDSCL0_LB_V_COUNTER 0x0d07
+#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2
+#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d08
+#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d09
+#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDSCL0_OBUF_CONTROL 0x0d0a
+#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2
+#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d0b
+#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+// base address: 0x0
+#define mmCM0_CM_CONTROL 0x0d1a
+#define mmCM0_CM_CONTROL_BASE_IDX 2
+#define mmCM0_CM_ICSC_CONTROL 0x0d1b
+#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2
+#define mmCM0_CM_ICSC_C11_C12 0x0d1c
+#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2
+#define mmCM0_CM_ICSC_C13_C14 0x0d1d
+#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2
+#define mmCM0_CM_ICSC_C21_C22 0x0d1e
+#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2
+#define mmCM0_CM_ICSC_C23_C24 0x0d1f
+#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2
+#define mmCM0_CM_ICSC_C31_C32 0x0d20
+#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2
+#define mmCM0_CM_ICSC_C33_C34 0x0d21
+#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2
+#define mmCM0_CM_ICSC_B_C11_C12 0x0d22
+#define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX 2
+#define mmCM0_CM_ICSC_B_C13_C14 0x0d23
+#define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX 2
+#define mmCM0_CM_ICSC_B_C21_C22 0x0d24
+#define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX 2
+#define mmCM0_CM_ICSC_B_C23_C24 0x0d25
+#define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX 2
+#define mmCM0_CM_ICSC_B_C31_C32 0x0d26
+#define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX 2
+#define mmCM0_CM_ICSC_B_C33_C34 0x0d27
+#define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d28
+#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d29
+#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d2a
+#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d2b
+#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d2c
+#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d2d
+#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d2e
+#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d2f
+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d30
+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d31
+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d32
+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d33
+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d34
+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
+#define mmCM0_CM_BIAS_CR_R 0x0d35
+#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2
+#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d36
+#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2
+#define mmCM0_CM_DGAM_CONTROL 0x0d37
+#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2
+#define mmCM0_CM_DGAM_LUT_INDEX 0x0d38
+#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM0_CM_DGAM_LUT_DATA 0x0d39
+#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2
+#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0d3a
+#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0d3b
+#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0d3c
+#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0d3d
+#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0d3e
+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0d3f
+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0d40
+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0d41
+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0d42
+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0d43
+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0d44
+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0d45
+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0d46
+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0d47
+#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0d48
+#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0d49
+#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0d4a
+#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0d4b
+#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0d4c
+#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0d4d
+#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0d4e
+#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0d4f
+#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0d50
+#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0d51
+#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0d52
+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0d53
+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0d54
+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0d55
+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0d56
+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0d57
+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0d58
+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0d59
+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0d5a
+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0d5b
+#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0d5c
+#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0d5d
+#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0d5e
+#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0d5f
+#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0d60
+#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0d61
+#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0d62
+#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_CONTROL 0x0d63
+#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d64
+#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d65
+#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0d66
+#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d67
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d68
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d69
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0d6a
+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0d6b
+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0d6c
+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d6d
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d6e
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d6f
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d70
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d71
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d72
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d73
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d74
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d75
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0d76
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0d77
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0d78
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0d79
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0d7a
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0d7b
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0d7c
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0d7d
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0d7e
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0d7f
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0d80
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0d81
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0d82
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0d83
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0d84
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0d85
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0d86
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0d87
+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0d88
+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0d89
+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0d8a
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0d8b
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0d8c
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0d8d
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0d8e
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0d8f
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0d90
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0d91
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0d92
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0d93
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0d94
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0d95
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0d96
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0d97
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0d98
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0d99
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0d9a
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0d9b
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0d9c
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0d9d
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0d9e
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0d9f
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0da0
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM0_CM_HDR_MULT_COEF 0x0da1
+#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2
+#define mmCM0_CM_MEM_PWR_CTRL 0x0da2
+#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCM0_CM_MEM_PWR_STATUS 0x0da3
+#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCM0_CM_DEALPHA 0x0da5
+#define mmCM0_CM_DEALPHA_BASE_IDX 2
+#define mmCM0_CM_COEF_FORMAT 0x0da6
+#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2
+#define mmCM0_CM_SHAPER_CONTROL 0x0da7
+#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2
+#define mmCM0_CM_SHAPER_OFFSET_R 0x0da8
+#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2
+#define mmCM0_CM_SHAPER_OFFSET_G 0x0da9
+#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2
+#define mmCM0_CM_SHAPER_OFFSET_B 0x0daa
+#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2
+#define mmCM0_CM_SHAPER_SCALE_R 0x0dab
+#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2
+#define mmCM0_CM_SHAPER_SCALE_G_B 0x0dac
+#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2
+#define mmCM0_CM_SHAPER_LUT_INDEX 0x0dad
+#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2
+#define mmCM0_CM_SHAPER_LUT_DATA 0x0dae
+#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2
+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0daf
+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0db0
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0db1
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0db2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0db3
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0db4
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0db5
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0db6
+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0db7
+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0db8
+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0db9
+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dba
+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0dbb
+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dbc
+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0dbd
+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dbe
+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0dbf
+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0dc0
+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0dc1
+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0dc2
+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0dc3
+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0dc4
+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0dc5
+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0dc6
+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0dc7
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0dc8
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0dc9
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dca
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dcb
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dcc
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dcd
+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dce
+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dcf
+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0dd0
+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0dd1
+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0dd2
+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0dd3
+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0dd4
+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0dd5
+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0dd6
+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0dd7
+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0dd8
+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0dd9
+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0dda
+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0ddb
+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0ddc
+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0ddd
+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM0_CM_MEM_PWR_CTRL2 0x0dde
+#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmCM0_CM_MEM_PWR_STATUS2 0x0ddf
+#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2
+#define mmCM0_CM_3DLUT_MODE 0x0de0
+#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2
+#define mmCM0_CM_3DLUT_INDEX 0x0de1
+#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2
+#define mmCM0_CM_3DLUT_DATA 0x0de2
+#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2
+#define mmCM0_CM_3DLUT_DATA_30BIT 0x0de3
+#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2
+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0de4
+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0de5
+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
+#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0de6
+#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
+#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0de7
+#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
+#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0de8
+#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
+#define mmCM0_CM_TEST_DEBUG_INDEX 0x0de9
+#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM0_CM_TEST_DEBUG_DATA 0x0dea
+#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3890
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0e24
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0e25
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0e26
+#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_CNTL 0x0e27
+#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_CNTL2 0x0e28
+#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0e29
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0e2a
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_HI 0x0e2b
+#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON13_PERFMON_LOW 0x0e2c
+#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+// base address: 0x5ac
+#define mmDPP_TOP1_DPP_CONTROL 0x0e30
+#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2
+#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31
+#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
+#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32
+#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
+#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33
+#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
+#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34
+#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
+#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35
+#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+// base address: 0x5ac
+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a
+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
+#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b
+#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c
+#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2
+#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d
+#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2
+#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e
+#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2
+#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f
+#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2
+#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40
+#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2
+#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41
+#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2
+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42
+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43
+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
+#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44
+#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
+#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45
+#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
+#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46
+#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
+#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48
+#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+// base address: 0x5ac
+#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e4b
+#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2
+#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e4c
+#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2
+#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e4d
+#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2
+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e4e
+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+// base address: 0x5ac
+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e55
+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e56
+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmDSCL1_SCL_MODE 0x0e57
+#define mmDSCL1_SCL_MODE_BASE_IDX 2
+#define mmDSCL1_SCL_TAP_CONTROL 0x0e58
+#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmDSCL1_DSCL_CONTROL 0x0e59
+#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2
+#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e5a
+#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e5b
+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e5c
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e5d
+#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e5e
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e5f
+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e60
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e61
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e62
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e63
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e64
+#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e65
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+#define mmDSCL1_SCL_BLACK_OFFSET 0x0e66
+#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2
+#define mmDSCL1_DSCL_UPDATE 0x0e67
+#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2
+#define mmDSCL1_DSCL_AUTOCAL 0x0e68
+#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2
+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e69
+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e6a
+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmDSCL1_OTG_H_BLANK 0x0e6b
+#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2
+#define mmDSCL1_OTG_V_BLANK 0x0e6c
+#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2
+#define mmDSCL1_RECOUT_START 0x0e6d
+#define mmDSCL1_RECOUT_START_BASE_IDX 2
+#define mmDSCL1_RECOUT_SIZE 0x0e6e
+#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2
+#define mmDSCL1_MPC_SIZE 0x0e6f
+#define mmDSCL1_MPC_SIZE_BASE_IDX 2
+#define mmDSCL1_LB_DATA_FORMAT 0x0e70
+#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2
+#define mmDSCL1_LB_MEMORY_CTRL 0x0e71
+#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmDSCL1_LB_V_COUNTER 0x0e72
+#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2
+#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e73
+#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e74
+#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDSCL1_OBUF_CONTROL 0x0e75
+#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2
+#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e76
+#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+// base address: 0x5ac
+#define mmCM1_CM_CONTROL 0x0e85
+#define mmCM1_CM_CONTROL_BASE_IDX 2
+#define mmCM1_CM_ICSC_CONTROL 0x0e86
+#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2
+#define mmCM1_CM_ICSC_C11_C12 0x0e87
+#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2
+#define mmCM1_CM_ICSC_C13_C14 0x0e88
+#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2
+#define mmCM1_CM_ICSC_C21_C22 0x0e89
+#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2
+#define mmCM1_CM_ICSC_C23_C24 0x0e8a
+#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2
+#define mmCM1_CM_ICSC_C31_C32 0x0e8b
+#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2
+#define mmCM1_CM_ICSC_C33_C34 0x0e8c
+#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2
+#define mmCM1_CM_ICSC_B_C11_C12 0x0e8d
+#define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX 2
+#define mmCM1_CM_ICSC_B_C13_C14 0x0e8e
+#define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX 2
+#define mmCM1_CM_ICSC_B_C21_C22 0x0e8f
+#define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX 2
+#define mmCM1_CM_ICSC_B_C23_C24 0x0e90
+#define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX 2
+#define mmCM1_CM_ICSC_B_C31_C32 0x0e91
+#define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX 2
+#define mmCM1_CM_ICSC_B_C33_C34 0x0e92
+#define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e93
+#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e94
+#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e95
+#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e96
+#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e97
+#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e98
+#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e99
+#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0e9a
+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0e9b
+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0e9c
+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0e9d
+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0e9e
+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0e9f
+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
+#define mmCM1_CM_BIAS_CR_R 0x0ea0
+#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2
+#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea1
+#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2
+#define mmCM1_CM_DGAM_CONTROL 0x0ea2
+#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2
+#define mmCM1_CM_DGAM_LUT_INDEX 0x0ea3
+#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM1_CM_DGAM_LUT_DATA 0x0ea4
+#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2
+#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ea5
+#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0ea6
+#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0ea7
+#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0ea8
+#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0ea9
+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eaa
+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab
+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0eac
+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0ead
+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0eae
+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0eaf
+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0eb0
+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0eb1
+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0eb2
+#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0eb3
+#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0eb4
+#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0eb5
+#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0eb6
+#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0eb7
+#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0eb8
+#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0eb9
+#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0eba
+#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0ebb
+#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0ebc
+#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0ebd
+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0ebe
+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0ebf
+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0ec0
+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0ec1
+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0ec2
+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0ec3
+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0ec4
+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0ec5
+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0ec6
+#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0ec7
+#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0ec8
+#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0ec9
+#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0eca
+#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0ecb
+#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0ecc
+#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0ecd
+#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_CONTROL 0x0ece
+#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ecf
+#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ed0
+#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0ed1
+#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ed2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ed3
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ed4
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0ed5
+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0ed6
+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0ed7
+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0ed8
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0ed9
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0eda
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0edb
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0edc
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0edd
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0ede
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0edf
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0ee0
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0ee1
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0ee2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0ee3
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0ee4
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0ee5
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0ee6
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0ee7
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0ee8
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0ee9
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0eea
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0eeb
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0eec
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0eed
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0eee
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0eef
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0ef0
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0ef1
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0ef2
+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0ef3
+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0ef4
+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0ef5
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0ef6
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0ef7
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0ef8
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0ef9
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0efa
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0efb
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0efc
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0efd
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0efe
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0eff
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f00
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f01
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f02
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f03
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f04
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f05
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f06
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f07
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f08
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f09
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f0a
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f0b
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM1_CM_HDR_MULT_COEF 0x0f0c
+#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2
+#define mmCM1_CM_MEM_PWR_CTRL 0x0f0d
+#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCM1_CM_MEM_PWR_STATUS 0x0f0e
+#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCM1_CM_DEALPHA 0x0f10
+#define mmCM1_CM_DEALPHA_BASE_IDX 2
+#define mmCM1_CM_COEF_FORMAT 0x0f11
+#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2
+#define mmCM1_CM_SHAPER_CONTROL 0x0f12
+#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2
+#define mmCM1_CM_SHAPER_OFFSET_R 0x0f13
+#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2
+#define mmCM1_CM_SHAPER_OFFSET_G 0x0f14
+#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2
+#define mmCM1_CM_SHAPER_OFFSET_B 0x0f15
+#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2
+#define mmCM1_CM_SHAPER_SCALE_R 0x0f16
+#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2
+#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f17
+#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2
+#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f18
+#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2
+#define mmCM1_CM_SHAPER_LUT_DATA 0x0f19
+#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2
+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f1a
+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f1b
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f1c
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f1d
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f1e
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f1f
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f20
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f21
+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f22
+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f23
+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f24
+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f25
+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f26
+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f27
+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f28
+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f29
+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f2a
+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f2b
+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f2c
+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f2d
+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f2e
+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f2f
+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f30
+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f31
+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f32
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f33
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f34
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f35
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f36
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f37
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f38
+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f39
+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f3a
+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f3b
+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f3c
+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f3d
+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f3e
+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f3f
+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f40
+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f41
+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f42
+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f43
+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f44
+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f45
+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f46
+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f47
+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f48
+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM1_CM_MEM_PWR_CTRL2 0x0f49
+#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmCM1_CM_MEM_PWR_STATUS2 0x0f4a
+#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2
+#define mmCM1_CM_3DLUT_MODE 0x0f4b
+#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2
+#define mmCM1_CM_3DLUT_INDEX 0x0f4c
+#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2
+#define mmCM1_CM_3DLUT_DATA 0x0f4d
+#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2
+#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f4e
+#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2
+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f4f
+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f50
+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
+#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f51
+#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
+#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f52
+#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
+#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f53
+#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
+#define mmCM1_CM_TEST_DEBUG_INDEX 0x0f54
+#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM1_CM_TEST_DEBUG_DATA 0x0f55
+#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3e3c
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x0f8f
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x0f90
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x0f91
+#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON14_PERFMON_CNTL 0x0f92
+#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON14_PERFMON_CNTL2 0x0f93
+#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x0f94
+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x0f95
+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON14_PERFMON_HI 0x0f96
+#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON14_PERFMON_LOW 0x0f97
+#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+// base address: 0xb58
+#define mmDPP_TOP2_DPP_CONTROL 0x0f9b
+#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2
+#define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c
+#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
+#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d
+#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
+#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e
+#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
+#define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f
+#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
+#define mmDPP_TOP2_HOST_READ_CONTROL 0x0fa0
+#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+// base address: 0xb58
+#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5
+#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
+#define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6
+#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7
+#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2
+#define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8
+#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2
+#define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9
+#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2
+#define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa
+#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2
+#define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab
+#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2
+#define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac
+#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2
+#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad
+#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae
+#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
+#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf
+#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
+#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0
+#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
+#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1
+#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
+#define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3
+#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+// base address: 0xb58
+#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fb6
+#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2
+#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fb7
+#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2
+#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fb8
+#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2
+#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fb9
+#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+// base address: 0xb58
+#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fc0
+#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
+#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fc1
+#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmDSCL2_SCL_MODE 0x0fc2
+#define mmDSCL2_SCL_MODE_BASE_IDX 2
+#define mmDSCL2_SCL_TAP_CONTROL 0x0fc3
+#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmDSCL2_DSCL_CONTROL 0x0fc4
+#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2
+#define mmDSCL2_DSCL_2TAP_CONTROL 0x0fc5
+#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
+#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fc6
+#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fc7
+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fc8
+#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fc9
+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fca
+#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fcb
+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fcc
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fcd
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fce
+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fcf
+#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fd0
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+#define mmDSCL2_SCL_BLACK_OFFSET 0x0fd1
+#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2
+#define mmDSCL2_DSCL_UPDATE 0x0fd2
+#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2
+#define mmDSCL2_DSCL_AUTOCAL 0x0fd3
+#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2
+#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fd4
+#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fd5
+#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmDSCL2_OTG_H_BLANK 0x0fd6
+#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2
+#define mmDSCL2_OTG_V_BLANK 0x0fd7
+#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2
+#define mmDSCL2_RECOUT_START 0x0fd8
+#define mmDSCL2_RECOUT_START_BASE_IDX 2
+#define mmDSCL2_RECOUT_SIZE 0x0fd9
+#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2
+#define mmDSCL2_MPC_SIZE 0x0fda
+#define mmDSCL2_MPC_SIZE_BASE_IDX 2
+#define mmDSCL2_LB_DATA_FORMAT 0x0fdb
+#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2
+#define mmDSCL2_LB_MEMORY_CTRL 0x0fdc
+#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmDSCL2_LB_V_COUNTER 0x0fdd
+#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2
+#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fde
+#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fdf
+#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDSCL2_OBUF_CONTROL 0x0fe0
+#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2
+#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0fe1
+#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+// base address: 0xb58
+#define mmCM2_CM_CONTROL 0x0ff0
+#define mmCM2_CM_CONTROL_BASE_IDX 2
+#define mmCM2_CM_ICSC_CONTROL 0x0ff1
+#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2
+#define mmCM2_CM_ICSC_C11_C12 0x0ff2
+#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2
+#define mmCM2_CM_ICSC_C13_C14 0x0ff3
+#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2
+#define mmCM2_CM_ICSC_C21_C22 0x0ff4
+#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2
+#define mmCM2_CM_ICSC_C23_C24 0x0ff5
+#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2
+#define mmCM2_CM_ICSC_C31_C32 0x0ff6
+#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2
+#define mmCM2_CM_ICSC_C33_C34 0x0ff7
+#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2
+#define mmCM2_CM_ICSC_B_C11_C12 0x0ff8
+#define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX 2
+#define mmCM2_CM_ICSC_B_C13_C14 0x0ff9
+#define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX 2
+#define mmCM2_CM_ICSC_B_C21_C22 0x0ffa
+#define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX 2
+#define mmCM2_CM_ICSC_B_C23_C24 0x0ffb
+#define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX 2
+#define mmCM2_CM_ICSC_B_C31_C32 0x0ffc
+#define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX 2
+#define mmCM2_CM_ICSC_B_C33_C34 0x0ffd
+#define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ffe
+#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0fff
+#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1000
+#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1001
+#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1002
+#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1003
+#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x1004
+#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x1005
+#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x1006
+#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x1007
+#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x1008
+#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x1009
+#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
+#define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x100a
+#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
+#define mmCM2_CM_BIAS_CR_R 0x100b
+#define mmCM2_CM_BIAS_CR_R_BASE_IDX 2
+#define mmCM2_CM_BIAS_Y_G_CB_B 0x100c
+#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2
+#define mmCM2_CM_DGAM_CONTROL 0x100d
+#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2
+#define mmCM2_CM_DGAM_LUT_INDEX 0x100e
+#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM2_CM_DGAM_LUT_DATA 0x100f
+#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2
+#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x1010
+#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x1011
+#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x1012
+#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x1013
+#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1014
+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1015
+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1016
+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x1017
+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x1018
+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x1019
+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x101a
+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x101b
+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x101c
+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x101d
+#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x101e
+#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x101f
+#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x1020
+#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x1021
+#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x1022
+#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x1023
+#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x1024
+#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x1025
+#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x1026
+#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x1027
+#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1028
+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1029
+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102a
+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x102b
+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x102c
+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x102d
+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x102e
+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x102f
+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x1030
+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x1031
+#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x1032
+#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x1033
+#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x1034
+#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x1035
+#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x1036
+#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x1037
+#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x1038
+#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_CONTROL 0x1039
+#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_LUT_INDEX 0x103a
+#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_LUT_DATA 0x103b
+#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x103c
+#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x103d
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x103e
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x103f
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x1040
+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x1041
+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x1042
+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1043
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1044
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1045
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1046
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1047
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1048
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1049
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x104a
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x104b
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x104c
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x104d
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x104e
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x104f
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x1050
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x1051
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x1052
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x1053
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x1054
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x1055
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1056
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1057
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1058
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1059
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x105a
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x105b
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x105c
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x105d
+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x105e
+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x105f
+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1060
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1061
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1062
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1063
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1064
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1065
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1066
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1067
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1068
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1069
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x106a
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x106b
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x106c
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x106d
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x106e
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x106f
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x1070
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x1071
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x1072
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x1073
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x1074
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x1075
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x1076
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM2_CM_HDR_MULT_COEF 0x1077
+#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2
+#define mmCM2_CM_MEM_PWR_CTRL 0x1078
+#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCM2_CM_MEM_PWR_STATUS 0x1079
+#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCM2_CM_DEALPHA 0x107b
+#define mmCM2_CM_DEALPHA_BASE_IDX 2
+#define mmCM2_CM_COEF_FORMAT 0x107c
+#define mmCM2_CM_COEF_FORMAT_BASE_IDX 2
+#define mmCM2_CM_SHAPER_CONTROL 0x107d
+#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2
+#define mmCM2_CM_SHAPER_OFFSET_R 0x107e
+#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2
+#define mmCM2_CM_SHAPER_OFFSET_G 0x107f
+#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2
+#define mmCM2_CM_SHAPER_OFFSET_B 0x1080
+#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2
+#define mmCM2_CM_SHAPER_SCALE_R 0x1081
+#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2
+#define mmCM2_CM_SHAPER_SCALE_G_B 0x1082
+#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2
+#define mmCM2_CM_SHAPER_LUT_INDEX 0x1083
+#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2
+#define mmCM2_CM_SHAPER_LUT_DATA 0x1084
+#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2
+#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x1085
+#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x1086
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x1087
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x1088
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x1089
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x108a
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x108b
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x108c
+#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x108d
+#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x108e
+#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x108f
+#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x1090
+#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x1091
+#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x1092
+#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x1093
+#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x1094
+#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x1095
+#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x1096
+#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x1097
+#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x1098
+#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x1099
+#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x109a
+#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x109b
+#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x109c
+#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x109d
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x109e
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x109f
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10a0
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10a1
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10a2
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10a3
+#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10a4
+#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10a5
+#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10a6
+#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10a7
+#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10a8
+#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10a9
+#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10aa
+#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10ab
+#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10ac
+#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10ad
+#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10ae
+#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10af
+#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10b0
+#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10b1
+#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10b2
+#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10b3
+#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM2_CM_MEM_PWR_CTRL2 0x10b4
+#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmCM2_CM_MEM_PWR_STATUS2 0x10b5
+#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2
+#define mmCM2_CM_3DLUT_MODE 0x10b6
+#define mmCM2_CM_3DLUT_MODE_BASE_IDX 2
+#define mmCM2_CM_3DLUT_INDEX 0x10b7
+#define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2
+#define mmCM2_CM_3DLUT_DATA 0x10b8
+#define mmCM2_CM_3DLUT_DATA_BASE_IDX 2
+#define mmCM2_CM_3DLUT_DATA_30BIT 0x10b9
+#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2
+#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ba
+#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
+#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10bb
+#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
+#define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10bc
+#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
+#define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10bd
+#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
+#define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10be
+#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
+#define mmCM2_CM_TEST_DEBUG_INDEX 0x10bf
+#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM2_CM_TEST_DEBUG_DATA 0x10c0
+#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x43e8
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x10fa
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x10fb
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x10fc
+#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON15_PERFMON_CNTL 0x10fd
+#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON15_PERFMON_CNTL2 0x10fe
+#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x10ff
+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x1100
+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON15_PERFMON_HI 0x1101
+#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON15_PERFMON_LOW 0x1102
+#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+// base address: 0x1104
+#define mmDPP_TOP3_DPP_CONTROL 0x1106
+#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2
+#define mmDPP_TOP3_DPP_SOFT_RESET 0x1107
+#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
+#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108
+#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
+#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109
+#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
+#define mmDPP_TOP3_DPP_CRC_CTRL 0x110a
+#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
+#define mmDPP_TOP3_HOST_READ_CONTROL 0x110b
+#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+// base address: 0x1104
+#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110
+#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
+#define mmCNVC_CFG3_FORMAT_CONTROL 0x1111
+#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112
+#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2
+#define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113
+#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2
+#define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114
+#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2
+#define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115
+#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2
+#define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116
+#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2
+#define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117
+#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2
+#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118
+#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119
+#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
+#define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a
+#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
+#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b
+#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
+#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c
+#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
+#define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e
+#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+// base address: 0x1104
+#define mmCNVC_CUR3_CURSOR0_CONTROL 0x1121
+#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2
+#define mmCNVC_CUR3_CURSOR0_COLOR0 0x1122
+#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2
+#define mmCNVC_CUR3_CURSOR0_COLOR1 0x1123
+#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2
+#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1124
+#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+// base address: 0x1104
+#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x112b
+#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
+#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x112c
+#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmDSCL3_SCL_MODE 0x112d
+#define mmDSCL3_SCL_MODE_BASE_IDX 2
+#define mmDSCL3_SCL_TAP_CONTROL 0x112e
+#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmDSCL3_DSCL_CONTROL 0x112f
+#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2
+#define mmDSCL3_DSCL_2TAP_CONTROL 0x1130
+#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
+#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1131
+#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1132
+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1133
+#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1134
+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1135
+#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1136
+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL3_SCL_VERT_FILTER_INIT 0x1137
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1138
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1139
+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x113a
+#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x113b
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+#define mmDSCL3_SCL_BLACK_OFFSET 0x113c
+#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2
+#define mmDSCL3_DSCL_UPDATE 0x113d
+#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2
+#define mmDSCL3_DSCL_AUTOCAL 0x113e
+#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2
+#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x113f
+#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1140
+#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmDSCL3_OTG_H_BLANK 0x1141
+#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2
+#define mmDSCL3_OTG_V_BLANK 0x1142
+#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2
+#define mmDSCL3_RECOUT_START 0x1143
+#define mmDSCL3_RECOUT_START_BASE_IDX 2
+#define mmDSCL3_RECOUT_SIZE 0x1144
+#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2
+#define mmDSCL3_MPC_SIZE 0x1145
+#define mmDSCL3_MPC_SIZE_BASE_IDX 2
+#define mmDSCL3_LB_DATA_FORMAT 0x1146
+#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2
+#define mmDSCL3_LB_MEMORY_CTRL 0x1147
+#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmDSCL3_LB_V_COUNTER 0x1148
+#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2
+#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1149
+#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x114a
+#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDSCL3_OBUF_CONTROL 0x114b
+#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2
+#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x114c
+#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+// base address: 0x1104
+#define mmCM3_CM_CONTROL 0x115b
+#define mmCM3_CM_CONTROL_BASE_IDX 2
+#define mmCM3_CM_ICSC_CONTROL 0x115c
+#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2
+#define mmCM3_CM_ICSC_C11_C12 0x115d
+#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2
+#define mmCM3_CM_ICSC_C13_C14 0x115e
+#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2
+#define mmCM3_CM_ICSC_C21_C22 0x115f
+#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2
+#define mmCM3_CM_ICSC_C23_C24 0x1160
+#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2
+#define mmCM3_CM_ICSC_C31_C32 0x1161
+#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2
+#define mmCM3_CM_ICSC_C33_C34 0x1162
+#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2
+#define mmCM3_CM_ICSC_B_C11_C12 0x1163
+#define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX 2
+#define mmCM3_CM_ICSC_B_C13_C14 0x1164
+#define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX 2
+#define mmCM3_CM_ICSC_B_C21_C22 0x1165
+#define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX 2
+#define mmCM3_CM_ICSC_B_C23_C24 0x1166
+#define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX 2
+#define mmCM3_CM_ICSC_B_C31_C32 0x1167
+#define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX 2
+#define mmCM3_CM_ICSC_B_C33_C34 0x1168
+#define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1169
+#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x116a
+#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x116b
+#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x116c
+#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x116d
+#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x116e
+#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x116f
+#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1170
+#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1171
+#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1172
+#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1173
+#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x1174
+#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
+#define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x1175
+#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
+#define mmCM3_CM_BIAS_CR_R 0x1176
+#define mmCM3_CM_BIAS_CR_R_BASE_IDX 2
+#define mmCM3_CM_BIAS_Y_G_CB_B 0x1177
+#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2
+#define mmCM3_CM_DGAM_CONTROL 0x1178
+#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2
+#define mmCM3_CM_DGAM_LUT_INDEX 0x1179
+#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM3_CM_DGAM_LUT_DATA 0x117a
+#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2
+#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x117b
+#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x117c
+#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x117d
+#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x117e
+#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x117f
+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1180
+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1181
+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x1182
+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x1183
+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x1184
+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x1185
+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1186
+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1187
+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1188
+#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1189
+#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x118a
+#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x118b
+#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x118c
+#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x118d
+#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x118e
+#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x118f
+#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x1190
+#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x1191
+#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x1192
+#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1193
+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1194
+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x1195
+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1196
+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1197
+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1198
+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1199
+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x119a
+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x119b
+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x119c
+#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x119d
+#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x119e
+#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x119f
+#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x11a0
+#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x11a1
+#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x11a2
+#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x11a3
+#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_CONTROL 0x11a4
+#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11a5
+#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_LUT_DATA 0x11a6
+#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x11a7
+#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11a8
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11a9
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11aa
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x11ab
+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x11ac
+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x11ad
+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11ae
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11af
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11b0
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11b1
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11b2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11b3
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11b4
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11b5
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11b6
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11b7
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11b8
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11b9
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11ba
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11bb
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11bc
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11bd
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11be
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11bf
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11c0
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11c1
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11c2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11c3
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11c4
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11c5
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11c6
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11c7
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x11c8
+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x11c9
+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x11ca
+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11cb
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11cc
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11cd
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11ce
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11cf
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11d0
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x11d1
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x11d2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x11d3
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x11d4
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x11d5
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x11d6
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x11d7
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x11d8
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x11d9
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x11da
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x11db
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x11dc
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x11dd
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x11de
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x11df
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x11e0
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x11e1
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM3_CM_HDR_MULT_COEF 0x11e2
+#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2
+#define mmCM3_CM_MEM_PWR_CTRL 0x11e3
+#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCM3_CM_MEM_PWR_STATUS 0x11e4
+#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCM3_CM_DEALPHA 0x11e6
+#define mmCM3_CM_DEALPHA_BASE_IDX 2
+#define mmCM3_CM_COEF_FORMAT 0x11e7
+#define mmCM3_CM_COEF_FORMAT_BASE_IDX 2
+#define mmCM3_CM_SHAPER_CONTROL 0x11e8
+#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2
+#define mmCM3_CM_SHAPER_OFFSET_R 0x11e9
+#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2
+#define mmCM3_CM_SHAPER_OFFSET_G 0x11ea
+#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2
+#define mmCM3_CM_SHAPER_OFFSET_B 0x11eb
+#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2
+#define mmCM3_CM_SHAPER_SCALE_R 0x11ec
+#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2
+#define mmCM3_CM_SHAPER_SCALE_G_B 0x11ed
+#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2
+#define mmCM3_CM_SHAPER_LUT_INDEX 0x11ee
+#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2
+#define mmCM3_CM_SHAPER_LUT_DATA 0x11ef
+#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2
+#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x11f0
+#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x11f1
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x11f2
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x11f3
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x11f4
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x11f5
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x11f6
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x11f7
+#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x11f8
+#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x11f9
+#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x11fa
+#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x11fb
+#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x11fc
+#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x11fd
+#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x11fe
+#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x11ff
+#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1200
+#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1201
+#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1202
+#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1203
+#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1204
+#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1205
+#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1206
+#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1207
+#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1208
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1209
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x120a
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x120b
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x120c
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x120d
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x120e
+#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x120f
+#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1210
+#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1211
+#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1212
+#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1213
+#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1214
+#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1215
+#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1216
+#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1217
+#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1218
+#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1219
+#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x121a
+#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x121b
+#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x121c
+#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x121d
+#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x121e
+#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM3_CM_MEM_PWR_CTRL2 0x121f
+#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmCM3_CM_MEM_PWR_STATUS2 0x1220
+#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2
+#define mmCM3_CM_3DLUT_MODE 0x1221
+#define mmCM3_CM_3DLUT_MODE_BASE_IDX 2
+#define mmCM3_CM_3DLUT_INDEX 0x1222
+#define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2
+#define mmCM3_CM_3DLUT_DATA 0x1223
+#define mmCM3_CM_3DLUT_DATA_BASE_IDX 2
+#define mmCM3_CM_3DLUT_DATA_30BIT 0x1224
+#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2
+#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1225
+#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
+#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1226
+#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
+#define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1227
+#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
+#define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1228
+#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
+#define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1229
+#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
+#define mmCM3_CM_TEST_DEBUG_INDEX 0x122a
+#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM3_CM_TEST_DEBUG_DATA 0x122b
+#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x4994
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x1265
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x1266
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x1267
+#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON16_PERFMON_CNTL 0x1268
+#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON16_PERFMON_CNTL2 0x1269
+#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x126a
+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x126b
+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON16_PERFMON_HI 0x126c
+#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON16_PERFMON_LOW 0x126d
+#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+// base address: 0x0
+#define mmMPCC0_MPCC_TOP_SEL 0x1271
+#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2
+#define mmMPCC0_MPCC_BOT_SEL 0x1272
+#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2
+#define mmMPCC0_MPCC_OPP_ID 0x1273
+#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2
+#define mmMPCC0_MPCC_CONTROL 0x1274
+#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2
+#define mmMPCC0_MPCC_SM_CONTROL 0x1275
+#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2
+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1276
+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
+#define mmMPCC0_MPCC_TOP_GAIN 0x1277
+#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 2
+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x1278
+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x1279
+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
+#define mmMPCC0_MPCC_BG_R_CR 0x127a
+#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2
+#define mmMPCC0_MPCC_BG_G_Y 0x127b
+#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2
+#define mmMPCC0_MPCC_BG_B_CB 0x127c
+#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2
+#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x127d
+#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 2
+#define mmMPCC0_MPCC_STALL_STATUS 0x127e
+#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2
+#define mmMPCC0_MPCC_STATUS 0x127f
+#define mmMPCC0_MPCC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+// base address: 0x6c
+#define mmMPCC1_MPCC_TOP_SEL 0x128c
+#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2
+#define mmMPCC1_MPCC_BOT_SEL 0x128d
+#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2
+#define mmMPCC1_MPCC_OPP_ID 0x128e
+#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2
+#define mmMPCC1_MPCC_CONTROL 0x128f
+#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2
+#define mmMPCC1_MPCC_SM_CONTROL 0x1290
+#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2
+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1291
+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
+#define mmMPCC1_MPCC_TOP_GAIN 0x1292
+#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 2
+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x1293
+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x1294
+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
+#define mmMPCC1_MPCC_BG_R_CR 0x1295
+#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2
+#define mmMPCC1_MPCC_BG_G_Y 0x1296
+#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2
+#define mmMPCC1_MPCC_BG_B_CB 0x1297
+#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2
+#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x1298
+#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 2
+#define mmMPCC1_MPCC_STALL_STATUS 0x1299
+#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2
+#define mmMPCC1_MPCC_STATUS 0x129a
+#define mmMPCC1_MPCC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+// base address: 0xd8
+#define mmMPCC2_MPCC_TOP_SEL 0x12a7
+#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2
+#define mmMPCC2_MPCC_BOT_SEL 0x12a8
+#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2
+#define mmMPCC2_MPCC_OPP_ID 0x12a9
+#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2
+#define mmMPCC2_MPCC_CONTROL 0x12aa
+#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2
+#define mmMPCC2_MPCC_SM_CONTROL 0x12ab
+#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2
+#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x12ac
+#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
+#define mmMPCC2_MPCC_TOP_GAIN 0x12ad
+#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 2
+#define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x12ae
+#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
+#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x12af
+#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
+#define mmMPCC2_MPCC_BG_R_CR 0x12b0
+#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2
+#define mmMPCC2_MPCC_BG_G_Y 0x12b1
+#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2
+#define mmMPCC2_MPCC_BG_B_CB 0x12b2
+#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2
+#define mmMPCC2_MPCC_MEM_PWR_CTRL 0x12b3
+#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 2
+#define mmMPCC2_MPCC_STALL_STATUS 0x12b4
+#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2
+#define mmMPCC2_MPCC_STATUS 0x12b5
+#define mmMPCC2_MPCC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+// base address: 0x144
+#define mmMPCC3_MPCC_TOP_SEL 0x12c2
+#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2
+#define mmMPCC3_MPCC_BOT_SEL 0x12c3
+#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2
+#define mmMPCC3_MPCC_OPP_ID 0x12c4
+#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2
+#define mmMPCC3_MPCC_CONTROL 0x12c5
+#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2
+#define mmMPCC3_MPCC_SM_CONTROL 0x12c6
+#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2
+#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x12c7
+#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
+#define mmMPCC3_MPCC_TOP_GAIN 0x12c8
+#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 2
+#define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x12c9
+#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
+#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x12ca
+#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
+#define mmMPCC3_MPCC_BG_R_CR 0x12cb
+#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2
+#define mmMPCC3_MPCC_BG_G_Y 0x12cc
+#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2
+#define mmMPCC3_MPCC_BG_B_CB 0x12cd
+#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2
+#define mmMPCC3_MPCC_MEM_PWR_CTRL 0x12ce
+#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 2
+#define mmMPCC3_MPCC_STALL_STATUS 0x12cf
+#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2
+#define mmMPCC3_MPCC_STATUS 0x12d0
+#define mmMPCC3_MPCC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc4_dispdec
+// base address: 0x1b0
+#define mmMPCC4_MPCC_TOP_SEL 0x12dd
+#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 2
+#define mmMPCC4_MPCC_BOT_SEL 0x12de
+#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 2
+#define mmMPCC4_MPCC_OPP_ID 0x12df
+#define mmMPCC4_MPCC_OPP_ID_BASE_IDX 2
+#define mmMPCC4_MPCC_CONTROL 0x12e0
+#define mmMPCC4_MPCC_CONTROL_BASE_IDX 2
+#define mmMPCC4_MPCC_SM_CONTROL 0x12e1
+#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 2
+#define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x12e2
+#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
+#define mmMPCC4_MPCC_TOP_GAIN 0x12e3
+#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 2
+#define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x12e4
+#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
+#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x12e5
+#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
+#define mmMPCC4_MPCC_BG_R_CR 0x12e6
+#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 2
+#define mmMPCC4_MPCC_BG_G_Y 0x12e7
+#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 2
+#define mmMPCC4_MPCC_BG_B_CB 0x12e8
+#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 2
+#define mmMPCC4_MPCC_MEM_PWR_CTRL 0x12e9
+#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 2
+#define mmMPCC4_MPCC_STALL_STATUS 0x12ea
+#define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX 2
+#define mmMPCC4_MPCC_STATUS 0x12eb
+#define mmMPCC4_MPCC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc5_dispdec
+// base address: 0x21c
+#define mmMPCC5_MPCC_TOP_SEL 0x12f8
+#define mmMPCC5_MPCC_TOP_SEL_BASE_IDX 2
+#define mmMPCC5_MPCC_BOT_SEL 0x12f9
+#define mmMPCC5_MPCC_BOT_SEL_BASE_IDX 2
+#define mmMPCC5_MPCC_OPP_ID 0x12fa
+#define mmMPCC5_MPCC_OPP_ID_BASE_IDX 2
+#define mmMPCC5_MPCC_CONTROL 0x12fb
+#define mmMPCC5_MPCC_CONTROL_BASE_IDX 2
+#define mmMPCC5_MPCC_SM_CONTROL 0x12fc
+#define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX 2
+#define mmMPCC5_MPCC_UPDATE_LOCK_SEL 0x12fd
+#define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
+#define mmMPCC5_MPCC_TOP_GAIN 0x12fe
+#define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX 2
+#define mmMPCC5_MPCC_BOT_GAIN_INSIDE 0x12ff
+#define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
+#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE 0x1300
+#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
+#define mmMPCC5_MPCC_BG_R_CR 0x1301
+#define mmMPCC5_MPCC_BG_R_CR_BASE_IDX 2
+#define mmMPCC5_MPCC_BG_G_Y 0x1302
+#define mmMPCC5_MPCC_BG_G_Y_BASE_IDX 2
+#define mmMPCC5_MPCC_BG_B_CB 0x1303
+#define mmMPCC5_MPCC_BG_B_CB_BASE_IDX 2
+#define mmMPCC5_MPCC_MEM_PWR_CTRL 0x1304
+#define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX 2
+#define mmMPCC5_MPCC_STALL_STATUS 0x1305
+#define mmMPCC5_MPCC_STALL_STATUS_BASE_IDX 2
+#define mmMPCC5_MPCC_STATUS 0x1306
+#define mmMPCC5_MPCC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc6_dispdec
+// base address: 0x288
+#define mmMPCC6_MPCC_TOP_SEL 0x1313
+#define mmMPCC6_MPCC_TOP_SEL_BASE_IDX 2
+#define mmMPCC6_MPCC_BOT_SEL 0x1314
+#define mmMPCC6_MPCC_BOT_SEL_BASE_IDX 2
+#define mmMPCC6_MPCC_OPP_ID 0x1315
+#define mmMPCC6_MPCC_OPP_ID_BASE_IDX 2
+#define mmMPCC6_MPCC_CONTROL 0x1316
+#define mmMPCC6_MPCC_CONTROL_BASE_IDX 2
+#define mmMPCC6_MPCC_SM_CONTROL 0x1317
+#define mmMPCC6_MPCC_SM_CONTROL_BASE_IDX 2
+#define mmMPCC6_MPCC_UPDATE_LOCK_SEL 0x1318
+#define mmMPCC6_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
+#define mmMPCC6_MPCC_TOP_GAIN 0x1319
+#define mmMPCC6_MPCC_TOP_GAIN_BASE_IDX 2
+#define mmMPCC6_MPCC_BOT_GAIN_INSIDE 0x131a
+#define mmMPCC6_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
+#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE 0x131b
+#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
+#define mmMPCC6_MPCC_BG_R_CR 0x131c
+#define mmMPCC6_MPCC_BG_R_CR_BASE_IDX 2
+#define mmMPCC6_MPCC_BG_G_Y 0x131d
+#define mmMPCC6_MPCC_BG_G_Y_BASE_IDX 2
+#define mmMPCC6_MPCC_BG_B_CB 0x131e
+#define mmMPCC6_MPCC_BG_B_CB_BASE_IDX 2
+#define mmMPCC6_MPCC_MEM_PWR_CTRL 0x131f
+#define mmMPCC6_MPCC_MEM_PWR_CTRL_BASE_IDX 2
+#define mmMPCC6_MPCC_STALL_STATUS 0x1320
+#define mmMPCC6_MPCC_STALL_STATUS_BASE_IDX 2
+#define mmMPCC6_MPCC_STATUS 0x1321
+#define mmMPCC6_MPCC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc7_dispdec
+// base address: 0x2f4
+#define mmMPCC7_MPCC_TOP_SEL 0x132e
+#define mmMPCC7_MPCC_TOP_SEL_BASE_IDX 2
+#define mmMPCC7_MPCC_BOT_SEL 0x132f
+#define mmMPCC7_MPCC_BOT_SEL_BASE_IDX 2
+#define mmMPCC7_MPCC_OPP_ID 0x1330
+#define mmMPCC7_MPCC_OPP_ID_BASE_IDX 2
+#define mmMPCC7_MPCC_CONTROL 0x1331
+#define mmMPCC7_MPCC_CONTROL_BASE_IDX 2
+#define mmMPCC7_MPCC_SM_CONTROL 0x1332
+#define mmMPCC7_MPCC_SM_CONTROL_BASE_IDX 2
+#define mmMPCC7_MPCC_UPDATE_LOCK_SEL 0x1333
+#define mmMPCC7_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
+#define mmMPCC7_MPCC_TOP_GAIN 0x1334
+#define mmMPCC7_MPCC_TOP_GAIN_BASE_IDX 2
+#define mmMPCC7_MPCC_BOT_GAIN_INSIDE 0x1335
+#define mmMPCC7_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
+#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE 0x1336
+#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
+#define mmMPCC7_MPCC_BG_R_CR 0x1337
+#define mmMPCC7_MPCC_BG_R_CR_BASE_IDX 2
+#define mmMPCC7_MPCC_BG_G_Y 0x1338
+#define mmMPCC7_MPCC_BG_G_Y_BASE_IDX 2
+#define mmMPCC7_MPCC_BG_B_CB 0x1339
+#define mmMPCC7_MPCC_BG_B_CB_BASE_IDX 2
+#define mmMPCC7_MPCC_MEM_PWR_CTRL 0x133a
+#define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX 2
+#define mmMPCC7_MPCC_STALL_STATUS 0x133b
+#define mmMPCC7_MPCC_STALL_STATUS_BASE_IDX 2
+#define mmMPCC7_MPCC_STATUS 0x133c
+#define mmMPCC7_MPCC_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+// base address: 0x0
+#define mmMPC_CLOCK_CONTROL 0x1349
+#define mmMPC_CLOCK_CONTROL_BASE_IDX 2
+#define mmMPC_SOFT_RESET 0x134a
+#define mmMPC_SOFT_RESET_BASE_IDX 2
+#define mmMPC_CRC_CTRL 0x134b
+#define mmMPC_CRC_CTRL_BASE_IDX 2
+#define mmMPC_CRC_SEL_CONTROL 0x134c
+#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2
+#define mmMPC_CRC_RESULT_AR 0x134d
+#define mmMPC_CRC_RESULT_AR_BASE_IDX 2
+#define mmMPC_CRC_RESULT_GB 0x134e
+#define mmMPC_CRC_RESULT_GB_BASE_IDX 2
+#define mmMPC_CRC_RESULT_C 0x134f
+#define mmMPC_CRC_RESULT_C_BASE_IDX 2
+#define mmMPC_PERFMON_EVENT_CTRL 0x1352
+#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2
+#define mmMPC_BYPASS_BG_AR 0x1353
+#define mmMPC_BYPASS_BG_AR_BASE_IDX 2
+#define mmMPC_BYPASS_BG_GB 0x1354
+#define mmMPC_BYPASS_BG_GB_BASE_IDX 2
+#define mmMPC_STALL_GRACE_WINDOW 0x1355
+#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2
+#define mmMPC_HOST_READ_CONTROL 0x1356
+#define mmMPC_HOST_READ_CONTROL_BASE_IDX 2
+#define mmMPC_PENDING_TAKEN_STATUS_REG1 0x1357
+#define mmMPC_PENDING_TAKEN_STATUS_REG1_BASE_IDX 2
+#define mmMPC_PENDING_TAKEN_STATUS_REG2 0x1358
+#define mmMPC_PENDING_TAKEN_STATUS_REG2_BASE_IDX 2
+#define mmMPC_PENDING_TAKEN_STATUS_REG3 0x1359
+#define mmMPC_PENDING_TAKEN_STATUS_REG3_BASE_IDX 2
+#define mmMPC_UPDATE_ACK_REG5 0x135b
+#define mmMPC_UPDATE_ACK_REG5_BASE_IDX 2
+#define mmMPC_UPDATE_ACK_REG6 0x135c
+#define mmMPC_UPDATE_ACK_REG6_BASE_IDX 2
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x135d
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 2
+#define mmADR_CFG_VUPDATE_LOCK_SET0 0x135e
+#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2
+#define mmADR_VUPDATE_LOCK_SET0 0x135f
+#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2
+#define mmCFG_VUPDATE_LOCK_SET0 0x1360
+#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 2
+#define mmCUR_VUPDATE_LOCK_SET0 0x1361
+#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 2
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x1362
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 2
+#define mmADR_CFG_VUPDATE_LOCK_SET1 0x1363
+#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2
+#define mmADR_VUPDATE_LOCK_SET1 0x1364
+#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2
+#define mmCFG_VUPDATE_LOCK_SET1 0x1365
+#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 2
+#define mmCUR_VUPDATE_LOCK_SET1 0x1366
+#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 2
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x1367
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 2
+#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1368
+#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2
+#define mmADR_VUPDATE_LOCK_SET2 0x1369
+#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2
+#define mmCFG_VUPDATE_LOCK_SET2 0x136a
+#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 2
+#define mmCUR_VUPDATE_LOCK_SET2 0x136b
+#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 2
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x136c
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 2
+#define mmADR_CFG_VUPDATE_LOCK_SET3 0x136d
+#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2
+#define mmADR_VUPDATE_LOCK_SET3 0x136e
+#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2
+#define mmCFG_VUPDATE_LOCK_SET3 0x136f
+#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 2
+#define mmCUR_VUPDATE_LOCK_SET3 0x1370
+#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 2
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4 0x1371
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4_BASE_IDX 2
+#define mmADR_CFG_VUPDATE_LOCK_SET4 0x1372
+#define mmADR_CFG_VUPDATE_LOCK_SET4_BASE_IDX 2
+#define mmADR_VUPDATE_LOCK_SET4 0x1373
+#define mmADR_VUPDATE_LOCK_SET4_BASE_IDX 2
+#define mmCFG_VUPDATE_LOCK_SET4 0x1374
+#define mmCFG_VUPDATE_LOCK_SET4_BASE_IDX 2
+#define mmCUR_VUPDATE_LOCK_SET4 0x1375
+#define mmCUR_VUPDATE_LOCK_SET4_BASE_IDX 2
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET5 0x1376
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET5_BASE_IDX 2
+#define mmADR_CFG_VUPDATE_LOCK_SET5 0x1377
+#define mmADR_CFG_VUPDATE_LOCK_SET5_BASE_IDX 2
+#define mmADR_VUPDATE_LOCK_SET5 0x1378
+#define mmADR_VUPDATE_LOCK_SET5_BASE_IDX 2
+#define mmCFG_VUPDATE_LOCK_SET5 0x1379
+#define mmCFG_VUPDATE_LOCK_SET5_BASE_IDX 2
+#define mmCUR_VUPDATE_LOCK_SET5 0x137a
+#define mmCUR_VUPDATE_LOCK_SET5_BASE_IDX 2
+#define mmMPC_OUT0_MUX 0x1385
+#define mmMPC_OUT0_MUX_BASE_IDX 2
+#define mmMPC_OUT0_DENORM_CONTROL 0x1386
+#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 2
+#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x1387
+#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 2
+#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x1388
+#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 2
+#define mmMPC_OUT1_MUX 0x1389
+#define mmMPC_OUT1_MUX_BASE_IDX 2
+#define mmMPC_OUT1_DENORM_CONTROL 0x138a
+#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 2
+#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x138b
+#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 2
+#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x138c
+#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 2
+#define mmMPC_OUT2_MUX 0x138d
+#define mmMPC_OUT2_MUX_BASE_IDX 2
+#define mmMPC_OUT2_DENORM_CONTROL 0x138e
+#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX 2
+#define mmMPC_OUT2_DENORM_CLAMP_G_Y 0x138f
+#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 2
+#define mmMPC_OUT2_DENORM_CLAMP_B_CB 0x1390
+#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 2
+#define mmMPC_OUT3_MUX 0x1391
+#define mmMPC_OUT3_MUX_BASE_IDX 2
+#define mmMPC_OUT3_DENORM_CONTROL 0x1392
+#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX 2
+#define mmMPC_OUT3_DENORM_CLAMP_G_Y 0x1393
+#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 2
+#define mmMPC_OUT3_DENORM_CLAMP_B_CB 0x1394
+#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 2
+#define mmMPC_OUT4_MUX 0x1395
+#define mmMPC_OUT4_MUX_BASE_IDX 2
+#define mmMPC_OUT4_DENORM_CONTROL 0x1396
+#define mmMPC_OUT4_DENORM_CONTROL_BASE_IDX 2
+#define mmMPC_OUT4_DENORM_CLAMP_G_Y 0x1397
+#define mmMPC_OUT4_DENORM_CLAMP_G_Y_BASE_IDX 2
+#define mmMPC_OUT4_DENORM_CLAMP_B_CB 0x1398
+#define mmMPC_OUT4_DENORM_CLAMP_B_CB_BASE_IDX 2
+#define mmMPC_OUT5_MUX 0x1399
+#define mmMPC_OUT5_MUX_BASE_IDX 2
+#define mmMPC_OUT5_DENORM_CONTROL 0x139a
+#define mmMPC_OUT5_DENORM_CONTROL_BASE_IDX 2
+#define mmMPC_OUT5_DENORM_CLAMP_G_Y 0x139b
+#define mmMPC_OUT5_DENORM_CLAMP_G_Y_BASE_IDX 2
+#define mmMPC_OUT5_DENORM_CLAMP_B_CB 0x139c
+#define mmMPC_OUT5_DENORM_CLAMP_B_CB_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+// base address: 0x0
+#define mmMPCC_OGAM0_MPCC_OGAM_MODE 0x13ae
+#define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x13af
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x13b0
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL 0x13b1
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x13b2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x13b3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x13b4
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13b5
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13b6
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13b7
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x13b8
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x13b9
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x13ba
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x13bb
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x13bc
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x13bd
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x13be
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x13bf
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x13c0
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x13c1
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x13c2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x13c3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x13c4
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x13c5
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x13c6
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x13c7
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x13c8
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x13c9
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x13ca
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x13cb
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x13cc
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x13cd
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x13ce
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x13cf
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x13d0
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x13d1
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x13d2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x13d3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x13d4
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x13d5
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x13d6
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x13d7
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x13d8
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x13d9
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x13da
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x13db
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x13dc
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x13dd
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x13de
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x13df
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x13e0
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x13e1
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x13e2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x13e3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x13e4
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x13e5
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x13e6
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x13e7
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x13e8
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x13e9
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x13ea
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x13eb
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+// base address: 0x104
+#define mmMPCC_OGAM1_MPCC_OGAM_MODE 0x13ef
+#define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x13f0
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x13f1
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL 0x13f2
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x13f3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x13f4
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x13f5
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13f6
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13f7
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13f8
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x13f9
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x13fa
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x13fb
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x13fc
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x13fd
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x13fe
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x13ff
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x1400
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x1401
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x1402
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x1403
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x1404
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x1405
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x1406
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x1407
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x1408
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x1409
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x140a
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x140b
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x140c
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x140d
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x140e
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x140f
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x1410
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x1411
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x1412
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1413
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1414
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1415
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x1416
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x1417
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x1418
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x1419
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x141a
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x141b
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x141c
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x141d
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x141e
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x141f
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x1420
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x1421
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x1422
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x1423
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x1424
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x1425
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x1426
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x1427
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x1428
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x1429
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x142a
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x142b
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x142c
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+// base address: 0x208
+#define mmMPCC_OGAM2_MPCC_OGAM_MODE 0x1430
+#define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x1431
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x1432
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL 0x1433
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x1434
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x1435
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x1436
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1437
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1438
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x1439
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x143a
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x143b
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x143c
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x143d
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x143e
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x143f
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x1440
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x1441
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x1442
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x1443
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x1444
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x1445
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x1446
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x1447
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x1448
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x1449
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x144a
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x144b
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x144c
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x144d
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x144e
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x144f
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x1450
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x1451
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x1452
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x1453
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1454
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1455
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1456
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x1457
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x1458
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x1459
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x145a
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x145b
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x145c
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x145d
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x145e
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x145f
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x1460
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x1461
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x1462
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x1463
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x1464
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x1465
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x1466
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x1467
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x1468
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x1469
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x146a
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x146b
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x146c
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x146d
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+// base address: 0x30c
+#define mmMPCC_OGAM3_MPCC_OGAM_MODE 0x1471
+#define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x1472
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x1473
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL 0x1474
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x1475
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x1476
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x1477
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1478
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1479
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x147a
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x147b
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x147c
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x147d
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x147e
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x147f
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x1480
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x1481
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x1482
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x1483
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x1484
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x1485
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x1486
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x1487
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x1488
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x1489
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x148a
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x148b
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x148c
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x148d
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x148e
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x148f
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x1490
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x1491
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x1492
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x1493
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x1494
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1495
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1496
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1497
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x1498
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x1499
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x149a
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x149b
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x149c
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x149d
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x149e
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x149f
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x14a0
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x14a1
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x14a2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x14a3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x14a4
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x14a5
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x14a6
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x14a7
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x14a8
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x14a9
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x14aa
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x14ab
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x14ac
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x14ad
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x14ae
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
+// base address: 0x410
+#define mmMPCC_OGAM4_MPCC_OGAM_MODE 0x14b2
+#define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x14b3
+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x14b4
+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL 0x14b5
+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x14b6
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x14b7
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x14b8
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14b9
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14ba
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14bb
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x14bc
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x14bd
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x14be
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x14bf
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x14c0
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x14c1
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x14c2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x14c3
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x14c4
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x14c5
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x14c6
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x14c7
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x14c8
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x14c9
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x14ca
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x14cb
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x14cc
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x14cd
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x14ce
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x14cf
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x14d0
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x14d1
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x14d2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x14d3
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x14d4
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x14d5
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x14d6
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x14d7
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x14d8
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x14d9
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x14da
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x14db
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x14dc
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x14dd
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x14de
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x14df
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x14e0
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x14e1
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x14e2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x14e3
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x14e4
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x14e5
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x14e6
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x14e7
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x14e8
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x14e9
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x14ea
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x14eb
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x14ec
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x14ed
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x14ee
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x14ef
+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec
+// base address: 0x514
+#define mmMPCC_OGAM5_MPCC_OGAM_MODE 0x14f3
+#define mmMPCC_OGAM5_MPCC_OGAM_MODE_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX 0x14f4
+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA 0x14f5
+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL 0x14f6
+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B 0x14f7
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G 0x14f8
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R 0x14f9
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14fa
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14fb
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14fc
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B 0x14fd
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B 0x14fe
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G 0x14ff
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G 0x1500
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R 0x1501
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R 0x1502
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 0x1503
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 0x1504
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 0x1505
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 0x1506
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 0x1507
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 0x1508
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 0x1509
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 0x150a
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 0x150b
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 0x150c
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 0x150d
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 0x150e
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 0x150f
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 0x1510
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 0x1511
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 0x1512
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 0x1513
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B 0x1514
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G 0x1515
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R 0x1516
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1517
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1518
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1519
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B 0x151a
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B 0x151b
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G 0x151c
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G 0x151d
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R 0x151e
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R 0x151f
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 0x1520
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 0x1521
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 0x1522
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 0x1523
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 0x1524
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 0x1525
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 0x1526
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 0x1527
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 0x1528
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 0x1529
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 0x152a
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 0x152b
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 0x152c
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 0x152d
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 0x152e
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 0x152f
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 0x1530
+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec
+// base address: 0x618
+#define mmMPCC_OGAM6_MPCC_OGAM_MODE 0x1534
+#define mmMPCC_OGAM6_MPCC_OGAM_MODE_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX 0x1535
+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA 0x1536
+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL 0x1537
+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B 0x1538
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G 0x1539
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R 0x153a
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x153b
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x153c
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x153d
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B 0x153e
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B 0x153f
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G 0x1540
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G 0x1541
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R 0x1542
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R 0x1543
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1 0x1544
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3 0x1545
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5 0x1546
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7 0x1547
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9 0x1548
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11 0x1549
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13 0x154a
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15 0x154b
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17 0x154c
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19 0x154d
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21 0x154e
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23 0x154f
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25 0x1550
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27 0x1551
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29 0x1552
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31 0x1553
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33 0x1554
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B 0x1555
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G 0x1556
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R 0x1557
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1558
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1559
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x155a
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B 0x155b
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B 0x155c
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G 0x155d
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G 0x155e
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R 0x155f
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R 0x1560
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1 0x1561
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3 0x1562
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5 0x1563
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7 0x1564
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9 0x1565
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11 0x1566
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13 0x1567
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15 0x1568
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17 0x1569
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19 0x156a
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21 0x156b
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23 0x156c
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25 0x156d
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27 0x156e
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29 0x156f
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31 0x1570
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33 0x1571
+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec
+// base address: 0x71c
+#define mmMPCC_OGAM7_MPCC_OGAM_MODE 0x1575
+#define mmMPCC_OGAM7_MPCC_OGAM_MODE_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX 0x1576
+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA 0x1577
+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL 0x1578
+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B 0x1579
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G 0x157a
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R 0x157b
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x157c
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x157d
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x157e
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B 0x157f
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B 0x1580
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G 0x1581
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G 0x1582
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R 0x1583
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R 0x1584
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1 0x1585
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3 0x1586
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5 0x1587
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7 0x1588
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9 0x1589
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11 0x158a
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13 0x158b
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15 0x158c
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17 0x158d
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19 0x158e
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21 0x158f
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23 0x1590
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25 0x1591
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27 0x1592
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29 0x1593
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31 0x1594
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33 0x1595
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B 0x1596
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G 0x1597
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R 0x1598
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1599
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x159a
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x159b
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B 0x159c
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B 0x159d
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G 0x159e
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G 0x159f
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R 0x15a0
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R 0x15a1
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1 0x15a2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3 0x15a3
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5 0x15a4
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7 0x15a5
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9 0x15a6
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11 0x15a7
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13 0x15a8
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15 0x15a9
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17 0x15aa
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19 0x15ab
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21 0x15ac
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23 0x15ad
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25 0x15ae
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27 0x15af
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29 0x15b0
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31 0x15b1
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33 0x15b2
+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+// base address: 0x0
+#define mmMPC_OUT_CSC_COEF_FORMAT 0x15b6
+#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 2
+#define mmMPC_OUT0_CSC_MODE 0x15b7
+#define mmMPC_OUT0_CSC_MODE_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C11_C12_A 0x15b8
+#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C13_C14_A 0x15b9
+#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C21_C22_A 0x15ba
+#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C23_C24_A 0x15bb
+#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C31_C32_A 0x15bc
+#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C33_C34_A 0x15bd
+#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C11_C12_B 0x15be
+#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C13_C14_B 0x15bf
+#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C21_C22_B 0x15c0
+#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C23_C24_B 0x15c1
+#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C31_C32_B 0x15c2
+#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 2
+#define mmMPC_OUT0_CSC_C33_C34_B 0x15c3
+#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 2
+#define mmMPC_OUT1_CSC_MODE 0x15c4
+#define mmMPC_OUT1_CSC_MODE_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C11_C12_A 0x15c5
+#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C13_C14_A 0x15c6
+#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C21_C22_A 0x15c7
+#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C23_C24_A 0x15c8
+#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C31_C32_A 0x15c9
+#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C33_C34_A 0x15ca
+#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C11_C12_B 0x15cb
+#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C13_C14_B 0x15cc
+#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C21_C22_B 0x15cd
+#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C23_C24_B 0x15ce
+#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C31_C32_B 0x15cf
+#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 2
+#define mmMPC_OUT1_CSC_C33_C34_B 0x15d0
+#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 2
+#define mmMPC_OUT2_CSC_MODE 0x15d1
+#define mmMPC_OUT2_CSC_MODE_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C11_C12_A 0x15d2
+#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C13_C14_A 0x15d3
+#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C21_C22_A 0x15d4
+#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C23_C24_A 0x15d5
+#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C31_C32_A 0x15d6
+#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C33_C34_A 0x15d7
+#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C11_C12_B 0x15d8
+#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C13_C14_B 0x15d9
+#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C21_C22_B 0x15da
+#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C23_C24_B 0x15db
+#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C31_C32_B 0x15dc
+#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX 2
+#define mmMPC_OUT2_CSC_C33_C34_B 0x15dd
+#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX 2
+#define mmMPC_OUT3_CSC_MODE 0x15de
+#define mmMPC_OUT3_CSC_MODE_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C11_C12_A 0x15df
+#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C13_C14_A 0x15e0
+#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C21_C22_A 0x15e1
+#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C23_C24_A 0x15e2
+#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C31_C32_A 0x15e3
+#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C33_C34_A 0x15e4
+#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C11_C12_B 0x15e5
+#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C13_C14_B 0x15e6
+#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C21_C22_B 0x15e7
+#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C23_C24_B 0x15e8
+#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C31_C32_B 0x15e9
+#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX 2
+#define mmMPC_OUT3_CSC_C33_C34_B 0x15ea
+#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX 2
+#define mmMPC_OUT4_CSC_MODE 0x15eb
+#define mmMPC_OUT4_CSC_MODE_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C11_C12_A 0x15ec
+#define mmMPC_OUT4_CSC_C11_C12_A_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C13_C14_A 0x15ed
+#define mmMPC_OUT4_CSC_C13_C14_A_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C21_C22_A 0x15ee
+#define mmMPC_OUT4_CSC_C21_C22_A_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C23_C24_A 0x15ef
+#define mmMPC_OUT4_CSC_C23_C24_A_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C31_C32_A 0x15f0
+#define mmMPC_OUT4_CSC_C31_C32_A_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C33_C34_A 0x15f1
+#define mmMPC_OUT4_CSC_C33_C34_A_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C11_C12_B 0x15f2
+#define mmMPC_OUT4_CSC_C11_C12_B_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C13_C14_B 0x15f3
+#define mmMPC_OUT4_CSC_C13_C14_B_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C21_C22_B 0x15f4
+#define mmMPC_OUT4_CSC_C21_C22_B_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C23_C24_B 0x15f5
+#define mmMPC_OUT4_CSC_C23_C24_B_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C31_C32_B 0x15f6
+#define mmMPC_OUT4_CSC_C31_C32_B_BASE_IDX 2
+#define mmMPC_OUT4_CSC_C33_C34_B 0x15f7
+#define mmMPC_OUT4_CSC_C33_C34_B_BASE_IDX 2
+#define mmMPC_OUT5_CSC_MODE 0x15f8
+#define mmMPC_OUT5_CSC_MODE_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C11_C12_A 0x15f9
+#define mmMPC_OUT5_CSC_C11_C12_A_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C13_C14_A 0x15fa
+#define mmMPC_OUT5_CSC_C13_C14_A_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C21_C22_A 0x15fb
+#define mmMPC_OUT5_CSC_C21_C22_A_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C23_C24_A 0x15fc
+#define mmMPC_OUT5_CSC_C23_C24_A_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C31_C32_A 0x15fd
+#define mmMPC_OUT5_CSC_C31_C32_A_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C33_C34_A 0x15fe
+#define mmMPC_OUT5_CSC_C33_C34_A_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C11_C12_B 0x15ff
+#define mmMPC_OUT5_CSC_C11_C12_B_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C13_C14_B 0x1600
+#define mmMPC_OUT5_CSC_C13_C14_B_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C21_C22_B 0x1601
+#define mmMPC_OUT5_CSC_C21_C22_B_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C23_C24_B 0x1602
+#define mmMPC_OUT5_CSC_C23_C24_B_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C31_C32_B 0x1603
+#define mmMPC_OUT5_CSC_C31_C32_B_BASE_IDX 2
+#define mmMPC_OUT5_CSC_C33_C34_B 0x1604
+#define mmMPC_OUT5_CSC_C33_C34_B_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x5964
+#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1659
+#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x165a
+#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x165b
+#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON17_PERFMON_CNTL 0x165c
+#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON17_PERFMON_CNTL2 0x165d
+#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x165e
+#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x165f
+#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON17_PERFMON_HI 0x1660
+#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON17_PERFMON_LOW 0x1661
+#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+// base address: 0x0
+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0
+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
+#define mmBL1_PWM_USER_LEVEL 0x17b1
+#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2
+#define mmBL1_PWM_TARGET_ABM_LEVEL 0x17b2
+#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
+#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x17b3
+#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
+#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x17b4
+#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5
+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
+#define mmBL1_PWM_ABM_CNTL 0x17b6
+#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2
+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7
+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
+#define mmBL1_PWM_GRP2_REG_LOCK 0x17b8
+#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
+#define mmDC_ABM1_CNTL 0x17b9
+#define mmDC_ABM1_CNTL_BASE_IDX 2
+#define mmDC_ABM1_IPCSC_COEFF_SEL 0x17ba
+#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x17be
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
+#define mmDC_ABM1_ACE_THRES_12 0x17c0
+#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2
+#define mmDC_ABM1_ACE_THRES_34 0x17c1
+#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2
+#define mmDC_ABM1_ACE_CNTL_MISC 0x17c2
+#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4
+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
+#define mmDC_ABM1_HG_MISC_CTRL 0x17c5
+#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2
+#define mmDC_ABM1_LS_SUM_OF_LUMA 0x17c6
+#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
+#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x17c7
+#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8
+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
+#define mmDC_ABM1_LS_PIXEL_COUNT 0x17c9
+#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca
+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb
+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc
+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
+#define mmDC_ABM1_HG_SAMPLE_RATE 0x17cd
+#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
+#define mmDC_ABM1_LS_SAMPLE_RATE 0x17ce
+#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf
+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0
+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1
+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2
+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3
+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_1 0x17d4
+#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_2 0x17d5
+#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_3 0x17d6
+#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_4 0x17d7
+#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_5 0x17d8
+#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_6 0x17d9
+#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_7 0x17da
+#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_8 0x17db
+#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_9 0x17dc
+#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_10 0x17dd
+#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_11 0x17de
+#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_12 0x17df
+#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_13 0x17e0
+#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_14 0x17e1
+#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_15 0x17e2
+#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_16 0x17e3
+#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_17 0x17e4
+#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_18 0x17e5
+#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_19 0x17e6
+#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_20 0x17e7
+#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_21 0x17e8
+#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_22 0x17e9
+#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_23 0x17ea
+#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2
+#define mmDC_ABM1_HG_RESULT_24 0x17eb
+#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2
+#define mmDC_ABM1_BL_MASTER_LOCK 0x17ec
+#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+// base address: 0x0
+#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c
+#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d
+#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e
+#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT0_FMT_CONTROL 0x1840
+#define mmFMT0_FMT_CONTROL_BASE_IDX 2
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842
+#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843
+#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844
+#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT0_FMT_CLAMP_CNTL 0x1845
+#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846
+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847
+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
+#define mmFMT0_FMT_422_CONTROL 0x1849
+#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+// base address: 0x0
+#define mmDPG0_DPG_CONTROL 0x1854
+#define mmDPG0_DPG_CONTROL_BASE_IDX 2
+#define mmDPG0_DPG_RAMP_CONTROL 0x1855
+#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2
+#define mmDPG0_DPG_DIMENSIONS 0x1856
+#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2
+#define mmDPG0_DPG_COLOUR_R_CR 0x1857
+#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2
+#define mmDPG0_DPG_COLOUR_G_Y 0x1858
+#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2
+#define mmDPG0_DPG_COLOUR_B_CB 0x1859
+#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2
+#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a
+#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2
+#define mmDPG0_DPG_STATUS 0x185b
+#define mmDPG0_DPG_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+// base address: 0x0
+#define mmOPPBUF0_OPPBUF_CONTROL 0x1884
+#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
+#define mmOPPBUF0_OPPBUF_CONTROL1 0x1889
+#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+// base address: 0x0
+#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
+#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+// base address: 0x0
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+// base address: 0x168
+#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896
+#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897
+#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898
+#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT1_FMT_CONTROL 0x189a
+#define mmFMT1_FMT_CONTROL_BASE_IDX 2
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c
+#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d
+#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e
+#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT1_FMT_CLAMP_CNTL 0x189f
+#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0
+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1
+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
+#define mmFMT1_FMT_422_CONTROL 0x18a3
+#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+// base address: 0x168
+#define mmDPG1_DPG_CONTROL 0x18ae
+#define mmDPG1_DPG_CONTROL_BASE_IDX 2
+#define mmDPG1_DPG_RAMP_CONTROL 0x18af
+#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2
+#define mmDPG1_DPG_DIMENSIONS 0x18b0
+#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2
+#define mmDPG1_DPG_COLOUR_R_CR 0x18b1
+#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2
+#define mmDPG1_DPG_COLOUR_G_Y 0x18b2
+#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2
+#define mmDPG1_DPG_COLOUR_B_CB 0x18b3
+#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2
+#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4
+#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2
+#define mmDPG1_DPG_STATUS 0x18b5
+#define mmDPG1_DPG_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+// base address: 0x168
+#define mmOPPBUF1_OPPBUF_CONTROL 0x18de
+#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
+#define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3
+#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+// base address: 0x168
+#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
+#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+// base address: 0x168
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+// base address: 0x2d0
+#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0
+#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1
+#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2
+#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT2_FMT_CONTROL 0x18f4
+#define mmFMT2_FMT_CONTROL_BASE_IDX 2
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6
+#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7
+#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8
+#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT2_FMT_CLAMP_CNTL 0x18f9
+#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa
+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb
+#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
+#define mmFMT2_FMT_422_CONTROL 0x18fd
+#define mmFMT2_FMT_422_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+// base address: 0x2d0
+#define mmDPG2_DPG_CONTROL 0x1908
+#define mmDPG2_DPG_CONTROL_BASE_IDX 2
+#define mmDPG2_DPG_RAMP_CONTROL 0x1909
+#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX 2
+#define mmDPG2_DPG_DIMENSIONS 0x190a
+#define mmDPG2_DPG_DIMENSIONS_BASE_IDX 2
+#define mmDPG2_DPG_COLOUR_R_CR 0x190b
+#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX 2
+#define mmDPG2_DPG_COLOUR_G_Y 0x190c
+#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX 2
+#define mmDPG2_DPG_COLOUR_B_CB 0x190d
+#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX 2
+#define mmDPG2_DPG_OFFSET_SEGMENT 0x190e
+#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2
+#define mmDPG2_DPG_STATUS 0x190f
+#define mmDPG2_DPG_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+// base address: 0x2d0
+#define mmOPPBUF2_OPPBUF_CONTROL 0x1938
+#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2
+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939
+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a
+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
+#define mmOPPBUF2_OPPBUF_CONTROL1 0x193d
+#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+// base address: 0x2d0
+#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940
+#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+// base address: 0x2d0
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+// base address: 0x438
+#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a
+#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b
+#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c
+#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT3_FMT_CONTROL 0x194e
+#define mmFMT3_FMT_CONTROL_BASE_IDX 2
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950
+#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951
+#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952
+#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT3_FMT_CLAMP_CNTL 0x1953
+#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954
+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955
+#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
+#define mmFMT3_FMT_422_CONTROL 0x1957
+#define mmFMT3_FMT_422_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+// base address: 0x438
+#define mmDPG3_DPG_CONTROL 0x1962
+#define mmDPG3_DPG_CONTROL_BASE_IDX 2
+#define mmDPG3_DPG_RAMP_CONTROL 0x1963
+#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX 2
+#define mmDPG3_DPG_DIMENSIONS 0x1964
+#define mmDPG3_DPG_DIMENSIONS_BASE_IDX 2
+#define mmDPG3_DPG_COLOUR_R_CR 0x1965
+#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX 2
+#define mmDPG3_DPG_COLOUR_G_Y 0x1966
+#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX 2
+#define mmDPG3_DPG_COLOUR_B_CB 0x1967
+#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX 2
+#define mmDPG3_DPG_OFFSET_SEGMENT 0x1968
+#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2
+#define mmDPG3_DPG_STATUS 0x1969
+#define mmDPG3_DPG_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+// base address: 0x438
+#define mmOPPBUF3_OPPBUF_CONTROL 0x1992
+#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2
+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993
+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994
+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
+#define mmOPPBUF3_OPPBUF_CONTROL1 0x1997
+#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+// base address: 0x438
+#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a
+#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+// base address: 0x438
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_fmt4_dispdec
+// base address: 0x5a0
+#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4
+#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5
+#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6
+#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7
+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT4_FMT_CONTROL 0x19a8
+#define mmFMT4_FMT_CONTROL_BASE_IDX 2
+#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9
+#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa
+#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab
+#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac
+#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT4_FMT_CLAMP_CNTL 0x19ad
+#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19ae
+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19af
+#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
+#define mmFMT4_FMT_422_CONTROL 0x19b1
+#define mmFMT4_FMT_422_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dpg4_dispdec
+// base address: 0x5a0
+#define mmDPG4_DPG_CONTROL 0x19bc
+#define mmDPG4_DPG_CONTROL_BASE_IDX 2
+#define mmDPG4_DPG_RAMP_CONTROL 0x19bd
+#define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX 2
+#define mmDPG4_DPG_DIMENSIONS 0x19be
+#define mmDPG4_DPG_DIMENSIONS_BASE_IDX 2
+#define mmDPG4_DPG_COLOUR_R_CR 0x19bf
+#define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX 2
+#define mmDPG4_DPG_COLOUR_G_Y 0x19c0
+#define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX 2
+#define mmDPG4_DPG_COLOUR_B_CB 0x19c1
+#define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX 2
+#define mmDPG4_DPG_OFFSET_SEGMENT 0x19c2
+#define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX 2
+#define mmDPG4_DPG_STATUS 0x19c3
+#define mmDPG4_DPG_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_oppbuf4_dispdec
+// base address: 0x5a0
+#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec
+#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2
+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed
+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee
+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
+#define mmOPPBUF4_OPPBUF_CONTROL1 0x19f1
+#define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe4_dispdec
+// base address: 0x5a0
+#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4
+#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
+// base address: 0x5a0
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd
+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_fmt5_dispdec
+// base address: 0x708
+#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe
+#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
+#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff
+#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
+#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00
+#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01
+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
+#define mmFMT5_FMT_CONTROL 0x1a02
+#define mmFMT5_FMT_CONTROL_BASE_IDX 2
+#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03
+#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
+#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04
+#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
+#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05
+#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
+#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06
+#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
+#define mmFMT5_FMT_CLAMP_CNTL 0x1a07
+#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a08
+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
+#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a09
+#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
+#define mmFMT5_FMT_422_CONTROL 0x1a0b
+#define mmFMT5_FMT_422_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dpg5_dispdec
+// base address: 0x708
+#define mmDPG5_DPG_CONTROL 0x1a16
+#define mmDPG5_DPG_CONTROL_BASE_IDX 2
+#define mmDPG5_DPG_RAMP_CONTROL 0x1a17
+#define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX 2
+#define mmDPG5_DPG_DIMENSIONS 0x1a18
+#define mmDPG5_DPG_DIMENSIONS_BASE_IDX 2
+#define mmDPG5_DPG_COLOUR_R_CR 0x1a19
+#define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX 2
+#define mmDPG5_DPG_COLOUR_G_Y 0x1a1a
+#define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX 2
+#define mmDPG5_DPG_COLOUR_B_CB 0x1a1b
+#define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX 2
+#define mmDPG5_DPG_OFFSET_SEGMENT 0x1a1c
+#define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX 2
+#define mmDPG5_DPG_STATUS 0x1a1d
+#define mmDPG5_DPG_STATUS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_oppbuf5_dispdec
+// base address: 0x708
+#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46
+#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2
+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47
+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48
+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
+#define mmOPPBUF5_OPPBUF_CONTROL1 0x1a4b
+#define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe5_dispdec
+// base address: 0x708
+#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e
+#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
+// base address: 0x708
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57
+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+// base address: 0x0
+#define mmOPP_TOP_CLK_CONTROL 0x1a5e
+#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+// base address: 0x0
+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64
+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+// base address: 0x4
+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65
+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+// base address: 0x8
+#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66
+#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dscrm3_dispdec
+// base address: 0xc
+#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67
+#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dscrm4_dispdec
+// base address: 0x10
+#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG 0x1a68
+#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_dscrm5_dispdec
+// base address: 0x14
+#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG 0x1a69
+#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x6af8
+#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1abe
+#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1abf
+#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1ac0
+#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON18_PERFMON_CNTL 0x1ac1
+#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON18_PERFMON_CNTL2 0x1ac2
+#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1ac3
+#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1ac4
+#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON18_PERFMON_HI 0x1ac5
+#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON18_PERFMON_LOW 0x1ac6
+#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+// base address: 0x0
+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
+#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
+#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
+#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc
+#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
+#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd
+#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace
+#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2
+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf
+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
+#define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0
+#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2
+#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1
+#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+// base address: 0x40
+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
+#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
+#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
+#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc
+#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
+#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add
+#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade
+#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2
+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf
+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
+#define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0
+#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2
+#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1
+#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+// base address: 0x80
+#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea
+#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
+#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb
+#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
+#define mmODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec
+#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
+#define mmODM2_OPTC_BYTES_PER_PIXEL 0x1aed
+#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmODM2_OPTC_WIDTH_CONTROL 0x1aee
+#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2
+#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef
+#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
+#define mmODM2_OPTC_MEMORY_CONFIG 0x1af0
+#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2
+#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1
+#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+// base address: 0xc0
+#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa
+#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
+#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb
+#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
+#define mmODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc
+#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
+#define mmODM3_OPTC_BYTES_PER_PIXEL 0x1afd
+#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmODM3_OPTC_WIDTH_CONTROL 0x1afe
+#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2
+#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff
+#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
+#define mmODM3_OPTC_MEMORY_CONFIG 0x1b00
+#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2
+#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01
+#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_odm4_dispdec
+// base address: 0x100
+#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a
+#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
+#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b
+#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
+#define mmODM4_OPTC_DATA_FORMAT_CONTROL 0x1b0c
+#define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
+#define mmODM4_OPTC_BYTES_PER_PIXEL 0x1b0d
+#define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmODM4_OPTC_WIDTH_CONTROL 0x1b0e
+#define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX 2
+#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0f
+#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
+#define mmODM4_OPTC_MEMORY_CONFIG 0x1b10
+#define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX 2
+#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b11
+#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_odm5_dispdec
+// base address: 0x140
+#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a
+#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
+#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b
+#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
+#define mmODM5_OPTC_DATA_FORMAT_CONTROL 0x1b1c
+#define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
+#define mmODM5_OPTC_BYTES_PER_PIXEL 0x1b1d
+#define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmODM5_OPTC_WIDTH_CONTROL 0x1b1e
+#define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX 2
+#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1f
+#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
+#define mmODM5_OPTC_MEMORY_CONFIG 0x1b20
+#define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX 2
+#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b21
+#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+// base address: 0x0
+#define mmOTG0_OTG_H_TOTAL 0x1b2a
+#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2
+#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b
+#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
+#define mmOTG0_OTG_H_SYNC_A 0x1b2c
+#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2
+#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
+#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e
+#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
+#define mmOTG0_OTG_V_TOTAL 0x1b2f
+#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2
+#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30
+#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
+#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31
+#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
+#define mmOTG0_OTG_V_TOTAL_MID 0x1b32
+#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
+#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33
+#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34
+#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35
+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmOTG0_OTG_V_BLANK_START_END 0x1b36
+#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
+#define mmOTG0_OTG_V_SYNC_A 0x1b37
+#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2
+#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38
+#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG0_OTG_TRIGA_CNTL 0x1b39
+#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a
+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b
+#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c
+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d
+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e
+#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f
+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmOTG0_OTG_CONTROL 0x1b41
+#define mmOTG0_OTG_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_BLANK_CONTROL 0x1b42
+#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43
+#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44
+#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45
+#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
+#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
+#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
+#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmOTG0_OTG_STATUS 0x1b49
+#define mmOTG0_OTG_STATUS_BASE_IDX 2
+#define mmOTG0_OTG_STATUS_POSITION 0x1b4a
+#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2
+#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b
+#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
+#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c
+#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d
+#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
+#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e
+#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
+#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f
+#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_COUNT_RESET 0x1b50
+#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2
+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51
+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52
+#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_STEREO_STATUS 0x1b53
+#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2
+#define mmOTG0_OTG_STEREO_CONTROL 0x1b54
+#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55
+#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56
+#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57
+#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58
+#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59
+#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a
+#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b
+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_MASTER_EN 0x1b5c
+#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2
+#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e
+#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f
+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmOTG0_OTG_BLACK_COLOR 0x1b60
+#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2
+#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b61
+#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_CRC_CNTL 0x1b68
+#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2
+#define mmOTG0_OTG_CRC_CNTL2 0x1b69
+#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2
+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a
+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b
+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c
+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d
+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e
+#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
+#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f
+#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70
+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71
+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72
+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73
+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74
+#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
+#define mmOTG0_OTG_CRC1_DATA_B 0x1b75
+#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
+#define mmOTG0_OTG_CRC2_DATA_RG 0x1b76
+#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2
+#define mmOTG0_OTG_CRC2_DATA_B 0x1b77
+#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2
+#define mmOTG0_OTG_CRC3_DATA_RG 0x1b78
+#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2
+#define mmOTG0_OTG_CRC3_DATA_B 0x1b79
+#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2
+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a
+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b
+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82
+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83
+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84
+#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85
+#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86
+#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87
+#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
+#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88
+#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
+#define mmOTG0_OTG_VREADY_PARAM 0x1b89
+#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2
+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a
+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
+#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b
+#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG0_OTG_GSL_CONTROL 0x1b8c
+#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d
+#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
+#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e
+#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
+#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f
+#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
+#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90
+#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
+#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91
+#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
+#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92
+#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
+#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93
+#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94
+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b95
+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b96
+#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmOTG0_OTG_DRR_CONTROL 0x1b97
+#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_REQUEST_CONTROL 0x1b98
+#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2
+#define mmOTG0_OTG_DSC_START_POSITION 0x1b99
+#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2
+#define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9a
+#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
+#define mmOTG0_OTG_SPARE_REGISTER 0x1b9c
+#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+// base address: 0x200
+#define mmOTG1_OTG_H_TOTAL 0x1baa
+#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2
+#define mmOTG1_OTG_H_BLANK_START_END 0x1bab
+#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
+#define mmOTG1_OTG_H_SYNC_A 0x1bac
+#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2
+#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad
+#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae
+#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
+#define mmOTG1_OTG_V_TOTAL 0x1baf
+#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2
+#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0
+#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
+#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1
+#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
+#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2
+#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
+#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
+#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4
+#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5
+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6
+#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
+#define mmOTG1_OTG_V_SYNC_A 0x1bb7
+#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2
+#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8
+#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9
+#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba
+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb
+#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc
+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd
+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe
+#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf
+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmOTG1_OTG_CONTROL 0x1bc1
+#define mmOTG1_OTG_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2
+#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3
+#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
+#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
+#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
+#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
+#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
+#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmOTG1_OTG_STATUS 0x1bc9
+#define mmOTG1_OTG_STATUS_BASE_IDX 2
+#define mmOTG1_OTG_STATUS_POSITION 0x1bca
+#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2
+#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb
+#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
+#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc
+#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd
+#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
+#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce
+#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
+#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf
+#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_COUNT_RESET 0x1bd0
+#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2
+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1
+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2
+#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_STEREO_STATUS 0x1bd3
+#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2
+#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4
+#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5
+#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6
+#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7
+#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8
+#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9
+#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_UPDATE_LOCK 0x1bda
+#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb
+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_MASTER_EN 0x1bdc
+#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2
+#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde
+#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf
+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmOTG1_OTG_BLACK_COLOR 0x1be0
+#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2
+#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be1
+#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_CRC_CNTL 0x1be8
+#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2
+#define mmOTG1_OTG_CRC_CNTL2 0x1be9
+#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2
+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea
+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb
+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec
+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed
+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee
+#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
+#define mmOTG1_OTG_CRC0_DATA_B 0x1bef
+#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0
+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1
+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2
+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3
+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4
+#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
+#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5
+#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
+#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6
+#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2
+#define mmOTG1_OTG_CRC2_DATA_B 0x1bf7
+#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2
+#define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8
+#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2
+#define mmOTG1_OTG_CRC3_DATA_B 0x1bf9
+#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2
+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa
+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb
+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02
+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03
+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04
+#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05
+#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06
+#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07
+#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
+#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08
+#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
+#define mmOTG1_OTG_VREADY_PARAM 0x1c09
+#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2
+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a
+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
+#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b
+#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG1_OTG_GSL_CONTROL 0x1c0c
+#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d
+#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
+#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e
+#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
+#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f
+#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
+#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10
+#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
+#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11
+#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
+#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12
+#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
+#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13
+#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14
+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c15
+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c16
+#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmOTG1_OTG_DRR_CONTROL 0x1c17
+#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_REQUEST_CONTROL 0x1c18
+#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2
+#define mmOTG1_OTG_DSC_START_POSITION 0x1c19
+#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2
+#define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1a
+#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
+#define mmOTG1_OTG_SPARE_REGISTER 0x1c1c
+#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+// base address: 0x400
+#define mmOTG2_OTG_H_TOTAL 0x1c2a
+#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2
+#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b
+#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2
+#define mmOTG2_OTG_H_SYNC_A 0x1c2c
+#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2
+#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d
+#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e
+#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2
+#define mmOTG2_OTG_V_TOTAL 0x1c2f
+#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2
+#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30
+#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2
+#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31
+#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2
+#define mmOTG2_OTG_V_TOTAL_MID 0x1c32
+#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2
+#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33
+#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34
+#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35
+#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmOTG2_OTG_V_BLANK_START_END 0x1c36
+#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2
+#define mmOTG2_OTG_V_SYNC_A 0x1c37
+#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2
+#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38
+#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG2_OTG_TRIGA_CNTL 0x1c39
+#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2
+#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a
+#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b
+#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2
+#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c
+#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d
+#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e
+#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f
+#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmOTG2_OTG_CONTROL 0x1c41
+#define mmOTG2_OTG_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_BLANK_CONTROL 0x1c42
+#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43
+#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44
+#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45
+#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2
+#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47
+#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48
+#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmOTG2_OTG_STATUS 0x1c49
+#define mmOTG2_OTG_STATUS_BASE_IDX 2
+#define mmOTG2_OTG_STATUS_POSITION 0x1c4a
+#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2
+#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b
+#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2
+#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c
+#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d
+#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2
+#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e
+#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2
+#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f
+#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_COUNT_RESET 0x1c50
+#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2
+#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51
+#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52
+#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_STEREO_STATUS 0x1c53
+#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2
+#define mmOTG2_OTG_STEREO_CONTROL 0x1c54
+#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55
+#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56
+#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57
+#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58
+#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59
+#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a
+#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b
+#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_MASTER_EN 0x1c5c
+#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2
+#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c5e
+#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c5f
+#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmOTG2_OTG_BLACK_COLOR 0x1c60
+#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2
+#define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c61
+#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62
+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63
+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64
+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65
+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66
+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67
+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_CRC_CNTL 0x1c68
+#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2
+#define mmOTG2_OTG_CRC_CNTL2 0x1c69
+#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX 2
+#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a
+#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b
+#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c
+#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d
+#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_CRC0_DATA_RG 0x1c6e
+#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2
+#define mmOTG2_OTG_CRC0_DATA_B 0x1c6f
+#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2
+#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70
+#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71
+#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72
+#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73
+#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_CRC1_DATA_RG 0x1c74
+#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2
+#define mmOTG2_OTG_CRC1_DATA_B 0x1c75
+#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2
+#define mmOTG2_OTG_CRC2_DATA_RG 0x1c76
+#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2
+#define mmOTG2_OTG_CRC2_DATA_B 0x1c77
+#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2
+#define mmOTG2_OTG_CRC3_DATA_RG 0x1c78
+#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2
+#define mmOTG2_OTG_CRC3_DATA_B 0x1c79
+#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2
+#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a
+#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b
+#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82
+#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83
+#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c84
+#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c85
+#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmOTG2_OTG_CLOCK_CONTROL 0x1c86
+#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c87
+#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2
+#define mmOTG2_OTG_VUPDATE_PARAM 0x1c88
+#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2
+#define mmOTG2_OTG_VREADY_PARAM 0x1c89
+#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2
+#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a
+#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
+#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b
+#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG2_OTG_GSL_CONTROL 0x1c8c
+#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8d
+#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2
+#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c8e
+#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2
+#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f
+#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
+#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c90
+#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2
+#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c91
+#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2
+#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c92
+#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2
+#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c93
+#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2
+#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c94
+#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c95
+#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c96
+#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmOTG2_OTG_DRR_CONTROL 0x1c97
+#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_REQUEST_CONTROL 0x1c98
+#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2
+#define mmOTG2_OTG_DSC_START_POSITION 0x1c99
+#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX 2
+#define mmOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9a
+#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
+#define mmOTG2_OTG_SPARE_REGISTER 0x1c9c
+#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+// base address: 0x600
+#define mmOTG3_OTG_H_TOTAL 0x1caa
+#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2
+#define mmOTG3_OTG_H_BLANK_START_END 0x1cab
+#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2
+#define mmOTG3_OTG_H_SYNC_A 0x1cac
+#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2
+#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad
+#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae
+#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2
+#define mmOTG3_OTG_V_TOTAL 0x1caf
+#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2
+#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0
+#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2
+#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1
+#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2
+#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2
+#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2
+#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3
+#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4
+#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5
+#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6
+#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2
+#define mmOTG3_OTG_V_SYNC_A 0x1cb7
+#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2
+#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8
+#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9
+#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2
+#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba
+#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb
+#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2
+#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc
+#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd
+#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe
+#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf
+#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmOTG3_OTG_CONTROL 0x1cc1
+#define mmOTG3_OTG_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2
+#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3
+#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4
+#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5
+#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2
+#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7
+#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8
+#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmOTG3_OTG_STATUS 0x1cc9
+#define mmOTG3_OTG_STATUS_BASE_IDX 2
+#define mmOTG3_OTG_STATUS_POSITION 0x1cca
+#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2
+#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb
+#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2
+#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc
+#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd
+#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2
+#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce
+#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
+#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf
+#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_COUNT_RESET 0x1cd0
+#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2
+#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1
+#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2
+#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_STEREO_STATUS 0x1cd3
+#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2
+#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4
+#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5
+#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6
+#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7
+#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8
+#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9
+#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_UPDATE_LOCK 0x1cda
+#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb
+#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_MASTER_EN 0x1cdc
+#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2
+#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1cde
+#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1cdf
+#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmOTG3_OTG_BLACK_COLOR 0x1ce0
+#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2
+#define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce1
+#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3
+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4
+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5
+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6
+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7
+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_CRC_CNTL 0x1ce8
+#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2
+#define mmOTG3_OTG_CRC_CNTL2 0x1ce9
+#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX 2
+#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea
+#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb
+#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec
+#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced
+#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_CRC0_DATA_RG 0x1cee
+#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2
+#define mmOTG3_OTG_CRC0_DATA_B 0x1cef
+#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2
+#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0
+#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1
+#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2
+#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3
+#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf4
+#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2
+#define mmOTG3_OTG_CRC1_DATA_B 0x1cf5
+#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2
+#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf6
+#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2
+#define mmOTG3_OTG_CRC2_DATA_B 0x1cf7
+#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2
+#define mmOTG3_OTG_CRC3_DATA_RG 0x1cf8
+#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2
+#define mmOTG3_OTG_CRC3_DATA_B 0x1cf9
+#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2
+#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa
+#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb
+#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02
+#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03
+#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d04
+#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d05
+#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmOTG3_OTG_CLOCK_CONTROL 0x1d06
+#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d07
+#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2
+#define mmOTG3_OTG_VUPDATE_PARAM 0x1d08
+#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2
+#define mmOTG3_OTG_VREADY_PARAM 0x1d09
+#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2
+#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a
+#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
+#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b
+#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG3_OTG_GSL_CONTROL 0x1d0c
+#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0d
+#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2
+#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d0e
+#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2
+#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f
+#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
+#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d10
+#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2
+#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d11
+#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2
+#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d12
+#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2
+#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d13
+#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2
+#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d14
+#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d15
+#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d16
+#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmOTG3_OTG_DRR_CONTROL 0x1d17
+#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_REQUEST_CONTROL 0x1d18
+#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2
+#define mmOTG3_OTG_DSC_START_POSITION 0x1d19
+#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX 2
+#define mmOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1a
+#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
+#define mmOTG3_OTG_SPARE_REGISTER 0x1d1c
+#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_otg4_dispdec
+// base address: 0x800
+#define mmOTG4_OTG_H_TOTAL 0x1d2a
+#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2
+#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b
+#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2
+#define mmOTG4_OTG_H_SYNC_A 0x1d2c
+#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2
+#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d
+#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e
+#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2
+#define mmOTG4_OTG_V_TOTAL 0x1d2f
+#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2
+#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30
+#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2
+#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31
+#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2
+#define mmOTG4_OTG_V_TOTAL_MID 0x1d32
+#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2
+#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33
+#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34
+#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35
+#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmOTG4_OTG_V_BLANK_START_END 0x1d36
+#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2
+#define mmOTG4_OTG_V_SYNC_A 0x1d37
+#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2
+#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38
+#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG4_OTG_TRIGA_CNTL 0x1d39
+#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2
+#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a
+#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b
+#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2
+#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c
+#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d
+#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e
+#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f
+#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmOTG4_OTG_CONTROL 0x1d41
+#define mmOTG4_OTG_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_BLANK_CONTROL 0x1d42
+#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43
+#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44
+#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45
+#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2
+#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47
+#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48
+#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmOTG4_OTG_STATUS 0x1d49
+#define mmOTG4_OTG_STATUS_BASE_IDX 2
+#define mmOTG4_OTG_STATUS_POSITION 0x1d4a
+#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2
+#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b
+#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2
+#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c
+#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d
+#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2
+#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e
+#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2
+#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f
+#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_COUNT_RESET 0x1d50
+#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2
+#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51
+#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52
+#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_STEREO_STATUS 0x1d53
+#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2
+#define mmOTG4_OTG_STEREO_CONTROL 0x1d54
+#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55
+#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56
+#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57
+#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58
+#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59
+#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a
+#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b
+#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_MASTER_EN 0x1d5c
+#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2
+#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d5e
+#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d5f
+#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmOTG4_OTG_BLACK_COLOR 0x1d60
+#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2
+#define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d61
+#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d62
+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d63
+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d64
+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d65
+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d66
+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d67
+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_CRC_CNTL 0x1d68
+#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2
+#define mmOTG4_OTG_CRC_CNTL2 0x1d69
+#define mmOTG4_OTG_CRC_CNTL2_BASE_IDX 2
+#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6a
+#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6b
+#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6c
+#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6d
+#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_CRC0_DATA_RG 0x1d6e
+#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2
+#define mmOTG4_OTG_CRC0_DATA_B 0x1d6f
+#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2
+#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d70
+#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d71
+#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d72
+#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d73
+#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_CRC1_DATA_RG 0x1d74
+#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2
+#define mmOTG4_OTG_CRC1_DATA_B 0x1d75
+#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2
+#define mmOTG4_OTG_CRC2_DATA_RG 0x1d76
+#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2
+#define mmOTG4_OTG_CRC2_DATA_B 0x1d77
+#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2
+#define mmOTG4_OTG_CRC3_DATA_RG 0x1d78
+#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2
+#define mmOTG4_OTG_CRC3_DATA_B 0x1d79
+#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2
+#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7a
+#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7b
+#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d82
+#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d83
+#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d84
+#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d85
+#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmOTG4_OTG_CLOCK_CONTROL 0x1d86
+#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d87
+#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2
+#define mmOTG4_OTG_VUPDATE_PARAM 0x1d88
+#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2
+#define mmOTG4_OTG_VREADY_PARAM 0x1d89
+#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2
+#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8a
+#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
+#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8b
+#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG4_OTG_GSL_CONTROL 0x1d8c
+#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8d
+#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2
+#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d8e
+#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2
+#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d8f
+#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
+#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d90
+#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2
+#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d91
+#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2
+#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d92
+#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2
+#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d93
+#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2
+#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d94
+#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d95
+#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d96
+#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmOTG4_OTG_DRR_CONTROL 0x1d97
+#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_REQUEST_CONTROL 0x1d98
+#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2
+#define mmOTG4_OTG_DSC_START_POSITION 0x1d99
+#define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX 2
+#define mmOTG4_OTG_PIPE_UPDATE_STATUS 0x1d9a
+#define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
+#define mmOTG4_OTG_SPARE_REGISTER 0x1d9c
+#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_otg5_dispdec
+// base address: 0xa00
+#define mmOTG5_OTG_H_TOTAL 0x1daa
+#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2
+#define mmOTG5_OTG_H_BLANK_START_END 0x1dab
+#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2
+#define mmOTG5_OTG_H_SYNC_A 0x1dac
+#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2
+#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad
+#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae
+#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2
+#define mmOTG5_OTG_V_TOTAL 0x1daf
+#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2
+#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0
+#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2
+#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1
+#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2
+#define mmOTG5_OTG_V_TOTAL_MID 0x1db2
+#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2
+#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3
+#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4
+#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
+#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5
+#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
+#define mmOTG5_OTG_V_BLANK_START_END 0x1db6
+#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2
+#define mmOTG5_OTG_V_SYNC_A 0x1db7
+#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2
+#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8
+#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2
+#define mmOTG5_OTG_TRIGA_CNTL 0x1db9
+#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2
+#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba
+#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb
+#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2
+#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc
+#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
+#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd
+#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
+#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe
+#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf
+#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
+#define mmOTG5_OTG_CONTROL 0x1dc1
+#define mmOTG5_OTG_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2
+#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3
+#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4
+#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5
+#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2
+#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7
+#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
+#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8
+#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
+#define mmOTG5_OTG_STATUS 0x1dc9
+#define mmOTG5_OTG_STATUS_BASE_IDX 2
+#define mmOTG5_OTG_STATUS_POSITION 0x1dca
+#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2
+#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb
+#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2
+#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc
+#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
+#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd
+#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2
+#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce
+#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2
+#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf
+#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_COUNT_RESET 0x1dd0
+#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2
+#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1
+#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
+#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2
+#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_STEREO_STATUS 0x1dd3
+#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2
+#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4
+#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5
+#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2
+#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6
+#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7
+#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2
+#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8
+#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2
+#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9
+#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_UPDATE_LOCK 0x1dda
+#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb
+#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_MASTER_EN 0x1ddc
+#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2
+#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1dde
+#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2
+#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1ddf
+#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
+#define mmOTG5_OTG_BLACK_COLOR 0x1de0
+#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2
+#define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de1
+#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2
+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de2
+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de3
+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de4
+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de5
+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de6
+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1de7
+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_CRC_CNTL 0x1de8
+#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2
+#define mmOTG5_OTG_CRC_CNTL2 0x1de9
+#define mmOTG5_OTG_CRC_CNTL2_BASE_IDX 2
+#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dea
+#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1deb
+#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dec
+#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ded
+#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_CRC0_DATA_RG 0x1dee
+#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2
+#define mmOTG5_OTG_CRC0_DATA_B 0x1def
+#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2
+#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df0
+#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df1
+#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df2
+#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df3
+#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_CRC1_DATA_RG 0x1df4
+#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2
+#define mmOTG5_OTG_CRC1_DATA_B 0x1df5
+#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2
+#define mmOTG5_OTG_CRC2_DATA_RG 0x1df6
+#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2
+#define mmOTG5_OTG_CRC2_DATA_B 0x1df7
+#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2
+#define mmOTG5_OTG_CRC3_DATA_RG 0x1df8
+#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2
+#define mmOTG5_OTG_CRC3_DATA_B 0x1df9
+#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2
+#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfa
+#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
+#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfb
+#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
+#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e02
+#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e03
+#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e04
+#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2
+#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e05
+#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
+#define mmOTG5_OTG_CLOCK_CONTROL 0x1e06
+#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e07
+#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2
+#define mmOTG5_OTG_VUPDATE_PARAM 0x1e08
+#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2
+#define mmOTG5_OTG_VREADY_PARAM 0x1e09
+#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2
+#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0a
+#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
+#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0b
+#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
+#define mmOTG5_OTG_GSL_CONTROL 0x1e0c
+#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0d
+#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2
+#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e0e
+#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2
+#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e0f
+#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
+#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e10
+#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2
+#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e11
+#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2
+#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e12
+#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2
+#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e13
+#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2
+#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e14
+#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e15
+#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e16
+#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
+#define mmOTG5_OTG_DRR_CONTROL 0x1e17
+#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_REQUEST_CONTROL 0x1e18
+#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2
+#define mmOTG5_OTG_DSC_START_POSITION 0x1e19
+#define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX 2
+#define mmOTG5_OTG_PIPE_UPDATE_STATUS 0x1e1a
+#define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
+#define mmOTG5_OTG_SPARE_REGISTER 0x1e1c
+#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+// base address: 0x0
+#define mmDWB_SOURCE_SELECT 0x1e2a
+#define mmDWB_SOURCE_SELECT_BASE_IDX 2
+#define mmGSL_SOURCE_SELECT 0x1e2b
+#define mmGSL_SOURCE_SELECT_BASE_IDX 2
+#define mmOPTC_CLOCK_CONTROL 0x1e2c
+#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2
+#define mmODM_MEM_PWR_CTRL 0x1e2d
+#define mmODM_MEM_PWR_CTRL_BASE_IDX 2
+#define mmODM_MEM_PWR_CTRL2 0x1e2e
+#define mmODM_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmODM_MEM_PWR_CTRL3 0x1e2f
+#define mmODM_MEM_PWR_CTRL3_BASE_IDX 2
+#define mmODM_MEM_PWR_STATUS 0x1e30
+#define mmODM_MEM_PWR_STATUS_BASE_IDX 2
+#define mmOPTC_MISC_SPARE_REGISTER 0x1e31
+#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x79a8
+#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1e6a
+#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1e6b
+#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1e6c
+#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON19_PERFMON_CNTL 0x1e6d
+#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON19_PERFMON_CNTL2 0x1e6e
+#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1e6f
+#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1e70
+#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON19_PERFMON_HI 0x1e71
+#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON19_PERFMON_LOW 0x1e72
+#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+// base address: 0x0
+#define mmDC_I2C_CONTROL 0x1e98
+#define mmDC_I2C_CONTROL_BASE_IDX 2
+#define mmDC_I2C_ARBITRATION 0x1e99
+#define mmDC_I2C_ARBITRATION_BASE_IDX 2
+#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a
+#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDC_I2C_SW_STATUS 0x1e9b
+#define mmDC_I2C_SW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c
+#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d
+#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e
+#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f
+#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0
+#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC6_HW_STATUS 0x1ea1
+#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
+#define mmDC_I2C_DDC1_SPEED 0x1ea2
+#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC1_SETUP 0x1ea3
+#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC2_SPEED 0x1ea4
+#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC2_SETUP 0x1ea5
+#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC3_SPEED 0x1ea6
+#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC3_SETUP 0x1ea7
+#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC4_SPEED 0x1ea8
+#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC4_SETUP 0x1ea9
+#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC5_SPEED 0x1eaa
+#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC5_SETUP 0x1eab
+#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
+#define mmDC_I2C_DDC6_SPEED 0x1eac
+#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
+#define mmDC_I2C_DDC6_SETUP 0x1ead
+#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
+#define mmDC_I2C_TRANSACTION0 0x1eae
+#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
+#define mmDC_I2C_TRANSACTION1 0x1eaf
+#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
+#define mmDC_I2C_TRANSACTION2 0x1eb0
+#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
+#define mmDC_I2C_TRANSACTION3 0x1eb1
+#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
+#define mmDC_I2C_DATA 0x1eb2
+#define mmDC_I2C_DATA_BASE_IDX 2
+#define mmDC_I2C_DDCVGA_SETUP 0x1eb5
+#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
+#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6
+#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
+#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
+#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+// base address: 0x0
+#define mmDIO_SCRATCH0 0x1eca
+#define mmDIO_SCRATCH0_BASE_IDX 2
+#define mmDIO_SCRATCH1 0x1ecb
+#define mmDIO_SCRATCH1_BASE_IDX 2
+#define mmDIO_SCRATCH2 0x1ecc
+#define mmDIO_SCRATCH2_BASE_IDX 2
+#define mmDIO_SCRATCH3 0x1ecd
+#define mmDIO_SCRATCH3_BASE_IDX 2
+#define mmDIO_SCRATCH4 0x1ece
+#define mmDIO_SCRATCH4_BASE_IDX 2
+#define mmDIO_SCRATCH5 0x1ecf
+#define mmDIO_SCRATCH5_BASE_IDX 2
+#define mmDIO_SCRATCH6 0x1ed0
+#define mmDIO_SCRATCH6_BASE_IDX 2
+#define mmDIO_SCRATCH7 0x1ed1
+#define mmDIO_SCRATCH7_BASE_IDX 2
+#define mmDCE_VCE_CONTROL 0x1ed2
+#define mmDCE_VCE_CONTROL_BASE_IDX 2
+#define mmDIO_MEM_PWR_STATUS 0x1edd
+#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDIO_MEM_PWR_CTRL 0x1ede
+#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDIO_MEM_PWR_CTRL2 0x1edf
+#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmDIO_CLK_CNTL 0x1ee0
+#define mmDIO_CLK_CNTL_BASE_IDX 2
+#define mmDIO_MEM_PWR_CTRL3 0x1ee1
+#define mmDIO_MEM_PWR_CTRL3_BASE_IDX 2
+#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4
+#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
+#define mmDIG_SOFT_RESET 0x1eee
+#define mmDIG_SOFT_RESET_BASE_IDX 2
+#define mmDIO_MEM_PWR_STATUS1 0x1ef0
+#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2
+#define mmDIO_CLK_CNTL2 0x1ef2
+#define mmDIO_CLK_CNTL2_BASE_IDX 2
+#define mmDIO_CLK_CNTL3 0x1ef3
+#define mmDIO_CLK_CNTL3_BASE_IDX 2
+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
+#define mmDIO_PSP_INTERRUPT_STATUS 0x1f00
+#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01
+#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
+#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02
+#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
+#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03
+#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+// base address: 0x0
+#define mmHPD0_DC_HPD_INT_STATUS 0x1f14
+#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15
+#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD0_DC_HPD_CONTROL 0x1f16
+#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+// base address: 0x20
+#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c
+#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d
+#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD1_DC_HPD_CONTROL 0x1f1e
+#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+// base address: 0x40
+#define mmHPD2_DC_HPD_INT_STATUS 0x1f24
+#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25
+#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD2_DC_HPD_CONTROL 0x1f26
+#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27
+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28
+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+// base address: 0x60
+#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c
+#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d
+#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD3_DC_HPD_CONTROL 0x1f2e
+#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f
+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30
+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_hpd4_dispdec
+// base address: 0x80
+#define mmHPD4_DC_HPD_INT_STATUS 0x1f34
+#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35
+#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD4_DC_HPD_CONTROL 0x1f36
+#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37
+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38
+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_hpd5_dispdec
+// base address: 0xa0
+#define mmHPD5_DC_HPD_INT_STATUS 0x1f3c
+#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
+#define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d
+#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
+#define mmHPD5_DC_HPD_CONTROL 0x1f3e
+#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
+#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f
+#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
+#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40
+#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+// base address: 0x7d10
+#define mmDC_PERFMON20_PERFCOUNTER_CNTL 0x1f44
+#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON20_PERFCOUNTER_CNTL2 0x1f45
+#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON20_PERFCOUNTER_STATE 0x1f46
+#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON20_PERFMON_CNTL 0x1f47
+#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON20_PERFMON_CNTL2 0x1f48
+#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x1f49
+#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON20_PERFMON_CVALUE_LOW 0x1f4a
+#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON20_PERFMON_HI 0x1f4b
+#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON20_PERFMON_LOW 0x1f4c
+#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+// base address: 0x0
+#define mmDP_AUX0_AUX_CONTROL 0x1f50
+#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51
+#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52
+#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_SW_STATUS 0x1f54
+#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_LS_STATUS 0x1f55
+#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_SW_DATA 0x1f56
+#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX0_AUX_LS_DATA 0x1f57
+#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66
+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+// base address: 0x70
+#define mmDP_AUX1_AUX_CONTROL 0x1f6c
+#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d
+#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e
+#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_SW_STATUS 0x1f70
+#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_LS_STATUS 0x1f71
+#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_SW_DATA 0x1f72
+#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX1_AUX_LS_DATA 0x1f73
+#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82
+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+// base address: 0xe0
+#define mmDP_AUX2_AUX_CONTROL 0x1f88
+#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89
+#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a
+#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c
+#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d
+#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_SW_DATA 0x1f8e
+#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX2_AUX_LS_DATA 0x1f8f
+#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+#define mmDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e
+#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+// base address: 0x150
+#define mmDP_AUX3_AUX_CONTROL 0x1fa4
+#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5
+#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6
+#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8
+#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9
+#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_SW_DATA 0x1faa
+#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX3_AUX_LS_DATA 0x1fab
+#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+#define mmDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba
+#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp_aux4_dispdec
+// base address: 0x1c0
+#define mmDP_AUX4_AUX_CONTROL 0x1fc0
+#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1
+#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2
+#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3
+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4
+#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5
+#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_SW_DATA 0x1fc6
+#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX4_AUX_LS_DATA 0x1fc7
+#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8
+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9
+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc
+#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd
+#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf
+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1
+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+#define mmDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6
+#define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp_aux5_dispdec
+// base address: 0x230
+#define mmDP_AUX5_AUX_CONTROL 0x1fdc
+#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd
+#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde
+#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf
+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_SW_STATUS 0x1fe0
+#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_LS_STATUS 0x1fe1
+#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_SW_DATA 0x1fe2
+#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
+#define mmDP_AUX5_AUX_LS_DATA 0x1fe3
+#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4
+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5
+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8
+#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9
+#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x1fea
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb
+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed
+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
+#define mmDP_AUX5_AUX_PHY_WAKE_CNTL 0x1ff2
+#define mmDP_AUX5_AUX_PHY_WAKE_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+// base address: 0x0
+#define mmDIG0_DIG_FE_CNTL 0x2068
+#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG0_DIG_CLOCK_PATTERN 0x206b
+#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG0_DIG_TEST_PATTERN 0x206c
+#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG0_DIG_FIFO_STATUS 0x206e
+#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x206f
+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x2070
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
+#define mmDIG0_HDMI_CONTROL 0x2071
+#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG0_HDMI_STATUS 0x2072
+#define mmDIG0_HDMI_STATUS_BASE_IDX 2
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079
+#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG0_HDMI_GC 0x207b
+#define mmDIG0_HDMI_GC_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_0 0x207d
+#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_1 0x207e
+#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_2 0x207f
+#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_3 0x2080
+#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC1_4 0x2081
+#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC2_0 0x2082
+#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC2_1 0x2083
+#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC2_2 0x2084
+#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG0_AFMT_ISRC2_3 0x2085
+#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
+#define mmDIG0_HDMI_DB_CONTROL 0x2088
+#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2
+#define mmDIG0_DME_CONTROL 0x2089
+#define mmDIG0_DME_CONTROL_BASE_IDX 2
+#define mmDIG0_AFMT_MPEG_INFO0 0x208a
+#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG0_AFMT_MPEG_INFO1 0x208b
+#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_HDR 0x208c
+#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_0 0x208d
+#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_1 0x208e
+#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_2 0x208f
+#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_3 0x2090
+#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_4 0x2091
+#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_5 0x2092
+#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_6 0x2093
+#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG0_AFMT_GENERIC_7 0x2094
+#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_32_0 0x2096
+#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_32_1 0x2097
+#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_44_0 0x2098
+#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_44_1 0x2099
+#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_48_0 0x209a
+#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_48_1 0x209b
+#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_STATUS_0 0x209c
+#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG0_HDMI_ACR_STATUS_1 0x209d
+#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_INFO0 0x209e
+#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_INFO1 0x209f
+#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG0_AFMT_60958_0 0x20a0
+#define mmDIG0_AFMT_60958_0_BASE_IDX 2
+#define mmDIG0_AFMT_60958_1 0x20a1
+#define mmDIG0_AFMT_60958_1_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2
+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3
+#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4
+#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5
+#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6
+#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG0_AFMT_60958_2 0x20a7
+#define mmDIG0_AFMT_60958_2_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8
+#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG0_AFMT_STATUS 0x20a9
+#define mmDIG0_AFMT_STATUS_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac
+#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad
+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG0_DIG_BE_CNTL 0x20af
+#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG0_DIG_BE_EN_CNTL 0x20b0
+#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG0_TMDS_CNTL 0x20d3
+#define mmDIG0_TMDS_CNTL_BASE_IDX 2
+#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4
+#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG0_TMDS_CTL_BITS 0x20da
+#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db
+#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20dc
+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG0_DIG_VERSION 0x20e0
+#define mmDIG0_DIG_VERSION_BASE_IDX 2
+#define mmDIG0_DIG_LANE_ENABLE 0x20e1
+#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG0_AFMT_CNTL 0x20e6
+#define mmDIG0_AFMT_CNTL_BASE_IDX 2
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20f6
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
+#define mmDIG0_FORCE_DIG_DISABLE 0x20f7
+#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+// base address: 0x0
+#define mmDP0_DP_LINK_CNTL 0x2108
+#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP0_DP_PIXEL_FORMAT 0x2109
+#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP0_DP_MSA_COLORIMETRY 0x210a
+#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP0_DP_CONFIG 0x210b
+#define mmDP0_DP_CONFIG_BASE_IDX 2
+#define mmDP0_DP_VID_STREAM_CNTL 0x210c
+#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP0_DP_STEER_FIFO 0x210d
+#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP0_DP_MSA_MISC 0x210e
+#define mmDP0_DP_MSA_MISC_BASE_IDX 2
+#define mmDP0_DP_VID_TIMING 0x2110
+#define mmDP0_DP_VID_TIMING_BASE_IDX 2
+#define mmDP0_DP_VID_N 0x2111
+#define mmDP0_DP_VID_N_BASE_IDX 2
+#define mmDP0_DP_VID_M 0x2112
+#define mmDP0_DP_VID_M_BASE_IDX 2
+#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113
+#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114
+#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP0_DP_VID_MSA_VBID 0x2115
+#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116
+#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_CNTL 0x2117
+#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP0_DP_DPHY_SYM0 0x2119
+#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP0_DP_DPHY_SYM1 0x211a
+#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP0_DP_DPHY_SYM2 0x211b
+#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c
+#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d
+#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e
+#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_EN 0x211f
+#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_CNTL 0x2120
+#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_RESULT 0x2121
+#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122
+#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123
+#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124
+#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL 0x212b
+#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL1 0x212c
+#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP0_DP_SEC_FRAMING1 0x212d
+#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP0_DP_SEC_FRAMING2 0x212e
+#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP0_DP_SEC_FRAMING3 0x212f
+#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP0_DP_SEC_FRAMING4 0x2130
+#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP0_DP_SEC_AUD_N 0x2131
+#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132
+#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP0_DP_SEC_AUD_M 0x2133
+#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134
+#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP0_DP_SEC_TIMESTAMP 0x2135
+#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP0_DP_SEC_PACKET_CNTL 0x2136
+#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP0_DP_MSE_RATE_CNTL 0x2137
+#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP0_DP_MSE_RATE_UPDATE 0x2139
+#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT0 0x213a
+#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT1 0x213b
+#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT2 0x213c
+#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT_UPDATE 0x213d
+#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP0_DP_MSE_LINK_TIMING 0x213e
+#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP0_DP_MSE_MISC_CNTL 0x213f
+#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT0_STATUS 0x2147
+#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT1_STATUS 0x2148
+#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP0_DP_MSE_SAT2_STATUS 0x2149
+#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
+#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c
+#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
+#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d
+#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
+#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e
+#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
+#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f
+#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
+#define mmDP0_DP_MSO_CNTL 0x2150
+#define mmDP0_DP_MSO_CNTL_BASE_IDX 2
+#define mmDP0_DP_MSO_CNTL1 0x2151
+#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2
+#define mmDP0_DP_DSC_CNTL 0x2152
+#define mmDP0_DP_DSC_CNTL_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL2 0x2153
+#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL3 0x2154
+#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL4 0x2155
+#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL5 0x2156
+#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL6 0x2157
+#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2
+#define mmDP0_DP_SEC_CNTL7 0x2158
+#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2
+#define mmDP0_DP_DB_CNTL 0x2159
+#define mmDP0_DP_DB_CNTL_BASE_IDX 2
+#define mmDP0_DP_MSA_VBID_MISC 0x215a
+#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2
+#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b
+#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
+#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c
+#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmDP0_DP_ALPM_CNTL 0x215d
+#define mmDP0_DP_ALPM_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+// base address: 0x400
+#define mmDIG1_DIG_FE_CNTL 0x2168
+#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG1_DIG_CLOCK_PATTERN 0x216b
+#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG1_DIG_TEST_PATTERN 0x216c
+#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG1_DIG_FIFO_STATUS 0x216e
+#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x216f
+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x2170
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
+#define mmDIG1_HDMI_CONTROL 0x2171
+#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG1_HDMI_STATUS 0x2172
+#define mmDIG1_HDMI_STATUS_BASE_IDX 2
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179
+#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG1_HDMI_GC 0x217b
+#define mmDIG1_HDMI_GC_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_0 0x217d
+#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_1 0x217e
+#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_2 0x217f
+#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_3 0x2180
+#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC1_4 0x2181
+#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC2_0 0x2182
+#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC2_1 0x2183
+#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC2_2 0x2184
+#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG1_AFMT_ISRC2_3 0x2185
+#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
+#define mmDIG1_HDMI_DB_CONTROL 0x2188
+#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2
+#define mmDIG1_DME_CONTROL 0x2189
+#define mmDIG1_DME_CONTROL_BASE_IDX 2
+#define mmDIG1_AFMT_MPEG_INFO0 0x218a
+#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG1_AFMT_MPEG_INFO1 0x218b
+#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_HDR 0x218c
+#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_0 0x218d
+#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_1 0x218e
+#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_2 0x218f
+#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_3 0x2190
+#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_4 0x2191
+#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_5 0x2192
+#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_6 0x2193
+#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG1_AFMT_GENERIC_7 0x2194
+#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_32_0 0x2196
+#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_32_1 0x2197
+#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_44_0 0x2198
+#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_44_1 0x2199
+#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_48_0 0x219a
+#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_48_1 0x219b
+#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_STATUS_0 0x219c
+#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG1_HDMI_ACR_STATUS_1 0x219d
+#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_INFO0 0x219e
+#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_INFO1 0x219f
+#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG1_AFMT_60958_0 0x21a0
+#define mmDIG1_AFMT_60958_0_BASE_IDX 2
+#define mmDIG1_AFMT_60958_1 0x21a1
+#define mmDIG1_AFMT_60958_1_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2
+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3
+#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4
+#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5
+#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6
+#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG1_AFMT_60958_2 0x21a7
+#define mmDIG1_AFMT_60958_2_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8
+#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG1_AFMT_STATUS 0x21a9
+#define mmDIG1_AFMT_STATUS_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac
+#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad
+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG1_DIG_BE_CNTL 0x21af
+#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG1_DIG_BE_EN_CNTL 0x21b0
+#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG1_TMDS_CNTL 0x21d3
+#define mmDIG1_TMDS_CNTL_BASE_IDX 2
+#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4
+#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG1_TMDS_CTL_BITS 0x21da
+#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db
+#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21dc
+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG1_DIG_VERSION 0x21e0
+#define mmDIG1_DIG_VERSION_BASE_IDX 2
+#define mmDIG1_DIG_LANE_ENABLE 0x21e1
+#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG1_AFMT_CNTL 0x21e6
+#define mmDIG1_AFMT_CNTL_BASE_IDX 2
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21f6
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
+#define mmDIG1_FORCE_DIG_DISABLE 0x21f7
+#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+// base address: 0x400
+#define mmDP1_DP_LINK_CNTL 0x2208
+#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP1_DP_PIXEL_FORMAT 0x2209
+#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP1_DP_MSA_COLORIMETRY 0x220a
+#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP1_DP_CONFIG 0x220b
+#define mmDP1_DP_CONFIG_BASE_IDX 2
+#define mmDP1_DP_VID_STREAM_CNTL 0x220c
+#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP1_DP_STEER_FIFO 0x220d
+#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP1_DP_MSA_MISC 0x220e
+#define mmDP1_DP_MSA_MISC_BASE_IDX 2
+#define mmDP1_DP_VID_TIMING 0x2210
+#define mmDP1_DP_VID_TIMING_BASE_IDX 2
+#define mmDP1_DP_VID_N 0x2211
+#define mmDP1_DP_VID_N_BASE_IDX 2
+#define mmDP1_DP_VID_M 0x2212
+#define mmDP1_DP_VID_M_BASE_IDX 2
+#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213
+#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214
+#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP1_DP_VID_MSA_VBID 0x2215
+#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216
+#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_CNTL 0x2217
+#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP1_DP_DPHY_SYM0 0x2219
+#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP1_DP_DPHY_SYM1 0x221a
+#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP1_DP_DPHY_SYM2 0x221b
+#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c
+#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d
+#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e
+#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_EN 0x221f
+#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_CNTL 0x2220
+#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_RESULT 0x2221
+#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222
+#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223
+#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224
+#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL 0x222b
+#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL1 0x222c
+#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP1_DP_SEC_FRAMING1 0x222d
+#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP1_DP_SEC_FRAMING2 0x222e
+#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP1_DP_SEC_FRAMING3 0x222f
+#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP1_DP_SEC_FRAMING4 0x2230
+#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP1_DP_SEC_AUD_N 0x2231
+#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232
+#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP1_DP_SEC_AUD_M 0x2233
+#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234
+#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP1_DP_SEC_TIMESTAMP 0x2235
+#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP1_DP_SEC_PACKET_CNTL 0x2236
+#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP1_DP_MSE_RATE_CNTL 0x2237
+#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP1_DP_MSE_RATE_UPDATE 0x2239
+#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT0 0x223a
+#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT1 0x223b
+#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT2 0x223c
+#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT_UPDATE 0x223d
+#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP1_DP_MSE_LINK_TIMING 0x223e
+#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP1_DP_MSE_MISC_CNTL 0x223f
+#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT0_STATUS 0x2247
+#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT1_STATUS 0x2248
+#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP1_DP_MSE_SAT2_STATUS 0x2249
+#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
+#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c
+#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
+#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d
+#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
+#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e
+#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
+#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f
+#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
+#define mmDP1_DP_MSO_CNTL 0x2250
+#define mmDP1_DP_MSO_CNTL_BASE_IDX 2
+#define mmDP1_DP_MSO_CNTL1 0x2251
+#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2
+#define mmDP1_DP_DSC_CNTL 0x2252
+#define mmDP1_DP_DSC_CNTL_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL2 0x2253
+#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL3 0x2254
+#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL4 0x2255
+#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL5 0x2256
+#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL6 0x2257
+#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2
+#define mmDP1_DP_SEC_CNTL7 0x2258
+#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2
+#define mmDP1_DP_DB_CNTL 0x2259
+#define mmDP1_DP_DB_CNTL_BASE_IDX 2
+#define mmDP1_DP_MSA_VBID_MISC 0x225a
+#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2
+#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b
+#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
+#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c
+#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmDP1_DP_ALPM_CNTL 0x225d
+#define mmDP1_DP_ALPM_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+// base address: 0x800
+#define mmDIG2_DIG_FE_CNTL 0x2268
+#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG2_DIG_CLOCK_PATTERN 0x226b
+#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG2_DIG_TEST_PATTERN 0x226c
+#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG2_DIG_FIFO_STATUS 0x226e
+#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG2_HDMI_METADATA_PACKET_CONTROL 0x226f
+#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x2270
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
+#define mmDIG2_HDMI_CONTROL 0x2271
+#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG2_HDMI_STATUS 0x2272
+#define mmDIG2_HDMI_STATUS_BASE_IDX 2
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279
+#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG2_HDMI_GC 0x227b
+#define mmDIG2_HDMI_GC_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_0 0x227d
+#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_1 0x227e
+#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_2 0x227f
+#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_3 0x2280
+#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC1_4 0x2281
+#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC2_0 0x2282
+#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC2_1 0x2283
+#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC2_2 0x2284
+#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG2_AFMT_ISRC2_3 0x2285
+#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
+#define mmDIG2_HDMI_DB_CONTROL 0x2288
+#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2
+#define mmDIG2_DME_CONTROL 0x2289
+#define mmDIG2_DME_CONTROL_BASE_IDX 2
+#define mmDIG2_AFMT_MPEG_INFO0 0x228a
+#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG2_AFMT_MPEG_INFO1 0x228b
+#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_HDR 0x228c
+#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_0 0x228d
+#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_1 0x228e
+#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_2 0x228f
+#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_3 0x2290
+#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_4 0x2291
+#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_5 0x2292
+#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_6 0x2293
+#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG2_AFMT_GENERIC_7 0x2294
+#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_32_0 0x2296
+#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_32_1 0x2297
+#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_44_0 0x2298
+#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_44_1 0x2299
+#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_48_0 0x229a
+#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_48_1 0x229b
+#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_STATUS_0 0x229c
+#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG2_HDMI_ACR_STATUS_1 0x229d
+#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_INFO0 0x229e
+#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_INFO1 0x229f
+#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG2_AFMT_60958_0 0x22a0
+#define mmDIG2_AFMT_60958_0_BASE_IDX 2
+#define mmDIG2_AFMT_60958_1 0x22a1
+#define mmDIG2_AFMT_60958_1_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2
+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3
+#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4
+#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5
+#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6
+#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG2_AFMT_60958_2 0x22a7
+#define mmDIG2_AFMT_60958_2_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8
+#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG2_AFMT_STATUS 0x22a9
+#define mmDIG2_AFMT_STATUS_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac
+#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad
+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG2_DIG_BE_CNTL 0x22af
+#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG2_DIG_BE_EN_CNTL 0x22b0
+#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG2_TMDS_CNTL 0x22d3
+#define mmDIG2_TMDS_CNTL_BASE_IDX 2
+#define mmDIG2_TMDS_CONTROL_CHAR 0x22d4
+#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG2_TMDS_CTL_BITS 0x22da
+#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db
+#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22dc
+#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd
+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de
+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG2_DIG_VERSION 0x22e0
+#define mmDIG2_DIG_VERSION_BASE_IDX 2
+#define mmDIG2_DIG_LANE_ENABLE 0x22e1
+#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG2_AFMT_CNTL 0x22e6
+#define mmDIG2_AFMT_CNTL_BASE_IDX 2
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22f6
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
+#define mmDIG2_FORCE_DIG_DISABLE 0x22f7
+#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+// base address: 0x800
+#define mmDP2_DP_LINK_CNTL 0x2308
+#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP2_DP_PIXEL_FORMAT 0x2309
+#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP2_DP_MSA_COLORIMETRY 0x230a
+#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP2_DP_CONFIG 0x230b
+#define mmDP2_DP_CONFIG_BASE_IDX 2
+#define mmDP2_DP_VID_STREAM_CNTL 0x230c
+#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP2_DP_STEER_FIFO 0x230d
+#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP2_DP_MSA_MISC 0x230e
+#define mmDP2_DP_MSA_MISC_BASE_IDX 2
+#define mmDP2_DP_VID_TIMING 0x2310
+#define mmDP2_DP_VID_TIMING_BASE_IDX 2
+#define mmDP2_DP_VID_N 0x2311
+#define mmDP2_DP_VID_N_BASE_IDX 2
+#define mmDP2_DP_VID_M 0x2312
+#define mmDP2_DP_VID_M_BASE_IDX 2
+#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313
+#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314
+#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP2_DP_VID_MSA_VBID 0x2315
+#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316
+#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_CNTL 0x2317
+#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP2_DP_DPHY_SYM0 0x2319
+#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP2_DP_DPHY_SYM1 0x231a
+#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP2_DP_DPHY_SYM2 0x231b
+#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c
+#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d
+#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e
+#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_EN 0x231f
+#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_CNTL 0x2320
+#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_RESULT 0x2321
+#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322
+#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323
+#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324
+#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL 0x232b
+#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL1 0x232c
+#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP2_DP_SEC_FRAMING1 0x232d
+#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP2_DP_SEC_FRAMING2 0x232e
+#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP2_DP_SEC_FRAMING3 0x232f
+#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP2_DP_SEC_FRAMING4 0x2330
+#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP2_DP_SEC_AUD_N 0x2331
+#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332
+#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP2_DP_SEC_AUD_M 0x2333
+#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334
+#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP2_DP_SEC_TIMESTAMP 0x2335
+#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP2_DP_SEC_PACKET_CNTL 0x2336
+#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP2_DP_MSE_RATE_CNTL 0x2337
+#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP2_DP_MSE_RATE_UPDATE 0x2339
+#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT0 0x233a
+#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT1 0x233b
+#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT2 0x233c
+#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT_UPDATE 0x233d
+#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP2_DP_MSE_LINK_TIMING 0x233e
+#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP2_DP_MSE_MISC_CNTL 0x233f
+#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344
+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345
+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT0_STATUS 0x2347
+#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT1_STATUS 0x2348
+#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP2_DP_MSE_SAT2_STATUS 0x2349
+#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
+#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c
+#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2
+#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d
+#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2
+#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e
+#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2
+#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f
+#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2
+#define mmDP2_DP_MSO_CNTL 0x2350
+#define mmDP2_DP_MSO_CNTL_BASE_IDX 2
+#define mmDP2_DP_MSO_CNTL1 0x2351
+#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2
+#define mmDP2_DP_DSC_CNTL 0x2352
+#define mmDP2_DP_DSC_CNTL_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL2 0x2353
+#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL3 0x2354
+#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL4 0x2355
+#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL5 0x2356
+#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL6 0x2357
+#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2
+#define mmDP2_DP_SEC_CNTL7 0x2358
+#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2
+#define mmDP2_DP_DB_CNTL 0x2359
+#define mmDP2_DP_DB_CNTL_BASE_IDX 2
+#define mmDP2_DP_MSA_VBID_MISC 0x235a
+#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2
+#define mmDP2_DP_SEC_METADATA_TRANSMISSION 0x235b
+#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
+#define mmDP2_DP_DSC_BYTES_PER_PIXEL 0x235c
+#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmDP2_DP_ALPM_CNTL 0x235d
+#define mmDP2_DP_ALPM_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+// base address: 0xc00
+#define mmDIG3_DIG_FE_CNTL 0x2368
+#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG3_DIG_CLOCK_PATTERN 0x236b
+#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG3_DIG_TEST_PATTERN 0x236c
+#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG3_DIG_FIFO_STATUS 0x236e
+#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG3_HDMI_METADATA_PACKET_CONTROL 0x236f
+#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2370
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
+#define mmDIG3_HDMI_CONTROL 0x2371
+#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG3_HDMI_STATUS 0x2372
+#define mmDIG3_HDMI_STATUS_BASE_IDX 2
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379
+#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG3_HDMI_GC 0x237b
+#define mmDIG3_HDMI_GC_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_0 0x237d
+#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_1 0x237e
+#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_2 0x237f
+#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_3 0x2380
+#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC1_4 0x2381
+#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC2_0 0x2382
+#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC2_1 0x2383
+#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC2_2 0x2384
+#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG3_AFMT_ISRC2_3 0x2385
+#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
+#define mmDIG3_HDMI_DB_CONTROL 0x2388
+#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2
+#define mmDIG3_DME_CONTROL 0x2389
+#define mmDIG3_DME_CONTROL_BASE_IDX 2
+#define mmDIG3_AFMT_MPEG_INFO0 0x238a
+#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG3_AFMT_MPEG_INFO1 0x238b
+#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_HDR 0x238c
+#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_0 0x238d
+#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_1 0x238e
+#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_2 0x238f
+#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_3 0x2390
+#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_4 0x2391
+#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_5 0x2392
+#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_6 0x2393
+#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG3_AFMT_GENERIC_7 0x2394
+#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_32_0 0x2396
+#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_32_1 0x2397
+#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_44_0 0x2398
+#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_44_1 0x2399
+#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_48_0 0x239a
+#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_48_1 0x239b
+#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_STATUS_0 0x239c
+#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG3_HDMI_ACR_STATUS_1 0x239d
+#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_INFO0 0x239e
+#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_INFO1 0x239f
+#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG3_AFMT_60958_0 0x23a0
+#define mmDIG3_AFMT_60958_0_BASE_IDX 2
+#define mmDIG3_AFMT_60958_1 0x23a1
+#define mmDIG3_AFMT_60958_1_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2
+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3
+#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4
+#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5
+#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6
+#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG3_AFMT_60958_2 0x23a7
+#define mmDIG3_AFMT_60958_2_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8
+#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG3_AFMT_STATUS 0x23a9
+#define mmDIG3_AFMT_STATUS_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac
+#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad
+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG3_DIG_BE_CNTL 0x23af
+#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG3_DIG_BE_EN_CNTL 0x23b0
+#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG3_TMDS_CNTL 0x23d3
+#define mmDIG3_TMDS_CNTL_BASE_IDX 2
+#define mmDIG3_TMDS_CONTROL_CHAR 0x23d4
+#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG3_TMDS_CTL_BITS 0x23da
+#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db
+#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23dc
+#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd
+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de
+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG3_DIG_VERSION 0x23e0
+#define mmDIG3_DIG_VERSION_BASE_IDX 2
+#define mmDIG3_DIG_LANE_ENABLE 0x23e1
+#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG3_AFMT_CNTL 0x23e6
+#define mmDIG3_AFMT_CNTL_BASE_IDX 2
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x23f6
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
+#define mmDIG3_FORCE_DIG_DISABLE 0x23f7
+#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+// base address: 0xc00
+#define mmDP3_DP_LINK_CNTL 0x2408
+#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP3_DP_PIXEL_FORMAT 0x2409
+#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP3_DP_MSA_COLORIMETRY 0x240a
+#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP3_DP_CONFIG 0x240b
+#define mmDP3_DP_CONFIG_BASE_IDX 2
+#define mmDP3_DP_VID_STREAM_CNTL 0x240c
+#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP3_DP_STEER_FIFO 0x240d
+#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP3_DP_MSA_MISC 0x240e
+#define mmDP3_DP_MSA_MISC_BASE_IDX 2
+#define mmDP3_DP_VID_TIMING 0x2410
+#define mmDP3_DP_VID_TIMING_BASE_IDX 2
+#define mmDP3_DP_VID_N 0x2411
+#define mmDP3_DP_VID_N_BASE_IDX 2
+#define mmDP3_DP_VID_M 0x2412
+#define mmDP3_DP_VID_M_BASE_IDX 2
+#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413
+#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414
+#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP3_DP_VID_MSA_VBID 0x2415
+#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416
+#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_CNTL 0x2417
+#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP3_DP_DPHY_SYM0 0x2419
+#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP3_DP_DPHY_SYM1 0x241a
+#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP3_DP_DPHY_SYM2 0x241b
+#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c
+#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d
+#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e
+#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_EN 0x241f
+#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_CNTL 0x2420
+#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_RESULT 0x2421
+#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422
+#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423
+#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424
+#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL 0x242b
+#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL1 0x242c
+#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP3_DP_SEC_FRAMING1 0x242d
+#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP3_DP_SEC_FRAMING2 0x242e
+#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP3_DP_SEC_FRAMING3 0x242f
+#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP3_DP_SEC_FRAMING4 0x2430
+#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP3_DP_SEC_AUD_N 0x2431
+#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432
+#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP3_DP_SEC_AUD_M 0x2433
+#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434
+#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP3_DP_SEC_TIMESTAMP 0x2435
+#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP3_DP_SEC_PACKET_CNTL 0x2436
+#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP3_DP_MSE_RATE_CNTL 0x2437
+#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP3_DP_MSE_RATE_UPDATE 0x2439
+#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT0 0x243a
+#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT1 0x243b
+#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT2 0x243c
+#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT_UPDATE 0x243d
+#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP3_DP_MSE_LINK_TIMING 0x243e
+#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP3_DP_MSE_MISC_CNTL 0x243f
+#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444
+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445
+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT0_STATUS 0x2447
+#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT1_STATUS 0x2448
+#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP3_DP_MSE_SAT2_STATUS 0x2449
+#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
+#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c
+#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2
+#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d
+#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2
+#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e
+#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2
+#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f
+#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2
+#define mmDP3_DP_MSO_CNTL 0x2450
+#define mmDP3_DP_MSO_CNTL_BASE_IDX 2
+#define mmDP3_DP_MSO_CNTL1 0x2451
+#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2
+#define mmDP3_DP_DSC_CNTL 0x2452
+#define mmDP3_DP_DSC_CNTL_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL2 0x2453
+#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL3 0x2454
+#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL4 0x2455
+#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL5 0x2456
+#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL6 0x2457
+#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2
+#define mmDP3_DP_SEC_CNTL7 0x2458
+#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2
+#define mmDP3_DP_DB_CNTL 0x2459
+#define mmDP3_DP_DB_CNTL_BASE_IDX 2
+#define mmDP3_DP_MSA_VBID_MISC 0x245a
+#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2
+#define mmDP3_DP_SEC_METADATA_TRANSMISSION 0x245b
+#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
+#define mmDP3_DP_DSC_BYTES_PER_PIXEL 0x245c
+#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmDP3_DP_ALPM_CNTL 0x245d
+#define mmDP3_DP_ALPM_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dig4_dispdec
+// base address: 0x1000
+#define mmDIG4_DIG_FE_CNTL 0x2468
+#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469
+#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a
+#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG4_DIG_CLOCK_PATTERN 0x246b
+#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG4_DIG_TEST_PATTERN 0x246c
+#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d
+#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG4_DIG_FIFO_STATUS 0x246e
+#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG4_HDMI_METADATA_PACKET_CONTROL 0x246f
+#define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x2470
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
+#define mmDIG4_HDMI_CONTROL 0x2471
+#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG4_HDMI_STATUS 0x2472
+#define mmDIG4_HDMI_STATUS_BASE_IDX 2
+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473
+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474
+#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475
+#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476
+#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477
+#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479
+#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG4_HDMI_GC 0x247b
+#define mmDIG4_HDMI_GC_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_0 0x247d
+#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_1 0x247e
+#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_2 0x247f
+#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_3 0x2480
+#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC1_4 0x2481
+#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC2_0 0x2482
+#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC2_1 0x2483
+#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC2_2 0x2484
+#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG4_AFMT_ISRC2_3 0x2485
+#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
+#define mmDIG4_HDMI_DB_CONTROL 0x2488
+#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2
+#define mmDIG4_DME_CONTROL 0x2489
+#define mmDIG4_DME_CONTROL_BASE_IDX 2
+#define mmDIG4_AFMT_MPEG_INFO0 0x248a
+#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG4_AFMT_MPEG_INFO1 0x248b
+#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_HDR 0x248c
+#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_0 0x248d
+#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_1 0x248e
+#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_2 0x248f
+#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_3 0x2490
+#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_4 0x2491
+#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_5 0x2492
+#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_6 0x2493
+#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG4_AFMT_GENERIC_7 0x2494
+#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_32_0 0x2496
+#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_32_1 0x2497
+#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_44_0 0x2498
+#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_44_1 0x2499
+#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_48_0 0x249a
+#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_48_1 0x249b
+#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_STATUS_0 0x249c
+#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG4_HDMI_ACR_STATUS_1 0x249d
+#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_INFO0 0x249e
+#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_INFO1 0x249f
+#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG4_AFMT_60958_0 0x24a0
+#define mmDIG4_AFMT_60958_0_BASE_IDX 2
+#define mmDIG4_AFMT_60958_1 0x24a1
+#define mmDIG4_AFMT_60958_1_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2
+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3
+#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4
+#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5
+#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6
+#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG4_AFMT_60958_2 0x24a7
+#define mmDIG4_AFMT_60958_2_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8
+#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG4_AFMT_STATUS 0x24a9
+#define mmDIG4_AFMT_STATUS_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac
+#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad
+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG4_DIG_BE_CNTL 0x24af
+#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG4_DIG_BE_EN_CNTL 0x24b0
+#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG4_TMDS_CNTL 0x24d3
+#define mmDIG4_TMDS_CNTL_BASE_IDX 2
+#define mmDIG4_TMDS_CONTROL_CHAR 0x24d4
+#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5
+#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6
+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG4_TMDS_CTL_BITS 0x24da
+#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db
+#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24dc
+#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd
+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de
+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG4_DIG_VERSION 0x24e0
+#define mmDIG4_DIG_VERSION_BASE_IDX 2
+#define mmDIG4_DIG_LANE_ENABLE 0x24e1
+#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG4_AFMT_CNTL 0x24e6
+#define mmDIG4_AFMT_CNTL_BASE_IDX 2
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x24f6
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
+#define mmDIG4_FORCE_DIG_DISABLE 0x24f7
+#define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp4_dispdec
+// base address: 0x1000
+#define mmDP4_DP_LINK_CNTL 0x2508
+#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP4_DP_PIXEL_FORMAT 0x2509
+#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP4_DP_MSA_COLORIMETRY 0x250a
+#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP4_DP_CONFIG 0x250b
+#define mmDP4_DP_CONFIG_BASE_IDX 2
+#define mmDP4_DP_VID_STREAM_CNTL 0x250c
+#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP4_DP_STEER_FIFO 0x250d
+#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP4_DP_MSA_MISC 0x250e
+#define mmDP4_DP_MSA_MISC_BASE_IDX 2
+#define mmDP4_DP_VID_TIMING 0x2510
+#define mmDP4_DP_VID_TIMING_BASE_IDX 2
+#define mmDP4_DP_VID_N 0x2511
+#define mmDP4_DP_VID_N_BASE_IDX 2
+#define mmDP4_DP_VID_M 0x2512
+#define mmDP4_DP_VID_M_BASE_IDX 2
+#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513
+#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514
+#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP4_DP_VID_MSA_VBID 0x2515
+#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516
+#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_CNTL 0x2517
+#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518
+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP4_DP_DPHY_SYM0 0x2519
+#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP4_DP_DPHY_SYM1 0x251a
+#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP4_DP_DPHY_SYM2 0x251b
+#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c
+#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d
+#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e
+#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_EN 0x251f
+#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_CNTL 0x2520
+#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_RESULT 0x2521
+#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522
+#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523
+#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524
+#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525
+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL 0x252b
+#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL1 0x252c
+#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP4_DP_SEC_FRAMING1 0x252d
+#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP4_DP_SEC_FRAMING2 0x252e
+#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP4_DP_SEC_FRAMING3 0x252f
+#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP4_DP_SEC_FRAMING4 0x2530
+#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP4_DP_SEC_AUD_N 0x2531
+#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532
+#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP4_DP_SEC_AUD_M 0x2533
+#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534
+#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP4_DP_SEC_TIMESTAMP 0x2535
+#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP4_DP_SEC_PACKET_CNTL 0x2536
+#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP4_DP_MSE_RATE_CNTL 0x2537
+#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP4_DP_MSE_RATE_UPDATE 0x2539
+#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT0 0x253a
+#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT1 0x253b
+#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT2 0x253c
+#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT_UPDATE 0x253d
+#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP4_DP_MSE_LINK_TIMING 0x253e
+#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP4_DP_MSE_MISC_CNTL 0x253f
+#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544
+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545
+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT0_STATUS 0x2547
+#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT1_STATUS 0x2548
+#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP4_DP_MSE_SAT2_STATUS 0x2549
+#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
+#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c
+#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2
+#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d
+#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2
+#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e
+#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2
+#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f
+#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2
+#define mmDP4_DP_MSO_CNTL 0x2550
+#define mmDP4_DP_MSO_CNTL_BASE_IDX 2
+#define mmDP4_DP_MSO_CNTL1 0x2551
+#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2
+#define mmDP4_DP_DSC_CNTL 0x2552
+#define mmDP4_DP_DSC_CNTL_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL2 0x2553
+#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL3 0x2554
+#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL4 0x2555
+#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL5 0x2556
+#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL6 0x2557
+#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2
+#define mmDP4_DP_SEC_CNTL7 0x2558
+#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2
+#define mmDP4_DP_DB_CNTL 0x2559
+#define mmDP4_DP_DB_CNTL_BASE_IDX 2
+#define mmDP4_DP_MSA_VBID_MISC 0x255a
+#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2
+#define mmDP4_DP_SEC_METADATA_TRANSMISSION 0x255b
+#define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
+#define mmDP4_DP_DSC_BYTES_PER_PIXEL 0x255c
+#define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmDP4_DP_ALPM_CNTL 0x255d
+#define mmDP4_DP_ALPM_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dig5_dispdec
+// base address: 0x1400
+#define mmDIG5_DIG_FE_CNTL 0x2568
+#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
+#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x2569
+#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
+#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x256a
+#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
+#define mmDIG5_DIG_CLOCK_PATTERN 0x256b
+#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
+#define mmDIG5_DIG_TEST_PATTERN 0x256c
+#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
+#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x256d
+#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
+#define mmDIG5_DIG_FIFO_STATUS 0x256e
+#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
+#define mmDIG5_HDMI_METADATA_PACKET_CONTROL 0x256f
+#define mmDIG5_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4 0x2570
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
+#define mmDIG5_HDMI_CONTROL 0x2571
+#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
+#define mmDIG5_HDMI_STATUS 0x2572
+#define mmDIG5_HDMI_STATUS_BASE_IDX 2
+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2573
+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2574
+#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2575
+#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2576
+#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2577
+#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x2578
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
+#define mmDIG5_AFMT_INTERRUPT_STATUS 0x2579
+#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDIG5_HDMI_GC 0x257b
+#define mmDIG5_HDMI_GC_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x257c
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_0 0x257d
+#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_1 0x257e
+#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_2 0x257f
+#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_3 0x2580
+#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC1_4 0x2581
+#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC2_0 0x2582
+#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC2_1 0x2583
+#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC2_2 0x2584
+#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
+#define mmDIG5_AFMT_ISRC2_3 0x2585
+#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x2586
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x2587
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
+#define mmDIG5_HDMI_DB_CONTROL 0x2588
+#define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2
+#define mmDIG5_DME_CONTROL 0x2589
+#define mmDIG5_DME_CONTROL_BASE_IDX 2
+#define mmDIG5_AFMT_MPEG_INFO0 0x258a
+#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
+#define mmDIG5_AFMT_MPEG_INFO1 0x258b
+#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_HDR 0x258c
+#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_0 0x258d
+#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_1 0x258e
+#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_2 0x258f
+#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_3 0x2590
+#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_4 0x2591
+#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_5 0x2592
+#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_6 0x2593
+#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
+#define mmDIG5_AFMT_GENERIC_7 0x2594
+#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x2595
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_32_0 0x2596
+#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_32_1 0x2597
+#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_44_0 0x2598
+#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_44_1 0x2599
+#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_48_0 0x259a
+#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_48_1 0x259b
+#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_STATUS_0 0x259c
+#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
+#define mmDIG5_HDMI_ACR_STATUS_1 0x259d
+#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_INFO0 0x259e
+#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_INFO1 0x259f
+#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
+#define mmDIG5_AFMT_60958_0 0x25a0
+#define mmDIG5_AFMT_60958_0_BASE_IDX 2
+#define mmDIG5_AFMT_60958_1 0x25a1
+#define mmDIG5_AFMT_60958_1_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x25a2
+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
+#define mmDIG5_AFMT_RAMP_CONTROL0 0x25a3
+#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
+#define mmDIG5_AFMT_RAMP_CONTROL1 0x25a4
+#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
+#define mmDIG5_AFMT_RAMP_CONTROL2 0x25a5
+#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
+#define mmDIG5_AFMT_RAMP_CONTROL3 0x25a6
+#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
+#define mmDIG5_AFMT_60958_2 0x25a7
+#define mmDIG5_AFMT_60958_2_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x25a8
+#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
+#define mmDIG5_AFMT_STATUS 0x25a9
+#define mmDIG5_AFMT_STATUS_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x25aa
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x25ab
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
+#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x25ac
+#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x25ad
+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
+#define mmDIG5_DIG_BE_CNTL 0x25af
+#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
+#define mmDIG5_DIG_BE_EN_CNTL 0x25b0
+#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
+#define mmDIG5_TMDS_CNTL 0x25d3
+#define mmDIG5_TMDS_CNTL_BASE_IDX 2
+#define mmDIG5_TMDS_CONTROL_CHAR 0x25d4
+#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
+#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d5
+#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25d6
+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25d7
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25d8
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
+#define mmDIG5_TMDS_CTL_BITS 0x25da
+#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
+#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25db
+#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
+#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR 0x25dc
+#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25dd
+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25de
+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
+#define mmDIG5_DIG_VERSION 0x25e0
+#define mmDIG5_DIG_VERSION_BASE_IDX 2
+#define mmDIG5_DIG_LANE_ENABLE 0x25e1
+#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
+#define mmDIG5_AFMT_CNTL 0x25e6
+#define mmDIG5_AFMT_CNTL_BASE_IDX 2
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL1 0x25e7
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5 0x25f6
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
+#define mmDIG5_FORCE_DIG_DISABLE 0x25f7
+#define mmDIG5_FORCE_DIG_DISABLE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dio_dp5_dispdec
+// base address: 0x1400
+#define mmDP5_DP_LINK_CNTL 0x2608
+#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
+#define mmDP5_DP_PIXEL_FORMAT 0x2609
+#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
+#define mmDP5_DP_MSA_COLORIMETRY 0x260a
+#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
+#define mmDP5_DP_CONFIG 0x260b
+#define mmDP5_DP_CONFIG_BASE_IDX 2
+#define mmDP5_DP_VID_STREAM_CNTL 0x260c
+#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
+#define mmDP5_DP_STEER_FIFO 0x260d
+#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
+#define mmDP5_DP_MSA_MISC 0x260e
+#define mmDP5_DP_MSA_MISC_BASE_IDX 2
+#define mmDP5_DP_VID_TIMING 0x2610
+#define mmDP5_DP_VID_TIMING_BASE_IDX 2
+#define mmDP5_DP_VID_N 0x2611
+#define mmDP5_DP_VID_N_BASE_IDX 2
+#define mmDP5_DP_VID_M 0x2612
+#define mmDP5_DP_VID_M_BASE_IDX 2
+#define mmDP5_DP_LINK_FRAMING_CNTL 0x2613
+#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
+#define mmDP5_DP_HBR2_EYE_PATTERN 0x2614
+#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
+#define mmDP5_DP_VID_MSA_VBID 0x2615
+#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
+#define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616
+#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_CNTL 0x2617
+#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618
+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
+#define mmDP5_DP_DPHY_SYM0 0x2619
+#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
+#define mmDP5_DP_DPHY_SYM1 0x261a
+#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
+#define mmDP5_DP_DPHY_SYM2 0x261b
+#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
+#define mmDP5_DP_DPHY_8B10B_CNTL 0x261c
+#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_PRBS_CNTL 0x261d
+#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e
+#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_EN 0x261f
+#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_CNTL 0x2620
+#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_RESULT 0x2621
+#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622
+#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623
+#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
+#define mmDP5_DP_DPHY_FAST_TRAINING 0x2624
+#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625
+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL 0x262b
+#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL1 0x262c
+#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
+#define mmDP5_DP_SEC_FRAMING1 0x262d
+#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
+#define mmDP5_DP_SEC_FRAMING2 0x262e
+#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
+#define mmDP5_DP_SEC_FRAMING3 0x262f
+#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
+#define mmDP5_DP_SEC_FRAMING4 0x2630
+#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
+#define mmDP5_DP_SEC_AUD_N 0x2631
+#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
+#define mmDP5_DP_SEC_AUD_N_READBACK 0x2632
+#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
+#define mmDP5_DP_SEC_AUD_M 0x2633
+#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
+#define mmDP5_DP_SEC_AUD_M_READBACK 0x2634
+#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
+#define mmDP5_DP_SEC_TIMESTAMP 0x2635
+#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
+#define mmDP5_DP_SEC_PACKET_CNTL 0x2636
+#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
+#define mmDP5_DP_MSE_RATE_CNTL 0x2637
+#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
+#define mmDP5_DP_MSE_RATE_UPDATE 0x2639
+#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT0 0x263a
+#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT1 0x263b
+#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT2 0x263c
+#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT_UPDATE 0x263d
+#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
+#define mmDP5_DP_MSE_LINK_TIMING 0x263e
+#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
+#define mmDP5_DP_MSE_MISC_CNTL 0x263f
+#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644
+#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
+#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645
+#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT0_STATUS 0x2647
+#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT1_STATUS 0x2648
+#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
+#define mmDP5_DP_MSE_SAT2_STATUS 0x2649
+#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
+#define mmDP5_DP_MSA_TIMING_PARAM1 0x264c
+#define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2
+#define mmDP5_DP_MSA_TIMING_PARAM2 0x264d
+#define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2
+#define mmDP5_DP_MSA_TIMING_PARAM3 0x264e
+#define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2
+#define mmDP5_DP_MSA_TIMING_PARAM4 0x264f
+#define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2
+#define mmDP5_DP_MSO_CNTL 0x2650
+#define mmDP5_DP_MSO_CNTL_BASE_IDX 2
+#define mmDP5_DP_MSO_CNTL1 0x2651
+#define mmDP5_DP_MSO_CNTL1_BASE_IDX 2
+#define mmDP5_DP_DSC_CNTL 0x2652
+#define mmDP5_DP_DSC_CNTL_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL2 0x2653
+#define mmDP5_DP_SEC_CNTL2_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL3 0x2654
+#define mmDP5_DP_SEC_CNTL3_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL4 0x2655
+#define mmDP5_DP_SEC_CNTL4_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL5 0x2656
+#define mmDP5_DP_SEC_CNTL5_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL6 0x2657
+#define mmDP5_DP_SEC_CNTL6_BASE_IDX 2
+#define mmDP5_DP_SEC_CNTL7 0x2658
+#define mmDP5_DP_SEC_CNTL7_BASE_IDX 2
+#define mmDP5_DP_DB_CNTL 0x2659
+#define mmDP5_DP_DB_CNTL_BASE_IDX 2
+#define mmDP5_DP_MSA_VBID_MISC 0x265a
+#define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2
+#define mmDP5_DP_SEC_METADATA_TRANSMISSION 0x265b
+#define mmDP5_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
+#define mmDP5_DP_DSC_BYTES_PER_PIXEL 0x265c
+#define mmDP5_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
+#define mmDP5_DP_ALPM_CNTL 0x265d
+#define mmDP5_DP_ALPM_CNTL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+// base address: 0x0
+#define mmDC_GENERICA 0x2868
+#define mmDC_GENERICA_BASE_IDX 2
+#define mmDC_GENERICB 0x2869
+#define mmDC_GENERICB_BASE_IDX 2
+#define mmDC_REF_CLK_CNTL 0x286b
+#define mmDC_REF_CLK_CNTL_BASE_IDX 2
+#define mmUNIPHYA_LINK_CNTL 0x286d
+#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYB_LINK_CNTL 0x286f
+#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYC_LINK_CNTL 0x2871
+#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
+#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYD_LINK_CNTL 0x2873
+#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
+#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYE_LINK_CNTL 0x2875
+#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
+#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmUNIPHYF_LINK_CNTL 0x2877
+#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
+#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878
+#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
+#define mmDCIO_WRCMD_DELAY 0x287e
+#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
+#define mmDC_PINSTRAPS 0x2880
+#define mmDC_PINSTRAPS_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_CNTL 0x2883
+#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_STATE 0x2884
+#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_REF_DIV 0x2885
+#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_DELAY1 0x2886
+#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
+#define mmLVTMA_PWRSEQ_DELAY2 0x2887
+#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
+#define mmBL_PWM_CNTL 0x2888
+#define mmBL_PWM_CNTL_BASE_IDX 2
+#define mmBL_PWM_CNTL2 0x2889
+#define mmBL_PWM_CNTL2_BASE_IDX 2
+#define mmBL_PWM_PERIOD_CNTL 0x288a
+#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
+#define mmBL_PWM_GRP1_REG_LOCK 0x288b
+#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
+#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c
+#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
+#define mmDCIO_CLOCK_CNTL 0x2895
+#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
+#define mmDCIO_SOFT_RESET 0x289e
+#define mmDCIO_SOFT_RESET_BASE_IDX 2
+#define mmAUXP_IMPCAL 0x28a3
+#define mmAUXP_IMPCAL_BASE_IDX 2
+#define mmAUXN_IMPCAL 0x28a4
+#define mmAUXN_IMPCAL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define mmDC_GPIO_GENERIC_MASK 0x28c8
+#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
+#define mmDC_GPIO_GENERIC_A 0x28c9
+#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
+#define mmDC_GPIO_GENERIC_EN 0x28ca
+#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
+#define mmDC_GPIO_GENERIC_Y 0x28cb
+#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC1_MASK 0x28d0
+#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC1_A 0x28d1
+#define mmDC_GPIO_DDC1_A_BASE_IDX 2
+#define mmDC_GPIO_DDC1_EN 0x28d2
+#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC1_Y 0x28d3
+#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC2_MASK 0x28d4
+#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC2_A 0x28d5
+#define mmDC_GPIO_DDC2_A_BASE_IDX 2
+#define mmDC_GPIO_DDC2_EN 0x28d6
+#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC2_Y 0x28d7
+#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC3_MASK 0x28d8
+#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC3_A 0x28d9
+#define mmDC_GPIO_DDC3_A_BASE_IDX 2
+#define mmDC_GPIO_DDC3_EN 0x28da
+#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC3_Y 0x28db
+#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC4_MASK 0x28dc
+#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC4_A 0x28dd
+#define mmDC_GPIO_DDC4_A_BASE_IDX 2
+#define mmDC_GPIO_DDC4_EN 0x28de
+#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC4_Y 0x28df
+#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC5_MASK 0x28e0
+#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC5_A 0x28e1
+#define mmDC_GPIO_DDC5_A_BASE_IDX 2
+#define mmDC_GPIO_DDC5_EN 0x28e2
+#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC5_Y 0x28e3
+#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
+#define mmDC_GPIO_DDC6_MASK 0x28e4
+#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDC6_A 0x28e5
+#define mmDC_GPIO_DDC6_A_BASE_IDX 2
+#define mmDC_GPIO_DDC6_EN 0x28e6
+#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
+#define mmDC_GPIO_DDC6_Y 0x28e7
+#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
+#define mmDC_GPIO_DDCVGA_MASK 0x28e8
+#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
+#define mmDC_GPIO_DDCVGA_A 0x28e9
+#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
+#define mmDC_GPIO_DDCVGA_EN 0x28ea
+#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
+#define mmDC_GPIO_DDCVGA_Y 0x28eb
+#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
+#define mmDC_GPIO_GENLK_MASK 0x28f0
+#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
+#define mmDC_GPIO_GENLK_A 0x28f1
+#define mmDC_GPIO_GENLK_A_BASE_IDX 2
+#define mmDC_GPIO_GENLK_EN 0x28f2
+#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
+#define mmDC_GPIO_GENLK_Y 0x28f3
+#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
+#define mmDC_GPIO_HPD_MASK 0x28f4
+#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
+#define mmDC_GPIO_HPD_A 0x28f5
+#define mmDC_GPIO_HPD_A_BASE_IDX 2
+#define mmDC_GPIO_HPD_EN 0x28f6
+#define mmDC_GPIO_HPD_EN_BASE_IDX 2
+#define mmDC_GPIO_HPD_Y 0x28f7
+#define mmDC_GPIO_HPD_Y_BASE_IDX 2
+#define mmDC_GPIO_PWRSEQ_MASK 0x28f8
+#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
+#define mmDC_GPIO_PWRSEQ_A 0x28f9
+#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
+#define mmDC_GPIO_PWRSEQ_EN 0x28fa
+#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
+#define mmDC_GPIO_PWRSEQ_Y 0x28fb
+#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
+#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc
+#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
+#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd
+#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
+#define mmPHY_AUX_CNTL 0x28ff
+#define mmPHY_AUX_CNTL_BASE_IDX 2
+#define mmDC_GPIO_TX12_EN 0x2915
+#define mmDC_GPIO_TX12_EN_BASE_IDX 2
+#define mmDC_GPIO_AUX_CTRL_0 0x2916
+#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
+#define mmDC_GPIO_AUX_CTRL_1 0x2917
+#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
+#define mmDC_GPIO_AUX_CTRL_2 0x2918
+#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
+#define mmDC_GPIO_RXEN 0x2919
+#define mmDC_GPIO_RXEN_BASE_IDX 2
+#define mmDC_GPIO_PULLUPEN 0x291a
+#define mmDC_GPIO_PULLUPEN_BASE_IDX 2
+#define mmDC_GPIO_AUX_CTRL_3 0x291b
+#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2
+#define mmDC_GPIO_AUX_CTRL_4 0x291c
+#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2
+#define mmDC_GPIO_AUX_CTRL_5 0x291d
+#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2
+#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e
+#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
+// base address: 0x0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
+// base address: 0xd80
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy5_dispdec
+// base address: 0x10e0
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2d60
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2d61
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2d62
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2d63
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x2d64
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x2d65
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x2d66
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x2d67
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x2d68
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x2d69
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2d6a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2d6b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2d6c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2d6d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2d6e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2d6f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2d70
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2d71
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2d72
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2d73
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x2d74
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x2d75
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x2d76
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x2d77
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x2d78
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x2d79
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2d7a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2d7b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2d7c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2d7d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2d7e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2d7f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2d80
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2d81
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2d82
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2d83
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x2d84
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x2d85
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x2d86
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x2d87
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x2d88
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x2d89
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2d8a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2d8b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2d8c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2d8d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2d8e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2d8f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy6_dispdec
+// base address: 0x1440
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x2e38
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x2e39
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x2e3a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x2e3b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x2e3c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x2e3d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x2e3e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x2e3f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x2e40
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x2e41
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x2e42
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x2e43
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x2e44
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x2e45
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x2e46
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x2e47
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x2e48
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x2e49
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2e4a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2e4b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2e4c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2e4d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2e4e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2e4f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2e50
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2e51
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2e52
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2e53
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x2e54
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x2e55
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x2e56
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x2e57
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x2e58
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x2e59
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2e5a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2e5b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2e5c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2e5d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2e5e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2e5f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2e60
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2e61
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2e62
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2e63
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x2e64
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x2e65
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x2e66
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x2e67
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+// base address: 0x0
+#define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000
+#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2
+#define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001
+#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+// base address: 0x0
+#define mmDSCCIF0_DSCCIF_CONFIG0 0x3005
+#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2
+#define mmDSCCIF0_DSCCIF_CONFIG1 0x3006
+#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+// base address: 0x0
+#define mmDSCC0_DSCC_CONFIG0 0x300a
+#define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2
+#define mmDSCC0_DSCC_CONFIG1 0x300b
+#define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2
+#define mmDSCC0_DSCC_STATUS 0x300c
+#define mmDSCC0_DSCC_STATUS_BASE_IDX 2
+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d
+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG0 0x300e
+#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG1 0x300f
+#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG2 0x3010
+#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG3 0x3011
+#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG4 0x3012
+#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG5 0x3013
+#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG6 0x3014
+#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG7 0x3015
+#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG8 0x3016
+#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG9 0x3017
+#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG10 0x3018
+#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG11 0x3019
+#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG12 0x301a
+#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG13 0x301b
+#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG14 0x301c
+#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG15 0x301d
+#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG16 0x301e
+#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG17 0x301f
+#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG18 0x3020
+#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG19 0x3021
+#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG20 0x3022
+#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG21 0x3023
+#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2
+#define mmDSCC0_DSCC_PPS_CONFIG22 0x3024
+#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2
+#define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025
+#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c
+#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
+#define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d
+#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e
+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f
+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030
+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031
+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a
+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc140
+#define mmDC_PERFMON21_PERFCOUNTER_CNTL 0x3050
+#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON21_PERFCOUNTER_CNTL2 0x3051
+#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON21_PERFCOUNTER_STATE 0x3052
+#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON21_PERFMON_CNTL 0x3053
+#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON21_PERFMON_CNTL2 0x3054
+#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x3055
+#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON21_PERFMON_CVALUE_LOW 0x3056
+#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON21_PERFMON_HI 0x3057
+#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON21_PERFMON_LOW 0x3058
+#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+// base address: 0x170
+#define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c
+#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2
+#define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d
+#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+// base address: 0x170
+#define mmDSCCIF1_DSCCIF_CONFIG0 0x3061
+#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2
+#define mmDSCCIF1_DSCCIF_CONFIG1 0x3062
+#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+// base address: 0x170
+#define mmDSCC1_DSCC_CONFIG0 0x3066
+#define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2
+#define mmDSCC1_DSCC_CONFIG1 0x3067
+#define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2
+#define mmDSCC1_DSCC_STATUS 0x3068
+#define mmDSCC1_DSCC_STATUS_BASE_IDX 2
+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069
+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG0 0x306a
+#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG1 0x306b
+#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG2 0x306c
+#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG3 0x306d
+#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG4 0x306e
+#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG5 0x306f
+#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG6 0x3070
+#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG7 0x3071
+#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG8 0x3072
+#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG9 0x3073
+#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG10 0x3074
+#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG11 0x3075
+#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG12 0x3076
+#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG13 0x3077
+#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG14 0x3078
+#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG15 0x3079
+#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG16 0x307a
+#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG17 0x307b
+#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG18 0x307c
+#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG19 0x307d
+#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG20 0x307e
+#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG21 0x307f
+#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2
+#define mmDSCC1_DSCC_PPS_CONFIG22 0x3080
+#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2
+#define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081
+#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088
+#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
+#define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089
+#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a
+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b
+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c
+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d
+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096
+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc2b0
+#define mmDC_PERFMON22_PERFCOUNTER_CNTL 0x30ac
+#define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON22_PERFCOUNTER_CNTL2 0x30ad
+#define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON22_PERFCOUNTER_STATE 0x30ae
+#define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON22_PERFMON_CNTL 0x30af
+#define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON22_PERFMON_CNTL2 0x30b0
+#define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x30b1
+#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON22_PERFMON_CVALUE_LOW 0x30b2
+#define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON22_PERFMON_HI 0x30b3
+#define mmDC_PERFMON22_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON22_PERFMON_LOW 0x30b4
+#define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+// base address: 0x2e0
+#define mmDSC_TOP2_DSC_TOP_CONTROL 0x30b8
+#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2
+#define mmDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9
+#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+// base address: 0x2e0
+#define mmDSCCIF2_DSCCIF_CONFIG0 0x30bd
+#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2
+#define mmDSCCIF2_DSCCIF_CONFIG1 0x30be
+#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+// base address: 0x2e0
+#define mmDSCC2_DSCC_CONFIG0 0x30c2
+#define mmDSCC2_DSCC_CONFIG0_BASE_IDX 2
+#define mmDSCC2_DSCC_CONFIG1 0x30c3
+#define mmDSCC2_DSCC_CONFIG1_BASE_IDX 2
+#define mmDSCC2_DSCC_STATUS 0x30c4
+#define mmDSCC2_DSCC_STATUS_BASE_IDX 2
+#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5
+#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG0 0x30c6
+#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG1 0x30c7
+#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG2 0x30c8
+#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG3 0x30c9
+#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG4 0x30ca
+#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG5 0x30cb
+#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG6 0x30cc
+#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG7 0x30cd
+#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG8 0x30ce
+#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG9 0x30cf
+#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG10 0x30d0
+#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG11 0x30d1
+#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG12 0x30d2
+#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG13 0x30d3
+#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG14 0x30d4
+#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG15 0x30d5
+#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG16 0x30d6
+#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG17 0x30d7
+#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG18 0x30d8
+#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG19 0x30d9
+#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG20 0x30da
+#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG21 0x30db
+#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2
+#define mmDSCC2_DSCC_PPS_CONFIG22 0x30dc
+#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2
+#define mmDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd
+#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de
+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df
+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0
+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1
+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2
+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3
+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4
+#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
+#define mmDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5
+#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
+#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6
+#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7
+#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8
+#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9
+#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2
+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc420
+#define mmDC_PERFMON23_PERFCOUNTER_CNTL 0x3108
+#define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON23_PERFCOUNTER_CNTL2 0x3109
+#define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON23_PERFCOUNTER_STATE 0x310a
+#define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON23_PERFMON_CNTL 0x310b
+#define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON23_PERFMON_CNTL2 0x310c
+#define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x310d
+#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON23_PERFMON_CVALUE_LOW 0x310e
+#define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON23_PERFMON_HI 0x310f
+#define mmDC_PERFMON23_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON23_PERFMON_LOW 0x3110
+#define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
+// base address: 0x450
+#define mmDSC_TOP3_DSC_TOP_CONTROL 0x3114
+#define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2
+#define mmDSC_TOP3_DSC_DEBUG_CONTROL 0x3115
+#define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
+// base address: 0x450
+#define mmDSCCIF3_DSCCIF_CONFIG0 0x3119
+#define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2
+#define mmDSCCIF3_DSCCIF_CONFIG1 0x311a
+#define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
+// base address: 0x450
+#define mmDSCC3_DSCC_CONFIG0 0x311e
+#define mmDSCC3_DSCC_CONFIG0_BASE_IDX 2
+#define mmDSCC3_DSCC_CONFIG1 0x311f
+#define mmDSCC3_DSCC_CONFIG1_BASE_IDX 2
+#define mmDSCC3_DSCC_STATUS 0x3120
+#define mmDSCC3_DSCC_STATUS_BASE_IDX 2
+#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121
+#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG0 0x3122
+#define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG1 0x3123
+#define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG2 0x3124
+#define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG3 0x3125
+#define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG4 0x3126
+#define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG5 0x3127
+#define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG6 0x3128
+#define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG7 0x3129
+#define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG8 0x312a
+#define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG9 0x312b
+#define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG10 0x312c
+#define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG11 0x312d
+#define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG12 0x312e
+#define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG13 0x312f
+#define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG14 0x3130
+#define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG15 0x3131
+#define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG16 0x3132
+#define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG17 0x3133
+#define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG18 0x3134
+#define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG19 0x3135
+#define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG20 0x3136
+#define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG21 0x3137
+#define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2
+#define mmDSCC3_DSCC_PPS_CONFIG22 0x3138
+#define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2
+#define mmDSCC3_DSCC_MEM_POWER_CONTROL 0x3139
+#define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a
+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b
+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c
+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d
+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e
+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f
+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC3_DSCC_MAX_ABS_ERROR0 0x3140
+#define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
+#define mmDSCC3_DSCC_MAX_ABS_ERROR1 0x3141
+#define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
+#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142
+#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143
+#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144
+#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145
+#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146
+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147
+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148
+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149
+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e
+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc590
+#define mmDC_PERFMON24_PERFCOUNTER_CNTL 0x3164
+#define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON24_PERFCOUNTER_CNTL2 0x3165
+#define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON24_PERFCOUNTER_STATE 0x3166
+#define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON24_PERFMON_CNTL 0x3167
+#define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON24_PERFMON_CNTL2 0x3168
+#define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC 0x3169
+#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON24_PERFMON_CVALUE_LOW 0x316a
+#define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON24_PERFMON_HI 0x316b
+#define mmDC_PERFMON24_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON24_PERFMON_LOW 0x316c
+#define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
+// base address: 0x5c0
+#define mmDSC_TOP4_DSC_TOP_CONTROL 0x3170
+#define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX 2
+#define mmDSC_TOP4_DSC_DEBUG_CONTROL 0x3171
+#define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
+// base address: 0x5c0
+#define mmDSCCIF4_DSCCIF_CONFIG0 0x3175
+#define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX 2
+#define mmDSCCIF4_DSCCIF_CONFIG1 0x3176
+#define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
+// base address: 0x5c0
+#define mmDSCC4_DSCC_CONFIG0 0x317a
+#define mmDSCC4_DSCC_CONFIG0_BASE_IDX 2
+#define mmDSCC4_DSCC_CONFIG1 0x317b
+#define mmDSCC4_DSCC_CONFIG1_BASE_IDX 2
+#define mmDSCC4_DSCC_STATUS 0x317c
+#define mmDSCC4_DSCC_STATUS_BASE_IDX 2
+#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS 0x317d
+#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG0 0x317e
+#define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG1 0x317f
+#define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG2 0x3180
+#define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG3 0x3181
+#define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG4 0x3182
+#define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG5 0x3183
+#define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG6 0x3184
+#define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG7 0x3185
+#define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG8 0x3186
+#define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG9 0x3187
+#define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG10 0x3188
+#define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG11 0x3189
+#define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG12 0x318a
+#define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG13 0x318b
+#define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG14 0x318c
+#define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG15 0x318d
+#define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG16 0x318e
+#define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG17 0x318f
+#define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG18 0x3190
+#define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG19 0x3191
+#define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG20 0x3192
+#define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG21 0x3193
+#define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX 2
+#define mmDSCC4_DSCC_PPS_CONFIG22 0x3194
+#define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX 2
+#define mmDSCC4_DSCC_MEM_POWER_CONTROL 0x3195
+#define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3196
+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3197
+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3198
+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3199
+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER 0x319a
+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER 0x319b
+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC4_DSCC_MAX_ABS_ERROR0 0x319c
+#define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
+#define mmDSCC4_DSCC_MAX_ABS_ERROR1 0x319d
+#define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
+#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x319e
+#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x319f
+#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31a0
+#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31a1
+#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31a2
+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31a3
+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x31a4
+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5
+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE 0x31aa
+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc700
+#define mmDC_PERFMON25_PERFCOUNTER_CNTL 0x31c0
+#define mmDC_PERFMON25_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON25_PERFCOUNTER_CNTL2 0x31c1
+#define mmDC_PERFMON25_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON25_PERFCOUNTER_STATE 0x31c2
+#define mmDC_PERFMON25_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON25_PERFMON_CNTL 0x31c3
+#define mmDC_PERFMON25_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON25_PERFMON_CNTL2 0x31c4
+#define mmDC_PERFMON25_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC 0x31c5
+#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON25_PERFMON_CVALUE_LOW 0x31c6
+#define mmDC_PERFMON25_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON25_PERFMON_HI 0x31c7
+#define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON25_PERFMON_LOW 0x31c8
+#define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec
+// base address: 0x730
+#define mmDSC_TOP5_DSC_TOP_CONTROL 0x31cc
+#define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX 2
+#define mmDSC_TOP5_DSC_DEBUG_CONTROL 0x31cd
+#define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec
+// base address: 0x730
+#define mmDSCCIF5_DSCCIF_CONFIG0 0x31d1
+#define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX 2
+#define mmDSCCIF5_DSCCIF_CONFIG1 0x31d2
+#define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec
+// base address: 0x730
+#define mmDSCC5_DSCC_CONFIG0 0x31d6
+#define mmDSCC5_DSCC_CONFIG0_BASE_IDX 2
+#define mmDSCC5_DSCC_CONFIG1 0x31d7
+#define mmDSCC5_DSCC_CONFIG1_BASE_IDX 2
+#define mmDSCC5_DSCC_STATUS 0x31d8
+#define mmDSCC5_DSCC_STATUS_BASE_IDX 2
+#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS 0x31d9
+#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG0 0x31da
+#define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG1 0x31db
+#define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG2 0x31dc
+#define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG3 0x31dd
+#define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG4 0x31de
+#define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG5 0x31df
+#define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG6 0x31e0
+#define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG7 0x31e1
+#define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG8 0x31e2
+#define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG9 0x31e3
+#define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG10 0x31e4
+#define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG11 0x31e5
+#define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG12 0x31e6
+#define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG13 0x31e7
+#define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG14 0x31e8
+#define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG15 0x31e9
+#define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG16 0x31ea
+#define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG17 0x31eb
+#define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG18 0x31ec
+#define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG19 0x31ed
+#define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG20 0x31ee
+#define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG21 0x31ef
+#define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX 2
+#define mmDSCC5_DSCC_PPS_CONFIG22 0x31f0
+#define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX 2
+#define mmDSCC5_DSCC_MEM_POWER_CONTROL 0x31f1
+#define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER 0x31f2
+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER 0x31f3
+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER 0x31f4
+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER 0x31f5
+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER 0x31f6
+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER 0x31f7
+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
+#define mmDSCC5_DSCC_MAX_ABS_ERROR0 0x31f8
+#define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
+#define mmDSCC5_DSCC_MAX_ABS_ERROR1 0x31f9
+#define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
+#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x31fa
+#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x31fb
+#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31fc
+#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31fd
+#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31fe
+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31ff
+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3200
+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201
+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
+#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE 0x3206
+#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc870
+#define mmDC_PERFMON26_PERFCOUNTER_CNTL 0x321c
+#define mmDC_PERFMON26_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON26_PERFCOUNTER_CNTL2 0x321d
+#define mmDC_PERFMON26_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON26_PERFCOUNTER_STATE 0x321e
+#define mmDC_PERFMON26_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON26_PERFMON_CNTL 0x321f
+#define mmDC_PERFMON26_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON26_PERFMON_CNTL2 0x3220
+#define mmDC_PERFMON26_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC 0x3221
+#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON26_PERFMON_CVALUE_LOW 0x3222
+#define mmDC_PERFMON26_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON26_PERFMON_HI 0x3223
+#define mmDC_PERFMON26_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON26_PERFMON_LOW 0x3224
+#define mmDC_PERFMON26_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+// base address: 0x0
+#define mmDMCUB_REGION0_OFFSET 0x3238
+#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION0_OFFSET_HIGH 0x3239
+#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION1_OFFSET 0x323a
+#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION1_OFFSET_HIGH 0x323b
+#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION2_OFFSET 0x323c
+#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION2_OFFSET_HIGH 0x323d
+#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION4_OFFSET 0x3240
+#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION4_OFFSET_HIGH 0x3241
+#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION5_OFFSET 0x3242
+#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION5_OFFSET_HIGH 0x3243
+#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION6_OFFSET 0x3244
+#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION6_OFFSET_HIGH 0x3245
+#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION7_OFFSET 0x3246
+#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION7_OFFSET_HIGH 0x3247
+#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION0_TOP_ADDRESS 0x3248
+#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION1_TOP_ADDRESS 0x3249
+#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION2_TOP_ADDRESS 0x324a
+#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION4_TOP_ADDRESS 0x324b
+#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION5_TOP_ADDRESS 0x324c
+#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION6_TOP_ADDRESS 0x324d
+#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION7_TOP_ADDRESS 0x324e
+#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x324f
+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x3250
+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x3251
+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x3252
+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x3253
+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x3254
+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x3255
+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x3256
+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x3257
+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x3258
+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x3259
+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x325a
+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x325b
+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x325c
+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x325d
+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x325e
+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2
+#define mmDMCUB_REGION3_CW0_OFFSET 0x325f
+#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x3260
+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION3_CW1_OFFSET 0x3261
+#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x3262
+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION3_CW2_OFFSET 0x3263
+#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x3264
+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION3_CW3_OFFSET 0x3265
+#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x3266
+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION3_CW4_OFFSET 0x3267
+#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x3268
+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION3_CW5_OFFSET 0x3269
+#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x326a
+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION3_CW6_OFFSET 0x326b
+#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x326c
+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_REGION3_CW7_OFFSET 0x326d
+#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2
+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x326e
+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2
+#define mmDMCUB_INTERRUPT_ENABLE 0x326f
+#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2
+#define mmDMCUB_INTERRUPT_ACK 0x3270
+#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2
+#define mmDMCUB_INTERRUPT_STATUS 0x3271
+#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDMCUB_INTERRUPT_TYPE 0x3272
+#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2
+#define mmDMCUB_EXT_INTERRUPT_STATUS 0x3273
+#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2
+#define mmDMCUB_EXT_INTERRUPT_CTXID 0x3274
+#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2
+#define mmDMCUB_EXT_INTERRUPT_ACK 0x3275
+#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2
+#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x3276
+#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2
+#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x3277
+#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2
+#define mmDMCUB_SEC_CNTL 0x3278
+#define mmDMCUB_SEC_CNTL_BASE_IDX 2
+#define mmDMCUB_MEM_CNTL 0x3279
+#define mmDMCUB_MEM_CNTL_BASE_IDX 2
+#define mmDMCUB_INBOX0_BASE_ADDRESS 0x327a
+#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_INBOX0_SIZE 0x327b
+#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2
+#define mmDMCUB_INBOX0_WPTR 0x327c
+#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2
+#define mmDMCUB_INBOX0_RPTR 0x327d
+#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2
+#define mmDMCUB_INBOX1_BASE_ADDRESS 0x327e
+#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_INBOX1_SIZE 0x327f
+#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2
+#define mmDMCUB_INBOX1_WPTR 0x3280
+#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2
+#define mmDMCUB_INBOX1_RPTR 0x3281
+#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2
+#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x3282
+#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_OUTBOX0_SIZE 0x3283
+#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2
+#define mmDMCUB_OUTBOX0_WPTR 0x3284
+#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2
+#define mmDMCUB_OUTBOX0_RPTR 0x3285
+#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2
+#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x3286
+#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2
+#define mmDMCUB_OUTBOX1_SIZE 0x3287
+#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2
+#define mmDMCUB_OUTBOX1_WPTR 0x3288
+#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2
+#define mmDMCUB_OUTBOX1_RPTR 0x3289
+#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2
+#define mmDMCUB_TIMER_TRIGGER0 0x328a
+#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2
+#define mmDMCUB_TIMER_TRIGGER1 0x328b
+#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2
+#define mmDMCUB_TIMER_WINDOW 0x328c
+#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2
+#define mmDMCUB_SCRATCH0 0x328d
+#define mmDMCUB_SCRATCH0_BASE_IDX 2
+#define mmDMCUB_SCRATCH1 0x328e
+#define mmDMCUB_SCRATCH1_BASE_IDX 2
+#define mmDMCUB_SCRATCH2 0x328f
+#define mmDMCUB_SCRATCH2_BASE_IDX 2
+#define mmDMCUB_SCRATCH3 0x3290
+#define mmDMCUB_SCRATCH3_BASE_IDX 2
+#define mmDMCUB_SCRATCH4 0x3291
+#define mmDMCUB_SCRATCH4_BASE_IDX 2
+#define mmDMCUB_SCRATCH5 0x3292
+#define mmDMCUB_SCRATCH5_BASE_IDX 2
+#define mmDMCUB_SCRATCH6 0x3293
+#define mmDMCUB_SCRATCH6_BASE_IDX 2
+#define mmDMCUB_SCRATCH7 0x3294
+#define mmDMCUB_SCRATCH7_BASE_IDX 2
+#define mmDMCUB_SCRATCH8 0x3295
+#define mmDMCUB_SCRATCH8_BASE_IDX 2
+#define mmDMCUB_SCRATCH9 0x3296
+#define mmDMCUB_SCRATCH9_BASE_IDX 2
+#define mmDMCUB_SCRATCH10 0x3297
+#define mmDMCUB_SCRATCH10_BASE_IDX 2
+#define mmDMCUB_SCRATCH11 0x3298
+#define mmDMCUB_SCRATCH11_BASE_IDX 2
+#define mmDMCUB_SCRATCH12 0x3299
+#define mmDMCUB_SCRATCH12_BASE_IDX 2
+#define mmDMCUB_SCRATCH13 0x329a
+#define mmDMCUB_SCRATCH13_BASE_IDX 2
+#define mmDMCUB_SCRATCH14 0x329b
+#define mmDMCUB_SCRATCH14_BASE_IDX 2
+#define mmDMCUB_SCRATCH15 0x329c
+#define mmDMCUB_SCRATCH15_BASE_IDX 2
+#define mmDMCUB_CNTL 0x32a0
+#define mmDMCUB_CNTL_BASE_IDX 2
+#define mmDMCUB_GPINT_DATAIN0 0x32a1
+#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2
+#define mmDMCUB_GPINT_DATAIN1 0x32a2
+#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2
+#define mmDMCUB_GPINT_DATAOUT 0x32a3
+#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2
+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x32a4
+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2
+#define mmDMCUB_LS_WAKE_INT_ENABLE 0x32a5
+#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2
+#define mmDMCUB_MEM_PWR_CNTL 0x32a6
+#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2
+#define mmDMCUB_TIMER_CURRENT 0x32a7
+#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2
+#define mmDMCUB_PROC_ID 0x32a9
+#define mmDMCUB_PROC_ID_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec
+// base address: 0xc6b8
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x3460
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x3461
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x3462
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x3463
+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x3464
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x3465
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x3466
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x3467
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x3468
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x3469
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x346a
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x346b
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x346c
+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x346d
+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x346e
+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x346f
+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x3470
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x3471
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x3472
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x3473
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x3474
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x3475
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x3476
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x3477
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x3478
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x3479
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x347a
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x347b
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x347c
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x347d
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x347e
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x347f
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x3480
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x3481
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x3482
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x3483
+#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x3484
+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x3485
+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x3486
+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x3487
+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x3489
+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x348a
+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x348b
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH 0x348c
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x348d
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH 0x348e
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x348f
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH 0x3490
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x3491
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH 0x3492
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION 0x3493
+#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION 0x3494
+#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION 0x3495
+#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION 0x3496
+#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp0_dispdec
+// base address: 0x0
+#define mmXFCP0_MMHUBBUB_XFC_CNTL 0x34a0
+#define mmXFCP0_MMHUBBUB_XFC_CNTL_BASE_IDX 2
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x34a1
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x34a2
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x34a3
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x34a4
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_CONFIG 0x34a5
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_SIZE 0x34a6
+#define mmXFCP0_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp1_dispdec
+// base address: 0x80
+#define mmXFCP1_MMHUBBUB_XFC_CNTL 0x34c0
+#define mmXFCP1_MMHUBBUB_XFC_CNTL_BASE_IDX 2
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x34c1
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x34c2
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x34c3
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x34c4
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_CONFIG 0x34c5
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_SIZE 0x34c6
+#define mmXFCP1_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp2_dispdec
+// base address: 0x100
+#define mmXFCP2_MMHUBBUB_XFC_CNTL 0x34e0
+#define mmXFCP2_MMHUBBUB_XFC_CNTL_BASE_IDX 2
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x34e1
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x34e2
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x34e3
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x34e4
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_CONFIG 0x34e5
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_SIZE 0x34e6
+#define mmXFCP2_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp3_dispdec
+// base address: 0x180
+#define mmXFCP3_MMHUBBUB_XFC_CNTL 0x3500
+#define mmXFCP3_MMHUBBUB_XFC_CNTL_BASE_IDX 2
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x3501
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x3502
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x3503
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x3504
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_CONFIG 0x3505
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_SIZE 0x3506
+#define mmXFCP3_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp4_dispdec
+// base address: 0x200
+#define mmXFCP4_MMHUBBUB_XFC_CNTL 0x3520
+#define mmXFCP4_MMHUBBUB_XFC_CNTL_BASE_IDX 2
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x3521
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x3522
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x3523
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x3524
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_CONFIG 0x3525
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_SIZE 0x3526
+#define mmXFCP4_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp5_dispdec
+// base address: 0x280
+#define mmXFCP5_MMHUBBUB_XFC_CNTL 0x3540
+#define mmXFCP5_MMHUBBUB_XFC_CNTL_BASE_IDX 2
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x3541
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x3542
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x3543
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x3544
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_CONFIG 0x3545
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_SIZE 0x3546
+#define mmXFCP5_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_mmhubbub_xfc_dispdec
+// base address: 0x0
+#define mmXFC_MEM_PWR_CNTL 0x35a0
+#define mmXFC_MEM_PWR_CNTL_BASE_IDX 2
+#define mmMMHUBBUB_XFC_XBUF_WR_SURF_CONFIG 0x35a1
+#define mmMMHUBBUB_XFC_XBUF_WR_SURF_CONFIG_BASE_IDX 2
+#define mmMMHUBBUB_XFC_XBUF_WR_CONFIG 0x35a2
+#define mmMMHUBBUB_XFC_XBUF_WR_CONFIG_BASE_IDX 2
+#define mmMMHUBBUB_XFC_IO_BACKPRESSURE_RELEASE_TIMER 0x35a3
+#define mmMMHUBBUB_XFC_IO_BACKPRESSURE_RELEASE_TIMER_BASE_IDX 2
+#define mmMMHUBBUB_XFC_GPU_CTRL 0x35a4
+#define mmMMHUBBUB_XFC_GPU_CTRL_BASE_IDX 2
+#define mmMMHUBBUB_XFC_XBUF_VM_CTRL 0x35a5
+#define mmMMHUBBUB_XFC_XBUF_VM_CTRL_BASE_IDX 2
+#define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_LSB 0x35a6
+#define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_LSB_BASE_IDX 2
+#define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_MSB 0x35a7
+#define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_MSB_BASE_IDX 2
+#define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_LSB 0x35a8
+#define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_LSB_BASE_IDX 2
+#define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_MSB 0x35a9
+#define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_MSB_BASE_IDX 2
+#define mmMMHUBBUB_XFC_GPU0_BASE_ADDR 0x35aa
+#define mmMMHUBBUB_XFC_GPU0_BASE_ADDR_BASE_IDX 2
+#define mmMMHUBBUB_XFC_GPU1_BASE_ADDR 0x35ab
+#define mmMMHUBBUB_XFC_GPU1_BASE_ADDR_BASE_IDX 2
+#define mmMMHUBBUB_XFC_GPU2_BASE_ADDR 0x35ac
+#define mmMMHUBBUB_XFC_GPU2_BASE_ADDR_BASE_IDX 2
+#define mmMMHUBBUB_XFC_GPU3_BASE_ADDR 0x35ad
+#define mmMMHUBBUB_XFC_GPU3_BASE_ADDR_BASE_IDX 2
+#define mmMMHUBBUB_XFCMON_CTRL 0x35ae
+#define mmMMHUBBUB_XFCMON_CTRL_BASE_IDX 2
+#define mmMMHUBBUB_XFCMON_TIMER 0x35af
+#define mmMMHUBBUB_XFCMON_TIMER_BASE_IDX 2
+#define mmMMHUBBUB_XFCMON_STAT_REQUESTS 0x35b0
+#define mmMMHUBBUB_XFCMON_STAT_REQUESTS_BASE_IDX 2
+#define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE 0x35b1
+#define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE_BASE_IDX 2
+#define mmMMHUBBUB_XFCMON_STAT_MAX_REQUESTS 0x35b2
+#define mmMMHUBBUB_XFCMON_STAT_MAX_REQUESTS_BASE_IDX 2
+#define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE_AT_MAX_REQUESTS 0x35b3
+#define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE_AT_MAX_REQUESTS_BASE_IDX 2
+#define mmMMHUBBUB_XFCMON_STAT_MAX_BACKPRESSURE 0x35b4
+#define mmMMHUBBUB_XFCMON_STAT_MAX_BACKPRESSURE_BASE_IDX 2
+#define mmMMHUBBUB_XFCMON_STAT_REQUESTS_AT_MAX_BACKPRESSURE 0x35b5
+#define mmMMHUBBUB_XFCMON_STAT_REQUESTS_AT_MAX_BACKPRESSURE_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp4_dispdec_dpp_top_dispdec
+// base address: 0xa42c
+#define mmDPP_TOP4_DPP_CONTROL 0x35d0
+#define mmDPP_TOP4_DPP_CONTROL_BASE_IDX 2
+#define mmDPP_TOP4_DPP_SOFT_RESET 0x35d1
+#define mmDPP_TOP4_DPP_SOFT_RESET_BASE_IDX 2
+#define mmDPP_TOP4_DPP_CRC_VAL_R_G 0x35d2
+#define mmDPP_TOP4_DPP_CRC_VAL_R_G_BASE_IDX 2
+#define mmDPP_TOP4_DPP_CRC_VAL_B_A 0x35d3
+#define mmDPP_TOP4_DPP_CRC_VAL_B_A_BASE_IDX 2
+#define mmDPP_TOP4_DPP_CRC_CTRL 0x35d4
+#define mmDPP_TOP4_DPP_CRC_CTRL_BASE_IDX 2
+#define mmDPP_TOP4_HOST_READ_CONTROL 0x35d5
+#define mmDPP_TOP4_HOST_READ_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp4_dispdec_cnvc_cfg_dispdec
+// base address: 0xa42c
+#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT 0x35da
+#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
+#define mmCNVC_CFG4_FORMAT_CONTROL 0x35db
+#define mmCNVC_CFG4_FORMAT_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG4_FCNV_FP_BIAS_R 0x35dc
+#define mmCNVC_CFG4_FCNV_FP_BIAS_R_BASE_IDX 2
+#define mmCNVC_CFG4_FCNV_FP_BIAS_G 0x35dd
+#define mmCNVC_CFG4_FCNV_FP_BIAS_G_BASE_IDX 2
+#define mmCNVC_CFG4_FCNV_FP_BIAS_B 0x35de
+#define mmCNVC_CFG4_FCNV_FP_BIAS_B_BASE_IDX 2
+#define mmCNVC_CFG4_FCNV_FP_SCALE_R 0x35df
+#define mmCNVC_CFG4_FCNV_FP_SCALE_R_BASE_IDX 2
+#define mmCNVC_CFG4_FCNV_FP_SCALE_G 0x35e0
+#define mmCNVC_CFG4_FCNV_FP_SCALE_G_BASE_IDX 2
+#define mmCNVC_CFG4_FCNV_FP_SCALE_B 0x35e1
+#define mmCNVC_CFG4_FCNV_FP_SCALE_B_BASE_IDX 2
+#define mmCNVC_CFG4_COLOR_KEYER_CONTROL 0x35e2
+#define mmCNVC_CFG4_COLOR_KEYER_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG4_COLOR_KEYER_ALPHA 0x35e3
+#define mmCNVC_CFG4_COLOR_KEYER_ALPHA_BASE_IDX 2
+#define mmCNVC_CFG4_COLOR_KEYER_RED 0x35e4
+#define mmCNVC_CFG4_COLOR_KEYER_RED_BASE_IDX 2
+#define mmCNVC_CFG4_COLOR_KEYER_GREEN 0x35e5
+#define mmCNVC_CFG4_COLOR_KEYER_GREEN_BASE_IDX 2
+#define mmCNVC_CFG4_COLOR_KEYER_BLUE 0x35e6
+#define mmCNVC_CFG4_COLOR_KEYER_BLUE_BASE_IDX 2
+#define mmCNVC_CFG4_ALPHA_2BIT_LUT 0x35e8
+#define mmCNVC_CFG4_ALPHA_2BIT_LUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp4_dispdec_cnvc_cur_dispdec
+// base address: 0xa42c
+#define mmCNVC_CUR4_CURSOR0_CONTROL 0x35eb
+#define mmCNVC_CUR4_CURSOR0_CONTROL_BASE_IDX 2
+#define mmCNVC_CUR4_CURSOR0_COLOR0 0x35ec
+#define mmCNVC_CUR4_CURSOR0_COLOR0_BASE_IDX 2
+#define mmCNVC_CUR4_CURSOR0_COLOR1 0x35ed
+#define mmCNVC_CUR4_CURSOR0_COLOR1_BASE_IDX 2
+#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS 0x35ee
+#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp4_dispdec_dscl_dispdec
+// base address: 0xa42c
+#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT 0x35f5
+#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
+#define mmDSCL4_SCL_COEF_RAM_TAP_DATA 0x35f6
+#define mmDSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmDSCL4_SCL_MODE 0x35f7
+#define mmDSCL4_SCL_MODE_BASE_IDX 2
+#define mmDSCL4_SCL_TAP_CONTROL 0x35f8
+#define mmDSCL4_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmDSCL4_DSCL_CONTROL 0x35f9
+#define mmDSCL4_DSCL_CONTROL_BASE_IDX 2
+#define mmDSCL4_DSCL_2TAP_CONTROL 0x35fa
+#define mmDSCL4_DSCL_2TAP_CONTROL_BASE_IDX 2
+#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x35fb
+#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x35fc
+#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL4_SCL_HORZ_FILTER_INIT 0x35fd
+#define mmDSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C 0x35fe
+#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL4_SCL_HORZ_FILTER_INIT_C 0x35ff
+#define mmDSCL4_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x3600
+#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL4_SCL_VERT_FILTER_INIT 0x3601
+#define mmDSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT 0x3602
+#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C 0x3603
+#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL4_SCL_VERT_FILTER_INIT_C 0x3604
+#define mmDSCL4_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C 0x3605
+#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+#define mmDSCL4_SCL_BLACK_OFFSET 0x3606
+#define mmDSCL4_SCL_BLACK_OFFSET_BASE_IDX 2
+#define mmDSCL4_DSCL_UPDATE 0x3607
+#define mmDSCL4_DSCL_UPDATE_BASE_IDX 2
+#define mmDSCL4_DSCL_AUTOCAL 0x3608
+#define mmDSCL4_DSCL_AUTOCAL_BASE_IDX 2
+#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x3609
+#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x360a
+#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmDSCL4_OTG_H_BLANK 0x360b
+#define mmDSCL4_OTG_H_BLANK_BASE_IDX 2
+#define mmDSCL4_OTG_V_BLANK 0x360c
+#define mmDSCL4_OTG_V_BLANK_BASE_IDX 2
+#define mmDSCL4_RECOUT_START 0x360d
+#define mmDSCL4_RECOUT_START_BASE_IDX 2
+#define mmDSCL4_RECOUT_SIZE 0x360e
+#define mmDSCL4_RECOUT_SIZE_BASE_IDX 2
+#define mmDSCL4_MPC_SIZE 0x360f
+#define mmDSCL4_MPC_SIZE_BASE_IDX 2
+#define mmDSCL4_LB_DATA_FORMAT 0x3610
+#define mmDSCL4_LB_DATA_FORMAT_BASE_IDX 2
+#define mmDSCL4_LB_MEMORY_CTRL 0x3611
+#define mmDSCL4_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmDSCL4_LB_V_COUNTER 0x3612
+#define mmDSCL4_LB_V_COUNTER_BASE_IDX 2
+#define mmDSCL4_DSCL_MEM_PWR_CTRL 0x3613
+#define mmDSCL4_DSCL_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDSCL4_DSCL_MEM_PWR_STATUS 0x3614
+#define mmDSCL4_DSCL_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDSCL4_OBUF_CONTROL 0x3615
+#define mmDSCL4_OBUF_CONTROL_BASE_IDX 2
+#define mmDSCL4_OBUF_MEM_PWR_CTRL 0x3616
+#define mmDSCL4_OBUF_MEM_PWR_CTRL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp4_dispdec_cm_dispdec
+// base address: 0xa42c
+#define mmCM4_CM_CONTROL 0x3625
+#define mmCM4_CM_CONTROL_BASE_IDX 2
+#define mmCM4_CM_ICSC_CONTROL 0x3626
+#define mmCM4_CM_ICSC_CONTROL_BASE_IDX 2
+#define mmCM4_CM_ICSC_C11_C12 0x3627
+#define mmCM4_CM_ICSC_C11_C12_BASE_IDX 2
+#define mmCM4_CM_ICSC_C13_C14 0x3628
+#define mmCM4_CM_ICSC_C13_C14_BASE_IDX 2
+#define mmCM4_CM_ICSC_C21_C22 0x3629
+#define mmCM4_CM_ICSC_C21_C22_BASE_IDX 2
+#define mmCM4_CM_ICSC_C23_C24 0x362a
+#define mmCM4_CM_ICSC_C23_C24_BASE_IDX 2
+#define mmCM4_CM_ICSC_C31_C32 0x362b
+#define mmCM4_CM_ICSC_C31_C32_BASE_IDX 2
+#define mmCM4_CM_ICSC_C33_C34 0x362c
+#define mmCM4_CM_ICSC_C33_C34_BASE_IDX 2
+#define mmCM4_CM_ICSC_B_C11_C12 0x362d
+#define mmCM4_CM_ICSC_B_C11_C12_BASE_IDX 2
+#define mmCM4_CM_ICSC_B_C13_C14 0x362e
+#define mmCM4_CM_ICSC_B_C13_C14_BASE_IDX 2
+#define mmCM4_CM_ICSC_B_C21_C22 0x362f
+#define mmCM4_CM_ICSC_B_C21_C22_BASE_IDX 2
+#define mmCM4_CM_ICSC_B_C23_C24 0x3630
+#define mmCM4_CM_ICSC_B_C23_C24_BASE_IDX 2
+#define mmCM4_CM_ICSC_B_C31_C32 0x3631
+#define mmCM4_CM_ICSC_B_C31_C32_BASE_IDX 2
+#define mmCM4_CM_ICSC_B_C33_C34 0x3632
+#define mmCM4_CM_ICSC_B_C33_C34_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_CONTROL 0x3633
+#define mmCM4_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_C11_C12 0x3634
+#define mmCM4_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_C13_C14 0x3635
+#define mmCM4_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_C21_C22 0x3636
+#define mmCM4_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_C23_C24 0x3637
+#define mmCM4_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_C31_C32 0x3638
+#define mmCM4_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_C33_C34 0x3639
+#define mmCM4_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_B_C11_C12 0x363a
+#define mmCM4_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_B_C13_C14 0x363b
+#define mmCM4_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_B_C21_C22 0x363c
+#define mmCM4_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_B_C23_C24 0x363d
+#define mmCM4_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_B_C31_C32 0x363e
+#define mmCM4_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
+#define mmCM4_CM_GAMUT_REMAP_B_C33_C34 0x363f
+#define mmCM4_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
+#define mmCM4_CM_BIAS_CR_R 0x3640
+#define mmCM4_CM_BIAS_CR_R_BASE_IDX 2
+#define mmCM4_CM_BIAS_Y_G_CB_B 0x3641
+#define mmCM4_CM_BIAS_Y_G_CB_B_BASE_IDX 2
+#define mmCM4_CM_DGAM_CONTROL 0x3642
+#define mmCM4_CM_DGAM_CONTROL_BASE_IDX 2
+#define mmCM4_CM_DGAM_LUT_INDEX 0x3643
+#define mmCM4_CM_DGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM4_CM_DGAM_LUT_DATA 0x3644
+#define mmCM4_CM_DGAM_LUT_DATA_BASE_IDX 2
+#define mmCM4_CM_DGAM_LUT_WRITE_EN_MASK 0x3645
+#define mmCM4_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_START_CNTL_B 0x3646
+#define mmCM4_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_START_CNTL_G 0x3647
+#define mmCM4_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_START_CNTL_R 0x3648
+#define mmCM4_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_B 0x3649
+#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_G 0x364a
+#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_R 0x364b
+#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_END_CNTL1_B 0x364c
+#define mmCM4_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_END_CNTL2_B 0x364d
+#define mmCM4_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_END_CNTL1_G 0x364e
+#define mmCM4_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_END_CNTL2_G 0x364f
+#define mmCM4_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_END_CNTL1_R 0x3650
+#define mmCM4_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_END_CNTL2_R 0x3651
+#define mmCM4_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_REGION_0_1 0x3652
+#define mmCM4_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_REGION_2_3 0x3653
+#define mmCM4_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_REGION_4_5 0x3654
+#define mmCM4_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_REGION_6_7 0x3655
+#define mmCM4_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_REGION_8_9 0x3656
+#define mmCM4_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_REGION_10_11 0x3657
+#define mmCM4_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_REGION_12_13 0x3658
+#define mmCM4_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMA_REGION_14_15 0x3659
+#define mmCM4_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_START_CNTL_B 0x365a
+#define mmCM4_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_START_CNTL_G 0x365b
+#define mmCM4_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_START_CNTL_R 0x365c
+#define mmCM4_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_B 0x365d
+#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_G 0x365e
+#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_R 0x365f
+#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_END_CNTL1_B 0x3660
+#define mmCM4_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_END_CNTL2_B 0x3661
+#define mmCM4_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_END_CNTL1_G 0x3662
+#define mmCM4_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_END_CNTL2_G 0x3663
+#define mmCM4_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_END_CNTL1_R 0x3664
+#define mmCM4_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_END_CNTL2_R 0x3665
+#define mmCM4_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_REGION_0_1 0x3666
+#define mmCM4_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_REGION_2_3 0x3667
+#define mmCM4_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_REGION_4_5 0x3668
+#define mmCM4_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_REGION_6_7 0x3669
+#define mmCM4_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_REGION_8_9 0x366a
+#define mmCM4_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_REGION_10_11 0x366b
+#define mmCM4_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_REGION_12_13 0x366c
+#define mmCM4_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM4_CM_DGAM_RAMB_REGION_14_15 0x366d
+#define mmCM4_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_CONTROL 0x366e
+#define mmCM4_CM_BLNDGAM_CONTROL_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_LUT_INDEX 0x366f
+#define mmCM4_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_LUT_DATA 0x3670
+#define mmCM4_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x3671
+#define mmCM4_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B 0x3672
+#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G 0x3673
+#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R 0x3674
+#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x3675
+#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x3676
+#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x3677
+#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B 0x3678
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B 0x3679
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G 0x367a
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G 0x367b
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R 0x367c
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R 0x367d
+#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1 0x367e
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3 0x367f
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5 0x3680
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7 0x3681
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9 0x3682
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11 0x3683
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13 0x3684
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15 0x3685
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17 0x3686
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19 0x3687
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21 0x3688
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23 0x3689
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25 0x368a
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27 0x368b
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29 0x368c
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31 0x368d
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33 0x368e
+#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B 0x368f
+#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G 0x3690
+#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R 0x3691
+#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x3692
+#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x3693
+#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x3694
+#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B 0x3695
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B 0x3696
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G 0x3697
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G 0x3698
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R 0x3699
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R 0x369a
+#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1 0x369b
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3 0x369c
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5 0x369d
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7 0x369e
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9 0x369f
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11 0x36a0
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13 0x36a1
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15 0x36a2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17 0x36a3
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19 0x36a4
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21 0x36a5
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23 0x36a6
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25 0x36a7
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27 0x36a8
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29 0x36a9
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31 0x36aa
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33 0x36ab
+#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM4_CM_HDR_MULT_COEF 0x36ac
+#define mmCM4_CM_HDR_MULT_COEF_BASE_IDX 2
+#define mmCM4_CM_MEM_PWR_CTRL 0x36ad
+#define mmCM4_CM_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCM4_CM_MEM_PWR_STATUS 0x36ae
+#define mmCM4_CM_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCM4_CM_DEALPHA 0x36b0
+#define mmCM4_CM_DEALPHA_BASE_IDX 2
+#define mmCM4_CM_COEF_FORMAT 0x36b1
+#define mmCM4_CM_COEF_FORMAT_BASE_IDX 2
+#define mmCM4_CM_SHAPER_CONTROL 0x36b2
+#define mmCM4_CM_SHAPER_CONTROL_BASE_IDX 2
+#define mmCM4_CM_SHAPER_OFFSET_R 0x36b3
+#define mmCM4_CM_SHAPER_OFFSET_R_BASE_IDX 2
+#define mmCM4_CM_SHAPER_OFFSET_G 0x36b4
+#define mmCM4_CM_SHAPER_OFFSET_G_BASE_IDX 2
+#define mmCM4_CM_SHAPER_OFFSET_B 0x36b5
+#define mmCM4_CM_SHAPER_OFFSET_B_BASE_IDX 2
+#define mmCM4_CM_SHAPER_SCALE_R 0x36b6
+#define mmCM4_CM_SHAPER_SCALE_R_BASE_IDX 2
+#define mmCM4_CM_SHAPER_SCALE_G_B 0x36b7
+#define mmCM4_CM_SHAPER_SCALE_G_B_BASE_IDX 2
+#define mmCM4_CM_SHAPER_LUT_INDEX 0x36b8
+#define mmCM4_CM_SHAPER_LUT_INDEX_BASE_IDX 2
+#define mmCM4_CM_SHAPER_LUT_DATA 0x36b9
+#define mmCM4_CM_SHAPER_LUT_DATA_BASE_IDX 2
+#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK 0x36ba
+#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B 0x36bb
+#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G 0x36bc
+#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R 0x36bd
+#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B 0x36be
+#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G 0x36bf
+#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R 0x36c0
+#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_0_1 0x36c1
+#define mmCM4_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_2_3 0x36c2
+#define mmCM4_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_4_5 0x36c3
+#define mmCM4_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_6_7 0x36c4
+#define mmCM4_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_8_9 0x36c5
+#define mmCM4_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_10_11 0x36c6
+#define mmCM4_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_12_13 0x36c7
+#define mmCM4_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_14_15 0x36c8
+#define mmCM4_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_16_17 0x36c9
+#define mmCM4_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_18_19 0x36ca
+#define mmCM4_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_20_21 0x36cb
+#define mmCM4_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_22_23 0x36cc
+#define mmCM4_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_24_25 0x36cd
+#define mmCM4_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_26_27 0x36ce
+#define mmCM4_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_28_29 0x36cf
+#define mmCM4_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_30_31 0x36d0
+#define mmCM4_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMA_REGION_32_33 0x36d1
+#define mmCM4_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B 0x36d2
+#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G 0x36d3
+#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R 0x36d4
+#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B 0x36d5
+#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G 0x36d6
+#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R 0x36d7
+#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_0_1 0x36d8
+#define mmCM4_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_2_3 0x36d9
+#define mmCM4_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_4_5 0x36da
+#define mmCM4_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_6_7 0x36db
+#define mmCM4_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_8_9 0x36dc
+#define mmCM4_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_10_11 0x36dd
+#define mmCM4_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_12_13 0x36de
+#define mmCM4_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_14_15 0x36df
+#define mmCM4_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_16_17 0x36e0
+#define mmCM4_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_18_19 0x36e1
+#define mmCM4_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_20_21 0x36e2
+#define mmCM4_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_22_23 0x36e3
+#define mmCM4_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_24_25 0x36e4
+#define mmCM4_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_26_27 0x36e5
+#define mmCM4_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_28_29 0x36e6
+#define mmCM4_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_30_31 0x36e7
+#define mmCM4_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM4_CM_SHAPER_RAMB_REGION_32_33 0x36e8
+#define mmCM4_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM4_CM_MEM_PWR_CTRL2 0x36e9
+#define mmCM4_CM_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmCM4_CM_MEM_PWR_STATUS2 0x36ea
+#define mmCM4_CM_MEM_PWR_STATUS2_BASE_IDX 2
+#define mmCM4_CM_3DLUT_MODE 0x36eb
+#define mmCM4_CM_3DLUT_MODE_BASE_IDX 2
+#define mmCM4_CM_3DLUT_INDEX 0x36ec
+#define mmCM4_CM_3DLUT_INDEX_BASE_IDX 2
+#define mmCM4_CM_3DLUT_DATA 0x36ed
+#define mmCM4_CM_3DLUT_DATA_BASE_IDX 2
+#define mmCM4_CM_3DLUT_DATA_30BIT 0x36ee
+#define mmCM4_CM_3DLUT_DATA_30BIT_BASE_IDX 2
+#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL 0x36ef
+#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
+#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR 0x36f0
+#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
+#define mmCM4_CM_3DLUT_OUT_OFFSET_R 0x36f1
+#define mmCM4_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
+#define mmCM4_CM_3DLUT_OUT_OFFSET_G 0x36f2
+#define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
+#define mmCM4_CM_3DLUT_OUT_OFFSET_B 0x36f3
+#define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
+#define mmCM4_CM_TEST_DEBUG_INDEX 0x36f4
+#define mmCM4_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM4_CM_TEST_DEBUG_DATA 0x36f5
+#define mmCM4_CM_TEST_DEBUG_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0xdcbc
+#define mmDC_PERFMON27_PERFCOUNTER_CNTL 0x372f
+#define mmDC_PERFMON27_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON27_PERFCOUNTER_CNTL2 0x3730
+#define mmDC_PERFMON27_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON27_PERFCOUNTER_STATE 0x3731
+#define mmDC_PERFMON27_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON27_PERFMON_CNTL 0x3732
+#define mmDC_PERFMON27_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON27_PERFMON_CNTL2 0x3733
+#define mmDC_PERFMON27_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC 0x3734
+#define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON27_PERFMON_CVALUE_LOW 0x3735
+#define mmDC_PERFMON27_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON27_PERFMON_HI 0x3736
+#define mmDC_PERFMON27_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON27_PERFMON_LOW 0x3737
+#define mmDC_PERFMON27_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp5_dispdec_dpp_top_dispdec
+// base address: 0xa9d8
+#define mmDPP_TOP5_DPP_CONTROL 0x373b
+#define mmDPP_TOP5_DPP_CONTROL_BASE_IDX 2
+#define mmDPP_TOP5_DPP_SOFT_RESET 0x373c
+#define mmDPP_TOP5_DPP_SOFT_RESET_BASE_IDX 2
+#define mmDPP_TOP5_DPP_CRC_VAL_R_G 0x373d
+#define mmDPP_TOP5_DPP_CRC_VAL_R_G_BASE_IDX 2
+#define mmDPP_TOP5_DPP_CRC_VAL_B_A 0x373e
+#define mmDPP_TOP5_DPP_CRC_VAL_B_A_BASE_IDX 2
+#define mmDPP_TOP5_DPP_CRC_CTRL 0x373f
+#define mmDPP_TOP5_DPP_CRC_CTRL_BASE_IDX 2
+#define mmDPP_TOP5_HOST_READ_CONTROL 0x3740
+#define mmDPP_TOP5_HOST_READ_CONTROL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp5_dispdec_cnvc_cfg_dispdec
+// base address: 0xa9d8
+#define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT 0x3745
+#define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
+#define mmCNVC_CFG5_FORMAT_CONTROL 0x3746
+#define mmCNVC_CFG5_FORMAT_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG5_FCNV_FP_BIAS_R 0x3747
+#define mmCNVC_CFG5_FCNV_FP_BIAS_R_BASE_IDX 2
+#define mmCNVC_CFG5_FCNV_FP_BIAS_G 0x3748
+#define mmCNVC_CFG5_FCNV_FP_BIAS_G_BASE_IDX 2
+#define mmCNVC_CFG5_FCNV_FP_BIAS_B 0x3749
+#define mmCNVC_CFG5_FCNV_FP_BIAS_B_BASE_IDX 2
+#define mmCNVC_CFG5_FCNV_FP_SCALE_R 0x374a
+#define mmCNVC_CFG5_FCNV_FP_SCALE_R_BASE_IDX 2
+#define mmCNVC_CFG5_FCNV_FP_SCALE_G 0x374b
+#define mmCNVC_CFG5_FCNV_FP_SCALE_G_BASE_IDX 2
+#define mmCNVC_CFG5_FCNV_FP_SCALE_B 0x374c
+#define mmCNVC_CFG5_FCNV_FP_SCALE_B_BASE_IDX 2
+#define mmCNVC_CFG5_COLOR_KEYER_CONTROL 0x374d
+#define mmCNVC_CFG5_COLOR_KEYER_CONTROL_BASE_IDX 2
+#define mmCNVC_CFG5_COLOR_KEYER_ALPHA 0x374e
+#define mmCNVC_CFG5_COLOR_KEYER_ALPHA_BASE_IDX 2
+#define mmCNVC_CFG5_COLOR_KEYER_RED 0x374f
+#define mmCNVC_CFG5_COLOR_KEYER_RED_BASE_IDX 2
+#define mmCNVC_CFG5_COLOR_KEYER_GREEN 0x3750
+#define mmCNVC_CFG5_COLOR_KEYER_GREEN_BASE_IDX 2
+#define mmCNVC_CFG5_COLOR_KEYER_BLUE 0x3751
+#define mmCNVC_CFG5_COLOR_KEYER_BLUE_BASE_IDX 2
+#define mmCNVC_CFG5_ALPHA_2BIT_LUT 0x3753
+#define mmCNVC_CFG5_ALPHA_2BIT_LUT_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp5_dispdec_cnvc_cur_dispdec
+// base address: 0xa9d8
+#define mmCNVC_CUR5_CURSOR0_CONTROL 0x3756
+#define mmCNVC_CUR5_CURSOR0_CONTROL_BASE_IDX 2
+#define mmCNVC_CUR5_CURSOR0_COLOR0 0x3757
+#define mmCNVC_CUR5_CURSOR0_COLOR0_BASE_IDX 2
+#define mmCNVC_CUR5_CURSOR0_COLOR1 0x3758
+#define mmCNVC_CUR5_CURSOR0_COLOR1_BASE_IDX 2
+#define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS 0x3759
+#define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp5_dispdec_dscl_dispdec
+// base address: 0xa9d8
+#define mmDSCL5_SCL_COEF_RAM_TAP_SELECT 0x3760
+#define mmDSCL5_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
+#define mmDSCL5_SCL_COEF_RAM_TAP_DATA 0x3761
+#define mmDSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
+#define mmDSCL5_SCL_MODE 0x3762
+#define mmDSCL5_SCL_MODE_BASE_IDX 2
+#define mmDSCL5_SCL_TAP_CONTROL 0x3763
+#define mmDSCL5_SCL_TAP_CONTROL_BASE_IDX 2
+#define mmDSCL5_DSCL_CONTROL 0x3764
+#define mmDSCL5_DSCL_CONTROL_BASE_IDX 2
+#define mmDSCL5_DSCL_2TAP_CONTROL 0x3765
+#define mmDSCL5_DSCL_2TAP_CONTROL_BASE_IDX 2
+#define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x3766
+#define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
+#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x3767
+#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL5_SCL_HORZ_FILTER_INIT 0x3768
+#define mmDSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2
+#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C 0x3769
+#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL5_SCL_HORZ_FILTER_INIT_C 0x376a
+#define mmDSCL5_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x376b
+#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
+#define mmDSCL5_SCL_VERT_FILTER_INIT 0x376c
+#define mmDSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2
+#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT 0x376d
+#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
+#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C 0x376e
+#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
+#define mmDSCL5_SCL_VERT_FILTER_INIT_C 0x376f
+#define mmDSCL5_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
+#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C 0x3770
+#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
+#define mmDSCL5_SCL_BLACK_OFFSET 0x3771
+#define mmDSCL5_SCL_BLACK_OFFSET_BASE_IDX 2
+#define mmDSCL5_DSCL_UPDATE 0x3772
+#define mmDSCL5_DSCL_UPDATE_BASE_IDX 2
+#define mmDSCL5_DSCL_AUTOCAL 0x3773
+#define mmDSCL5_DSCL_AUTOCAL_BASE_IDX 2
+#define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x3774
+#define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
+#define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x3775
+#define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
+#define mmDSCL5_OTG_H_BLANK 0x3776
+#define mmDSCL5_OTG_H_BLANK_BASE_IDX 2
+#define mmDSCL5_OTG_V_BLANK 0x3777
+#define mmDSCL5_OTG_V_BLANK_BASE_IDX 2
+#define mmDSCL5_RECOUT_START 0x3778
+#define mmDSCL5_RECOUT_START_BASE_IDX 2
+#define mmDSCL5_RECOUT_SIZE 0x3779
+#define mmDSCL5_RECOUT_SIZE_BASE_IDX 2
+#define mmDSCL5_MPC_SIZE 0x377a
+#define mmDSCL5_MPC_SIZE_BASE_IDX 2
+#define mmDSCL5_LB_DATA_FORMAT 0x377b
+#define mmDSCL5_LB_DATA_FORMAT_BASE_IDX 2
+#define mmDSCL5_LB_MEMORY_CTRL 0x377c
+#define mmDSCL5_LB_MEMORY_CTRL_BASE_IDX 2
+#define mmDSCL5_LB_V_COUNTER 0x377d
+#define mmDSCL5_LB_V_COUNTER_BASE_IDX 2
+#define mmDSCL5_DSCL_MEM_PWR_CTRL 0x377e
+#define mmDSCL5_DSCL_MEM_PWR_CTRL_BASE_IDX 2
+#define mmDSCL5_DSCL_MEM_PWR_STATUS 0x377f
+#define mmDSCL5_DSCL_MEM_PWR_STATUS_BASE_IDX 2
+#define mmDSCL5_OBUF_CONTROL 0x3780
+#define mmDSCL5_OBUF_CONTROL_BASE_IDX 2
+#define mmDSCL5_OBUF_MEM_PWR_CTRL 0x3781
+#define mmDSCL5_OBUF_MEM_PWR_CTRL_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp5_dispdec_cm_dispdec
+// base address: 0xa9d8
+#define mmCM5_CM_CONTROL 0x3790
+#define mmCM5_CM_CONTROL_BASE_IDX 2
+#define mmCM5_CM_ICSC_CONTROL 0x3791
+#define mmCM5_CM_ICSC_CONTROL_BASE_IDX 2
+#define mmCM5_CM_ICSC_C11_C12 0x3792
+#define mmCM5_CM_ICSC_C11_C12_BASE_IDX 2
+#define mmCM5_CM_ICSC_C13_C14 0x3793
+#define mmCM5_CM_ICSC_C13_C14_BASE_IDX 2
+#define mmCM5_CM_ICSC_C21_C22 0x3794
+#define mmCM5_CM_ICSC_C21_C22_BASE_IDX 2
+#define mmCM5_CM_ICSC_C23_C24 0x3795
+#define mmCM5_CM_ICSC_C23_C24_BASE_IDX 2
+#define mmCM5_CM_ICSC_C31_C32 0x3796
+#define mmCM5_CM_ICSC_C31_C32_BASE_IDX 2
+#define mmCM5_CM_ICSC_C33_C34 0x3797
+#define mmCM5_CM_ICSC_C33_C34_BASE_IDX 2
+#define mmCM5_CM_ICSC_B_C11_C12 0x3798
+#define mmCM5_CM_ICSC_B_C11_C12_BASE_IDX 2
+#define mmCM5_CM_ICSC_B_C13_C14 0x3799
+#define mmCM5_CM_ICSC_B_C13_C14_BASE_IDX 2
+#define mmCM5_CM_ICSC_B_C21_C22 0x379a
+#define mmCM5_CM_ICSC_B_C21_C22_BASE_IDX 2
+#define mmCM5_CM_ICSC_B_C23_C24 0x379b
+#define mmCM5_CM_ICSC_B_C23_C24_BASE_IDX 2
+#define mmCM5_CM_ICSC_B_C31_C32 0x379c
+#define mmCM5_CM_ICSC_B_C31_C32_BASE_IDX 2
+#define mmCM5_CM_ICSC_B_C33_C34 0x379d
+#define mmCM5_CM_ICSC_B_C33_C34_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_CONTROL 0x379e
+#define mmCM5_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_C11_C12 0x379f
+#define mmCM5_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_C13_C14 0x37a0
+#define mmCM5_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_C21_C22 0x37a1
+#define mmCM5_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_C23_C24 0x37a2
+#define mmCM5_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_C31_C32 0x37a3
+#define mmCM5_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_C33_C34 0x37a4
+#define mmCM5_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_B_C11_C12 0x37a5
+#define mmCM5_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_B_C13_C14 0x37a6
+#define mmCM5_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_B_C21_C22 0x37a7
+#define mmCM5_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_B_C23_C24 0x37a8
+#define mmCM5_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_B_C31_C32 0x37a9
+#define mmCM5_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
+#define mmCM5_CM_GAMUT_REMAP_B_C33_C34 0x37aa
+#define mmCM5_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
+#define mmCM5_CM_BIAS_CR_R 0x37ab
+#define mmCM5_CM_BIAS_CR_R_BASE_IDX 2
+#define mmCM5_CM_BIAS_Y_G_CB_B 0x37ac
+#define mmCM5_CM_BIAS_Y_G_CB_B_BASE_IDX 2
+#define mmCM5_CM_DGAM_CONTROL 0x37ad
+#define mmCM5_CM_DGAM_CONTROL_BASE_IDX 2
+#define mmCM5_CM_DGAM_LUT_INDEX 0x37ae
+#define mmCM5_CM_DGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM5_CM_DGAM_LUT_DATA 0x37af
+#define mmCM5_CM_DGAM_LUT_DATA_BASE_IDX 2
+#define mmCM5_CM_DGAM_LUT_WRITE_EN_MASK 0x37b0
+#define mmCM5_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_START_CNTL_B 0x37b1
+#define mmCM5_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_START_CNTL_G 0x37b2
+#define mmCM5_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_START_CNTL_R 0x37b3
+#define mmCM5_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_B 0x37b4
+#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_G 0x37b5
+#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_R 0x37b6
+#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_END_CNTL1_B 0x37b7
+#define mmCM5_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_END_CNTL2_B 0x37b8
+#define mmCM5_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_END_CNTL1_G 0x37b9
+#define mmCM5_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_END_CNTL2_G 0x37ba
+#define mmCM5_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_END_CNTL1_R 0x37bb
+#define mmCM5_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_END_CNTL2_R 0x37bc
+#define mmCM5_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_REGION_0_1 0x37bd
+#define mmCM5_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_REGION_2_3 0x37be
+#define mmCM5_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_REGION_4_5 0x37bf
+#define mmCM5_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_REGION_6_7 0x37c0
+#define mmCM5_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_REGION_8_9 0x37c1
+#define mmCM5_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_REGION_10_11 0x37c2
+#define mmCM5_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_REGION_12_13 0x37c3
+#define mmCM5_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMA_REGION_14_15 0x37c4
+#define mmCM5_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_START_CNTL_B 0x37c5
+#define mmCM5_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_START_CNTL_G 0x37c6
+#define mmCM5_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_START_CNTL_R 0x37c7
+#define mmCM5_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_B 0x37c8
+#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_G 0x37c9
+#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_R 0x37ca
+#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_END_CNTL1_B 0x37cb
+#define mmCM5_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_END_CNTL2_B 0x37cc
+#define mmCM5_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_END_CNTL1_G 0x37cd
+#define mmCM5_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_END_CNTL2_G 0x37ce
+#define mmCM5_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_END_CNTL1_R 0x37cf
+#define mmCM5_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_END_CNTL2_R 0x37d0
+#define mmCM5_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_REGION_0_1 0x37d1
+#define mmCM5_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_REGION_2_3 0x37d2
+#define mmCM5_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_REGION_4_5 0x37d3
+#define mmCM5_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_REGION_6_7 0x37d4
+#define mmCM5_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_REGION_8_9 0x37d5
+#define mmCM5_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_REGION_10_11 0x37d6
+#define mmCM5_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_REGION_12_13 0x37d7
+#define mmCM5_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM5_CM_DGAM_RAMB_REGION_14_15 0x37d8
+#define mmCM5_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_CONTROL 0x37d9
+#define mmCM5_CM_BLNDGAM_CONTROL_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_LUT_INDEX 0x37da
+#define mmCM5_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_LUT_DATA 0x37db
+#define mmCM5_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x37dc
+#define mmCM5_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B 0x37dd
+#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G 0x37de
+#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R 0x37df
+#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x37e0
+#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x37e1
+#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x37e2
+#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B 0x37e3
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B 0x37e4
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G 0x37e5
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G 0x37e6
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R 0x37e7
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R 0x37e8
+#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1 0x37e9
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3 0x37ea
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5 0x37eb
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7 0x37ec
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9 0x37ed
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11 0x37ee
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13 0x37ef
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15 0x37f0
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17 0x37f1
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19 0x37f2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21 0x37f3
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23 0x37f4
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25 0x37f5
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27 0x37f6
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29 0x37f7
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31 0x37f8
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33 0x37f9
+#define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B 0x37fa
+#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G 0x37fb
+#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R 0x37fc
+#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x37fd
+#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x37fe
+#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x37ff
+#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B 0x3800
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B 0x3801
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G 0x3802
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G 0x3803
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R 0x3804
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R 0x3805
+#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1 0x3806
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3 0x3807
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5 0x3808
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7 0x3809
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9 0x380a
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11 0x380b
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13 0x380c
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15 0x380d
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17 0x380e
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19 0x380f
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21 0x3810
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23 0x3811
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25 0x3812
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27 0x3813
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29 0x3814
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31 0x3815
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33 0x3816
+#define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM5_CM_HDR_MULT_COEF 0x3817
+#define mmCM5_CM_HDR_MULT_COEF_BASE_IDX 2
+#define mmCM5_CM_MEM_PWR_CTRL 0x3818
+#define mmCM5_CM_MEM_PWR_CTRL_BASE_IDX 2
+#define mmCM5_CM_MEM_PWR_STATUS 0x3819
+#define mmCM5_CM_MEM_PWR_STATUS_BASE_IDX 2
+#define mmCM5_CM_DEALPHA 0x381b
+#define mmCM5_CM_DEALPHA_BASE_IDX 2
+#define mmCM5_CM_COEF_FORMAT 0x381c
+#define mmCM5_CM_COEF_FORMAT_BASE_IDX 2
+#define mmCM5_CM_SHAPER_CONTROL 0x381d
+#define mmCM5_CM_SHAPER_CONTROL_BASE_IDX 2
+#define mmCM5_CM_SHAPER_OFFSET_R 0x381e
+#define mmCM5_CM_SHAPER_OFFSET_R_BASE_IDX 2
+#define mmCM5_CM_SHAPER_OFFSET_G 0x381f
+#define mmCM5_CM_SHAPER_OFFSET_G_BASE_IDX 2
+#define mmCM5_CM_SHAPER_OFFSET_B 0x3820
+#define mmCM5_CM_SHAPER_OFFSET_B_BASE_IDX 2
+#define mmCM5_CM_SHAPER_SCALE_R 0x3821
+#define mmCM5_CM_SHAPER_SCALE_R_BASE_IDX 2
+#define mmCM5_CM_SHAPER_SCALE_G_B 0x3822
+#define mmCM5_CM_SHAPER_SCALE_G_B_BASE_IDX 2
+#define mmCM5_CM_SHAPER_LUT_INDEX 0x3823
+#define mmCM5_CM_SHAPER_LUT_INDEX_BASE_IDX 2
+#define mmCM5_CM_SHAPER_LUT_DATA 0x3824
+#define mmCM5_CM_SHAPER_LUT_DATA_BASE_IDX 2
+#define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK 0x3825
+#define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_START_CNTL_B 0x3826
+#define mmCM5_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_START_CNTL_G 0x3827
+#define mmCM5_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_START_CNTL_R 0x3828
+#define mmCM5_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_END_CNTL_B 0x3829
+#define mmCM5_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_END_CNTL_G 0x382a
+#define mmCM5_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_END_CNTL_R 0x382b
+#define mmCM5_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_0_1 0x382c
+#define mmCM5_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_2_3 0x382d
+#define mmCM5_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_4_5 0x382e
+#define mmCM5_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_6_7 0x382f
+#define mmCM5_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_8_9 0x3830
+#define mmCM5_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_10_11 0x3831
+#define mmCM5_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_12_13 0x3832
+#define mmCM5_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_14_15 0x3833
+#define mmCM5_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_16_17 0x3834
+#define mmCM5_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_18_19 0x3835
+#define mmCM5_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_20_21 0x3836
+#define mmCM5_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_22_23 0x3837
+#define mmCM5_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_24_25 0x3838
+#define mmCM5_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_26_27 0x3839
+#define mmCM5_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_28_29 0x383a
+#define mmCM5_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_30_31 0x383b
+#define mmCM5_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMA_REGION_32_33 0x383c
+#define mmCM5_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_START_CNTL_B 0x383d
+#define mmCM5_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_START_CNTL_G 0x383e
+#define mmCM5_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_START_CNTL_R 0x383f
+#define mmCM5_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_END_CNTL_B 0x3840
+#define mmCM5_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_END_CNTL_G 0x3841
+#define mmCM5_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_END_CNTL_R 0x3842
+#define mmCM5_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_0_1 0x3843
+#define mmCM5_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_2_3 0x3844
+#define mmCM5_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_4_5 0x3845
+#define mmCM5_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_6_7 0x3846
+#define mmCM5_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_8_9 0x3847
+#define mmCM5_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_10_11 0x3848
+#define mmCM5_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_12_13 0x3849
+#define mmCM5_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_14_15 0x384a
+#define mmCM5_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_16_17 0x384b
+#define mmCM5_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_18_19 0x384c
+#define mmCM5_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_20_21 0x384d
+#define mmCM5_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_22_23 0x384e
+#define mmCM5_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_24_25 0x384f
+#define mmCM5_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_26_27 0x3850
+#define mmCM5_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_28_29 0x3851
+#define mmCM5_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_30_31 0x3852
+#define mmCM5_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
+#define mmCM5_CM_SHAPER_RAMB_REGION_32_33 0x3853
+#define mmCM5_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
+#define mmCM5_CM_MEM_PWR_CTRL2 0x3854
+#define mmCM5_CM_MEM_PWR_CTRL2_BASE_IDX 2
+#define mmCM5_CM_MEM_PWR_STATUS2 0x3855
+#define mmCM5_CM_MEM_PWR_STATUS2_BASE_IDX 2
+#define mmCM5_CM_3DLUT_MODE 0x3856
+#define mmCM5_CM_3DLUT_MODE_BASE_IDX 2
+#define mmCM5_CM_3DLUT_INDEX 0x3857
+#define mmCM5_CM_3DLUT_INDEX_BASE_IDX 2
+#define mmCM5_CM_3DLUT_DATA 0x3858
+#define mmCM5_CM_3DLUT_DATA_BASE_IDX 2
+#define mmCM5_CM_3DLUT_DATA_30BIT 0x3859
+#define mmCM5_CM_3DLUT_DATA_30BIT_BASE_IDX 2
+#define mmCM5_CM_3DLUT_READ_WRITE_CONTROL 0x385a
+#define mmCM5_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
+#define mmCM5_CM_3DLUT_OUT_NORM_FACTOR 0x385b
+#define mmCM5_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
+#define mmCM5_CM_3DLUT_OUT_OFFSET_R 0x385c
+#define mmCM5_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
+#define mmCM5_CM_3DLUT_OUT_OFFSET_G 0x385d
+#define mmCM5_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
+#define mmCM5_CM_3DLUT_OUT_OFFSET_B 0x385e
+#define mmCM5_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
+#define mmCM5_CM_TEST_DEBUG_INDEX 0x385f
+#define mmCM5_CM_TEST_DEBUG_INDEX_BASE_IDX 2
+#define mmCM5_CM_TEST_DEBUG_DATA 0x3860
+#define mmCM5_CM_TEST_DEBUG_DATA_BASE_IDX 2
+
+
+// addressBlock: dce_dc_dpp5_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0xe268
+#define mmDC_PERFMON28_PERFCOUNTER_CNTL 0x389a
+#define mmDC_PERFMON28_PERFCOUNTER_CNTL_BASE_IDX 2
+#define mmDC_PERFMON28_PERFCOUNTER_CNTL2 0x389b
+#define mmDC_PERFMON28_PERFCOUNTER_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON28_PERFCOUNTER_STATE 0x389c
+#define mmDC_PERFMON28_PERFCOUNTER_STATE_BASE_IDX 2
+#define mmDC_PERFMON28_PERFMON_CNTL 0x389d
+#define mmDC_PERFMON28_PERFMON_CNTL_BASE_IDX 2
+#define mmDC_PERFMON28_PERFMON_CNTL2 0x389e
+#define mmDC_PERFMON28_PERFMON_CNTL2_BASE_IDX 2
+#define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC 0x389f
+#define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
+#define mmDC_PERFMON28_PERFMON_CVALUE_LOW 0x38a0
+#define mmDC_PERFMON28_PERFMON_CVALUE_LOW_BASE_IDX 2
+#define mmDC_PERFMON28_PERFMON_HI 0x38a1
+#define mmDC_PERFMON28_PERFMON_HI_BASE_IDX 2
+#define mmDC_PERFMON28_PERFMON_LOW 0x38a2
+#define mmDC_PERFMON28_PERFMON_LOW_BASE_IDX 2
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+// base address: 0x0
+#define mmCORB_WRITE_POINTER 0x0000
+#define mmCORB_WRITE_POINTER_BASE_IDX 0
+#define mmCORB_READ_POINTER 0x0000
+#define mmCORB_READ_POINTER_BASE_IDX 0
+#define mmCORB_CONTROL 0x0001
+#define mmCORB_CONTROL_BASE_IDX 0
+#define mmCORB_STATUS 0x0001
+#define mmCORB_STATUS_BASE_IDX 0
+#define mmCORB_SIZE 0x0001
+#define mmCORB_SIZE_BASE_IDX 0
+#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
+#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
+#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmRIRB_WRITE_POINTER 0x0004
+#define mmRIRB_WRITE_POINTER_BASE_IDX 0
+#define mmRESPONSE_INTERRUPT_COUNT 0x0004
+#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
+#define mmRIRB_CONTROL 0x0005
+#define mmRIRB_CONTROL_BASE_IDX 0
+#define mmRIRB_STATUS 0x0005
+#define mmRIRB_STATUS_BASE_IDX 0
+#define mmRIRB_SIZE 0x0005
+#define mmRIRB_SIZE_BASE_IDX 0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
+#define mmIMMEDIATE_COMMAND_STATUS 0x0008
+#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
+#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+// base address: 0x0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+// base address: 0x0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
+
+
+// addressBlock: dce_dc_hda_azroot_azdec
+// base address: 0x0
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
+
+
+// addressBlock: dce_dc_hda_azstream0_azdec
+// base address: 0x0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
+#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_hda_azstream1_azdec
+// base address: 0x20
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
+#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_hda_azstream2_azdec
+// base address: 0x40
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
+#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_hda_azstream3_azdec
+// base address: 0x60
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
+#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_hda_azstream4_azdec
+// base address: 0x80
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
+#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_hda_azstream5_azdec
+// base address: 0xa0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
+#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_hda_azstream6_azdec
+// base address: 0xc0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
+#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: dce_dc_hda_azstream7_azdec
+// base address: 0xe0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
+#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
+
+
+// addressBlock: vga_vgaseqind
+// base address: 0x0
+#define ixSEQ00 0x0000
+#define ixSEQ01 0x0001
+#define ixSEQ02 0x0002
+#define ixSEQ03 0x0003
+#define ixSEQ04 0x0004
+
+
+// addressBlock: vga_vgacrtind
+// base address: 0x0
+#define ixCRT00 0x0000
+#define ixCRT01 0x0001
+#define ixCRT02 0x0002
+#define ixCRT03 0x0003
+#define ixCRT04 0x0004
+#define ixCRT05 0x0005
+#define ixCRT06 0x0006
+#define ixCRT07 0x0007
+#define ixCRT08 0x0008
+#define ixCRT09 0x0009
+#define ixCRT0A 0x000a
+#define ixCRT0B 0x000b
+#define ixCRT0C 0x000c
+#define ixCRT0D 0x000d
+#define ixCRT0E 0x000e
+#define ixCRT0F 0x000f
+#define ixCRT10 0x0010
+#define ixCRT11 0x0011
+#define ixCRT12 0x0012
+#define ixCRT13 0x0013
+#define ixCRT14 0x0014
+#define ixCRT15 0x0015
+#define ixCRT16 0x0016
+#define ixCRT17 0x0017
+#define ixCRT18 0x0018
+#define ixCRT1E 0x001e
+#define ixCRT1F 0x001f
+#define ixCRT22 0x0022
+
+
+// addressBlock: vga_vgagrphind
+// base address: 0x0
+#define ixGRA00 0x0000
+#define ixGRA01 0x0001
+#define ixGRA02 0x0002
+#define ixGRA03 0x0003
+#define ixGRA04 0x0004
+#define ixGRA05 0x0005
+#define ixGRA06 0x0006
+#define ixGRA07 0x0007
+#define ixGRA08 0x0008
+
+
+// addressBlock: vga_vgaattrind
+// base address: 0x0
+#define ixATTR00 0x0000
+#define ixATTR01 0x0001
+#define ixATTR02 0x0002
+#define ixATTR03 0x0003
+#define ixATTR04 0x0004
+#define ixATTR05 0x0005
+#define ixATTR06 0x0006
+#define ixATTR07 0x0007
+#define ixATTR08 0x0008
+#define ixATTR09 0x0009
+#define ixATTR0A 0x000a
+#define ixATTR0B 0x000b
+#define ixATTR0C 0x000c
+#define ixATTR0D 0x000d
+#define ixATTR0E 0x000e
+#define ixATTR0F 0x000f
+#define ixATTR10 0x0010
+#define ixATTR11 0x0011
+#define ixATTR12 0x0012
+#define ixATTR13 0x0013
+#define ixATTR14 0x0014
+
+
+// addressBlock: azendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
+
+
+// addressBlock: azendpoint_descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0 0x0001
+#define ixAUDIO_DESCRIPTOR1 0x0002
+#define ixAUDIO_DESCRIPTOR2 0x0003
+#define ixAUDIO_DESCRIPTOR3 0x0004
+#define ixAUDIO_DESCRIPTOR4 0x0005
+#define ixAUDIO_DESCRIPTOR5 0x0006
+#define ixAUDIO_DESCRIPTOR6 0x0007
+#define ixAUDIO_DESCRIPTOR7 0x0008
+#define ixAUDIO_DESCRIPTOR8 0x0009
+#define ixAUDIO_DESCRIPTOR9 0x000a
+#define ixAUDIO_DESCRIPTOR10 0x000b
+#define ixAUDIO_DESCRIPTOR11 0x000c
+#define ixAUDIO_DESCRIPTOR12 0x000d
+#define ixAUDIO_DESCRIPTOR13 0x000e
+
+
+// addressBlock: azendpoint_sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
+#define ixSINK_DESCRIPTION0 0x0005
+#define ixSINK_DESCRIPTION1 0x0006
+#define ixSINK_DESCRIPTION2 0x0007
+#define ixSINK_DESCRIPTION3 0x0008
+#define ixSINK_DESCRIPTION4 0x0009
+#define ixSINK_DESCRIPTION5 0x000a
+#define ixSINK_DESCRIPTION6 0x000b
+#define ixSINK_DESCRIPTION7 0x000c
+#define ixSINK_DESCRIPTION8 0x000d
+#define ixSINK_DESCRIPTION9 0x000e
+#define ixSINK_DESCRIPTION10 0x000f
+#define ixSINK_DESCRIPTION11 0x0010
+#define ixSINK_DESCRIPTION12 0x0011
+#define ixSINK_DESCRIPTION13 0x0012
+#define ixSINK_DESCRIPTION14 0x0013
+#define ixSINK_DESCRIPTION15 0x0014
+#define ixSINK_DESCRIPTION16 0x0015
+#define ixSINK_DESCRIPTION17 0x0016
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
+
+
+// addressBlock: azf0controller_azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0 0x0000
+#define ixAZALIA_CRC0_CHANNEL1 0x0001
+#define ixAZALIA_CRC0_CHANNEL2 0x0002
+#define ixAZALIA_CRC0_CHANNEL3 0x0003
+#define ixAZALIA_CRC0_CHANNEL4 0x0004
+#define ixAZALIA_CRC0_CHANNEL5 0x0005
+#define ixAZALIA_CRC0_CHANNEL6 0x0006
+#define ixAZALIA_CRC0_CHANNEL7 0x0007
+
+
+// addressBlock: azf0controller_azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0 0x0000
+#define ixAZALIA_CRC1_CHANNEL1 0x0001
+#define ixAZALIA_CRC1_CHANNEL2 0x0002
+#define ixAZALIA_CRC1_CHANNEL3 0x0003
+#define ixAZALIA_CRC1_CHANNEL4 0x0004
+#define ixAZALIA_CRC1_CHANNEL5 0x0005
+#define ixAZALIA_CRC1_CHANNEL6 0x0006
+#define ixAZALIA_CRC1_CHANNEL7 0x0007
+
+
+// addressBlock: azinputendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
+
+
+// addressBlock: azroot_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
new file mode 100644
index 000000000000..10c83fecd147
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
@@ -0,0 +1,68024 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_2_0_0_SH_MASK_HEADER
+#define _dcn_2_0_0_SH_MASK_HEADER
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+//VGA_MEM_WRITE_PAGE_ADDR
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
+//VGA_MEM_READ_PAGE_ADDR
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
+//VGA_RENDER_CONTROL
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L
+//VGA_SEQUENCER_RESET_CONTROL
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L
+//VGA_MODE_CONTROL
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L
+//VGA_SURFACE_PITCH_SELECT
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L
+//VGA_MEMORY_BASE_ADDRESS
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//VGA_DISPBUF1_SURFACE_ADDR
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL
+//VGA_DISPBUF2_SURFACE_ADDR
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL
+//VGA_MEMORY_BASE_ADDRESS_HIGH
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//VGA_HDP_CONTROL
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L
+//VGA_CACHE_CONTROL
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L
+//D1VGA_CONTROL
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L
+//D2VGA_CONTROL
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L
+//VGA_STATUS
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L
+//VGA_INTERRUPT_CONTROL
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L
+//VGA_STATUS_CLEAR
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L
+//VGA_INTERRUPT_STATUS
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L
+//VGA_MAIN_CONTROL
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L
+//VGA_TEST_CONTROL
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L
+//VGA_QOS_CTRL
+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0
+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4
+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL
+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L
+//CRTC8_IDX
+#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
+#define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL
+//CRTC8_DATA
+#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL
+//GENFC_WT
+#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
+#define GENFC_WT__VSYNC_SEL_W_MASK 0x08L
+//GENS1
+#define GENS1__NO_DISPLAY__SHIFT 0x0
+#define GENS1__VGA_VSTATUS__SHIFT 0x3
+#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
+#define GENS1__NO_DISPLAY_MASK 0x01L
+#define GENS1__VGA_VSTATUS_MASK 0x08L
+#define GENS1__PIXEL_READ_BACK_MASK 0x30L
+//ATTRDW
+#define ATTRDW__ATTR_DATA__SHIFT 0x0
+#define ATTRDW__ATTR_DATA_MASK 0xFFL
+//ATTRX
+#define ATTRX__ATTR_IDX__SHIFT 0x0
+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
+#define ATTRX__ATTR_IDX_MASK 0x1FL
+#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20L
+//ATTRDR
+#define ATTRDR__ATTR_DATA__SHIFT 0x0
+#define ATTRDR__ATTR_DATA_MASK 0xFFL
+//GENMO_WT
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L
+#define GENMO_WT__VGA_RAM_EN_MASK 0x02L
+#define GENMO_WT__VGA_CKSEL_MASK 0x0CL
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L
+#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L
+#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L
+//GENS0
+#define GENS0__SENSE_SWITCH__SHIFT 0x4
+#define GENS0__CRT_INTR__SHIFT 0x7
+#define GENS0__SENSE_SWITCH_MASK 0x10L
+#define GENS0__CRT_INTR_MASK 0x80L
+//GENENB
+#define GENENB__BLK_IO_BASE__SHIFT 0x0
+#define GENENB__BLK_IO_BASE_MASK 0xFFL
+//SEQ8_IDX
+#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
+#define SEQ8_IDX__SEQ_IDX_MASK 0x07L
+//SEQ8_DATA
+#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
+#define SEQ8_DATA__SEQ_DATA_MASK 0xFFL
+//DAC_MASK
+#define DAC_MASK__DAC_MASK__SHIFT 0x0
+#define DAC_MASK__DAC_MASK_MASK 0xFFL
+//DAC_R_INDEX
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL
+//DAC_W_INDEX
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL
+//DAC_DATA
+#define DAC_DATA__DAC_DATA__SHIFT 0x0
+#define DAC_DATA__DAC_DATA_MASK 0x3FL
+//GENFC_RD
+#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK 0x08L
+//GENMO_RD
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L
+#define GENMO_RD__VGA_RAM_EN_MASK 0x02L
+#define GENMO_RD__VGA_CKSEL_MASK 0x0CL
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L
+#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L
+#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L
+//GRPH8_IDX
+#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
+#define GRPH8_IDX__GRPH_IDX_MASK 0x0FL
+//GRPH8_DATA
+#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
+#define GRPH8_DATA__GRPH_DATA_MASK 0xFFL
+//CRTC8_IDX_1
+#define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0
+#define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL
+//CRTC8_DATA_1
+#define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0
+#define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL
+//GENFC_WT_1
+#define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3
+#define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L
+//GENS1_1
+#define GENS1_1__NO_DISPLAY__SHIFT 0x0
+#define GENS1_1__VGA_VSTATUS__SHIFT 0x3
+#define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4
+#define GENS1_1__NO_DISPLAY_MASK 0x01L
+#define GENS1_1__VGA_VSTATUS_MASK 0x08L
+#define GENS1_1__PIXEL_READ_BACK_MASK 0x30L
+//D3VGA_CONTROL
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L
+//D4VGA_CONTROL
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L
+//D5VGA_CONTROL
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L
+//D6VGA_CONTROL
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L
+//VGA_SOURCE_SELECT
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+//PHYPLLA_PIXCLK_RESYNC_CNTL
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//PHYPLLB_PIXCLK_RESYNC_CNTL
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//PHYPLLC_PIXCLK_RESYNC_CNTL
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//PHYPLLD_PIXCLK_RESYNC_CNTL
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//DP_DTO_DBUF_EN
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L
+//DSCCLK3_DTO_PARAM
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT 0x0
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT 0x10
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK 0x000000FFL
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK 0x00FF0000L
+//DSCCLK4_DTO_PARAM
+#define DSCCLK4_DTO_PARAM__DSCCLK4_DTO_PHASE__SHIFT 0x0
+#define DSCCLK4_DTO_PARAM__DSCCLK4_DTO_MODULO__SHIFT 0x10
+#define DSCCLK4_DTO_PARAM__DSCCLK4_DTO_PHASE_MASK 0x000000FFL
+#define DSCCLK4_DTO_PARAM__DSCCLK4_DTO_MODULO_MASK 0x00FF0000L
+//DSCCLK5_DTO_PARAM
+#define DSCCLK5_DTO_PARAM__DSCCLK5_DTO_PHASE__SHIFT 0x0
+#define DSCCLK5_DTO_PARAM__DSCCLK5_DTO_MODULO__SHIFT 0x10
+#define DSCCLK5_DTO_PARAM__DSCCLK5_DTO_PHASE_MASK 0x000000FFL
+#define DSCCLK5_DTO_PARAM__DSCCLK5_DTO_MODULO_MASK 0x00FF0000L
+//DPREFCLK_CGTT_BLK_CTRL_REG
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//REFCLK_CNTL
+#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0
+#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1
+#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x00000001L
+#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x00000002L
+//REFCLK_CGTT_BLK_CTRL_REG
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//PHYPLLE_PIXCLK_RESYNC_CNTL
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//DCCG_PERFMON_CNTL2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L
+//DCCG_DS_DTO_INCR
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL
+//DCCG_DS_DTO_MODULO
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL
+//DCCG_DS_CNTL
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L
+//DCCG_DS_HW_CAL_INTERVAL
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL
+//DPREFCLK_CNTL
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L
+//DCE_VERSION
+#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0
+#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL
+#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L
+//DCCG_GTC_CNTL
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L
+//DCCG_GTC_DTO_INCR
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL
+//DCCG_GTC_DTO_MODULO
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL
+//DCCG_GTC_CURRENT
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL
+//DSCCLK0_DTO_PARAM
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT 0x0
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT 0x10
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK 0x000000FFL
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK 0x00FF0000L
+//DSCCLK1_DTO_PARAM
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT 0x0
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT 0x10
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK 0x000000FFL
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK 0x00FF0000L
+//DSCCLK2_DTO_PARAM
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT 0x0
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT 0x10
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK 0x000000FFL
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK 0x00FF0000L
+//MILLISECOND_TIME_BASE_DIV
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
+//DISPCLK_FREQ_CHANGE_CNTL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L
+//DC_MEM_GLOBAL_PWR_REQ_CNTL
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L
+//DCCG_PERFMON_CNTL
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT 0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK 0x00000700L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L
+//DCCG_GATE_DISABLE_CNTL
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT 0xb
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT 0xc
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000400L
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK 0x00000800L
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK 0x00001000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x00200000L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L
+//DISPCLK_CGTT_BLK_CTRL_REG
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//SOCCLK_CGTT_BLK_CTRL_REG
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//DCCG_CAC_STATUS
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL
+//MICROSECOND_TIME_BASE_DIV
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
+//DCCG_GATE_DISABLE_CNTL2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L
+//SYMCLK_CGTT_BLK_CTRL_REG
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//PHYPLLF_PIXCLK_RESYNC_CNTL
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
+//DCCG_DISP_CNTL_REG
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L
+//OTG0_PIXEL_RATE_CNTL
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT 0x8
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT 0x9
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT 0xe
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK 0x00000100L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK 0x00000200L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK 0x0000C000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO0_PHASE
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO0_MODULO
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL
+//OTG0_PHYPLL_PIXEL_RATE_CNTL
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//OTG1_PIXEL_RATE_CNTL
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT 0x8
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT 0xe
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK 0x00000100L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK 0x0000C000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO1_PHASE
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO1_MODULO
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL
+//OTG1_PHYPLL_PIXEL_RATE_CNTL
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//OTG2_PIXEL_RATE_CNTL
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT 0x8
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT 0x9
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT 0xe
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT 0x10
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK 0x00000100L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK 0x00000200L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK 0x0000C000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO2_PHASE
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO2_MODULO
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL
+//OTG2_PHYPLL_PIXEL_RATE_CNTL
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//OTG3_PIXEL_RATE_CNTL
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT 0x8
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT 0x9
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT 0xe
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT 0x10
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK 0x00000100L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK 0x00000200L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK 0x0000C000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO3_PHASE
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO3_MODULO
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL
+//OTG3_PHYPLL_PIXEL_RATE_CNTL
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//OTG4_PIXEL_RATE_CNTL
+#define OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
+#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
+#define OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL__SHIFT 0x8
+#define OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL__SHIFT 0x9
+#define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define OTG4_PIXEL_RATE_CNTL__OTG4_DIO_FIFO_ERROR__SHIFT 0xe
+#define OTG4_PIXEL_RATE_CNTL__OTG4_DIO_ERROR_COUNT__SHIFT 0x10
+#define OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L
+#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x00000020L
+#define OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL_MASK 0x00000100L
+#define OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL_MASK 0x00000200L
+#define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define OTG4_PIXEL_RATE_CNTL__OTG4_DIO_FIFO_ERROR_MASK 0x0000C000L
+#define OTG4_PIXEL_RATE_CNTL__OTG4_DIO_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO4_PHASE
+#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
+#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO4_MODULO
+#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
+#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xFFFFFFFFL
+//OTG4_PHYPLL_PIXEL_RATE_CNTL
+#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//OTG5_PIXEL_RATE_CNTL
+#define OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
+#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
+#define OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL__SHIFT 0x8
+#define OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL__SHIFT 0x9
+#define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_HALF_RATE_EN__SHIFT 0xb
+#define OTG5_PIXEL_RATE_CNTL__OTG5_DIO_FIFO_ERROR__SHIFT 0xe
+#define OTG5_PIXEL_RATE_CNTL__OTG5_DIO_ERROR_COUNT__SHIFT 0x10
+#define OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE_MASK 0x00000003L
+#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L
+#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x00000020L
+#define OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL_MASK 0x00000100L
+#define OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL_MASK 0x00000200L
+#define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_HALF_RATE_EN_MASK 0x00000800L
+#define OTG5_PIXEL_RATE_CNTL__OTG5_DIO_FIFO_ERROR_MASK 0x0000C000L
+#define OTG5_PIXEL_RATE_CNTL__OTG5_DIO_ERROR_COUNT_MASK 0x0FFF0000L
+//DP_DTO5_PHASE
+#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
+#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xFFFFFFFFL
+//DP_DTO5_MODULO
+#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
+#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xFFFFFFFFL
+//OTG5_PHYPLL_PIXEL_RATE_CNTL
+#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4
+#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L
+#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L
+//DPPCLK_CGTT_BLK_CTRL_REG
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+//DPPCLK0_DTO_PARAM
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT 0x0
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK 0x000000FFL
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK 0x00FF0000L
+//DPPCLK1_DTO_PARAM
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT 0x0
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK 0x000000FFL
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK 0x00FF0000L
+//DPPCLK2_DTO_PARAM
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT 0x0
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT 0x10
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK 0x000000FFL
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK 0x00FF0000L
+//DPPCLK3_DTO_PARAM
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT 0x0
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT 0x10
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK 0x000000FFL
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK 0x00FF0000L
+//DPPCLK4_DTO_PARAM
+#define DPPCLK4_DTO_PARAM__DPPCLK4_DTO_PHASE__SHIFT 0x0
+#define DPPCLK4_DTO_PARAM__DPPCLK4_DTO_MODULO__SHIFT 0x10
+#define DPPCLK4_DTO_PARAM__DPPCLK4_DTO_PHASE_MASK 0x000000FFL
+#define DPPCLK4_DTO_PARAM__DPPCLK4_DTO_MODULO_MASK 0x00FF0000L
+//DPPCLK5_DTO_PARAM
+#define DPPCLK5_DTO_PARAM__DPPCLK5_DTO_PHASE__SHIFT 0x0
+#define DPPCLK5_DTO_PARAM__DPPCLK5_DTO_MODULO__SHIFT 0x10
+#define DPPCLK5_DTO_PARAM__DPPCLK5_DTO_PHASE_MASK 0x000000FFL
+#define DPPCLK5_DTO_PARAM__DPPCLK5_DTO_MODULO_MASK 0x00FF0000L
+//DCCG_CAC_STATUS2
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT 0x0
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK 0x0000007FL
+//SYMCLKA_CLOCK_ENABLE
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKB_CLOCK_ENABLE
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKC_CLOCK_ENABLE
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKD_CLOCK_ENABLE
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKE_CLOCK_ENABLE
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L
+//SYMCLKF_CLOCK_ENABLE
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L
+//DCCG_SOFT_RESET
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x00000002L
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L
+//DSCCLK_DTO_CTRL
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT 0x0
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT 0x1
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT 0x2
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT 0x3
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT 0x4
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT 0x5
+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE__SHIFT 0x6
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT 0x8
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT 0x9
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT 0xb
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT 0xc
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT 0xd
+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN__SHIFT 0xe
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK 0x00000001L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK 0x00000002L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK 0x00000004L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK 0x00000008L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK 0x00000010L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK 0x00000020L
+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE_MASK 0x00000040L
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK 0x00000100L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK 0x00000200L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK 0x00000400L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK 0x00000800L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK 0x00001000L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK 0x00002000L
+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN_MASK 0x00004000L
+//DCCG_AUDIO_DTO_SOURCE
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x00003000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x00010000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L
+//DCCG_AUDIO_DTO0_PHASE
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL
+//DCCG_AUDIO_DTO0_MODULE
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_PHASE
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_MODULE
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL
+//DCCG_VSYNC_OTG0_LATCH_VALUE
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL
+//DCCG_VSYNC_OTG1_LATCH_VALUE
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL
+//DCCG_VSYNC_OTG2_LATCH_VALUE
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL
+//DCCG_VSYNC_OTG3_LATCH_VALUE
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL
+//DCCG_VSYNC_OTG4_LATCH_VALUE
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL
+//DCCG_VSYNC_OTG5_LATCH_VALUE
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL
+//DPPCLK_DTO_CTRL
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT 0x0
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT 0x1
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT 0x4
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT 0x5
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT 0x8
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT 0x9
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT 0xc
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT 0xd
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT 0x10
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT 0x11
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT 0x14
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT 0x15
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK 0x00000001L
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK 0x00000002L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK 0x00000010L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK 0x00000020L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK 0x00000100L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK 0x00000200L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK 0x00001000L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK 0x00002000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK 0x00010000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK 0x00020000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK 0x00100000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK 0x00200000L
+//DCCG_VSYNC_CNT_CTRL
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT 0x1
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK 0x00000002L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L
+//DCCG_VSYNC_CNT_INT_CTRL
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x8
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x9
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0xb
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0xc
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0xd
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00000100L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00000200L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00000400L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00000800L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00001000L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00002000L
+//FORCE_SYMCLK_DISABLE
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT 0x0
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT 0x1
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT 0x2
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT 0x3
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT 0x4
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT 0x5
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT 0x6
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK 0x00000001L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK 0x00000002L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK 0x00000004L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK 0x00000008L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK 0x00000010L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK 0x00000020L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK 0x00000040L
+//DCCG_TEST_CLK_SEL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT 0xe
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK 0x0000C000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+//DENTIST_DISPCLK_CNTL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK 0x00200000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK 0x00400000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+//DC_PERFMON0_PERFCOUNTER_CNTL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_CNTL2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_STATE
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON0_PERFMON_CNTL
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON0_PERFMON_CNTL2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON0_PERFMON_CVALUE_LOW
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON0_PERFMON_HI
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON0_PERFMON_LOW
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
+//DC_PERFMON1_PERFCOUNTER_CNTL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_CNTL2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_STATE
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON1_PERFMON_CNTL
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON1_PERFMON_CNTL2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON1_PERFMON_CVALUE_LOW
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON1_PERFMON_HI
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON1_PERFMON_LOW
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dccg_dccg_pll_dispdec
+//PLL_MACRO_CNTL_RESERVED0
+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED1
+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED2
+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED3
+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED4
+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED5
+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED6
+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED7
+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED8
+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED9
+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED10
+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED11
+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED12
+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED13
+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED14
+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED15
+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED16
+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED17
+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED18
+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED19
+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED20
+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED21
+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED22
+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED23
+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED24
+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED25
+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED26
+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED27
+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED28
+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED29
+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED30
+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED31
+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED32
+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED33
+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED34
+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED35
+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED36
+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED37
+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED38
+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED39
+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED40
+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//PLL_MACRO_CNTL_RESERVED41
+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+//RBBMIF_TIMEOUT
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L
+//RBBMIF_STATUS
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xFFFFFFFFL
+//RBBMIF_STATUS_2
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT 0x0
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK 0x0000001FL
+//RBBMIF_INT_STATUS
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK 0x0003FFFCL
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L
+//RBBMIF_TIMEOUT_DIS
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT 0x1e
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT 0x1f
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK 0x40000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK 0x80000000L
+//RBBMIF_TIMEOUT_DIS_2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT 0x0
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT 0x1
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT 0x2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT 0x3
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT 0x4
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK 0x00000001L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK 0x00000002L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK 0x00000004L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK 0x00000008L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK 0x00000010L
+//RBBMIF_STATUS_FLAG
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+//DOMAIN0_PG_CONFIG
+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE__SHIFT 0x8
+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE_MASK 0x00000100L
+//DOMAIN0_PG_STATUS
+#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN1_PG_CONFIG
+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE__SHIFT 0x8
+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE_MASK 0x00000100L
+//DOMAIN1_PG_STATUS
+#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN2_PG_CONFIG
+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE__SHIFT 0x8
+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE_MASK 0x00000100L
+//DOMAIN2_PG_STATUS
+#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN3_PG_CONFIG
+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE__SHIFT 0x8
+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE_MASK 0x00000100L
+//DOMAIN3_PG_STATUS
+#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN4_PG_CONFIG
+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE__SHIFT 0x8
+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE_MASK 0x00000100L
+//DOMAIN4_PG_STATUS
+#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN5_PG_CONFIG
+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE__SHIFT 0x8
+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE_MASK 0x00000100L
+//DOMAIN5_PG_STATUS
+#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN6_PG_CONFIG
+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE__SHIFT 0x8
+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE_MASK 0x00000100L
+//DOMAIN6_PG_STATUS
+#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN7_PG_CONFIG
+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE__SHIFT 0x8
+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE_MASK 0x00000100L
+//DOMAIN7_PG_STATUS
+#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN8_PG_CONFIG
+#define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_GATE__SHIFT 0x8
+#define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_GATE_MASK 0x00000100L
+//DOMAIN8_PG_STATUS
+#define DOMAIN8_PG_STATUS__DOMAIN8_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN8_PG_STATUS__DOMAIN8_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN8_PG_STATUS__DOMAIN8_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN8_PG_STATUS__DOMAIN8_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN9_PG_CONFIG
+#define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_GATE__SHIFT 0x8
+#define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_GATE_MASK 0x00000100L
+//DOMAIN9_PG_STATUS
+#define DOMAIN9_PG_STATUS__DOMAIN9_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN9_PG_STATUS__DOMAIN9_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN9_PG_STATUS__DOMAIN9_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN9_PG_STATUS__DOMAIN9_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN10_PG_CONFIG
+#define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_GATE__SHIFT 0x8
+#define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_GATE_MASK 0x00000100L
+//DOMAIN10_PG_STATUS
+#define DOMAIN10_PG_STATUS__DOMAIN10_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN10_PG_STATUS__DOMAIN10_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN10_PG_STATUS__DOMAIN10_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN10_PG_STATUS__DOMAIN10_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN11_PG_CONFIG
+#define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_GATE__SHIFT 0x8
+#define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_GATE_MASK 0x00000100L
+//DOMAIN11_PG_STATUS
+#define DOMAIN11_PG_STATUS__DOMAIN11_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN11_PG_STATUS__DOMAIN11_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN11_PG_STATUS__DOMAIN11_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN11_PG_STATUS__DOMAIN11_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN16_PG_CONFIG
+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE__SHIFT 0x8
+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE_MASK 0x00000100L
+//DOMAIN16_PG_STATUS
+#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN17_PG_CONFIG
+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE__SHIFT 0x8
+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE_MASK 0x00000100L
+//DOMAIN17_PG_STATUS
+#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN18_PG_CONFIG
+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE__SHIFT 0x8
+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE_MASK 0x00000100L
+//DOMAIN18_PG_STATUS
+#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN19_PG_CONFIG
+#define DOMAIN19_PG_CONFIG__DOMAIN19_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN19_PG_CONFIG__DOMAIN19_POWER_GATE__SHIFT 0x8
+#define DOMAIN19_PG_CONFIG__DOMAIN19_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN19_PG_CONFIG__DOMAIN19_POWER_GATE_MASK 0x00000100L
+//DOMAIN19_PG_STATUS
+#define DOMAIN19_PG_STATUS__DOMAIN19_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN19_PG_STATUS__DOMAIN19_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN19_PG_STATUS__DOMAIN19_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN19_PG_STATUS__DOMAIN19_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN20_PG_CONFIG
+#define DOMAIN20_PG_CONFIG__DOMAIN20_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN20_PG_CONFIG__DOMAIN20_POWER_GATE__SHIFT 0x8
+#define DOMAIN20_PG_CONFIG__DOMAIN20_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN20_PG_CONFIG__DOMAIN20_POWER_GATE_MASK 0x00000100L
+//DOMAIN20_PG_STATUS
+#define DOMAIN20_PG_STATUS__DOMAIN20_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN20_PG_STATUS__DOMAIN20_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN20_PG_STATUS__DOMAIN20_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN20_PG_STATUS__DOMAIN20_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DOMAIN21_PG_CONFIG
+#define DOMAIN21_PG_CONFIG__DOMAIN21_POWER_FORCEON__SHIFT 0x0
+#define DOMAIN21_PG_CONFIG__DOMAIN21_POWER_GATE__SHIFT 0x8
+#define DOMAIN21_PG_CONFIG__DOMAIN21_POWER_FORCEON_MASK 0x00000001L
+#define DOMAIN21_PG_CONFIG__DOMAIN21_POWER_GATE_MASK 0x00000100L
+//DOMAIN21_PG_STATUS
+#define DOMAIN21_PG_STATUS__DOMAIN21_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DOMAIN21_PG_STATUS__DOMAIN21_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DOMAIN21_PG_STATUS__DOMAIN21_DESIRED_PWR_STATE_MASK 0x10000000L
+#define DOMAIN21_PG_STATUS__DOMAIN21_PGFSM_PWR_STATUS_MASK 0xC0000000L
+//DCPG_INTERRUPT_STATUS
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x8
+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9
+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0xa
+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0xc
+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xd
+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0xe
+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xf
+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x10
+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0x11
+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x12
+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x14
+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x16
+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x18
+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x19
+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x1a
+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x1b
+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x1c
+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x1d
+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x1e
+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x1f
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L
+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00000100L
+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L
+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00000400L
+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L
+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00001000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00004000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00010000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00040000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00100000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00400000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x01000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x02000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x04000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x08000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x10000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x20000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x40000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x80000000L
+//DCPG_INTERRUPT_STATUS_2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x1
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x4
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x6
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT 0x8
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT 0x9
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT 0xa
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000004L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000010L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000040L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED_MASK 0x00000100L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED_MASK 0x00000400L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L
+//DCPG_INTERRUPT_CONTROL_1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK__SHIFT 0x10
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK__SHIFT 0x12
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK__SHIFT 0x14
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x15
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK__SHIFT 0x16
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK__SHIFT 0x18
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x19
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK__SHIFT 0x1a
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK__SHIFT 0x1c
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1d
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK__SHIFT 0x1e
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0x1f
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK_MASK 0x00010000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00020000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK_MASK 0x00040000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK_MASK 0x00100000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00200000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK_MASK 0x00400000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK_MASK 0x01000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x02000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK_MASK 0x04000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x08000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK_MASK 0x10000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x20000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK_MASK 0x40000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x80000000L
+//DCPG_INTERRUPT_CONTROL_2
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK__SHIFT 0x0
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x1
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK__SHIFT 0x2
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0x3
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK__SHIFT 0x4
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x5
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK__SHIFT 0x6
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0x7
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK__SHIFT 0x8
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x9
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK__SHIFT 0xa
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xb
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK__SHIFT 0xc
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK__SHIFT 0xe
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK__SHIFT 0x10
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK__SHIFT 0x12
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK__SHIFT 0x14
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x15
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK__SHIFT 0x16
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK__SHIFT 0x18
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x19
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK__SHIFT 0x1a
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK__SHIFT 0x1c
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x1d
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK__SHIFT 0x1e
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x1f
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK_MASK 0x00000001L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000002L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK_MASK 0x00000004L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00000008L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK_MASK 0x00000010L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000020L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK_MASK 0x00000040L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00000080L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK_MASK 0x00000100L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000200L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK_MASK 0x00000400L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00000800L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK_MASK 0x00001000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00002000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK_MASK 0x00004000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK_MASK 0x00010000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00020000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK_MASK 0x00040000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK_MASK 0x00100000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00200000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK_MASK 0x00400000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK_MASK 0x01000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x02000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK_MASK 0x04000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x08000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK_MASK 0x10000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x20000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK_MASK 0x40000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x80000000L
+//DCPG_INTERRUPT_CONTROL_3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT 0x0
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x1
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT 0x2
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT 0x4
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x5
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT 0x6
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT 0x8
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x9
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT 0xa
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0xb
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT 0xc
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT 0xe
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0xf
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK__SHIFT 0x10
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK__SHIFT 0x12
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK__SHIFT 0x14
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR__SHIFT 0x15
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK__SHIFT 0x16
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK 0x00000001L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000002L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK 0x00000004L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000008L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK 0x00000010L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000020L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK 0x00000040L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK 0x00000100L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000200L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK 0x00000400L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000800L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK 0x00001000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00002000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK 0x00004000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00008000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK_MASK 0x00010000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR_MASK 0x00020000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK_MASK 0x00040000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK_MASK 0x00100000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR_MASK 0x00200000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK_MASK 0x00400000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
+//DC_IP_REQUEST_CNTL
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON2_PERFCOUNTER_CNTL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_CNTL2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_STATE
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON2_PERFMON_CNTL
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON2_PERFMON_CNTL2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON2_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON2_PERFMON_CVALUE_LOW
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON2_PERFMON_HI
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON2_PERFMON_LOW
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+//CC_DC_PIPE_DIS
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT 0x10
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK 0x00010000L
+//DMU_CLK_CNTL
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x4
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x5
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT 0x6
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT 0x8
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT 0x9
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT 0xa
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x0000000FL
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000010L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00000020L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK 0x00000040L
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK 0x00000100L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK 0x00000200L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK 0x00000400L
+//DMU_MEM_PWR_CNTL
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x1
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0x3
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x4
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0x8
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0x9
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000006L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000008L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000030L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00000100L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00000200L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
+//DMCU_SMU_INTERRUPT_CNTL
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x00000001L
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xFFFF0000L
+//SMU_INTERRUPT_CONTROL
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L
+//DMU_MISC_ALLOW_DS_FORCE
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT 0x0
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT 0x4
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK 0x00000001L
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+//DMCU_CTRL
+#define DMCU_CTRL__RESET_UC__SHIFT 0x0
+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
+#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10
+#define DMCU_CTRL__RESET_UC_MASK 0x00000001L
+#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L
+#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L
+//DMCU_STATUS
+#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
+#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L
+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L
+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L
+//DMCU_PC_START_ADDR
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L
+//DMCU_FW_START_ADDR
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L
+//DMCU_FW_END_ADDR
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L
+//DMCU_FW_ISR_START_ADDR
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L
+//DMCU_FW_CS_HI
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL
+//DMCU_FW_CS_LO
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL
+//DMCU_RAM_ACCESS_CTRL
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L
+//DMCU_ERAM_WR_CTRL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L
+//DMCU_ERAM_WR_DATA
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL
+//DMCU_ERAM_RD_CTRL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L
+//DMCU_ERAM_RD_DATA
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL
+//DMCU_IRAM_WR_CTRL
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL
+//DMCU_IRAM_WR_DATA
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL
+//DMCU_IRAM_RD_CTRL
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL
+//DMCU_IRAM_RD_DATA
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL
+//DMCU_EVENT_TRIGGER
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L
+//DMCU_UC_INTERNAL_INT_STATUS
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L
+//DMCU_SS_INTERRUPT_CNTL_STATUS
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L
+//DMCU_INTERRUPT_STATUS
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L
+//DMCU_INTERRUPT_STATUS_1
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L
+//DMCU_INTERRUPT_TO_HOST_EN_MASK
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000010L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000020L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L
+//DMCU_INTERRUPT_TO_UC_EN_MASK
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+//DC_DMCU_SCRATCH
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL
+//DMCU_INT_CNT
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L
+//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL
+//DMCU_UC_CLK_GATING_CNTL
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L
+//MASTER_COMM_DATA_REG1
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L
+//MASTER_COMM_DATA_REG2
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L
+//MASTER_COMM_DATA_REG3
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L
+//MASTER_COMM_CMD_REG
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L
+//MASTER_COMM_CNTL_REG
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L
+//SLAVE_COMM_DATA_REG1
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L
+//SLAVE_COMM_DATA_REG2
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L
+//SLAVE_COMM_DATA_REG3
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L
+//SLAVE_COMM_CMD_REG
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L
+//SLAVE_COMM_CNTL_REG
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L
+//DMCU_PERFMON_INTERRUPT_STATUS2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L
+//DMCU_PERFMON_INTERRUPT_STATUS4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L
+//DMCU_PERFMON_INTERRUPT_STATUS5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+//DMCU_DPRX_INTERRUPT_STATUS1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
+//DMCU_INTERRUPT_STATUS_CONTINUE
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000008L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000010L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00000020L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00000040L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00000080L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00001000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00001000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00002000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00004000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00004000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00010000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00020000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x00040000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK 0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK 0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK 0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK 0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK 0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK 0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK 0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK 0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK 0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK 0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK 0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK 0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK 0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK 0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK 0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK 0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK 0x10000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK 0x10000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK 0x00001000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK 0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK 0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK 0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK 0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK 0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK 0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK 0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK 0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK 0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK 0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK 0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK 0x10000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK 0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK 0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK 0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK 0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
+//DMCU_INT_CNT_CONTINUE
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT 0x0
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT 0x8
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT 0x10
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK 0x000000FFL
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK 0x0000FF00L
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK 0x00FF0000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
+//DMCU_INTERRUPT_STATUS_2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000001L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000002L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000004L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000008L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00000008L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK 0x00000010L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK 0x00000010L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK 0x00000020L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK 0x00000020L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000040L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000040L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000100L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00000200L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK 0x00000400L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK 0x00000800L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK 0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK 0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK 0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK 0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK 0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK 0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK 0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK 0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK 0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK 0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK 0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK 0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK 0x00400000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK 0x00400000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK 0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK 0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK 0x00400000L
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+//DC_GPU_TIMER_START_POSITION_V_UPDATE
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L
+//DC_GPU_TIMER_START_POSITION_VSTARTUP
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L
+//DC_GPU_TIMER_READ
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL
+//DC_GPU_TIMER_READ_CNTL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L
+//DISP_INTERRUPT_STATUS
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE14
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE15
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE19
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE20
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE21
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE22
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK 0x80000000L
+//DC_GPU_TIMER_START_POSITION_VREADY
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L
+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L
+//DISP_INTERRUPT_STATUS_CONTINUE23
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK 0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK 0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK 0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE24
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK 0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK 0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK 0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK 0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK 0x02000000L
+//DCCG_INTERRUPT_DEST
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT 0x0
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT 0x1
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT 0x2
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT 0x3
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT 0x4
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT 0x5
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT 0xe
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT 0xf
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK 0x00000001L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK 0x00000002L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK 0x00000004L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK 0x00000008L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK 0x00000010L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK 0x00000020L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L
+//DMU_INTERRUPT_DEST
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT 0x0
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT 0x1
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT 0x2
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT 0x3
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT 0x4
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT 0x5
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT 0x6
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT 0x7
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT 0x8
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT 0x9
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT 0xa
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT 0xb
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT 0xe
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT 0xf
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x10
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT 0x11
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT 0x12
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x13
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT 0x18
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT 0x19
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1a
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT 0x1b
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT 0x1c
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK 0x00000001L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK 0x00000002L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK 0x00000004L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK 0x00000008L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK 0x00000010L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK 0x00000020L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK 0x00000040L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK 0x00000080L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK 0x00000100L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK 0x00000200L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK 0x00000400L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK 0x00000800L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK 0x00004000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK 0x00008000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK 0x00010000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK 0x00020000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK 0x00040000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK 0x00080000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK 0x01000000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK 0x02000000L
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x04000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK 0x08000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK 0x10000000L
+//DCPG_INTERRUPT_DEST
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT 0x0
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT 0x1
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT 0x2
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT 0x3
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT 0x4
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT 0x5
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT 0x6
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT 0x7
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST__SHIFT 0x8
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST__SHIFT 0x9
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST__SHIFT 0xa
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST__SHIFT 0xb
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST__SHIFT 0xc
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST__SHIFT 0xd
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST__SHIFT 0xe
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST__SHIFT 0xf
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x18
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x19
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1a
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1b
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1c
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1d
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1e
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1f
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST_MASK 0x00000100L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST_MASK 0x00000200L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST_MASK 0x00000400L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST_MASK 0x00000800L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST_MASK 0x00001000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST_MASK 0x00002000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST_MASK 0x00004000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST_MASK 0x00008000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST_MASK 0x01000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST_MASK 0x02000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST_MASK 0x04000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST_MASK 0x08000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST_MASK 0x10000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST_MASK 0x20000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST_MASK 0x40000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST_MASK 0x80000000L
+//DCPG_INTERRUPT_DEST2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT 0x0
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT 0x1
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT 0x2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT 0x3
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT 0x4
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT 0x5
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x6
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x7
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x8
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x9
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xa
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xb
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000040L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000080L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000100L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000200L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000400L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000800L
+//MMHUBBUB_INTERRUPT_DEST
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT 0x0
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT 0x1
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT 0x2
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT 0x3
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT 0x4
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT 0x5
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK 0x00000001L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK 0x00000002L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK 0x00000004L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK 0x00000008L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK 0x00000010L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK 0x00000020L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+//WB_INTERRUPT_DEST
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT 0x0
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x1
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT 0x8
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x9
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT 0xa
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0xb
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK 0x00000001L
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000002L
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK 0x00000100L
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000200L
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK 0x00000400L
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000800L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L
+//DCHUB_INTERRUPT_DEST
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x0
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x2
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT 0x3
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x4
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x5
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x6
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT 0x7
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x8
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x9
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xa
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT 0xb
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0xc
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT 0xd
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xe
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT 0xf
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x10
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x11
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x12
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT 0x13
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x14
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x15
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x16
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT 0x17
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x18
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x19
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1a
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT 0x1b
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x1c
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1d
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1e
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST__SHIFT 0x1f
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000001L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000002L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000004L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK 0x00000008L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000010L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000020L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000040L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK 0x00000080L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000100L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000200L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000400L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK 0x00000800L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00001000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK 0x00002000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00004000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK 0x00008000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00010000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK 0x00020000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00040000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK 0x00080000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00100000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK 0x00200000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00400000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK 0x00800000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK 0x01000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK 0x02000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK 0x04000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK 0x08000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK 0x10000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK 0x20000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK 0x40000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT_DEST_MASK 0x80000000L
+//DCHUB_PERFCOUNTER_INTERRUPT_DEST
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1c
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1d
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x10000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x20000000L
+//DCHUB_INTERRUPT_DEST2
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x0
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x1
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x2
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x3
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x4
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x5
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x6
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x7
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x8
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x9
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xa
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xb
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xc
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xd
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xe
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xf
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT 0x18
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000001L
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000002L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000004L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000008L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000010L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000020L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000040L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000080L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000100L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000200L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000400L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000800L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK 0x00001000L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00002000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK 0x00004000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00008000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK 0x01000000L
+//DPP_PERFCOUNTER_INTERRUPT_DEST
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L
+//MPC_INTERRUPT_DEST
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT 0x0
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT 0x1
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT 0x2
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT 0x3
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT 0x4
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT 0x5
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT 0x6
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT 0x7
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK 0x00000001L
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK 0x00000002L
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK 0x00000004L
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK 0x00000008L
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK 0x00000010L
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK 0x00000020L
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK 0x00000040L
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK 0x00000080L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+//OPP_INTERRUPT_DEST
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+//OPTC_INTERRUPT_DEST
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x18
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x19
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1a
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1b
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1c
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1d
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x01000000L
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x02000000L
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x04000000L
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x08000000L
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x10000000L
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x20000000L
+//OTG0_INTERRUPT_DEST
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L
+//OTG1_INTERRUPT_DEST
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L
+//OTG2_INTERRUPT_DEST
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L
+//OTG3_INTERRUPT_DEST
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L
+//OTG4_INTERRUPT_DEST
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L
+//OTG5_INTERRUPT_DEST
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L
+//DIG_INTERRUPT_DEST
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x0
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x1
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x2
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x3
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x4
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x5
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x6
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x7
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x8
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x9
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xa
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xb
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xc
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xd
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xe
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xf
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000001L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000002L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000004L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000008L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000010L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000020L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000040L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000080L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000100L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000200L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000400L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000800L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00001000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00002000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00004000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00008000L
+//I2C_DDC_HPD_INTERRUPT_DEST
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT 0x0
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT 0x1
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT 0x2
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT 0x3
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT 0x4
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT 0x5
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT 0x6
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT 0x7
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x10
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x11
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x12
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x13
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x14
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x15
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x16
+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x17
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK 0x00000002L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK 0x00000004L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK 0x00000008L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK 0x00000010L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK 0x00000020L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK 0x00000040L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK 0x00000080L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK 0x00010000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK 0x00020000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK 0x00040000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK 0x00080000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK 0x00100000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK 0x00200000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK 0x00400000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST_MASK 0x00800000L
+//DIO_INTERRUPT_DEST
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L
+//DCIO_INTERRUPT_DEST
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x0
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x1
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x2
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x3
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x4
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x5
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x6
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x10
+#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST__SHIFT 0x18
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000001L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000002L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000004L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000008L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000010L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000020L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000040L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00010000L
+#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST_MASK 0x01000000L
+//HPD_INTERRUPT_DEST
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT 0x0
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT 0x1
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT 0x2
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT 0x3
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT 0x4
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT 0x5
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT 0x8
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT 0x9
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT 0xa
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT 0xb
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT 0xc
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT 0xd
+#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST__SHIFT 0xe
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK 0x00000001L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK 0x00000002L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK 0x00000004L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK 0x00000008L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK 0x00000010L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK 0x00000020L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK 0x00000100L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK 0x00000200L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK 0x00000400L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK 0x00000800L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK 0x00001000L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK 0x00002000L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST_MASK 0x00004000L
+//AZ_INTERRUPT_DEST
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x0
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x1
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x2
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x3
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x4
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x5
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x6
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x7
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT 0x8
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT 0x9
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT 0xa
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT 0xb
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT 0xc
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT 0xd
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT 0xe
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT 0xf
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT 0x10
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT 0x11
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT 0x12
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT 0x13
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT 0x14
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT 0x15
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT 0x16
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT 0x17
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1e
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1f
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000001L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000002L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000004L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000008L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000010L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000020L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000040L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000080L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK 0x00000100L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK 0x00000200L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK 0x00000400L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK 0x00000800L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK 0x00001000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK 0x00002000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK 0x00004000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK 0x00008000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK 0x00010000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK 0x00020000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK 0x00040000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK 0x00080000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK 0x00100000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK 0x00200000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK 0x00400000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK 0x00800000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x40000000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x80000000L
+//AUX_INTERRUPT_DEST
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT 0x0
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT 0x1
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT 0x2
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT 0x3
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT 0x4
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT 0x5
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT 0x6
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT 0x7
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT 0x8
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT 0x9
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT 0xa
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT 0xb
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x10
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x11
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x12
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x13
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x14
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x15
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x16
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x17
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x18
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x19
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x1a
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x1b
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK 0x00000002L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK 0x00000004L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK 0x00000008L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK 0x00000010L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK 0x00000020L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK 0x00000040L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK 0x00000080L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK 0x00000100L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK 0x00000200L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK 0x00000400L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK 0x00000800L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00010000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00020000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00040000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00080000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00100000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00200000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00400000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00800000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x01000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x02000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x04000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x08000000L
+//DSC_INTERRUPT_DEST
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x0
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x1
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x4
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x5
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x6
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x7
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x8
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x9
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xa
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xb
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0xc
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0xd
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x10
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x11
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x14
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x15
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000001L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000002L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000010L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000020L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000040L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000080L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000100L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000200L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000400L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000800L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00001000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00002000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00010000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00020000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00100000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00200000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L
+
+
+// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
+//WB_ENABLE
+#define WB_ENABLE__WB_ENABLE__SHIFT 0x0
+#define WB_ENABLE__WB_ENABLE_MASK 0x00000001L
+//WB_EC_CONFIG
+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0
+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2
+#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3
+#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7
+#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8
+#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15
+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17
+#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE__SHIFT 0x18
+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L
+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L
+#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L
+#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L
+#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L
+#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L
+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L
+#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE_MASK 0x03000000L
+//CNV_MODE
+#define CNV_MODE__CNV_OUT_BPC__SHIFT 0x4
+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8
+#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc
+#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd
+#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf
+#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
+#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12
+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13
+#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14
+#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT__SHIFT 0x1e
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f
+#define CNV_MODE__CNV_OUT_BPC_MASK 0x00000010L
+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L
+#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L
+#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L
+#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L
+#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L
+#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L
+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L
+#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L
+#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT_MASK 0x40000000L
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L
+//CNV_WINDOW_START
+#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
+#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L
+//CNV_WINDOW_SIZE
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L
+//CNV_UPDATE
+#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
+#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
+#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
+#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L
+#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L
+#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L
+//CNV_SOURCE_SIZE
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L
+//CNV_TEST_CNTL
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L
+//CNV_TEST_CRC_RED
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L
+//CNV_TEST_CRC_GREEN
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//CNV_TEST_CRC_BLUE
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L
+//WB_DEBUG_CTRL
+#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0
+#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6
+#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x00000001L
+#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0x000000C0L
+//WB_DBG_MODE
+#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0
+#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1
+#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2
+#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3
+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8
+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10
+#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x00000001L
+#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x00000002L
+#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x00000004L
+#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x00000008L
+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x00000100L
+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7FFF0000L
+//WB_HW_DEBUG
+#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0
+#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xFFFFFFFFL
+//WB_SOFT_RESET
+#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0
+#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L
+//WB_WARM_UP_MODE_CTL1
+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0
+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10
+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f
+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL
+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L
+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L
+//WB_WARM_UP_MODE_CTL2
+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0
+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x10
+#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP__SHIFT 0x14
+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000003FFL
+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00010000L
+#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP_MASK 0x00100000L
+//CNV_TEST_DEBUG_INDEX
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//CNV_TEST_DEBUG_DATA
+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0
+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
+//WBSCL_COEF_RAM_SELECT
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L
+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L
+//WBSCL_COEF_RAM_TAP_DATA
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//WBSCL_MODE
+#define WBSCL_MODE__WBSCL_MODE__SHIFT 0x0
+#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH__SHIFT 0x4
+#define WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L
+#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH_MASK 0x00000010L
+//WBSCL_TAP_CONTROL
+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0
+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4
+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8
+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc
+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL
+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L
+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L
+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L
+//WBSCL_DEST_SIZE
+#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0
+#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10
+#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL
+#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L
+//WBSCL_HORZ_FILTER_SCALE_RATIO
+#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0
+#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL
+//WBSCL_HORZ_FILTER_INIT_Y_RGB
+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0
+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18
+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL
+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L
+//WBSCL_HORZ_FILTER_INIT_CBCR
+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0
+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18
+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL
+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L
+//WBSCL_VERT_FILTER_SCALE_RATIO
+#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0
+#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL
+//WBSCL_VERT_FILTER_INIT_Y_RGB
+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0
+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18
+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL
+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L
+//WBSCL_VERT_FILTER_INIT_CBCR
+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0
+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18
+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL
+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L
+//WBSCL_ROUND_OFFSET
+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0
+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x000003FFL
+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0x03FF0000L
+//WBSCL_OVERFLOW_STATUS
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L
+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L
+//WBSCL_COEF_RAM_CONFLICT_STATUS
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L
+//WBSCL_TEST_CNTL
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L
+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L
+//WBSCL_TEST_CRC_RED
+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x0
+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10
+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x000003FFL
+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L
+//WBSCL_TEST_CRC_GREEN
+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0
+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10
+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL
+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L
+//WBSCL_TEST_CRC_BLUE
+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x0
+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10
+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x000003FFL
+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L
+//WBSCL_BACKPRESSURE_CNT_EN
+#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0
+#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L
+//WB_MCIF_BACKPRESSURE_CNT
+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0
+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10
+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL
+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L
+//WBSCL_CLAMP_Y_RGB
+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0
+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x10
+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000003FFL
+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x03FF0000L
+//WBSCL_CLAMP_CBCR
+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x0
+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x10
+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR_MASK 0x000003FFL
+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR_MASK 0x03FF0000L
+//WBSCL_OUTSIDE_PIX_STRATEGY
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L
+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x03FF0000L
+//WBSCL_OUTSIDE_PIX_STRATEGY_CBCR
+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x0
+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x10
+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR_MASK 0x03FF0000L
+//WBSCL_DEBUG
+#define WBSCL_DEBUG__WBSCL_DEBUG__SHIFT 0x0
+#define WBSCL_DEBUG__WBSCL_DEBUG_MASK 0xFFFFFFFFL
+//WBSCL_TEST_DEBUG_INDEX
+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX__SHIFT 0x0
+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//WBSCL_TEST_DEBUG_DATA
+#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA__SHIFT 0x0
+#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON3_PERFCOUNTER_CNTL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_CNTL2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_STATE
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON3_PERFMON_CNTL
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON3_PERFMON_CNTL2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON3_PERFMON_CVALUE_LOW
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON3_PERFMON_HI
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON3_PERFMON_LOW
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+//MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
+//MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R
+#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
+//MCIF_WB0_MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
+//MCIF_WB0_MCIF_WB_BUF_PITCH
+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
+//MCIF_WB0_MCIF_WB_BUF_1_STATUS
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB0_MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB0_MCIF_WB_BUF_2_STATUS
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB0_MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB0_MCIF_WB_BUF_3_STATUS
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB0_MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB0_MCIF_WB_BUF_4_STATUS
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB0_MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
+//MCIF_WB0_MCIF_WB_SCLK_CHANGE
+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
+//MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX
+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA
+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
+//MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0007FFFFL
+//MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
+//MCIF_WB0_MCIF_WB_WATERMARK
+#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
+//MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
+//MCIF_WB0_MCIF_WB_WARM_UP_CNTL
+#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
+#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
+//MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
+//MCIF_WB0_MULTI_LEVEL_QOS_CTRL
+#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
+#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+//MCIF_WB0_MCIF_WB_SECURITY_LEVEL
+#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK 0x00000007L
+//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
+//MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+//MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+//MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+//MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
+//MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
+//MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R
+#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
+//MCIF_WB1_MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
+//MCIF_WB1_MCIF_WB_BUF_PITCH
+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
+//MCIF_WB1_MCIF_WB_BUF_1_STATUS
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB1_MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB1_MCIF_WB_BUF_2_STATUS
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB1_MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB1_MCIF_WB_BUF_3_STATUS
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB1_MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB1_MCIF_WB_BUF_4_STATUS
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB1_MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
+//MCIF_WB1_MCIF_WB_SCLK_CHANGE
+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
+//MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX
+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA
+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
+//MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0007FFFFL
+//MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
+//MCIF_WB1_MCIF_WB_WATERMARK
+#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
+//MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
+//MCIF_WB1_MCIF_WB_WARM_UP_CNTL
+#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
+#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
+//MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
+//MCIF_WB1_MULTI_LEVEL_QOS_CTRL
+#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
+#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+//MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
+//MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+//MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+//MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+//MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+//WBIF0_MISC_CTRL
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L
+//WBIF0_SMU_WM_CONTROL
+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL__SHIFT 0x14
+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ__SHIFT 0x16
+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18
+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19
+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL_MASK 0x00300000L
+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ_MASK 0x00400000L
+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L
+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L
+//WBIF0_PHASE0_OUTSTANDING_COUNTER
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+//WBIF0_PHASE1_OUTSTANDING_COUNTER
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+//VGA_SRC_SPLIT_CNTL
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT 0x0
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK 0x00000003L
+//MMHUBBUB_MEM_PWR_STATUS
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x1f
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x80000000L
+//MMHUBBUB_MEM_PWR_CNTL
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x0
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x1
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000001L
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000002L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L
+//MMHUBBUB_CLOCK_CNTL
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT 0x6
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT 0x7
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x8
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa
+#define MMHUBBUB_CLOCK_CNTL__DCFCLK_R_XFC_GATE_DIS__SHIFT 0x10
+#define MMHUBBUB_CLOCK_CNTL__DCFCLK_G_XFC_GATE_DIS__SHIFT 0x11
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK 0x00000040L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK 0x00000080L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000100L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L
+#define MMHUBBUB_CLOCK_CNTL__DCFCLK_R_XFC_GATE_DIS_MASK 0x00010000L
+#define MMHUBBUB_CLOCK_CNTL__DCFCLK_G_XFC_GATE_DIS_MASK 0x00020000L
+//MMHUBBUB_SOFT_RESET
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT 0x1
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT 0x8
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK 0x00000002L
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK 0x00000100L
+//DMU_IF_ERR_STATUS
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT 0x0
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT 0x4
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK 0x00000001L
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK 0x00000010L
+//MMHUBBUB_CLIENT_UNIT_ID
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT 0x0
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT 0x8
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK 0x0000003FL
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK 0x00003F00L
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+//MCIF_CONTROL
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L
+//MCIF_WRITE_COMBINE_CONTROL
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL
+//MCIF_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+//MCIF_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+//MCIF_PHASE2_OUTSTANDING_COUNTER
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON4_PERFCOUNTER_CNTL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_CNTL2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_STATE
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON4_PERFMON_CNTL
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON4_PERFMON_CNTL2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON4_PERFMON_CVALUE_LOW
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON4_PERFMON_HI
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON4_PERFMON_LOW
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+//AZF0STREAM0_AZALIA_STREAM_INDEX
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM0_AZALIA_STREAM_DATA
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+//AZF0STREAM1_AZALIA_STREAM_INDEX
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM1_AZALIA_STREAM_DATA
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+//AZF0STREAM2_AZALIA_STREAM_INDEX
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM2_AZALIA_STREAM_DATA
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+//AZF0STREAM3_AZALIA_STREAM_INDEX
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM3_AZALIA_STREAM_DATA
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+//AZF0STREAM4_AZALIA_STREAM_INDEX
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM4_AZALIA_STREAM_DATA
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+//AZF0STREAM5_AZALIA_STREAM_INDEX
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM5_AZALIA_STREAM_DATA
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+//AZF0STREAM6_AZALIA_STREAM_INDEX
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM6_AZALIA_STREAM_DATA
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+//AZF0STREAM7_AZALIA_STREAM_INDEX
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM7_AZALIA_STREAM_DATA
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+//AZ_CLOCK_CNTL
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x10
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0x18
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00010000L
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x1F000000L
+
+
+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON5_PERFCOUNTER_CNTL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_CNTL2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_STATE
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON5_PERFMON_CNTL
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON5_PERFMON_CNTL2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON5_PERFMON_CVALUE_LOW
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON5_PERFMON_HI
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON5_PERFMON_LOW
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+//AZALIA_CONTROLLER_CLOCK_GATING
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L
+//AZALIA_AUDIO_DTO
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L
+//AZALIA_AUDIO_DTO_CONTROL
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L
+//AZALIA_SOCCLK_CONTROL
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L
+//AZALIA_UNDERFLOW_FILLER_SAMPLE
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL
+//AZALIA_DATA_DMA_CONTROL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L
+//AZALIA_BDL_DMA_CONTROL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L
+//AZALIA_RIRB_AND_DP_CONTROL
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L
+//AZALIA_CORB_DMA_CONTROL
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L
+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL
+//AZALIA_CYCLIC_BUFFER_SYNC
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L
+//AZALIA_GLOBAL_CAPABILITIES
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L
+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L
+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L
+//AZALIA_INPUT_PAYLOAD_CAPABILITY
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L
+//AZALIA_INPUT_CRC0_CONTROL0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L
+//AZALIA_INPUT_CRC0_CONTROL1
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CONTROL2
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+//AZALIA_INPUT_CRC0_CONTROL3
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+//AZALIA_INPUT_CRC0_RESULT
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L
+//AZALIA_INPUT_CRC1_CONTROL1
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL2
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+//AZALIA_INPUT_CRC1_CONTROL3
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+//AZALIA_INPUT_CRC1_RESULT
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL0
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L
+//AZALIA_CRC0_CONTROL1
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL2
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+//AZALIA_CRC0_CONTROL3
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+//AZALIA_CRC0_RESULT
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL0
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L
+//AZALIA_CRC1_CONTROL1
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL2
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL
+//AZALIA_CRC1_CONTROL3
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L
+//AZALIA_CRC1_RESULT
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL
+//AZALIA_MEM_PWR_CTRL
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L
+//AZALIA_MEM_PWR_STATUS
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL
+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL
+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L
+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL
+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+//AZALIA_F0_GTC_GROUP_OFFSET0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET1
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET2
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET3
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET4
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET5
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET6
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL
+//REG_DC_AUDIO_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+//AZF0STREAM8_AZALIA_STREAM_INDEX
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM8_AZALIA_STREAM_DATA
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+//AZF0STREAM9_AZALIA_STREAM_INDEX
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM9_AZALIA_STREAM_DATA
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+//AZF0STREAM10_AZALIA_STREAM_INDEX
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM10_AZALIA_STREAM_DATA
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+//AZF0STREAM11_AZALIA_STREAM_INDEX
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM11_AZALIA_STREAM_DATA
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+//AZF0STREAM12_AZALIA_STREAM_INDEX
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM12_AZALIA_STREAM_DATA
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+//AZF0STREAM13_AZALIA_STREAM_INDEX
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM13_AZALIA_STREAM_DATA
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+//AZF0STREAM14_AZALIA_STREAM_INDEX
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM14_AZALIA_STREAM_DATA
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+//AZF0STREAM15_AZALIA_STREAM_INDEX
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
+//AZF0STREAM15_AZALIA_STREAM_DATA
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
+//DCHUBBUB_SDPIF_CFG0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT 0x6
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0xa
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT 0xb
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xc
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0xd
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xe
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xf
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_UNIT_ID_BITMASK__SHIFT 0x10
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x19
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK 0x000003C0L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000400L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK 0x00000800L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00001000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00002000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00004000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00008000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_UNIT_ID_BITMASK_MASK 0x01FF0000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x7E000000L
+//VM_REQUEST_PHYSICAL
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT 0x0
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT 0x3
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK 0x00000001L
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK 0x00000008L
+//DCHUBBUB_FORCE_IO_STATUS_0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L
+//DCHUBBUB_FORCE_IO_STATUS_1
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL
+//DCN_VM_FB_LOCATION_BASE
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
+//DCN_VM_FB_LOCATION_TOP
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
+//DCN_VM_FB_OFFSET
+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
+//DCN_VM_AGP_BOT
+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define DCN_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
+//DCN_VM_AGP_TOP
+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define DCN_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
+//DCN_VM_AGP_BASE
+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define DCN_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_START
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT 0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK 0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_END
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT 0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK 0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
+//DCHUBBUB_SDPIF_PIPE_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x3
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT 0x6
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT 0x9
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE4_SEC_LVL__SHIFT 0xc
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE5_SEC_LVL__SHIFT 0xf
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK 0x00000E00L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE4_SEC_LVL_MASK 0x00007000L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE5_SEC_LVL_MASK 0x00038000L
+//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT 0x0
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT 0x3
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT 0x6
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT 0x9
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE4_DMDATA_SEC_LVL__SHIFT 0xc
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE5_DMDATA_SEC_LVL__SHIFT 0xf
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK 0x00000E00L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE4_DMDATA_SEC_LVL_MASK 0x00007000L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE5_DMDATA_SEC_LVL_MASK 0x00038000L
+//DCHUBBUB_SDPIF_MEM_PWR_CTRL
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L
+//DCHUBBUB_SDPIF_MEM_PWR_STATUS
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L
+//DCHUBBUB_SDPIF_CFG1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT 0x0
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT 0x1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT 0x2
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT 0x8
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK 0x00000001L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK 0x00000002L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK 0x00000004L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK 0x00000100L
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
+//DCHUBBUB_RET_PATH_DCC_CFG
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK 0x00000001L
+//DCHUBBUB_RET_PATH_DCC_CFG0_0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG0_1
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_1
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_1
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_1
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG4_0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG4_1
+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG5_0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG5_1
+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG6_0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG6_1
+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG7_0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG7_1
+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG8_0
+#define DCHUBBUB_RET_PATH_DCC_CFG8_0__DCC_CFG8_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG8_0__DCC_CFG8_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG8_1
+#define DCHUBBUB_RET_PATH_DCC_CFG8_1__DCC_CFG8_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG8_1__DCC_CFG8_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG9_0
+#define DCHUBBUB_RET_PATH_DCC_CFG9_0__DCC_CFG9_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG9_0__DCC_CFG9_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG9_1
+#define DCHUBBUB_RET_PATH_DCC_CFG9_1__DCC_CFG9_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG9_1__DCC_CFG9_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG10_0
+#define DCHUBBUB_RET_PATH_DCC_CFG10_0__DCC_CFG10_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG10_0__DCC_CFG10_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG10_1
+#define DCHUBBUB_RET_PATH_DCC_CFG10_1__DCC_CFG10_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG10_1__DCC_CFG10_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG11_0
+#define DCHUBBUB_RET_PATH_DCC_CFG11_0__DCC_CFG11_CONSTANT_0__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG11_0__DCC_CFG11_CONSTANT_0_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG11_1
+#define DCHUBBUB_RET_PATH_DCC_CFG11_1__DCC_CFG11_CONSTANT_1__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG11_1__DCC_CFG11_CONSTANT_1_MASK 0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L
+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L
+//DCHUBBUB_CRC_CTRL
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB__SHIFT 0xf
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0x14
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00007000L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB_MASK 0x00008000L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00100000L
+//DCHUBBUB_CRC0_VAL_R_G
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT 0x0
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x10
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK 0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFF0000L
+//DCHUBBUB_CRC0_VAL_B_A
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT 0x0
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x10
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK 0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_R_G
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT 0x0
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x10
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK 0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_B_A
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT 0x0
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x10
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK 0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_dispdec
+//DCHUBBUB_ARB_DF_REQ_OUTSTAND
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0x10
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000001FFL
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x01FF0000L
+//DCHUBBUB_ARB_SAT_LEVEL
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL
+//DCHUBBUB_ARB_QOS_FORCE
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L
+//DCHUBBUB_ARB_DRAM_STATE_CNTL
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT 0x8
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT 0x9
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK 0x00000100L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK 0x00000200L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A
+#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__SHIFT 0x0
+#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B
+#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__SHIFT 0x0
+#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C
+#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__SHIFT 0x0
+#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D
+#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__SHIFT 0x0
+#define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0x001FFFFFL
+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK__SHIFT 0x6
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK_MASK 0x00000040L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L
+//DCHUBBUB_ARB_TIMEOUT_ENABLE
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L
+//DCHUBBUB_GLOBAL_TIMER_CNTL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L
+//SURFACE_CHECK0_ADDRESS_LSB
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL
+//SURFACE_CHECK0_ADDRESS_MSB
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L
+//SURFACE_CHECK1_ADDRESS_LSB
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL
+//SURFACE_CHECK1_ADDRESS_MSB
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L
+//SURFACE_CHECK2_ADDRESS_LSB
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL
+//SURFACE_CHECK2_ADDRESS_MSB
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L
+//SURFACE_CHECK3_ADDRESS_LSB
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL
+//SURFACE_CHECK3_ADDRESS_MSB
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L
+//VTG0_CONTROL
+#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0x10
+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f
+#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x7FFF0000L
+#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L
+//VTG1_CONTROL
+#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0x10
+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f
+#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x7FFF0000L
+#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L
+//VTG2_CONTROL
+#define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0x10
+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f
+#define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x7FFF0000L
+#define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L
+//VTG3_CONTROL
+#define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10
+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f
+#define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x7FFF0000L
+#define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L
+//VTG4_CONTROL
+#define VTG4_CONTROL__VTG4_FP2__SHIFT 0x0
+#define VTG4_CONTROL__VTG4_VCOUNT_INIT__SHIFT 0x10
+#define VTG4_CONTROL__VTG4_ENABLE__SHIFT 0x1f
+#define VTG4_CONTROL__VTG4_FP2_MASK 0x00007FFFL
+#define VTG4_CONTROL__VTG4_VCOUNT_INIT_MASK 0x7FFF0000L
+#define VTG4_CONTROL__VTG4_ENABLE_MASK 0x80000000L
+//VTG5_CONTROL
+#define VTG5_CONTROL__VTG5_FP2__SHIFT 0x0
+#define VTG5_CONTROL__VTG5_VCOUNT_INIT__SHIFT 0x10
+#define VTG5_CONTROL__VTG5_ENABLE__SHIFT 0x1f
+#define VTG5_CONTROL__VTG5_FP2_MASK 0x00007FFFL
+#define VTG5_CONTROL__VTG5_VCOUNT_INIT_MASK 0x7FFF0000L
+#define VTG5_CONTROL__VTG5_ENABLE_MASK 0x80000000L
+//DCHUBBUB_SOFT_RESET
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L
+//DCHUBBUB_CLOCK_CNTL
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L
+//DCFCLK_CNTL
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x007FF800L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT 0x13
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK 0x7FF80000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L
+//DCHUBBUB_VLINE_SNAPSHOT
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L
+//DCHUBBUB_CTRL_STATUS
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT 0x0
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK 0x00000001L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT 0x6
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK 0x0000003FL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK 0xFFFFFFC0L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT 0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT 0x1b
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT 0x1c
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK 0x07FFFFFFL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK 0x08000000L
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK 0x10000000L
+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT 0x0
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT 0x1
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT 0x2
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT 0x3
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK 0x00000001L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK 0x00000002L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK 0x00000004L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK 0x000000F8L
+//DCHUBBUB_TEST_DEBUG_INDEX
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK 0x000000FFL
+//DCHUBBUB_TEST_DEBUG_DATA
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+//FMON_CTRL
+#define FMON_CTRL__FMON_START__SHIFT 0x0
+#define FMON_CTRL__FMON_MODE__SHIFT 0x1
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7
+#define FMON_CTRL__FMON_STATE__SHIFT 0x9
+#define FMON_CTRL__FMON_URG_FILTER__SHIFT 0xc
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xd
+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT 0x11
+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT 0x16
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x1b
+#define FMON_CTRL__FMON_START_MASK 0x00000001L
+#define FMON_CTRL__FMON_MODE_MASK 0x00000006L
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000180L
+#define FMON_CTRL__FMON_STATE_MASK 0x00000600L
+#define FMON_CTRL__FMON_URG_FILTER_MASK 0x00001000L
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0001E000L
+#define FMON_CTRL__FMON_FILTER_UID_1_MASK 0x003E0000L
+#define FMON_CTRL__FMON_FILTER_UID_2_MASK 0x07C00000L
+#define FMON_CTRL__FMON_SOF_SEL_MASK 0x38000000L
+
+
+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON6_PERFCOUNTER_CNTL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_CNTL2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_STATE
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON6_PERFMON_CNTL
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON6_PERFMON_CNTL2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON6_PERFMON_CVALUE_LOW
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON6_PERFMON_HI
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON6_PERFMON_LOW
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
+//DCN_VM_CONTEXT0_CNTL
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_CNTL
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_CNTL
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_CNTL
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_CNTL
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_CNTL
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_CNTL
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_CNTL
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_CNTL
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_CNTL
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT10_CNTL
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT11_CNTL
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT12_CNTL
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT13_CNTL
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT14_CNTL
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT15_CNTL
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT 0x1
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c
+#define DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d
+#define DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L
+#define DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L
+//DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB__DCN_VM_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L
+//DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB__DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB__DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//DCN_VM_FAULT_CNTL
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT 0x0
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT 0x1
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT 0x2
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT 0x8
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT 0x9
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK 0x00000001L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK 0x00000002L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK 0x00000004L
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK 0x00000100L
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK 0x00000200L
+//DCN_VM_FAULT_STATUS
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT 0x0
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT 0x10
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT 0x14
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT 0x18
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT 0x1f
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK 0x0000FFFFL
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK 0x000F0000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK 0x00300000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK 0x0F000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK 0x80000000L
+//DCN_VM_FAULT_ADDR_MSB
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT 0x0
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK 0x0000000FL
+//DCN_VM_FAULT_ADDR_LSB
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT 0x0
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+//HUBP0_DCSURF_SURFACE_CONFIG
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L
+//HUBP0_DCSURF_ADDR_CONFIG
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L
+//HUBP0_DCSURF_TILING_CONFIG
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9
+#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L
+#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L
+//HUBP0_DCSURF_PRI_VIEWPORT_START
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L
+//HUBP0_DCHUBP_CNTL
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L
+//HUBP0_HUBP_CLK_CNTL
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L
+//HUBP0_DCHUBP_VMPG_CONFIG
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L
+//HUBP0_HUBPREQ_DEBUG_DB
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+//HUBPREQ0_DCSURF_SURFACE_PITCH
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L
+//HUBPREQ0_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L
+//HUBPREQ0_VMID_SETTINGS_0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_CONTROL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL2
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L
+//HUBPREQ0_DCSURF_QUEUE_CONTROL
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__GPUID__SHIFT 0x0
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT 0x4
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT 0x8
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT 0x9
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT 0xc
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT 0x10
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT 0x11
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT 0x14
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT 0x18
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__GPUID_MASK 0x00000007L
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK 0x00000070L
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK 0x00000100L
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK 0x00000200L
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK 0x0000F000L
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK 0x00010000L
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK 0x00020000L
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK 0x00700000L
+#define HUBPREQ0_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK 0x07000000L
+//HUBPREQ0_DCSURF_FRAME_PACING_TIME
+#define HUBPREQ0_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT 0x0
+#define HUBPREQ0_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK 0xFFFFFFFFL
+//HUBPREQ0_SURFACE_CURRENT_PACING_COUNTER
+#define HUBPREQ0_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT 0x0
+#define HUBPREQ0_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ0_DCN_EXPANSION_MODE
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L
+//HUBPREQ0_DCN_TTU_QOS_WM
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L
+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ0_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ0_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ0_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ0_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ0_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ0_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL
+//HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT 0x1e
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK 0x40000000L
+//HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL
+//HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ0_DC_VM_CONTEXT0_CNTL
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define HUBPREQ0_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+//HUBPREQ0_BLANK_OFFSET_0
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L
+//HUBPREQ0_BLANK_OFFSET_1
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL
+//HUBPREQ0_DST_DIMENSIONS
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL
+//HUBPREQ0_DST_AFTER_SCALER
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L
+//HUBPREQ0_PREFETCH_SETTINGS
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L
+//HUBPREQ0_PREFETCH_SETTINGS_C
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L
+//HUBPREQ0_VBLANK_PARAMETERS_1
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_2
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_3
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_4
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000001FL
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L
+//HUBPREQ0_FLIP_PARAMETERS_1
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_2
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_1
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_2
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_3
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_4
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_5
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_6
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_7
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ0_PER_LINE_DELIVERY_PRE
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L
+//HUBPREQ0_PER_LINE_DELIVERY
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L
+//HUBPREQ0_CURSOR_SETTINGS
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L
+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL
+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL
+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L
+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+//HUBPRET0_HUBPRET_CONTROL
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L
+//HUBPRET0_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L
+//HUBPRET0_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L
+//HUBPRET0_HUBPRET_READ_LINE0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE1
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L
+//HUBPRET0_HUBPRET_INTERRUPT
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L
+//HUBPRET0_HUBPRET_READ_LINE_VALUE
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_STATUS
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+//CURSOR0_0_CURSOR_CONTROL
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//CURSOR0_0_CURSOR_SIZE
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L
+//CURSOR0_0_CURSOR_POSITION
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//CURSOR0_0_CURSOR_HOT_SPOT
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L
+//CURSOR0_0_CURSOR_STEREO_CONTROL
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L
+//CURSOR0_0_CURSOR_DST_OFFSET
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL
+//CURSOR0_0_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L
+//CURSOR0_0_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L
+//CURSOR0_0_DMDATA_ADDRESS_HIGH
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L
+//CURSOR0_0_DMDATA_ADDRESS_LOW
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//CURSOR0_0_DMDATA_CNTL
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L
+//CURSOR0_0_DMDATA_QOS_CNTL
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L
+//CURSOR0_0_DMDATA_STATUS
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L
+//CURSOR0_0_DMDATA_SW_CNTL
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L
+//CURSOR0_0_DMDATA_SW_DATA
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON7_PERFCOUNTER_CNTL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_CNTL2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_STATE
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON7_PERFMON_CNTL
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON7_PERFMON_CNTL2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON7_PERFMON_CVALUE_LOW
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON7_PERFMON_HI
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON7_PERFMON_LOW
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpxfc_dispdec
+//HUBPXFC0_HUBP_XFC_CNTL
+#define HUBPXFC0_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define HUBPXFC0_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define HUBPXFC0_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define HUBPXFC0_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define HUBPXFC0_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define HUBPXFC0_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT 0x8
+#define HUBPXFC0_HUBP_XFC_CNTL__RD_VMID__SHIFT 0x14
+#define HUBPXFC0_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT 0x18
+#define HUBPXFC0_HUBP_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define HUBPXFC0_HUBP_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define HUBPXFC0_HUBP_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define HUBPXFC0_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define HUBPXFC0_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define HUBPXFC0_HUBP_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define HUBPXFC0_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK 0x00000100L
+#define HUBPXFC0_HUBP_XFC_CNTL__RD_VMID_MASK 0x00F00000L
+#define HUBPXFC0_HUBP_XFC_CNTL__CHUNK_SIZE_MASK 0x07000000L
+//HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC0_HUBP_XFC_XBUF_RD_PITCH
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK 0x00003FFFL
+//HUBPXFC0_HUBP_XFC_DELAY_CONFIG0
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT 0x8
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT 0x10
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK 0x000000FFL
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK 0x0000FF00L
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK 0x00FF0000L
+//HUBPXFC0_HUBP_XFC_DELAY_CONFIG1
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK 0x000FFFFFL
+//HUBPXFC0_HUBP_XFC_DELAY_CONFIG2
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT 0x1f
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK 0x000FFFFFL
+#define HUBPXFC0_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK 0x80000000L
+//HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT 0x1
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT 0x4
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT 0x1c
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT 0x1d
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT 0x1e
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT 0x1f
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK 0x00000001L
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK 0x00000002L
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK 0x0FFFFFF0L
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK 0x10000000L
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK 0x20000000L
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK 0x40000000L
+#define HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK 0x80000000L
+//HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0
+#define HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT 0x10
+#define HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK 0xFFFF0000L
+//HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1
+#define HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT 0x10
+#define HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK 0x03FF0000L
+//HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0
+#define HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK 0x007FFFFFL
+//HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1
+#define HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK 0x003FFFFFL
+//HUBPXFC0_HUBP_XFC_MPC_CONFIG
+#define HUBPXFC0_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT 0x0
+#define HUBPXFC0_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT 0x10
+#define HUBPXFC0_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK 0x00001FFFL
+#define HUBPXFC0_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK 0x1FFF0000L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+//HUBP1_DCSURF_SURFACE_CONFIG
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L
+//HUBP1_DCSURF_ADDR_CONFIG
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L
+//HUBP1_DCSURF_TILING_CONFIG
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9
+#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L
+#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L
+//HUBP1_DCSURF_PRI_VIEWPORT_START
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L
+//HUBP1_DCHUBP_CNTL
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L
+//HUBP1_HUBP_CLK_CNTL
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L
+//HUBP1_DCHUBP_VMPG_CONFIG
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L
+//HUBP1_HUBPREQ_DEBUG_DB
+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0
+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+//HUBPREQ1_DCSURF_SURFACE_PITCH
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L
+//HUBPREQ1_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L
+//HUBPREQ1_VMID_SETTINGS_0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT 0x0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK 0x0000000FL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_CONTROL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL2
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L
+//HUBPREQ1_DCSURF_QUEUE_CONTROL
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__GPUID__SHIFT 0x0
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT 0x4
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT 0x8
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT 0x9
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT 0xc
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT 0x10
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT 0x11
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT 0x14
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT 0x18
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__GPUID_MASK 0x00000007L
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK 0x00000070L
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK 0x00000100L
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK 0x00000200L
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK 0x0000F000L
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK 0x00010000L
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK 0x00020000L
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK 0x00700000L
+#define HUBPREQ1_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK 0x07000000L
+//HUBPREQ1_DCSURF_FRAME_PACING_TIME
+#define HUBPREQ1_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT 0x0
+#define HUBPREQ1_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK 0xFFFFFFFFL
+//HUBPREQ1_SURFACE_CURRENT_PACING_COUNTER
+#define HUBPREQ1_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT 0x0
+#define HUBPREQ1_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ1_DCN_EXPANSION_MODE
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L
+//HUBPREQ1_DCN_TTU_QOS_WM
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L
+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ1_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ1_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ1_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ1_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ1_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ1_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL
+//HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT 0x1e
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK 0x40000000L
+//HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL
+//HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ1_DC_VM_CONTEXT0_CNTL
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define HUBPREQ1_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+//HUBPREQ1_BLANK_OFFSET_0
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L
+//HUBPREQ1_BLANK_OFFSET_1
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL
+//HUBPREQ1_DST_DIMENSIONS
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL
+//HUBPREQ1_DST_AFTER_SCALER
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L
+//HUBPREQ1_PREFETCH_SETTINGS
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L
+//HUBPREQ1_PREFETCH_SETTINGS_C
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L
+//HUBPREQ1_VBLANK_PARAMETERS_1
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_2
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_3
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_4
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000001FL
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L
+//HUBPREQ1_FLIP_PARAMETERS_1
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_2
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_1
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_2
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_3
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_4
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_5
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_6
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_7
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ1_PER_LINE_DELIVERY_PRE
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L
+//HUBPREQ1_PER_LINE_DELIVERY
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L
+//HUBPREQ1_CURSOR_SETTINGS
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L
+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL
+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL
+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L
+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+//HUBPRET1_HUBPRET_CONTROL
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L
+//HUBPRET1_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L
+//HUBPRET1_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L
+//HUBPRET1_HUBPRET_READ_LINE0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE1
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L
+//HUBPRET1_HUBPRET_INTERRUPT
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L
+//HUBPRET1_HUBPRET_READ_LINE_VALUE
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_STATUS
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+//CURSOR0_1_CURSOR_CONTROL
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//CURSOR0_1_CURSOR_SIZE
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L
+//CURSOR0_1_CURSOR_POSITION
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//CURSOR0_1_CURSOR_HOT_SPOT
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L
+//CURSOR0_1_CURSOR_STEREO_CONTROL
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L
+//CURSOR0_1_CURSOR_DST_OFFSET
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL
+//CURSOR0_1_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L
+//CURSOR0_1_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L
+//CURSOR0_1_DMDATA_ADDRESS_HIGH
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L
+//CURSOR0_1_DMDATA_ADDRESS_LOW
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//CURSOR0_1_DMDATA_CNTL
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L
+//CURSOR0_1_DMDATA_QOS_CNTL
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L
+//CURSOR0_1_DMDATA_STATUS
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L
+//CURSOR0_1_DMDATA_SW_CNTL
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L
+//CURSOR0_1_DMDATA_SW_DATA
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON8_PERFCOUNTER_CNTL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_CNTL2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_STATE
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON8_PERFMON_CNTL
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON8_PERFMON_CNTL2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON8_PERFMON_CVALUE_LOW
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON8_PERFMON_HI
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON8_PERFMON_LOW
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpxfc_dispdec
+//HUBPXFC1_HUBP_XFC_CNTL
+#define HUBPXFC1_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define HUBPXFC1_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define HUBPXFC1_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define HUBPXFC1_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define HUBPXFC1_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define HUBPXFC1_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT 0x8
+#define HUBPXFC1_HUBP_XFC_CNTL__RD_VMID__SHIFT 0x14
+#define HUBPXFC1_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT 0x18
+#define HUBPXFC1_HUBP_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define HUBPXFC1_HUBP_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define HUBPXFC1_HUBP_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define HUBPXFC1_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define HUBPXFC1_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define HUBPXFC1_HUBP_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define HUBPXFC1_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK 0x00000100L
+#define HUBPXFC1_HUBP_XFC_CNTL__RD_VMID_MASK 0x00F00000L
+#define HUBPXFC1_HUBP_XFC_CNTL__CHUNK_SIZE_MASK 0x07000000L
+//HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC1_HUBP_XFC_XBUF_RD_PITCH
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK 0x00003FFFL
+//HUBPXFC1_HUBP_XFC_DELAY_CONFIG0
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT 0x8
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT 0x10
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK 0x000000FFL
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK 0x0000FF00L
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK 0x00FF0000L
+//HUBPXFC1_HUBP_XFC_DELAY_CONFIG1
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK 0x000FFFFFL
+//HUBPXFC1_HUBP_XFC_DELAY_CONFIG2
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT 0x1f
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK 0x000FFFFFL
+#define HUBPXFC1_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK 0x80000000L
+//HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT 0x1
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT 0x4
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT 0x1c
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT 0x1d
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT 0x1e
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT 0x1f
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK 0x00000001L
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK 0x00000002L
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK 0x0FFFFFF0L
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK 0x10000000L
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK 0x20000000L
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK 0x40000000L
+#define HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK 0x80000000L
+//HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0
+#define HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT 0x10
+#define HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK 0xFFFF0000L
+//HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1
+#define HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT 0x10
+#define HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK 0x03FF0000L
+//HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0
+#define HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK 0x007FFFFFL
+//HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1
+#define HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK 0x003FFFFFL
+//HUBPXFC1_HUBP_XFC_MPC_CONFIG
+#define HUBPXFC1_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT 0x0
+#define HUBPXFC1_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT 0x10
+#define HUBPXFC1_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK 0x00001FFFL
+#define HUBPXFC1_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK 0x1FFF0000L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+//HUBP2_DCSURF_SURFACE_CONFIG
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L
+//HUBP2_DCSURF_ADDR_CONFIG
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L
+//HUBP2_DCSURF_TILING_CONFIG
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9
+#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L
+#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L
+//HUBP2_DCSURF_PRI_VIEWPORT_START
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L
+//HUBP2_DCHUBP_CNTL
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L
+//HUBP2_HUBP_CLK_CNTL
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L
+//HUBP2_DCHUBP_VMPG_CONFIG
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L
+//HUBP2_HUBPREQ_DEBUG_DB
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+//HUBPREQ2_DCSURF_SURFACE_PITCH
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L
+//HUBPREQ2_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L
+//HUBPREQ2_VMID_SETTINGS_0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT 0x0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK 0x0000000FL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_CONTROL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL2
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L
+//HUBPREQ2_DCSURF_QUEUE_CONTROL
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__GPUID__SHIFT 0x0
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT 0x4
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT 0x8
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT 0x9
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT 0xc
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT 0x10
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT 0x11
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT 0x14
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT 0x18
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__GPUID_MASK 0x00000007L
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK 0x00000070L
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK 0x00000100L
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK 0x00000200L
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK 0x0000F000L
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK 0x00010000L
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK 0x00020000L
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK 0x00700000L
+#define HUBPREQ2_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK 0x07000000L
+//HUBPREQ2_DCSURF_FRAME_PACING_TIME
+#define HUBPREQ2_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT 0x0
+#define HUBPREQ2_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK 0xFFFFFFFFL
+//HUBPREQ2_SURFACE_CURRENT_PACING_COUNTER
+#define HUBPREQ2_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT 0x0
+#define HUBPREQ2_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ2_DCN_EXPANSION_MODE
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L
+//HUBPREQ2_DCN_TTU_QOS_WM
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L
+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ2_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ2_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ2_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ2_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ2_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ2_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL
+//HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT 0x1e
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK 0x40000000L
+//HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL
+//HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ2_DC_VM_CONTEXT0_CNTL
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define HUBPREQ2_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+//HUBPREQ2_BLANK_OFFSET_0
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L
+//HUBPREQ2_BLANK_OFFSET_1
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL
+//HUBPREQ2_DST_DIMENSIONS
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL
+//HUBPREQ2_DST_AFTER_SCALER
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L
+//HUBPREQ2_PREFETCH_SETTINGS
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L
+//HUBPREQ2_PREFETCH_SETTINGS_C
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L
+//HUBPREQ2_VBLANK_PARAMETERS_1
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_2
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_3
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_4
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000001FL
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L
+//HUBPREQ2_FLIP_PARAMETERS_1
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_2
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_1
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_2
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_3
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_4
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_5
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_6
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_7
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ2_PER_LINE_DELIVERY_PRE
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L
+//HUBPREQ2_PER_LINE_DELIVERY
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L
+//HUBPREQ2_CURSOR_SETTINGS
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L
+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL
+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL
+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L
+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+//HUBPRET2_HUBPRET_CONTROL
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L
+//HUBPRET2_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L
+//HUBPRET2_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L
+//HUBPRET2_HUBPRET_READ_LINE0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE1
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L
+//HUBPRET2_HUBPRET_INTERRUPT
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L
+//HUBPRET2_HUBPRET_READ_LINE_VALUE
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_STATUS
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+//CURSOR0_2_CURSOR_CONTROL
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//CURSOR0_2_CURSOR_SIZE
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L
+//CURSOR0_2_CURSOR_POSITION
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//CURSOR0_2_CURSOR_HOT_SPOT
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L
+//CURSOR0_2_CURSOR_STEREO_CONTROL
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L
+//CURSOR0_2_CURSOR_DST_OFFSET
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL
+//CURSOR0_2_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L
+//CURSOR0_2_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L
+//CURSOR0_2_DMDATA_ADDRESS_HIGH
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L
+//CURSOR0_2_DMDATA_ADDRESS_LOW
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//CURSOR0_2_DMDATA_CNTL
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L
+//CURSOR0_2_DMDATA_QOS_CNTL
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L
+//CURSOR0_2_DMDATA_STATUS
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L
+//CURSOR0_2_DMDATA_SW_CNTL
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L
+//CURSOR0_2_DMDATA_SW_DATA
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON9_PERFCOUNTER_CNTL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_CNTL2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_STATE
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON9_PERFMON_CNTL
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON9_PERFMON_CNTL2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON9_PERFMON_CVALUE_LOW
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON9_PERFMON_HI
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON9_PERFMON_LOW
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpxfc_dispdec
+//HUBPXFC2_HUBP_XFC_CNTL
+#define HUBPXFC2_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define HUBPXFC2_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define HUBPXFC2_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define HUBPXFC2_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define HUBPXFC2_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define HUBPXFC2_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT 0x8
+#define HUBPXFC2_HUBP_XFC_CNTL__RD_VMID__SHIFT 0x14
+#define HUBPXFC2_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT 0x18
+#define HUBPXFC2_HUBP_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define HUBPXFC2_HUBP_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define HUBPXFC2_HUBP_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define HUBPXFC2_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define HUBPXFC2_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define HUBPXFC2_HUBP_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define HUBPXFC2_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK 0x00000100L
+#define HUBPXFC2_HUBP_XFC_CNTL__RD_VMID_MASK 0x00F00000L
+#define HUBPXFC2_HUBP_XFC_CNTL__CHUNK_SIZE_MASK 0x07000000L
+//HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC2_HUBP_XFC_XBUF_RD_PITCH
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK 0x00003FFFL
+//HUBPXFC2_HUBP_XFC_DELAY_CONFIG0
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT 0x8
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT 0x10
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK 0x000000FFL
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK 0x0000FF00L
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK 0x00FF0000L
+//HUBPXFC2_HUBP_XFC_DELAY_CONFIG1
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK 0x000FFFFFL
+//HUBPXFC2_HUBP_XFC_DELAY_CONFIG2
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT 0x1f
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK 0x000FFFFFL
+#define HUBPXFC2_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK 0x80000000L
+//HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT 0x1
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT 0x4
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT 0x1c
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT 0x1d
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT 0x1e
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT 0x1f
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK 0x00000001L
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK 0x00000002L
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK 0x0FFFFFF0L
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK 0x10000000L
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK 0x20000000L
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK 0x40000000L
+#define HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK 0x80000000L
+//HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0
+#define HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT 0x10
+#define HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK 0xFFFF0000L
+//HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1
+#define HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT 0x10
+#define HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK 0x03FF0000L
+//HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0
+#define HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK 0x007FFFFFL
+//HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1
+#define HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK 0x003FFFFFL
+//HUBPXFC2_HUBP_XFC_MPC_CONFIG
+#define HUBPXFC2_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT 0x0
+#define HUBPXFC2_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT 0x10
+#define HUBPXFC2_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK 0x00001FFFL
+#define HUBPXFC2_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK 0x1FFF0000L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+//HUBP3_DCSURF_SURFACE_CONFIG
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L
+//HUBP3_DCSURF_ADDR_CONFIG
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L
+//HUBP3_DCSURF_TILING_CONFIG
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9
+#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L
+#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L
+//HUBP3_DCSURF_PRI_VIEWPORT_START
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L
+//HUBP3_DCHUBP_CNTL
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L
+//HUBP3_HUBP_CLK_CNTL
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L
+//HUBP3_DCHUBP_VMPG_CONFIG
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L
+//HUBP3_HUBPREQ_DEBUG_DB
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+//HUBPREQ3_DCSURF_SURFACE_PITCH
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L
+//HUBPREQ3_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L
+//HUBPREQ3_VMID_SETTINGS_0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT 0x0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK 0x0000000FL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_CONTROL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL2
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L
+//HUBPREQ3_DCSURF_QUEUE_CONTROL
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__GPUID__SHIFT 0x0
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT 0x4
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT 0x8
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT 0x9
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT 0xc
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT 0x10
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT 0x11
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT 0x14
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT 0x18
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__GPUID_MASK 0x00000007L
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK 0x00000070L
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK 0x00000100L
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK 0x00000200L
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK 0x0000F000L
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK 0x00010000L
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK 0x00020000L
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK 0x00700000L
+#define HUBPREQ3_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK 0x07000000L
+//HUBPREQ3_DCSURF_FRAME_PACING_TIME
+#define HUBPREQ3_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT 0x0
+#define HUBPREQ3_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK 0xFFFFFFFFL
+//HUBPREQ3_SURFACE_CURRENT_PACING_COUNTER
+#define HUBPREQ3_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT 0x0
+#define HUBPREQ3_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ3_DCN_EXPANSION_MODE
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L
+//HUBPREQ3_DCN_TTU_QOS_WM
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L
+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ3_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ3_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ3_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ3_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ3_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ3_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL
+//HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT 0x1e
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK 0x40000000L
+//HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL
+//HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ3_DC_VM_CONTEXT0_CNTL
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define HUBPREQ3_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+//HUBPREQ3_BLANK_OFFSET_0
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L
+//HUBPREQ3_BLANK_OFFSET_1
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL
+//HUBPREQ3_DST_DIMENSIONS
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL
+//HUBPREQ3_DST_AFTER_SCALER
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L
+//HUBPREQ3_PREFETCH_SETTINGS
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L
+//HUBPREQ3_PREFETCH_SETTINGS_C
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L
+//HUBPREQ3_VBLANK_PARAMETERS_1
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_2
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_3
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_4
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000001FL
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L
+//HUBPREQ3_FLIP_PARAMETERS_1
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_2
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_1
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_2
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_3
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_4
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_5
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_6
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_7
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ3_PER_LINE_DELIVERY_PRE
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L
+//HUBPREQ3_PER_LINE_DELIVERY
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L
+//HUBPREQ3_CURSOR_SETTINGS
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L
+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL
+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL
+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L
+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+//HUBPRET3_HUBPRET_CONTROL
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L
+//HUBPRET3_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L
+//HUBPRET3_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L
+//HUBPRET3_HUBPRET_READ_LINE0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE1
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L
+//HUBPRET3_HUBPRET_INTERRUPT
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L
+//HUBPRET3_HUBPRET_READ_LINE_VALUE
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_STATUS
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+//CURSOR0_3_CURSOR_CONTROL
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//CURSOR0_3_CURSOR_SIZE
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L
+//CURSOR0_3_CURSOR_POSITION
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//CURSOR0_3_CURSOR_HOT_SPOT
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L
+//CURSOR0_3_CURSOR_STEREO_CONTROL
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L
+//CURSOR0_3_CURSOR_DST_OFFSET
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL
+//CURSOR0_3_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L
+//CURSOR0_3_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L
+//CURSOR0_3_DMDATA_ADDRESS_HIGH
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L
+//CURSOR0_3_DMDATA_ADDRESS_LOW
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//CURSOR0_3_DMDATA_CNTL
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L
+//CURSOR0_3_DMDATA_QOS_CNTL
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L
+//CURSOR0_3_DMDATA_STATUS
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L
+//CURSOR0_3_DMDATA_SW_CNTL
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L
+//CURSOR0_3_DMDATA_SW_DATA
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON10_PERFCOUNTER_CNTL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_CNTL2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_STATE
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON10_PERFMON_CNTL
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON10_PERFMON_CNTL2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON10_PERFMON_CVALUE_LOW
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON10_PERFMON_HI
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON10_PERFMON_LOW
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpxfc_dispdec
+//HUBPXFC3_HUBP_XFC_CNTL
+#define HUBPXFC3_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define HUBPXFC3_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define HUBPXFC3_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define HUBPXFC3_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define HUBPXFC3_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define HUBPXFC3_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT 0x8
+#define HUBPXFC3_HUBP_XFC_CNTL__RD_VMID__SHIFT 0x14
+#define HUBPXFC3_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT 0x18
+#define HUBPXFC3_HUBP_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define HUBPXFC3_HUBP_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define HUBPXFC3_HUBP_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define HUBPXFC3_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define HUBPXFC3_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define HUBPXFC3_HUBP_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define HUBPXFC3_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK 0x00000100L
+#define HUBPXFC3_HUBP_XFC_CNTL__RD_VMID_MASK 0x00F00000L
+#define HUBPXFC3_HUBP_XFC_CNTL__CHUNK_SIZE_MASK 0x07000000L
+//HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC3_HUBP_XFC_XBUF_RD_PITCH
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK 0x00003FFFL
+//HUBPXFC3_HUBP_XFC_DELAY_CONFIG0
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT 0x8
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT 0x10
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK 0x000000FFL
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK 0x0000FF00L
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK 0x00FF0000L
+//HUBPXFC3_HUBP_XFC_DELAY_CONFIG1
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK 0x000FFFFFL
+//HUBPXFC3_HUBP_XFC_DELAY_CONFIG2
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT 0x1f
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK 0x000FFFFFL
+#define HUBPXFC3_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK 0x80000000L
+//HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT 0x1
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT 0x4
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT 0x1c
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT 0x1d
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT 0x1e
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT 0x1f
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK 0x00000001L
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK 0x00000002L
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK 0x0FFFFFF0L
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK 0x10000000L
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK 0x20000000L
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK 0x40000000L
+#define HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK 0x80000000L
+//HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0
+#define HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT 0x10
+#define HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK 0xFFFF0000L
+//HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1
+#define HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT 0x10
+#define HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK 0x03FF0000L
+//HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0
+#define HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK 0x007FFFFFL
+//HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1
+#define HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK 0x003FFFFFL
+//HUBPXFC3_HUBP_XFC_MPC_CONFIG
+#define HUBPXFC3_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT 0x0
+#define HUBPXFC3_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT 0x10
+#define HUBPXFC3_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK 0x00001FFFL
+#define HUBPXFC3_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK 0x1FFF0000L
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dispdec
+//HUBP4_DCSURF_SURFACE_CONFIG
+#define HUBP4_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define HUBP4_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8
+#define HUBP4_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa
+#define HUBP4_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+#define HUBP4_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L
+#define HUBP4_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L
+//HUBP4_DCSURF_ADDR_CONFIG
+#define HUBP4_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HUBP4_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3
+#define HUBP4_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6
+#define HUBP4_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8
+#define HUBP4_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa
+#define HUBP4_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc
+#define HUBP4_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define HUBP4_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L
+#define HUBP4_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L
+#define HUBP4_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L
+#define HUBP4_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L
+#define HUBP4_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L
+//HUBP4_DCSURF_TILING_CONFIG
+#define HUBP4_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0
+#define HUBP4_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7
+#define HUBP4_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9
+#define HUBP4_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa
+#define HUBP4_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb
+#define HUBP4_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL
+#define HUBP4_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L
+#define HUBP4_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L
+#define HUBP4_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L
+#define HUBP4_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L
+//HUBP4_DCSURF_PRI_VIEWPORT_START
+#define HUBP4_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP4_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP4_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP4_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP4_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP4_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP4_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP4_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP4_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP4_DCSURF_SEC_VIEWPORT_START
+#define HUBP4_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP4_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP4_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP4_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP4_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP4_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP4_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP4_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP4_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP4_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L
+//HUBP4_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L
+#define HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L
+//HUBP4_DCHUBP_CNTL
+#define HUBP4_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0
+#define HUBP4_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1
+#define HUBP4_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2
+#define HUBP4_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3
+#define HUBP4_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4
+#define HUBP4_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8
+#define HUBP4_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9
+#define HUBP4_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc
+#define HUBP4_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd
+#define HUBP4_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10
+#define HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14
+#define HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18
+#define HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a
+#define HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b
+#define HUBP4_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c
+#define HUBP4_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f
+#define HUBP4_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L
+#define HUBP4_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L
+#define HUBP4_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L
+#define HUBP4_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L
+#define HUBP4_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L
+#define HUBP4_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L
+#define HUBP4_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L
+#define HUBP4_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L
+#define HUBP4_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L
+#define HUBP4_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L
+#define HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L
+#define HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L
+#define HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L
+#define HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L
+#define HUBP4_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L
+#define HUBP4_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L
+//HUBP4_HUBP_CLK_CNTL
+#define HUBP4_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17
+#define HUBP4_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c
+#define HUBP4_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L
+#define HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L
+#define HUBP4_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L
+//HUBP4_DCHUBP_VMPG_CONFIG
+#define HUBP4_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0
+#define HUBP4_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L
+//HUBP4_HUBPREQ_DEBUG_DB
+#define HUBP4_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0
+#define HUBP4_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL
+//HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L
+//HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L
+#define HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubpreq_dispdec
+//HUBPREQ4_DCSURF_SURFACE_PITCH
+#define HUBPREQ4_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10
+#define HUBPREQ4_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL
+#define HUBPREQ4_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L
+//HUBPREQ4_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ4_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10
+#define HUBPREQ4_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL
+#define HUBPREQ4_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L
+//HUBPREQ4_VMID_SETTINGS_0
+#define HUBPREQ4_VMID_SETTINGS_0__VMID__SHIFT 0x0
+#define HUBPREQ4_VMID_SETTINGS_0__VMID_MASK 0x0000000FL
+//HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_SURFACE_CONTROL
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L
+#define HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L
+//HUBPREQ4_DCSURF_FLIP_CONTROL
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L
+//HUBPREQ4_DCSURF_FLIP_CONTROL2
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L
+#define HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L
+//HUBPREQ4_DCSURF_QUEUE_CONTROL
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__GPUID__SHIFT 0x0
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT 0x4
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT 0x8
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT 0x9
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT 0xc
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT 0x10
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT 0x11
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT 0x14
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT 0x18
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__GPUID_MASK 0x00000007L
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK 0x00000070L
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK 0x00000100L
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK 0x00000200L
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK 0x0000F000L
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK 0x00010000L
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK 0x00020000L
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK 0x00700000L
+#define HUBPREQ4_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK 0x07000000L
+//HUBPREQ4_DCSURF_FRAME_PACING_TIME
+#define HUBPREQ4_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT 0x0
+#define HUBPREQ4_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK 0xFFFFFFFFL
+//HUBPREQ4_SURFACE_CURRENT_PACING_COUNTER
+#define HUBPREQ4_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT 0x0
+#define HUBPREQ4_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L
+#define HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L
+//HUBPREQ4_DCSURF_SURFACE_INUSE
+#define HUBPREQ4_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ4_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ4_DCN_EXPANSION_MODE
+#define HUBPREQ4_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0
+#define HUBPREQ4_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2
+#define HUBPREQ4_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4
+#define HUBPREQ4_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6
+#define HUBPREQ4_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L
+#define HUBPREQ4_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL
+#define HUBPREQ4_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L
+#define HUBPREQ4_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L
+//HUBPREQ4_DCN_TTU_QOS_WM
+#define HUBPREQ4_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0
+#define HUBPREQ4_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10
+#define HUBPREQ4_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL
+#define HUBPREQ4_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L
+//HUBPREQ4_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ4_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0
+#define HUBPREQ4_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c
+#define HUBPREQ4_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL
+#define HUBPREQ4_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L
+//HUBPREQ4_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ4_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ4_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ4_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ4_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ4_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ4_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ4_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ4_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ4_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ4_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ4_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ4_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ4_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ4_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ4_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ4_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ4_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ4_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ4_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ4_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ4_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ4_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ4_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ4_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ4_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ4_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ4_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ4_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ4_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ4_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ4_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ4_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ4_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ4_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ4_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ4_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ4_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ4_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ4_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0
+#define HUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0
+#define HUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL
+//HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT 0x1e
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK 0x40000000L
+//HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL
+//HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ4_DC_VM_CONTEXT0_CNTL
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define HUBPREQ4_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+//HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+//HUBPREQ4_BLANK_OFFSET_0
+#define HUBPREQ4_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0
+#define HUBPREQ4_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10
+#define HUBPREQ4_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL
+#define HUBPREQ4_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L
+//HUBPREQ4_BLANK_OFFSET_1
+#define HUBPREQ4_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0
+#define HUBPREQ4_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL
+//HUBPREQ4_DST_DIMENSIONS
+#define HUBPREQ4_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0
+#define HUBPREQ4_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL
+//HUBPREQ4_DST_AFTER_SCALER
+#define HUBPREQ4_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0
+#define HUBPREQ4_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10
+#define HUBPREQ4_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL
+#define HUBPREQ4_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L
+//HUBPREQ4_PREFETCH_SETTINGS
+#define HUBPREQ4_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0
+#define HUBPREQ4_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18
+#define HUBPREQ4_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL
+#define HUBPREQ4_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L
+//HUBPREQ4_PREFETCH_SETTINGS_C
+#define HUBPREQ4_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0
+#define HUBPREQ4_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL
+//HUBPREQ4_VBLANK_PARAMETERS_0
+#define HUBPREQ4_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0
+#define HUBPREQ4_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8
+#define HUBPREQ4_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL
+#define HUBPREQ4_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L
+//HUBPREQ4_VBLANK_PARAMETERS_1
+#define HUBPREQ4_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0
+#define HUBPREQ4_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ4_VBLANK_PARAMETERS_2
+#define HUBPREQ4_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0
+#define HUBPREQ4_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ4_VBLANK_PARAMETERS_3
+#define HUBPREQ4_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0
+#define HUBPREQ4_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ4_VBLANK_PARAMETERS_4
+#define HUBPREQ4_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0
+#define HUBPREQ4_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ4_FLIP_PARAMETERS_0
+#define HUBPREQ4_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0
+#define HUBPREQ4_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8
+#define HUBPREQ4_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000001FL
+#define HUBPREQ4_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L
+//HUBPREQ4_FLIP_PARAMETERS_1
+#define HUBPREQ4_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0
+#define HUBPREQ4_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ4_FLIP_PARAMETERS_2
+#define HUBPREQ4_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0
+#define HUBPREQ4_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ4_NOM_PARAMETERS_0
+#define HUBPREQ4_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ4_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ4_NOM_PARAMETERS_1
+#define HUBPREQ4_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0
+#define HUBPREQ4_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ4_NOM_PARAMETERS_2
+#define HUBPREQ4_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ4_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ4_NOM_PARAMETERS_3
+#define HUBPREQ4_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0
+#define HUBPREQ4_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ4_NOM_PARAMETERS_4
+#define HUBPREQ4_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ4_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ4_NOM_PARAMETERS_5
+#define HUBPREQ4_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0
+#define HUBPREQ4_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ4_NOM_PARAMETERS_6
+#define HUBPREQ4_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ4_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ4_NOM_PARAMETERS_7
+#define HUBPREQ4_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0
+#define HUBPREQ4_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ4_PER_LINE_DELIVERY_PRE
+#define HUBPREQ4_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0
+#define HUBPREQ4_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10
+#define HUBPREQ4_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL
+#define HUBPREQ4_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L
+//HUBPREQ4_PER_LINE_DELIVERY
+#define HUBPREQ4_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0
+#define HUBPREQ4_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10
+#define HUBPREQ4_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL
+#define HUBPREQ4_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L
+//HUBPREQ4_CURSOR_SETTINGS
+#define HUBPREQ4_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0
+#define HUBPREQ4_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8
+#define HUBPREQ4_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10
+#define HUBPREQ4_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18
+#define HUBPREQ4_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL
+#define HUBPREQ4_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L
+#define HUBPREQ4_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L
+#define HUBPREQ4_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L
+//HUBPREQ4_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ4_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0
+#define HUBPREQ4_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL
+//HUBPREQ4_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ4_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0
+#define HUBPREQ4_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL
+//HUBPREQ4_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L
+#define HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L
+//HUBPREQ4_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6
+#define HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L
+#define HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubpret_dispdec
+//HUBPRET4_HUBPRET_CONTROL
+#define HUBPRET4_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0
+#define HUBPRET4_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc
+#define HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10
+#define HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12
+#define HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14
+#define HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16
+#define HUBPRET4_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18
+#define HUBPRET4_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL
+#define HUBPRET4_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L
+#define HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L
+#define HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L
+#define HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L
+#define HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L
+#define HUBPRET4_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L
+//HUBPRET4_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L
+#define HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L
+//HUBPRET4_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET4_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPRET4_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPRET4_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPRET4_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPRET4_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPRET4_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L
+//HUBPRET4_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET4_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0
+#define HUBPRET4_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10
+#define HUBPRET4_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL
+#define HUBPRET4_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L
+//HUBPRET4_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET4_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0
+#define HUBPRET4_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10
+#define HUBPRET4_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL
+#define HUBPRET4_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L
+//HUBPRET4_HUBPRET_READ_LINE0
+#define HUBPRET4_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0
+#define HUBPRET4_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10
+#define HUBPRET4_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL
+#define HUBPRET4_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L
+//HUBPRET4_HUBPRET_READ_LINE1
+#define HUBPRET4_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0
+#define HUBPRET4_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10
+#define HUBPRET4_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL
+#define HUBPRET4_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L
+//HUBPRET4_HUBPRET_INTERRUPT
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L
+#define HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L
+//HUBPRET4_HUBPRET_READ_LINE_VALUE
+#define HUBPRET4_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0
+#define HUBPRET4_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10
+#define HUBPRET4_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL
+#define HUBPRET4_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L
+//HUBPRET4_HUBPRET_READ_LINE_STATUS
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L
+#define HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_cursor0_dispdec
+//CURSOR0_4_CURSOR_CONTROL
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L
+#define CURSOR0_4_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L
+//CURSOR0_4_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_4_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define CURSOR0_4_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//CURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//CURSOR0_4_CURSOR_SIZE
+#define CURSOR0_4_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define CURSOR0_4_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define CURSOR0_4_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL
+#define CURSOR0_4_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L
+//CURSOR0_4_CURSOR_POSITION
+#define CURSOR0_4_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define CURSOR0_4_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define CURSOR0_4_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define CURSOR0_4_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//CURSOR0_4_CURSOR_HOT_SPOT
+#define CURSOR0_4_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define CURSOR0_4_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define CURSOR0_4_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL
+#define CURSOR0_4_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L
+//CURSOR0_4_CURSOR_STEREO_CONTROL
+#define CURSOR0_4_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define CURSOR0_4_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define CURSOR0_4_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12
+#define CURSOR0_4_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define CURSOR0_4_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L
+#define CURSOR0_4_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L
+//CURSOR0_4_CURSOR_DST_OFFSET
+#define CURSOR0_4_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0
+#define CURSOR0_4_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL
+//CURSOR0_4_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_4_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0
+#define CURSOR0_4_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2
+#define CURSOR0_4_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4
+#define CURSOR0_4_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L
+#define CURSOR0_4_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L
+#define CURSOR0_4_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L
+//CURSOR0_4_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_4_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0
+#define CURSOR0_4_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L
+//CURSOR0_4_DMDATA_ADDRESS_HIGH
+#define CURSOR0_4_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_4_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c
+#define CURSOR0_4_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d
+#define CURSOR0_4_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e
+#define CURSOR0_4_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL
+#define CURSOR0_4_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L
+#define CURSOR0_4_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L
+#define CURSOR0_4_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L
+//CURSOR0_4_DMDATA_ADDRESS_LOW
+#define CURSOR0_4_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0
+#define CURSOR0_4_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//CURSOR0_4_DMDATA_CNTL
+#define CURSOR0_4_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0
+#define CURSOR0_4_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1
+#define CURSOR0_4_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2
+#define CURSOR0_4_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10
+#define CURSOR0_4_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L
+#define CURSOR0_4_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L
+#define CURSOR0_4_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L
+#define CURSOR0_4_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L
+//CURSOR0_4_DMDATA_QOS_CNTL
+#define CURSOR0_4_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0
+#define CURSOR0_4_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4
+#define CURSOR0_4_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10
+#define CURSOR0_4_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L
+#define CURSOR0_4_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L
+#define CURSOR0_4_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L
+//CURSOR0_4_DMDATA_STATUS
+#define CURSOR0_4_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0
+#define CURSOR0_4_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2
+#define CURSOR0_4_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4
+#define CURSOR0_4_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L
+#define CURSOR0_4_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L
+#define CURSOR0_4_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L
+//CURSOR0_4_DMDATA_SW_CNTL
+#define CURSOR0_4_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0
+#define CURSOR0_4_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1
+#define CURSOR0_4_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10
+#define CURSOR0_4_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L
+#define CURSOR0_4_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L
+#define CURSOR0_4_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L
+//CURSOR0_4_DMDATA_SW_DATA
+#define CURSOR0_4_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0
+#define CURSOR0_4_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON11_PERFCOUNTER_CNTL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_CNTL2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_STATE
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON11_PERFMON_CNTL
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON11_PERFMON_CNTL2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON11_PERFMON_CVALUE_LOW
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON11_PERFMON_HI
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON11_PERFMON_LOW
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp4_dispdec_hubpxfc_dispdec
+//HUBPXFC4_HUBP_XFC_CNTL
+#define HUBPXFC4_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define HUBPXFC4_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define HUBPXFC4_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define HUBPXFC4_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define HUBPXFC4_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define HUBPXFC4_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT 0x8
+#define HUBPXFC4_HUBP_XFC_CNTL__RD_VMID__SHIFT 0x14
+#define HUBPXFC4_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT 0x18
+#define HUBPXFC4_HUBP_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define HUBPXFC4_HUBP_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define HUBPXFC4_HUBP_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define HUBPXFC4_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define HUBPXFC4_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define HUBPXFC4_HUBP_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define HUBPXFC4_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK 0x00000100L
+#define HUBPXFC4_HUBP_XFC_CNTL__RD_VMID_MASK 0x00F00000L
+#define HUBPXFC4_HUBP_XFC_CNTL__CHUNK_SIZE_MASK 0x07000000L
+//HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC4_HUBP_XFC_XBUF_RD_PITCH
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK 0x00003FFFL
+//HUBPXFC4_HUBP_XFC_DELAY_CONFIG0
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT 0x8
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT 0x10
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK 0x000000FFL
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK 0x0000FF00L
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK 0x00FF0000L
+//HUBPXFC4_HUBP_XFC_DELAY_CONFIG1
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK 0x000FFFFFL
+//HUBPXFC4_HUBP_XFC_DELAY_CONFIG2
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT 0x1f
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK 0x000FFFFFL
+#define HUBPXFC4_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK 0x80000000L
+//HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT 0x1
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT 0x4
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT 0x1c
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT 0x1d
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT 0x1e
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT 0x1f
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK 0x00000001L
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK 0x00000002L
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK 0x0FFFFFF0L
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK 0x10000000L
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK 0x20000000L
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK 0x40000000L
+#define HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK 0x80000000L
+//HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0
+#define HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT 0x10
+#define HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK 0xFFFF0000L
+//HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1
+#define HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT 0x10
+#define HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK 0x03FF0000L
+//HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0
+#define HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK 0x007FFFFFL
+//HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1
+#define HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK 0x003FFFFFL
+//HUBPXFC4_HUBP_XFC_MPC_CONFIG
+#define HUBPXFC4_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT 0x0
+#define HUBPXFC4_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT 0x10
+#define HUBPXFC4_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK 0x00001FFFL
+#define HUBPXFC4_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK 0x1FFF0000L
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dispdec
+//HUBP5_DCSURF_SURFACE_CONFIG
+#define HUBP5_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define HUBP5_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8
+#define HUBP5_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa
+#define HUBP5_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+#define HUBP5_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L
+#define HUBP5_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L
+//HUBP5_DCSURF_ADDR_CONFIG
+#define HUBP5_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HUBP5_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3
+#define HUBP5_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6
+#define HUBP5_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8
+#define HUBP5_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa
+#define HUBP5_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc
+#define HUBP5_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define HUBP5_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L
+#define HUBP5_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L
+#define HUBP5_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L
+#define HUBP5_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L
+#define HUBP5_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L
+//HUBP5_DCSURF_TILING_CONFIG
+#define HUBP5_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0
+#define HUBP5_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7
+#define HUBP5_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9
+#define HUBP5_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa
+#define HUBP5_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb
+#define HUBP5_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL
+#define HUBP5_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L
+#define HUBP5_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L
+#define HUBP5_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L
+#define HUBP5_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L
+//HUBP5_DCSURF_PRI_VIEWPORT_START
+#define HUBP5_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP5_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP5_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP5_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP5_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP5_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP5_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP5_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP5_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP5_DCSURF_SEC_VIEWPORT_START
+#define HUBP5_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0
+#define HUBP5_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10
+#define HUBP5_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL
+#define HUBP5_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L
+//HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0
+#define HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10
+#define HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL
+#define HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
+//HUBP5_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP5_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0
+#define HUBP5_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10
+#define HUBP5_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL
+#define HUBP5_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L
+//HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0
+#define HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10
+#define HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL
+#define HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L
+//HUBP5_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L
+//HUBP5_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L
+#define HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L
+//HUBP5_DCHUBP_CNTL
+#define HUBP5_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0
+#define HUBP5_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1
+#define HUBP5_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2
+#define HUBP5_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3
+#define HUBP5_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4
+#define HUBP5_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8
+#define HUBP5_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9
+#define HUBP5_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc
+#define HUBP5_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd
+#define HUBP5_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10
+#define HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14
+#define HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18
+#define HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a
+#define HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b
+#define HUBP5_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c
+#define HUBP5_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f
+#define HUBP5_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L
+#define HUBP5_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L
+#define HUBP5_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L
+#define HUBP5_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L
+#define HUBP5_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L
+#define HUBP5_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L
+#define HUBP5_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L
+#define HUBP5_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L
+#define HUBP5_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L
+#define HUBP5_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L
+#define HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L
+#define HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L
+#define HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L
+#define HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L
+#define HUBP5_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L
+#define HUBP5_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L
+//HUBP5_HUBP_CLK_CNTL
+#define HUBP5_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17
+#define HUBP5_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c
+#define HUBP5_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L
+#define HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L
+#define HUBP5_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L
+//HUBP5_DCHUBP_VMPG_CONFIG
+#define HUBP5_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0
+#define HUBP5_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L
+//HUBP5_HUBPREQ_DEBUG_DB
+#define HUBP5_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0
+#define HUBP5_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL
+//HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L
+//HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L
+#define HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubpreq_dispdec
+//HUBPREQ5_DCSURF_SURFACE_PITCH
+#define HUBPREQ5_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10
+#define HUBPREQ5_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL
+#define HUBPREQ5_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L
+//HUBPREQ5_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ5_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10
+#define HUBPREQ5_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL
+#define HUBPREQ5_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L
+//HUBPREQ5_VMID_SETTINGS_0
+#define HUBPREQ5_VMID_SETTINGS_0__VMID__SHIFT 0x0
+#define HUBPREQ5_VMID_SETTINGS_0__VMID_MASK 0x0000000FL
+//HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_SURFACE_CONTROL
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L
+#define HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L
+//HUBPREQ5_DCSURF_FLIP_CONTROL
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L
+//HUBPREQ5_DCSURF_FLIP_CONTROL2
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L
+#define HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L
+//HUBPREQ5_DCSURF_QUEUE_CONTROL
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__GPUID__SHIFT 0x0
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT 0x4
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT 0x8
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT 0x9
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT 0xc
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT 0x10
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT 0x11
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT 0x14
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT 0x18
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__GPUID_MASK 0x00000007L
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK 0x00000070L
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK 0x00000100L
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK 0x00000200L
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK 0x0000F000L
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK 0x00010000L
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK 0x00020000L
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK 0x00700000L
+#define HUBPREQ5_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK 0x07000000L
+//HUBPREQ5_DCSURF_FRAME_PACING_TIME
+#define HUBPREQ5_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT 0x0
+#define HUBPREQ5_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK 0xFFFFFFFFL
+//HUBPREQ5_SURFACE_CURRENT_PACING_COUNTER
+#define HUBPREQ5_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT 0x0
+#define HUBPREQ5_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L
+#define HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L
+//HUBPREQ5_DCSURF_SURFACE_INUSE
+#define HUBPREQ5_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ5_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
+//HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
+#define HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
+//HUBPREQ5_DCN_EXPANSION_MODE
+#define HUBPREQ5_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0
+#define HUBPREQ5_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2
+#define HUBPREQ5_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4
+#define HUBPREQ5_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6
+#define HUBPREQ5_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L
+#define HUBPREQ5_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL
+#define HUBPREQ5_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L
+#define HUBPREQ5_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L
+//HUBPREQ5_DCN_TTU_QOS_WM
+#define HUBPREQ5_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0
+#define HUBPREQ5_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10
+#define HUBPREQ5_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL
+#define HUBPREQ5_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L
+//HUBPREQ5_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ5_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0
+#define HUBPREQ5_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c
+#define HUBPREQ5_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL
+#define HUBPREQ5_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L
+//HUBPREQ5_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ5_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ5_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ5_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ5_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ5_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ5_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ5_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ5_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ5_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ5_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ5_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ5_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ5_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ5_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ5_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ5_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ5_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ5_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ5_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ5_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ5_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ5_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ5_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ5_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ5_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ5_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ5_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ5_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ5_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ5_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ5_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
+#define HUBPREQ5_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
+#define HUBPREQ5_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
+#define HUBPREQ5_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
+#define HUBPREQ5_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
+#define HUBPREQ5_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
+//HUBPREQ5_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ5_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
+#define HUBPREQ5_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
+//HUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0
+#define HUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0
+#define HUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL
+//HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L
+//HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL
+//HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT 0x1e
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK 0x40000000L
+//HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL
+//HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0
+#define HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPREQ5_DC_VM_CONTEXT0_CNTL
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define HUBPREQ5_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+//HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+//HUBPREQ5_BLANK_OFFSET_0
+#define HUBPREQ5_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0
+#define HUBPREQ5_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10
+#define HUBPREQ5_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL
+#define HUBPREQ5_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L
+//HUBPREQ5_BLANK_OFFSET_1
+#define HUBPREQ5_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0
+#define HUBPREQ5_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL
+//HUBPREQ5_DST_DIMENSIONS
+#define HUBPREQ5_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0
+#define HUBPREQ5_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL
+//HUBPREQ5_DST_AFTER_SCALER
+#define HUBPREQ5_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0
+#define HUBPREQ5_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10
+#define HUBPREQ5_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL
+#define HUBPREQ5_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L
+//HUBPREQ5_PREFETCH_SETTINGS
+#define HUBPREQ5_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0
+#define HUBPREQ5_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18
+#define HUBPREQ5_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL
+#define HUBPREQ5_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L
+//HUBPREQ5_PREFETCH_SETTINGS_C
+#define HUBPREQ5_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0
+#define HUBPREQ5_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL
+//HUBPREQ5_VBLANK_PARAMETERS_0
+#define HUBPREQ5_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0
+#define HUBPREQ5_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8
+#define HUBPREQ5_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL
+#define HUBPREQ5_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L
+//HUBPREQ5_VBLANK_PARAMETERS_1
+#define HUBPREQ5_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0
+#define HUBPREQ5_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ5_VBLANK_PARAMETERS_2
+#define HUBPREQ5_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0
+#define HUBPREQ5_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ5_VBLANK_PARAMETERS_3
+#define HUBPREQ5_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0
+#define HUBPREQ5_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL
+//HUBPREQ5_VBLANK_PARAMETERS_4
+#define HUBPREQ5_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0
+#define HUBPREQ5_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL
+//HUBPREQ5_FLIP_PARAMETERS_0
+#define HUBPREQ5_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0
+#define HUBPREQ5_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8
+#define HUBPREQ5_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000001FL
+#define HUBPREQ5_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L
+//HUBPREQ5_FLIP_PARAMETERS_1
+#define HUBPREQ5_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0
+#define HUBPREQ5_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ5_FLIP_PARAMETERS_2
+#define HUBPREQ5_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0
+#define HUBPREQ5_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL
+//HUBPREQ5_NOM_PARAMETERS_0
+#define HUBPREQ5_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ5_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ5_NOM_PARAMETERS_1
+#define HUBPREQ5_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0
+#define HUBPREQ5_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ5_NOM_PARAMETERS_2
+#define HUBPREQ5_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ5_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ5_NOM_PARAMETERS_3
+#define HUBPREQ5_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0
+#define HUBPREQ5_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ5_NOM_PARAMETERS_4
+#define HUBPREQ5_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0
+#define HUBPREQ5_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL
+//HUBPREQ5_NOM_PARAMETERS_5
+#define HUBPREQ5_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0
+#define HUBPREQ5_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL
+//HUBPREQ5_NOM_PARAMETERS_6
+#define HUBPREQ5_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0
+#define HUBPREQ5_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL
+//HUBPREQ5_NOM_PARAMETERS_7
+#define HUBPREQ5_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0
+#define HUBPREQ5_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL
+//HUBPREQ5_PER_LINE_DELIVERY_PRE
+#define HUBPREQ5_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0
+#define HUBPREQ5_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10
+#define HUBPREQ5_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL
+#define HUBPREQ5_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L
+//HUBPREQ5_PER_LINE_DELIVERY
+#define HUBPREQ5_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0
+#define HUBPREQ5_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10
+#define HUBPREQ5_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL
+#define HUBPREQ5_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L
+//HUBPREQ5_CURSOR_SETTINGS
+#define HUBPREQ5_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0
+#define HUBPREQ5_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8
+#define HUBPREQ5_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10
+#define HUBPREQ5_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18
+#define HUBPREQ5_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL
+#define HUBPREQ5_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L
+#define HUBPREQ5_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L
+#define HUBPREQ5_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L
+//HUBPREQ5_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ5_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0
+#define HUBPREQ5_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL
+//HUBPREQ5_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ5_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0
+#define HUBPREQ5_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL
+//HUBPREQ5_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L
+#define HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L
+//HUBPREQ5_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6
+#define HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L
+#define HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubpret_dispdec
+//HUBPRET5_HUBPRET_CONTROL
+#define HUBPRET5_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0
+#define HUBPRET5_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc
+#define HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10
+#define HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12
+#define HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14
+#define HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16
+#define HUBPRET5_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18
+#define HUBPRET5_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL
+#define HUBPRET5_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L
+#define HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L
+#define HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L
+#define HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L
+#define HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L
+#define HUBPRET5_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L
+//HUBPRET5_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L
+#define HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L
+//HUBPRET5_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET5_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0
+#define HUBPRET5_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2
+#define HUBPRET5_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4
+#define HUBPRET5_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L
+#define HUBPRET5_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL
+#define HUBPRET5_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L
+//HUBPRET5_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET5_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0
+#define HUBPRET5_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10
+#define HUBPRET5_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL
+#define HUBPRET5_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L
+//HUBPRET5_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET5_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0
+#define HUBPRET5_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10
+#define HUBPRET5_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL
+#define HUBPRET5_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L
+//HUBPRET5_HUBPRET_READ_LINE0
+#define HUBPRET5_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0
+#define HUBPRET5_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10
+#define HUBPRET5_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL
+#define HUBPRET5_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L
+//HUBPRET5_HUBPRET_READ_LINE1
+#define HUBPRET5_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0
+#define HUBPRET5_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10
+#define HUBPRET5_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL
+#define HUBPRET5_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L
+//HUBPRET5_HUBPRET_INTERRUPT
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L
+#define HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L
+//HUBPRET5_HUBPRET_READ_LINE_VALUE
+#define HUBPRET5_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0
+#define HUBPRET5_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10
+#define HUBPRET5_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL
+#define HUBPRET5_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L
+//HUBPRET5_HUBPRET_READ_LINE_STATUS
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L
+#define HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_cursor0_dispdec
+//CURSOR0_5_CURSOR_CONTROL
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L
+#define CURSOR0_5_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L
+//CURSOR0_5_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_5_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define CURSOR0_5_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
+//CURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
+//CURSOR0_5_CURSOR_SIZE
+#define CURSOR0_5_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define CURSOR0_5_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define CURSOR0_5_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL
+#define CURSOR0_5_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L
+//CURSOR0_5_CURSOR_POSITION
+#define CURSOR0_5_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define CURSOR0_5_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define CURSOR0_5_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL
+#define CURSOR0_5_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L
+//CURSOR0_5_CURSOR_HOT_SPOT
+#define CURSOR0_5_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define CURSOR0_5_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define CURSOR0_5_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL
+#define CURSOR0_5_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L
+//CURSOR0_5_CURSOR_STEREO_CONTROL
+#define CURSOR0_5_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define CURSOR0_5_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define CURSOR0_5_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12
+#define CURSOR0_5_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L
+#define CURSOR0_5_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L
+#define CURSOR0_5_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L
+//CURSOR0_5_CURSOR_DST_OFFSET
+#define CURSOR0_5_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0
+#define CURSOR0_5_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL
+//CURSOR0_5_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_5_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0
+#define CURSOR0_5_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2
+#define CURSOR0_5_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4
+#define CURSOR0_5_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L
+#define CURSOR0_5_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L
+#define CURSOR0_5_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L
+//CURSOR0_5_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_5_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0
+#define CURSOR0_5_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L
+//CURSOR0_5_DMDATA_ADDRESS_HIGH
+#define CURSOR0_5_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0
+#define CURSOR0_5_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c
+#define CURSOR0_5_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d
+#define CURSOR0_5_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e
+#define CURSOR0_5_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL
+#define CURSOR0_5_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L
+#define CURSOR0_5_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L
+#define CURSOR0_5_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L
+//CURSOR0_5_DMDATA_ADDRESS_LOW
+#define CURSOR0_5_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0
+#define CURSOR0_5_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//CURSOR0_5_DMDATA_CNTL
+#define CURSOR0_5_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0
+#define CURSOR0_5_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1
+#define CURSOR0_5_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2
+#define CURSOR0_5_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10
+#define CURSOR0_5_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L
+#define CURSOR0_5_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L
+#define CURSOR0_5_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L
+#define CURSOR0_5_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L
+//CURSOR0_5_DMDATA_QOS_CNTL
+#define CURSOR0_5_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0
+#define CURSOR0_5_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4
+#define CURSOR0_5_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10
+#define CURSOR0_5_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L
+#define CURSOR0_5_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L
+#define CURSOR0_5_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L
+//CURSOR0_5_DMDATA_STATUS
+#define CURSOR0_5_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0
+#define CURSOR0_5_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2
+#define CURSOR0_5_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4
+#define CURSOR0_5_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L
+#define CURSOR0_5_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L
+#define CURSOR0_5_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L
+//CURSOR0_5_DMDATA_SW_CNTL
+#define CURSOR0_5_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0
+#define CURSOR0_5_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1
+#define CURSOR0_5_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10
+#define CURSOR0_5_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L
+#define CURSOR0_5_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L
+#define CURSOR0_5_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L
+//CURSOR0_5_DMDATA_SW_DATA
+#define CURSOR0_5_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0
+#define CURSOR0_5_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON12_PERFCOUNTER_CNTL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_CNTL2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_STATE
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON12_PERFMON_CNTL
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON12_PERFMON_CNTL2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON12_PERFMON_CVALUE_LOW
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON12_PERFMON_HI
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON12_PERFMON_LOW
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp5_dispdec_hubpxfc_dispdec
+//HUBPXFC5_HUBP_XFC_CNTL
+#define HUBPXFC5_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define HUBPXFC5_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define HUBPXFC5_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define HUBPXFC5_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define HUBPXFC5_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define HUBPXFC5_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT 0x8
+#define HUBPXFC5_HUBP_XFC_CNTL__RD_VMID__SHIFT 0x14
+#define HUBPXFC5_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT 0x18
+#define HUBPXFC5_HUBP_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define HUBPXFC5_HUBP_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define HUBPXFC5_HUBP_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define HUBPXFC5_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define HUBPXFC5_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define HUBPXFC5_HUBP_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define HUBPXFC5_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK 0x00000100L
+#define HUBPXFC5_HUBP_XFC_CNTL__RD_VMID_MASK 0x00F00000L
+#define HUBPXFC5_HUBP_XFC_CNTL__CHUNK_SIZE_MASK 0x07000000L
+//HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//HUBPXFC5_HUBP_XFC_XBUF_RD_PITCH
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK 0x00003FFFL
+//HUBPXFC5_HUBP_XFC_DELAY_CONFIG0
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT 0x8
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT 0x10
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK 0x000000FFL
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK 0x0000FF00L
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK 0x00FF0000L
+//HUBPXFC5_HUBP_XFC_DELAY_CONFIG1
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK 0x000FFFFFL
+//HUBPXFC5_HUBP_XFC_DELAY_CONFIG2
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT 0x1f
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK 0x000FFFFFL
+#define HUBPXFC5_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK 0x80000000L
+//HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT 0x1
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT 0x4
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT 0x1c
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT 0x1d
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT 0x1e
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT 0x1f
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK 0x00000001L
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK 0x00000002L
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK 0x0FFFFFF0L
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK 0x10000000L
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK 0x20000000L
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK 0x40000000L
+#define HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK 0x80000000L
+//HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0
+#define HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT 0x10
+#define HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK 0xFFFF0000L
+//HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1
+#define HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT 0x10
+#define HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK 0x03FF0000L
+//HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0
+#define HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK 0x007FFFFFL
+//HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1
+#define HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK 0x003FFFFFL
+//HUBPXFC5_HUBP_XFC_MPC_CONFIG
+#define HUBPXFC5_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT 0x0
+#define HUBPXFC5_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT 0x10
+#define HUBPXFC5_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK 0x00001FFFL
+#define HUBPXFC5_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK 0x1FFF0000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+//DPP_TOP0_DPP_CONTROL
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L
+//DPP_TOP0_DPP_SOFT_RESET
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L
+//DPP_TOP0_DPP_CRC_VAL_R_G
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L
+//DPP_TOP0_DPP_CRC_VAL_B_A
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L
+//DPP_TOP0_DPP_CRC_CTRL
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L
+//DPP_TOP0_HOST_READ_CONTROL
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+//CNVC_CFG0_FORMAT_CONTROL
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L
+//CNVC_CFG0_FCNV_FP_BIAS_R
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_G
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_B
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_R
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_G
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_B
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL
+//CNVC_CFG0_COLOR_KEYER_CONTROL
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L
+//CNVC_CFG0_COLOR_KEYER_ALPHA
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_RED
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_GREEN
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_BLUE
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG0_ALPHA_2BIT_LUT
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+//CNVC_CUR0_CURSOR0_CONTROL
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L
+//CNVC_CUR0_CURSOR0_COLOR0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_COLOR1
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+//DSCL0_SCL_COEF_RAM_TAP_SELECT
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L
+//DSCL0_SCL_COEF_RAM_TAP_DATA
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//DSCL0_SCL_MODE
+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18
+#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L
+//DSCL0_SCL_TAP_CONTROL
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L
+//DSCL0_DSCL_CONTROL
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+//DSCL0_DSCL_2TAP_CONTROL
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L
+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT_C
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L
+//DSCL0_SCL_BLACK_OFFSET
+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0
+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10
+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L
+//DSCL0_DSCL_UPDATE
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+//DSCL0_DSCL_AUTOCAL
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L
+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//DSCL0_OTG_H_BLANK
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L
+//DSCL0_OTG_V_BLANK
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L
+//DSCL0_RECOUT_START
+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0
+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10
+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL
+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L
+//DSCL0_RECOUT_SIZE
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L
+//DSCL0_MPC_SIZE
+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0
+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10
+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL
+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L
+//DSCL0_LB_DATA_FORMAT
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L
+//DSCL0_LB_MEMORY_CTRL
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L
+//DSCL0_LB_V_COUNTER
+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10
+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L
+//DSCL0_DSCL_MEM_PWR_CTRL
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L
+//DSCL0_DSCL_MEM_PWR_STATUS
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L
+//DSCL0_OBUF_CONTROL
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L
+//DSCL0_OBUF_MEM_PWR_CTRL
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+//CM0_CM_CONTROL
+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT 0x0
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8
+#define CM0_CM_CONTROL__CM_BYPASS_MASK 0x00000001L
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L
+//CM0_CM_ICSC_CONTROL
+#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0
+#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L
+//CM0_CM_ICSC_C11_C12
+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0
+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10
+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L
+//CM0_CM_ICSC_C13_C14
+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0
+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10
+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L
+//CM0_CM_ICSC_C21_C22
+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0
+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10
+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L
+//CM0_CM_ICSC_C23_C24
+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0
+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10
+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L
+//CM0_CM_ICSC_C31_C32
+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0
+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10
+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L
+//CM0_CM_ICSC_C33_C34
+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0
+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10
+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L
+//CM0_CM_ICSC_B_C11_C12
+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0
+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10
+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L
+//CM0_CM_ICSC_B_C13_C14
+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0
+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10
+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L
+//CM0_CM_ICSC_B_C21_C22
+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0
+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10
+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L
+//CM0_CM_ICSC_B_C23_C24
+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0
+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10
+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L
+//CM0_CM_ICSC_B_C31_C32
+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0
+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10
+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L
+//CM0_CM_ICSC_B_C33_C34
+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0
+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10
+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL
+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_CONTROL
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L
+//CM0_CM_GAMUT_REMAP_C11_C12
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C13_C14
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C21_C22
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C23_C24
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C31_C32
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C33_C34
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C11_C12
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C13_C14
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C21_C22
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C23_C24
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C31_C32
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C33_C34
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L
+//CM0_CM_BIAS_CR_R
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL
+//CM0_CM_BIAS_Y_G_CB_B
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L
+//CM0_CM_DGAM_CONTROL
+#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0
+#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L
+//CM0_CM_DGAM_LUT_INDEX
+#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0
+#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL
+//CM0_CM_DGAM_LUT_DATA
+#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0
+#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM0_CM_DGAM_LUT_WRITE_EN_MASK
+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc
+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L
+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L
+//CM0_CM_DGAM_RAMA_START_CNTL_B
+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM0_CM_DGAM_RAMA_START_CNTL_G
+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM0_CM_DGAM_RAMA_START_CNTL_R
+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM0_CM_DGAM_RAMA_SLOPE_CNTL_B
+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM0_CM_DGAM_RAMA_SLOPE_CNTL_G
+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM0_CM_DGAM_RAMA_SLOPE_CNTL_R
+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM0_CM_DGAM_RAMA_END_CNTL1_B
+#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM0_CM_DGAM_RAMA_END_CNTL2_B
+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM0_CM_DGAM_RAMA_END_CNTL1_G
+#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM0_CM_DGAM_RAMA_END_CNTL2_G
+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM0_CM_DGAM_RAMA_END_CNTL1_R
+#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM0_CM_DGAM_RAMA_END_CNTL2_R
+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM0_CM_DGAM_RAMA_REGION_0_1
+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMA_REGION_2_3
+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMA_REGION_4_5
+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMA_REGION_6_7
+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMA_REGION_8_9
+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMA_REGION_10_11
+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMA_REGION_12_13
+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMA_REGION_14_15
+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMB_START_CNTL_B
+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM0_CM_DGAM_RAMB_START_CNTL_G
+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM0_CM_DGAM_RAMB_START_CNTL_R
+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM0_CM_DGAM_RAMB_SLOPE_CNTL_B
+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM0_CM_DGAM_RAMB_SLOPE_CNTL_G
+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM0_CM_DGAM_RAMB_SLOPE_CNTL_R
+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM0_CM_DGAM_RAMB_END_CNTL1_B
+#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM0_CM_DGAM_RAMB_END_CNTL2_B
+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM0_CM_DGAM_RAMB_END_CNTL1_G
+#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM0_CM_DGAM_RAMB_END_CNTL2_G
+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM0_CM_DGAM_RAMB_END_CNTL1_R
+#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM0_CM_DGAM_RAMB_END_CNTL2_R
+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM0_CM_DGAM_RAMB_REGION_0_1
+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMB_REGION_2_3
+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMB_REGION_4_5
+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMB_REGION_6_7
+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMB_REGION_8_9
+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMB_REGION_10_11
+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMB_REGION_12_13
+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_DGAM_RAMB_REGION_14_15
+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_CONTROL
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L
+//CM0_CM_BLNDGAM_LUT_INDEX
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL
+//CM0_CM_BLNDGAM_LUT_DATA
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK
+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_HDR_MULT_COEF
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL
+//CM0_CM_MEM_PWR_CTRL
+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0
+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6
+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L
+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L
+//CM0_CM_MEM_PWR_STATUS
+#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2
+#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL
+//CM0_CM_DEALPHA
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L
+//CM0_CM_COEF_FORMAT
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0
+#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L
+#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L
+//CM0_CM_SHAPER_CONTROL
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L
+//CM0_CM_SHAPER_OFFSET_R
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_G
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_B
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL
+//CM0_CM_SHAPER_SCALE_R
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL
+//CM0_CM_SHAPER_SCALE_G_B
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L
+//CM0_CM_SHAPER_LUT_INDEX
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL
+//CM0_CM_SHAPER_LUT_DATA
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL
+//CM0_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L
+//CM0_CM_SHAPER_RAMA_START_CNTL_B
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_G
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_R
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_B
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_G
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_R
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_REGION_0_1
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_2_3
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_4_5
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_6_7
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_8_9
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_10_11
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_12_13
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_14_15
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_16_17
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_18_19
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_20_21
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_22_23
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_24_25
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_26_27
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_28_29
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_30_31
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_32_33
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_B
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_G
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_R
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_B
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_G
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_R
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_REGION_0_1
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_2_3
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_4_5
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_6_7
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_8_9
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_10_11
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_12_13
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_14_15
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_16_17
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_18_19
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_20_21
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_22_23
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_24_25
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_26_27
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_28_29
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_30_31
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_32_33
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM0_CM_MEM_PWR_CTRL2
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L
+//CM0_CM_MEM_PWR_STATUS2
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L
+//CM0_CM_3DLUT_MODE
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L
+//CM0_CM_3DLUT_INDEX
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL
+//CM0_CM_3DLUT_DATA
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L
+//CM0_CM_3DLUT_DATA_30BIT
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL
+//CM0_CM_3DLUT_READ_WRITE_CONTROL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L
+//CM0_CM_3DLUT_OUT_NORM_FACTOR
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL
+//CM0_CM_3DLUT_OUT_OFFSET_R
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_G
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_B
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
+//CM0_CM_TEST_DEBUG_INDEX
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//CM0_CM_TEST_DEBUG_DATA
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON13_PERFCOUNTER_CNTL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_CNTL2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_STATE
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON13_PERFMON_CNTL
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON13_PERFMON_CNTL2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON13_PERFMON_CVALUE_LOW
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON13_PERFMON_HI
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON13_PERFMON_LOW
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+//DPP_TOP1_DPP_CONTROL
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L
+//DPP_TOP1_DPP_SOFT_RESET
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L
+//DPP_TOP1_DPP_CRC_VAL_R_G
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L
+//DPP_TOP1_DPP_CRC_VAL_B_A
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L
+//DPP_TOP1_DPP_CRC_CTRL
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L
+//DPP_TOP1_HOST_READ_CONTROL
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+//CNVC_CFG1_FORMAT_CONTROL
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L
+//CNVC_CFG1_FCNV_FP_BIAS_R
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_G
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_B
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_R
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_G
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_B
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL
+//CNVC_CFG1_COLOR_KEYER_CONTROL
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L
+//CNVC_CFG1_COLOR_KEYER_ALPHA
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_RED
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_GREEN
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_BLUE
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG1_ALPHA_2BIT_LUT
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+//CNVC_CUR1_CURSOR0_CONTROL
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L
+//CNVC_CUR1_CURSOR0_COLOR0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_COLOR1
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+//DSCL1_SCL_COEF_RAM_TAP_SELECT
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L
+//DSCL1_SCL_COEF_RAM_TAP_DATA
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//DSCL1_SCL_MODE
+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18
+#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L
+//DSCL1_SCL_TAP_CONTROL
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L
+//DSCL1_DSCL_CONTROL
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+//DSCL1_DSCL_2TAP_CONTROL
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L
+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT_C
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L
+//DSCL1_SCL_BLACK_OFFSET
+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0
+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10
+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L
+//DSCL1_DSCL_UPDATE
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+//DSCL1_DSCL_AUTOCAL
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L
+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//DSCL1_OTG_H_BLANK
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L
+//DSCL1_OTG_V_BLANK
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L
+//DSCL1_RECOUT_START
+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0
+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10
+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL
+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L
+//DSCL1_RECOUT_SIZE
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L
+//DSCL1_MPC_SIZE
+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0
+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10
+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL
+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L
+//DSCL1_LB_DATA_FORMAT
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L
+//DSCL1_LB_MEMORY_CTRL
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L
+//DSCL1_LB_V_COUNTER
+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10
+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L
+//DSCL1_DSCL_MEM_PWR_CTRL
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L
+//DSCL1_DSCL_MEM_PWR_STATUS
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L
+//DSCL1_OBUF_CONTROL
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L
+//DSCL1_OBUF_MEM_PWR_CTRL
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+//CM1_CM_CONTROL
+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT 0x0
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8
+#define CM1_CM_CONTROL__CM_BYPASS_MASK 0x00000001L
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L
+//CM1_CM_ICSC_CONTROL
+#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0
+#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L
+//CM1_CM_ICSC_C11_C12
+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0
+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10
+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L
+//CM1_CM_ICSC_C13_C14
+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0
+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10
+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L
+//CM1_CM_ICSC_C21_C22
+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0
+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10
+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L
+//CM1_CM_ICSC_C23_C24
+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0
+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10
+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L
+//CM1_CM_ICSC_C31_C32
+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0
+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10
+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L
+//CM1_CM_ICSC_C33_C34
+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0
+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10
+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L
+//CM1_CM_ICSC_B_C11_C12
+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0
+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10
+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L
+//CM1_CM_ICSC_B_C13_C14
+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0
+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10
+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L
+//CM1_CM_ICSC_B_C21_C22
+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0
+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10
+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L
+//CM1_CM_ICSC_B_C23_C24
+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0
+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10
+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L
+//CM1_CM_ICSC_B_C31_C32
+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0
+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10
+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L
+//CM1_CM_ICSC_B_C33_C34
+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0
+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10
+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL
+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_CONTROL
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L
+//CM1_CM_GAMUT_REMAP_C11_C12
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C13_C14
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C21_C22
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C23_C24
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C31_C32
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C33_C34
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C11_C12
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C13_C14
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C21_C22
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C23_C24
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C31_C32
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C33_C34
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L
+//CM1_CM_BIAS_CR_R
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL
+//CM1_CM_BIAS_Y_G_CB_B
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L
+//CM1_CM_DGAM_CONTROL
+#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0
+#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L
+//CM1_CM_DGAM_LUT_INDEX
+#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0
+#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL
+//CM1_CM_DGAM_LUT_DATA
+#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0
+#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM1_CM_DGAM_LUT_WRITE_EN_MASK
+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc
+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L
+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L
+//CM1_CM_DGAM_RAMA_START_CNTL_B
+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM1_CM_DGAM_RAMA_START_CNTL_G
+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM1_CM_DGAM_RAMA_START_CNTL_R
+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM1_CM_DGAM_RAMA_SLOPE_CNTL_B
+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM1_CM_DGAM_RAMA_SLOPE_CNTL_G
+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM1_CM_DGAM_RAMA_SLOPE_CNTL_R
+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM1_CM_DGAM_RAMA_END_CNTL1_B
+#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM1_CM_DGAM_RAMA_END_CNTL2_B
+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM1_CM_DGAM_RAMA_END_CNTL1_G
+#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM1_CM_DGAM_RAMA_END_CNTL2_G
+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM1_CM_DGAM_RAMA_END_CNTL1_R
+#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM1_CM_DGAM_RAMA_END_CNTL2_R
+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM1_CM_DGAM_RAMA_REGION_0_1
+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMA_REGION_2_3
+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMA_REGION_4_5
+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMA_REGION_6_7
+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMA_REGION_8_9
+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMA_REGION_10_11
+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMA_REGION_12_13
+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMA_REGION_14_15
+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMB_START_CNTL_B
+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM1_CM_DGAM_RAMB_START_CNTL_G
+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM1_CM_DGAM_RAMB_START_CNTL_R
+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM1_CM_DGAM_RAMB_SLOPE_CNTL_B
+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM1_CM_DGAM_RAMB_SLOPE_CNTL_G
+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM1_CM_DGAM_RAMB_SLOPE_CNTL_R
+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM1_CM_DGAM_RAMB_END_CNTL1_B
+#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM1_CM_DGAM_RAMB_END_CNTL2_B
+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM1_CM_DGAM_RAMB_END_CNTL1_G
+#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM1_CM_DGAM_RAMB_END_CNTL2_G
+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM1_CM_DGAM_RAMB_END_CNTL1_R
+#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM1_CM_DGAM_RAMB_END_CNTL2_R
+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM1_CM_DGAM_RAMB_REGION_0_1
+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMB_REGION_2_3
+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMB_REGION_4_5
+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMB_REGION_6_7
+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMB_REGION_8_9
+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMB_REGION_10_11
+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMB_REGION_12_13
+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_DGAM_RAMB_REGION_14_15
+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_CONTROL
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L
+//CM1_CM_BLNDGAM_LUT_INDEX
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL
+//CM1_CM_BLNDGAM_LUT_DATA
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK
+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_HDR_MULT_COEF
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL
+//CM1_CM_MEM_PWR_CTRL
+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0
+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6
+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L
+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L
+//CM1_CM_MEM_PWR_STATUS
+#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2
+#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL
+//CM1_CM_DEALPHA
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L
+//CM1_CM_COEF_FORMAT
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0
+#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L
+#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L
+//CM1_CM_SHAPER_CONTROL
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L
+//CM1_CM_SHAPER_OFFSET_R
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_G
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_B
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL
+//CM1_CM_SHAPER_SCALE_R
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL
+//CM1_CM_SHAPER_SCALE_G_B
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L
+//CM1_CM_SHAPER_LUT_INDEX
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL
+//CM1_CM_SHAPER_LUT_DATA
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL
+//CM1_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L
+//CM1_CM_SHAPER_RAMA_START_CNTL_B
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_G
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_R
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_B
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_G
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_R
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_REGION_0_1
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_2_3
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_4_5
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_6_7
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_8_9
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_10_11
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_12_13
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_14_15
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_16_17
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_18_19
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_20_21
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_22_23
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_24_25
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_26_27
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_28_29
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_30_31
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_32_33
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_B
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_G
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_R
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_B
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_G
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_R
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_REGION_0_1
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_2_3
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_4_5
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_6_7
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_8_9
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_10_11
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_12_13
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_14_15
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_16_17
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_18_19
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_20_21
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_22_23
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_24_25
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_26_27
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_28_29
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_30_31
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_32_33
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM1_CM_MEM_PWR_CTRL2
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L
+//CM1_CM_MEM_PWR_STATUS2
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L
+//CM1_CM_3DLUT_MODE
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L
+//CM1_CM_3DLUT_INDEX
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL
+//CM1_CM_3DLUT_DATA
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L
+//CM1_CM_3DLUT_DATA_30BIT
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL
+//CM1_CM_3DLUT_READ_WRITE_CONTROL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L
+//CM1_CM_3DLUT_OUT_NORM_FACTOR
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL
+//CM1_CM_3DLUT_OUT_OFFSET_R
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_G
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_B
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
+//CM1_CM_TEST_DEBUG_INDEX
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//CM1_CM_TEST_DEBUG_DATA
+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON14_PERFCOUNTER_CNTL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_CNTL2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_STATE
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON14_PERFMON_CNTL
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON14_PERFMON_CNTL2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON14_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON14_PERFMON_CVALUE_LOW
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON14_PERFMON_HI
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON14_PERFMON_LOW
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+//DPP_TOP2_DPP_CONTROL
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L
+//DPP_TOP2_DPP_SOFT_RESET
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L
+//DPP_TOP2_DPP_CRC_VAL_R_G
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L
+//DPP_TOP2_DPP_CRC_VAL_B_A
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L
+//DPP_TOP2_DPP_CRC_CTRL
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L
+//DPP_TOP2_HOST_READ_CONTROL
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+//CNVC_CFG2_FORMAT_CONTROL
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L
+//CNVC_CFG2_FCNV_FP_BIAS_R
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_G
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_B
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_R
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_G
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_B
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL
+//CNVC_CFG2_COLOR_KEYER_CONTROL
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L
+//CNVC_CFG2_COLOR_KEYER_ALPHA
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_RED
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_GREEN
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_BLUE
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG2_ALPHA_2BIT_LUT
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+//CNVC_CUR2_CURSOR0_CONTROL
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L
+//CNVC_CUR2_CURSOR0_COLOR0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_COLOR1
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+//DSCL2_SCL_COEF_RAM_TAP_SELECT
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L
+//DSCL2_SCL_COEF_RAM_TAP_DATA
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//DSCL2_SCL_MODE
+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18
+#define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L
+//DSCL2_SCL_TAP_CONTROL
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L
+//DSCL2_DSCL_CONTROL
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+//DSCL2_DSCL_2TAP_CONTROL
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L
+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT_C
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L
+//DSCL2_SCL_BLACK_OFFSET
+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0
+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10
+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L
+//DSCL2_DSCL_UPDATE
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+//DSCL2_DSCL_AUTOCAL
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L
+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//DSCL2_OTG_H_BLANK
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L
+//DSCL2_OTG_V_BLANK
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L
+//DSCL2_RECOUT_START
+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0
+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10
+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL
+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L
+//DSCL2_RECOUT_SIZE
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L
+//DSCL2_MPC_SIZE
+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0
+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10
+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL
+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L
+//DSCL2_LB_DATA_FORMAT
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L
+//DSCL2_LB_MEMORY_CTRL
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L
+//DSCL2_LB_V_COUNTER
+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10
+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L
+//DSCL2_DSCL_MEM_PWR_CTRL
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L
+//DSCL2_DSCL_MEM_PWR_STATUS
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L
+//DSCL2_OBUF_CONTROL
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L
+//DSCL2_OBUF_MEM_PWR_CTRL
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+//CM2_CM_CONTROL
+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT 0x0
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8
+#define CM2_CM_CONTROL__CM_BYPASS_MASK 0x00000001L
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L
+//CM2_CM_ICSC_CONTROL
+#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0
+#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L
+//CM2_CM_ICSC_C11_C12
+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0
+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10
+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L
+//CM2_CM_ICSC_C13_C14
+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0
+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10
+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L
+//CM2_CM_ICSC_C21_C22
+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0
+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10
+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L
+//CM2_CM_ICSC_C23_C24
+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0
+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10
+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L
+//CM2_CM_ICSC_C31_C32
+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0
+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10
+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L
+//CM2_CM_ICSC_C33_C34
+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0
+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10
+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L
+//CM2_CM_ICSC_B_C11_C12
+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0
+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10
+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L
+//CM2_CM_ICSC_B_C13_C14
+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0
+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10
+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L
+//CM2_CM_ICSC_B_C21_C22
+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0
+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10
+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L
+//CM2_CM_ICSC_B_C23_C24
+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0
+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10
+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L
+//CM2_CM_ICSC_B_C31_C32
+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0
+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10
+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L
+//CM2_CM_ICSC_B_C33_C34
+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0
+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10
+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL
+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_CONTROL
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L
+//CM2_CM_GAMUT_REMAP_C11_C12
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C13_C14
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C21_C22
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C23_C24
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C31_C32
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C33_C34
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C11_C12
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C13_C14
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C21_C22
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C23_C24
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C31_C32
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C33_C34
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L
+//CM2_CM_BIAS_CR_R
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL
+//CM2_CM_BIAS_Y_G_CB_B
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L
+//CM2_CM_DGAM_CONTROL
+#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0
+#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L
+//CM2_CM_DGAM_LUT_INDEX
+#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0
+#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL
+//CM2_CM_DGAM_LUT_DATA
+#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0
+#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM2_CM_DGAM_LUT_WRITE_EN_MASK
+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc
+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L
+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L
+//CM2_CM_DGAM_RAMA_START_CNTL_B
+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM2_CM_DGAM_RAMA_START_CNTL_G
+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM2_CM_DGAM_RAMA_START_CNTL_R
+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM2_CM_DGAM_RAMA_SLOPE_CNTL_B
+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM2_CM_DGAM_RAMA_SLOPE_CNTL_G
+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM2_CM_DGAM_RAMA_SLOPE_CNTL_R
+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM2_CM_DGAM_RAMA_END_CNTL1_B
+#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM2_CM_DGAM_RAMA_END_CNTL2_B
+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM2_CM_DGAM_RAMA_END_CNTL1_G
+#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM2_CM_DGAM_RAMA_END_CNTL2_G
+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM2_CM_DGAM_RAMA_END_CNTL1_R
+#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM2_CM_DGAM_RAMA_END_CNTL2_R
+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM2_CM_DGAM_RAMA_REGION_0_1
+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMA_REGION_2_3
+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMA_REGION_4_5
+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMA_REGION_6_7
+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMA_REGION_8_9
+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMA_REGION_10_11
+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMA_REGION_12_13
+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMA_REGION_14_15
+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMB_START_CNTL_B
+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM2_CM_DGAM_RAMB_START_CNTL_G
+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM2_CM_DGAM_RAMB_START_CNTL_R
+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM2_CM_DGAM_RAMB_SLOPE_CNTL_B
+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM2_CM_DGAM_RAMB_SLOPE_CNTL_G
+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM2_CM_DGAM_RAMB_SLOPE_CNTL_R
+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM2_CM_DGAM_RAMB_END_CNTL1_B
+#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM2_CM_DGAM_RAMB_END_CNTL2_B
+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM2_CM_DGAM_RAMB_END_CNTL1_G
+#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM2_CM_DGAM_RAMB_END_CNTL2_G
+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM2_CM_DGAM_RAMB_END_CNTL1_R
+#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM2_CM_DGAM_RAMB_END_CNTL2_R
+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM2_CM_DGAM_RAMB_REGION_0_1
+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMB_REGION_2_3
+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMB_REGION_4_5
+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMB_REGION_6_7
+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMB_REGION_8_9
+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMB_REGION_10_11
+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMB_REGION_12_13
+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_DGAM_RAMB_REGION_14_15
+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_CONTROL
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L
+//CM2_CM_BLNDGAM_LUT_INDEX
+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0
+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL
+//CM2_CM_BLNDGAM_LUT_DATA
+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0
+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK
+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_HDR_MULT_COEF
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL
+//CM2_CM_MEM_PWR_CTRL
+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0
+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6
+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L
+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L
+//CM2_CM_MEM_PWR_STATUS
+#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0
+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2
+#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL
+//CM2_CM_DEALPHA
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L
+//CM2_CM_COEF_FORMAT
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0
+#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L
+#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L
+//CM2_CM_SHAPER_CONTROL
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L
+//CM2_CM_SHAPER_OFFSET_R
+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0
+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL
+//CM2_CM_SHAPER_OFFSET_G
+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0
+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL
+//CM2_CM_SHAPER_OFFSET_B
+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0
+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL
+//CM2_CM_SHAPER_SCALE_R
+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0
+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL
+//CM2_CM_SHAPER_SCALE_G_B
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L
+//CM2_CM_SHAPER_LUT_INDEX
+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0
+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL
+//CM2_CM_SHAPER_LUT_DATA
+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0
+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL
+//CM2_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L
+//CM2_CM_SHAPER_RAMA_START_CNTL_B
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM2_CM_SHAPER_RAMA_START_CNTL_G
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM2_CM_SHAPER_RAMA_START_CNTL_R
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_B
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_G
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_R
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_REGION_0_1
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_2_3
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_4_5
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_6_7
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_8_9
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_10_11
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_12_13
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_14_15
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_16_17
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_18_19
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_20_21
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_22_23
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_24_25
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_26_27
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_28_29
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_30_31
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_32_33
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_B
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_G
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_R
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_B
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_G
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_R
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_REGION_0_1
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_2_3
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_4_5
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_6_7
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_8_9
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_10_11
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_12_13
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_14_15
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_16_17
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_18_19
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_20_21
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_22_23
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_24_25
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_26_27
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_28_29
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_30_31
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_32_33
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM2_CM_MEM_PWR_CTRL2
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L
+//CM2_CM_MEM_PWR_STATUS2
+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4
+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6
+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L
+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L
+//CM2_CM_3DLUT_MODE
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L
+//CM2_CM_3DLUT_INDEX
+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0
+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL
+//CM2_CM_3DLUT_DATA
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L
+//CM2_CM_3DLUT_DATA_30BIT
+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2
+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL
+//CM2_CM_3DLUT_READ_WRITE_CONTROL
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L
+//CM2_CM_3DLUT_OUT_NORM_FACTOR
+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0
+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL
+//CM2_CM_3DLUT_OUT_OFFSET_R
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L
+//CM2_CM_3DLUT_OUT_OFFSET_G
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L
+//CM2_CM_3DLUT_OUT_OFFSET_B
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
+//CM2_CM_TEST_DEBUG_INDEX
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//CM2_CM_TEST_DEBUG_DATA
+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON15_PERFCOUNTER_CNTL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_CNTL2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_STATE
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON15_PERFMON_CNTL
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON15_PERFMON_CNTL2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON15_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON15_PERFMON_CVALUE_LOW
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON15_PERFMON_HI
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON15_PERFMON_LOW
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+//DPP_TOP3_DPP_CONTROL
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L
+//DPP_TOP3_DPP_SOFT_RESET
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L
+//DPP_TOP3_DPP_CRC_VAL_R_G
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L
+//DPP_TOP3_DPP_CRC_VAL_B_A
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L
+//DPP_TOP3_DPP_CRC_CTRL
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L
+//DPP_TOP3_HOST_READ_CONTROL
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+//CNVC_CFG3_FORMAT_CONTROL
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L
+//CNVC_CFG3_FCNV_FP_BIAS_R
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_G
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_B
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_R
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_G
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_B
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL
+//CNVC_CFG3_COLOR_KEYER_CONTROL
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L
+//CNVC_CFG3_COLOR_KEYER_ALPHA
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_RED
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_GREEN
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_BLUE
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG3_ALPHA_2BIT_LUT
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+//CNVC_CUR3_CURSOR0_CONTROL
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L
+//CNVC_CUR3_CURSOR0_COLOR0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_COLOR1
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+//DSCL3_SCL_COEF_RAM_TAP_SELECT
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L
+//DSCL3_SCL_COEF_RAM_TAP_DATA
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//DSCL3_SCL_MODE
+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18
+#define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L
+//DSCL3_SCL_TAP_CONTROL
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L
+//DSCL3_DSCL_CONTROL
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+//DSCL3_DSCL_2TAP_CONTROL
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L
+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT_C
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L
+//DSCL3_SCL_BLACK_OFFSET
+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0
+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10
+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L
+//DSCL3_DSCL_UPDATE
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+//DSCL3_DSCL_AUTOCAL
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L
+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//DSCL3_OTG_H_BLANK
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L
+//DSCL3_OTG_V_BLANK
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L
+//DSCL3_RECOUT_START
+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0
+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10
+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL
+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L
+//DSCL3_RECOUT_SIZE
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L
+//DSCL3_MPC_SIZE
+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0
+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10
+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL
+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L
+//DSCL3_LB_DATA_FORMAT
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L
+//DSCL3_LB_MEMORY_CTRL
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L
+//DSCL3_LB_V_COUNTER
+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10
+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L
+//DSCL3_DSCL_MEM_PWR_CTRL
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L
+//DSCL3_DSCL_MEM_PWR_STATUS
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L
+//DSCL3_OBUF_CONTROL
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L
+//DSCL3_OBUF_MEM_PWR_CTRL
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+//CM3_CM_CONTROL
+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT 0x0
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8
+#define CM3_CM_CONTROL__CM_BYPASS_MASK 0x00000001L
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L
+//CM3_CM_ICSC_CONTROL
+#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0
+#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L
+//CM3_CM_ICSC_C11_C12
+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0
+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10
+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L
+//CM3_CM_ICSC_C13_C14
+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0
+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10
+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L
+//CM3_CM_ICSC_C21_C22
+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0
+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10
+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L
+//CM3_CM_ICSC_C23_C24
+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0
+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10
+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L
+//CM3_CM_ICSC_C31_C32
+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0
+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10
+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L
+//CM3_CM_ICSC_C33_C34
+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0
+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10
+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L
+//CM3_CM_ICSC_B_C11_C12
+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0
+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10
+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L
+//CM3_CM_ICSC_B_C13_C14
+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0
+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10
+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L
+//CM3_CM_ICSC_B_C21_C22
+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0
+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10
+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L
+//CM3_CM_ICSC_B_C23_C24
+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0
+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10
+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L
+//CM3_CM_ICSC_B_C31_C32
+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0
+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10
+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L
+//CM3_CM_ICSC_B_C33_C34
+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0
+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10
+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL
+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_CONTROL
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L
+//CM3_CM_GAMUT_REMAP_C11_C12
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C13_C14
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C21_C22
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C23_C24
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C31_C32
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C33_C34
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C11_C12
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C13_C14
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C21_C22
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C23_C24
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C31_C32
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C33_C34
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L
+//CM3_CM_BIAS_CR_R
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL
+//CM3_CM_BIAS_Y_G_CB_B
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L
+//CM3_CM_DGAM_CONTROL
+#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0
+#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L
+//CM3_CM_DGAM_LUT_INDEX
+#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0
+#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL
+//CM3_CM_DGAM_LUT_DATA
+#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0
+#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM3_CM_DGAM_LUT_WRITE_EN_MASK
+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc
+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L
+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L
+//CM3_CM_DGAM_RAMA_START_CNTL_B
+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM3_CM_DGAM_RAMA_START_CNTL_G
+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM3_CM_DGAM_RAMA_START_CNTL_R
+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM3_CM_DGAM_RAMA_SLOPE_CNTL_B
+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM3_CM_DGAM_RAMA_SLOPE_CNTL_G
+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM3_CM_DGAM_RAMA_SLOPE_CNTL_R
+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM3_CM_DGAM_RAMA_END_CNTL1_B
+#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM3_CM_DGAM_RAMA_END_CNTL2_B
+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM3_CM_DGAM_RAMA_END_CNTL1_G
+#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM3_CM_DGAM_RAMA_END_CNTL2_G
+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM3_CM_DGAM_RAMA_END_CNTL1_R
+#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM3_CM_DGAM_RAMA_END_CNTL2_R
+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM3_CM_DGAM_RAMA_REGION_0_1
+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMA_REGION_2_3
+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMA_REGION_4_5
+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMA_REGION_6_7
+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMA_REGION_8_9
+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMA_REGION_10_11
+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMA_REGION_12_13
+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMA_REGION_14_15
+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMB_START_CNTL_B
+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM3_CM_DGAM_RAMB_START_CNTL_G
+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM3_CM_DGAM_RAMB_START_CNTL_R
+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM3_CM_DGAM_RAMB_SLOPE_CNTL_B
+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM3_CM_DGAM_RAMB_SLOPE_CNTL_G
+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM3_CM_DGAM_RAMB_SLOPE_CNTL_R
+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM3_CM_DGAM_RAMB_END_CNTL1_B
+#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM3_CM_DGAM_RAMB_END_CNTL2_B
+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM3_CM_DGAM_RAMB_END_CNTL1_G
+#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM3_CM_DGAM_RAMB_END_CNTL2_G
+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM3_CM_DGAM_RAMB_END_CNTL1_R
+#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM3_CM_DGAM_RAMB_END_CNTL2_R
+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM3_CM_DGAM_RAMB_REGION_0_1
+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMB_REGION_2_3
+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMB_REGION_4_5
+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMB_REGION_6_7
+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMB_REGION_8_9
+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMB_REGION_10_11
+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMB_REGION_12_13
+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_DGAM_RAMB_REGION_14_15
+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_CONTROL
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L
+//CM3_CM_BLNDGAM_LUT_INDEX
+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0
+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL
+//CM3_CM_BLNDGAM_LUT_DATA
+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0
+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK
+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_HDR_MULT_COEF
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL
+//CM3_CM_MEM_PWR_CTRL
+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0
+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6
+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L
+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L
+//CM3_CM_MEM_PWR_STATUS
+#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0
+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2
+#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL
+//CM3_CM_DEALPHA
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L
+//CM3_CM_COEF_FORMAT
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0
+#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L
+#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L
+//CM3_CM_SHAPER_CONTROL
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L
+//CM3_CM_SHAPER_OFFSET_R
+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0
+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL
+//CM3_CM_SHAPER_OFFSET_G
+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0
+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL
+//CM3_CM_SHAPER_OFFSET_B
+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0
+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL
+//CM3_CM_SHAPER_SCALE_R
+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0
+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL
+//CM3_CM_SHAPER_SCALE_G_B
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L
+//CM3_CM_SHAPER_LUT_INDEX
+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0
+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL
+//CM3_CM_SHAPER_LUT_DATA
+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0
+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL
+//CM3_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L
+//CM3_CM_SHAPER_RAMA_START_CNTL_B
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM3_CM_SHAPER_RAMA_START_CNTL_G
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM3_CM_SHAPER_RAMA_START_CNTL_R
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_B
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_G
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_R
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_REGION_0_1
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_2_3
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_4_5
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_6_7
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_8_9
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_10_11
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_12_13
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_14_15
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_16_17
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_18_19
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_20_21
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_22_23
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_24_25
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_26_27
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_28_29
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_30_31
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_32_33
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_B
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_G
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_R
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_B
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_G
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_R
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_REGION_0_1
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_2_3
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_4_5
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_6_7
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_8_9
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_10_11
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_12_13
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_14_15
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_16_17
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_18_19
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_20_21
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_22_23
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_24_25
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_26_27
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_28_29
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_30_31
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_32_33
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM3_CM_MEM_PWR_CTRL2
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L
+//CM3_CM_MEM_PWR_STATUS2
+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4
+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6
+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L
+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L
+//CM3_CM_3DLUT_MODE
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L
+//CM3_CM_3DLUT_INDEX
+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0
+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL
+//CM3_CM_3DLUT_DATA
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L
+//CM3_CM_3DLUT_DATA_30BIT
+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2
+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL
+//CM3_CM_3DLUT_READ_WRITE_CONTROL
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L
+//CM3_CM_3DLUT_OUT_NORM_FACTOR
+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0
+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL
+//CM3_CM_3DLUT_OUT_OFFSET_R
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L
+//CM3_CM_3DLUT_OUT_OFFSET_G
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L
+//CM3_CM_3DLUT_OUT_OFFSET_B
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
+//CM3_CM_TEST_DEBUG_INDEX
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//CM3_CM_TEST_DEBUG_DATA
+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON16_PERFCOUNTER_CNTL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_CNTL2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_STATE
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON16_PERFMON_CNTL
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON16_PERFMON_CNTL2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON16_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON16_PERFMON_CVALUE_LOW
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON16_PERFMON_HI
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON16_PERFMON_LOW
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+//MPCC0_MPCC_TOP_SEL
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL
+//MPCC0_MPCC_BOT_SEL
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL
+//MPCC0_MPCC_OPP_ID
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL
+//MPCC0_MPCC_CONTROL
+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18
+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L
+//MPCC0_MPCC_SM_CONTROL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//MPCC0_MPCC_UPDATE_LOCK_SEL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L
+//MPCC0_MPCC_TOP_GAIN
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_INSIDE
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL
+//MPCC0_MPCC_BG_R_CR
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL
+//MPCC0_MPCC_BG_G_Y
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL
+//MPCC0_MPCC_BG_B_CB
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL
+//MPCC0_MPCC_MEM_PWR_CTRL
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L
+//MPCC0_MPCC_STALL_STATUS
+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0
+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4
+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8
+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc
+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L
+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L
+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L
+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L
+//MPCC0_MPCC_STATUS
+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0
+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2
+#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d
+#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e
+#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f
+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L
+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L
+#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L
+#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L
+#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+//MPCC1_MPCC_TOP_SEL
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL
+//MPCC1_MPCC_BOT_SEL
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL
+//MPCC1_MPCC_OPP_ID
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL
+//MPCC1_MPCC_CONTROL
+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18
+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L
+//MPCC1_MPCC_SM_CONTROL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//MPCC1_MPCC_UPDATE_LOCK_SEL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L
+//MPCC1_MPCC_TOP_GAIN
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_INSIDE
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL
+//MPCC1_MPCC_BG_R_CR
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL
+//MPCC1_MPCC_BG_G_Y
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL
+//MPCC1_MPCC_BG_B_CB
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL
+//MPCC1_MPCC_MEM_PWR_CTRL
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L
+//MPCC1_MPCC_STALL_STATUS
+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0
+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4
+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8
+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc
+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L
+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L
+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L
+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L
+//MPCC1_MPCC_STATUS
+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0
+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2
+#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d
+#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e
+#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f
+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L
+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L
+#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L
+#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L
+#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+//MPCC2_MPCC_TOP_SEL
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL
+//MPCC2_MPCC_BOT_SEL
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL
+//MPCC2_MPCC_OPP_ID
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL
+//MPCC2_MPCC_CONTROL
+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18
+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L
+//MPCC2_MPCC_SM_CONTROL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//MPCC2_MPCC_UPDATE_LOCK_SEL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L
+//MPCC2_MPCC_TOP_GAIN
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_INSIDE
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL
+//MPCC2_MPCC_BG_R_CR
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL
+//MPCC2_MPCC_BG_G_Y
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL
+//MPCC2_MPCC_BG_B_CB
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL
+//MPCC2_MPCC_MEM_PWR_CTRL
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L
+//MPCC2_MPCC_STALL_STATUS
+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0
+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4
+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8
+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc
+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L
+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L
+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L
+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L
+//MPCC2_MPCC_STATUS
+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0
+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2
+#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d
+#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e
+#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f
+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L
+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L
+#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L
+#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L
+#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+//MPCC3_MPCC_TOP_SEL
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL
+//MPCC3_MPCC_BOT_SEL
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL
+//MPCC3_MPCC_OPP_ID
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL
+//MPCC3_MPCC_CONTROL
+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18
+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L
+//MPCC3_MPCC_SM_CONTROL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//MPCC3_MPCC_UPDATE_LOCK_SEL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L
+//MPCC3_MPCC_TOP_GAIN
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_INSIDE
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL
+//MPCC3_MPCC_BG_R_CR
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL
+//MPCC3_MPCC_BG_G_Y
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL
+//MPCC3_MPCC_BG_B_CB
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL
+//MPCC3_MPCC_MEM_PWR_CTRL
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L
+//MPCC3_MPCC_STALL_STATUS
+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0
+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4
+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8
+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc
+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L
+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L
+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L
+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L
+//MPCC3_MPCC_STATUS
+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0
+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2
+#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d
+#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e
+#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f
+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L
+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L
+#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L
+#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L
+#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc4_dispdec
+//MPCC4_MPCC_TOP_SEL
+#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0
+#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL
+//MPCC4_MPCC_BOT_SEL
+#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0
+#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL
+//MPCC4_MPCC_OPP_ID
+#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0
+#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL
+//MPCC4_MPCC_CONTROL
+#define MPCC4_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0
+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4
+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6
+#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7
+#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8
+#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb
+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10
+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18
+#define MPCC4_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L
+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L
+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L
+#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L
+#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L
+#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L
+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L
+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L
+//MPCC4_MPCC_SM_CONTROL
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//MPCC4_MPCC_UPDATE_LOCK_SEL
+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0
+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4
+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL
+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L
+//MPCC4_MPCC_TOP_GAIN
+#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0
+#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL
+//MPCC4_MPCC_BOT_GAIN_INSIDE
+#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0
+#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL
+//MPCC4_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0
+#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL
+//MPCC4_MPCC_BG_R_CR
+#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0
+#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL
+//MPCC4_MPCC_BG_G_Y
+#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0
+#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL
+//MPCC4_MPCC_BG_B_CB
+#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0
+#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL
+//MPCC4_MPCC_MEM_PWR_CTRL
+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0
+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2
+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4
+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L
+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L
+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L
+//MPCC4_MPCC_STALL_STATUS
+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0
+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4
+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8
+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc
+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L
+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L
+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L
+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L
+//MPCC4_MPCC_STATUS
+#define MPCC4_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0
+#define MPCC4_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1
+#define MPCC4_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2
+#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d
+#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e
+#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f
+#define MPCC4_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L
+#define MPCC4_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L
+#define MPCC4_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L
+#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L
+#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L
+#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc5_dispdec
+//MPCC5_MPCC_TOP_SEL
+#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0
+#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL
+//MPCC5_MPCC_BOT_SEL
+#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0
+#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL
+//MPCC5_MPCC_OPP_ID
+#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0
+#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL
+//MPCC5_MPCC_CONTROL
+#define MPCC5_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0
+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4
+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6
+#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7
+#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8
+#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb
+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10
+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18
+#define MPCC5_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L
+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L
+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L
+#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L
+#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L
+#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L
+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L
+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L
+//MPCC5_MPCC_SM_CONTROL
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//MPCC5_MPCC_UPDATE_LOCK_SEL
+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0
+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4
+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL
+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L
+//MPCC5_MPCC_TOP_GAIN
+#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0
+#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL
+//MPCC5_MPCC_BOT_GAIN_INSIDE
+#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0
+#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL
+//MPCC5_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0
+#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL
+//MPCC5_MPCC_BG_R_CR
+#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0
+#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL
+//MPCC5_MPCC_BG_G_Y
+#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0
+#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL
+//MPCC5_MPCC_BG_B_CB
+#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0
+#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL
+//MPCC5_MPCC_MEM_PWR_CTRL
+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0
+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2
+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4
+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L
+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L
+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L
+//MPCC5_MPCC_STALL_STATUS
+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0
+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4
+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8
+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc
+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L
+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L
+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L
+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L
+//MPCC5_MPCC_STATUS
+#define MPCC5_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0
+#define MPCC5_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1
+#define MPCC5_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2
+#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d
+#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e
+#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f
+#define MPCC5_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L
+#define MPCC5_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L
+#define MPCC5_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L
+#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L
+#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L
+#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc6_dispdec
+//MPCC6_MPCC_TOP_SEL
+#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0
+#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL
+//MPCC6_MPCC_BOT_SEL
+#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0
+#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL
+//MPCC6_MPCC_OPP_ID
+#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0
+#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL
+//MPCC6_MPCC_CONTROL
+#define MPCC6_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0
+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4
+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6
+#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7
+#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8
+#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb
+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10
+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18
+#define MPCC6_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L
+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L
+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L
+#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L
+#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L
+#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L
+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L
+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L
+//MPCC6_MPCC_SM_CONTROL
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//MPCC6_MPCC_UPDATE_LOCK_SEL
+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0
+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4
+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL
+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L
+//MPCC6_MPCC_TOP_GAIN
+#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0
+#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL
+//MPCC6_MPCC_BOT_GAIN_INSIDE
+#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0
+#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL
+//MPCC6_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0
+#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL
+//MPCC6_MPCC_BG_R_CR
+#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0
+#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL
+//MPCC6_MPCC_BG_G_Y
+#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0
+#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL
+//MPCC6_MPCC_BG_B_CB
+#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0
+#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL
+//MPCC6_MPCC_MEM_PWR_CTRL
+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0
+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2
+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4
+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L
+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L
+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L
+//MPCC6_MPCC_STALL_STATUS
+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0
+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4
+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8
+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc
+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L
+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L
+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L
+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L
+//MPCC6_MPCC_STATUS
+#define MPCC6_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0
+#define MPCC6_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1
+#define MPCC6_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2
+#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d
+#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e
+#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f
+#define MPCC6_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L
+#define MPCC6_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L
+#define MPCC6_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L
+#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L
+#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L
+#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc7_dispdec
+//MPCC7_MPCC_TOP_SEL
+#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0
+#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL
+//MPCC7_MPCC_BOT_SEL
+#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0
+#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL
+//MPCC7_MPCC_OPP_ID
+#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0
+#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL
+//MPCC7_MPCC_CONTROL
+#define MPCC7_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0
+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4
+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6
+#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7
+#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8
+#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb
+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10
+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18
+#define MPCC7_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L
+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L
+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L
+#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L
+#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L
+#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L
+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L
+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L
+//MPCC7_MPCC_SM_CONTROL
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L
+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L
+//MPCC7_MPCC_UPDATE_LOCK_SEL
+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0
+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4
+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL
+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L
+//MPCC7_MPCC_TOP_GAIN
+#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0
+#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL
+//MPCC7_MPCC_BOT_GAIN_INSIDE
+#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0
+#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL
+//MPCC7_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0
+#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL
+//MPCC7_MPCC_BG_R_CR
+#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0
+#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL
+//MPCC7_MPCC_BG_G_Y
+#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0
+#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL
+//MPCC7_MPCC_BG_B_CB
+#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0
+#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL
+//MPCC7_MPCC_MEM_PWR_CTRL
+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0
+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2
+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4
+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L
+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L
+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L
+//MPCC7_MPCC_STALL_STATUS
+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0
+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4
+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8
+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc
+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L
+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L
+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L
+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L
+//MPCC7_MPCC_STATUS
+#define MPCC7_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0
+#define MPCC7_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1
+#define MPCC7_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2
+#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d
+#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e
+#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f
+#define MPCC7_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L
+#define MPCC7_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L
+#define MPCC7_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L
+#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L
+#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L
+#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+//MPC_CLOCK_CONTROL
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x1
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0x4
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000002L
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x00000030L
+//MPC_SOFT_RESET
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3
+#define MPC_SOFT_RESET__MPCC4_SOFT_RESET__SHIFT 0x4
+#define MPC_SOFT_RESET__MPCC5_SOFT_RESET__SHIFT 0x5
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd
+#define MPC_SOFT_RESET__MPC_SFR4_SOFT_RESET__SHIFT 0xe
+#define MPC_SOFT_RESET__MPC_SFR5_SOFT_RESET__SHIFT 0xf
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17
+#define MPC_SOFT_RESET__MPC_SFT4_SOFT_RESET__SHIFT 0x18
+#define MPC_SOFT_RESET__MPC_SFT5_SOFT_RESET__SHIFT 0x19
+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L
+#define MPC_SOFT_RESET__MPCC4_SOFT_RESET_MASK 0x00000010L
+#define MPC_SOFT_RESET__MPCC5_SOFT_RESET_MASK 0x00000020L
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L
+#define MPC_SOFT_RESET__MPC_SFR4_SOFT_RESET_MASK 0x00004000L
+#define MPC_SOFT_RESET__MPC_SFR5_SOFT_RESET_MASK 0x00008000L
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L
+#define MPC_SOFT_RESET__MPC_SFT4_SOFT_RESET_MASK 0x01000000L
+#define MPC_SOFT_RESET__MPC_SFT5_SOFT_RESET_MASK 0x02000000L
+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L
+//MPC_CRC_CTRL
+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT 0x1e
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f
+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK 0x40000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L
+//MPC_CRC_SEL_CONTROL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L
+//MPC_CRC_RESULT_AR
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT 0x0
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT 0x10
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK 0x0000FFFFL
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK 0xFFFF0000L
+//MPC_CRC_RESULT_GB
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT 0x0
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT 0x10
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK 0x0000FFFFL
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK 0xFFFF0000L
+//MPC_CRC_RESULT_C
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT 0x0
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK 0x0000FFFFL
+//MPC_PERFMON_EVENT_CTRL
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT 0x0
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK 0x00000001L
+//MPC_BYPASS_BG_AR
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L
+//MPC_BYPASS_BG_GB
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L
+//MPC_STALL_GRACE_WINDOW
+#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD__SHIFT 0x0
+#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD_MASK 0x000000FFL
+//MPC_HOST_READ_CONTROL
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL
+//MPC_PENDING_TAKEN_STATUS_REG1
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT 0x0
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN__SHIFT 0x1
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT 0x2
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN__SHIFT 0x3
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT 0x4
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN__SHIFT 0x5
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT 0x6
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN__SHIFT 0x7
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT 0x8
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN__SHIFT 0x9
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT 0xa
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN__SHIFT 0xb
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT 0xc
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN__SHIFT 0xd
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT 0xe
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN__SHIFT 0xf
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT 0x10
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN__SHIFT 0x11
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT 0x12
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN__SHIFT 0x13
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT 0x14
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN__SHIFT 0x15
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT 0x16
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN__SHIFT 0x17
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_SURFACE_UPDATE_PENDING__SHIFT 0x18
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_SURFACE_UPDATE_TAKEN__SHIFT 0x19
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_CONFIG_UPDATE_PENDING__SHIFT 0x1a
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_CONFIG_UPDATE_TAKEN__SHIFT 0x1b
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_CURSOR_UPDATE_PENDING__SHIFT 0x1c
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_CURSOR_UPDATE_TAKEN__SHIFT 0x1d
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING_MASK 0x00000001L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN_MASK 0x00000002L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING_MASK 0x00000004L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN_MASK 0x00000008L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING_MASK 0x00000010L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN_MASK 0x00000020L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING_MASK 0x00000040L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN_MASK 0x00000080L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING_MASK 0x00000100L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN_MASK 0x00000200L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING_MASK 0x00000400L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN_MASK 0x00000800L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING_MASK 0x00001000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN_MASK 0x00002000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING_MASK 0x00004000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN_MASK 0x00008000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING_MASK 0x00010000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN_MASK 0x00020000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING_MASK 0x00040000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN_MASK 0x00080000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING_MASK 0x00100000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN_MASK 0x00200000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING_MASK 0x00400000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN_MASK 0x00800000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_SURFACE_UPDATE_PENDING_MASK 0x01000000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_SURFACE_UPDATE_TAKEN_MASK 0x02000000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_CONFIG_UPDATE_PENDING_MASK 0x04000000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_CONFIG_UPDATE_TAKEN_MASK 0x08000000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_CURSOR_UPDATE_PENDING_MASK 0x10000000L
+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP4_CURSOR_UPDATE_TAKEN_MASK 0x20000000L
+//MPC_PENDING_TAKEN_STATUS_REG2
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_SURFACE_UPDATE_PENDING__SHIFT 0x0
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_SURFACE_UPDATE_TAKEN__SHIFT 0x1
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_CONFIG_UPDATE_PENDING__SHIFT 0x2
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_CONFIG_UPDATE_TAKEN__SHIFT 0x3
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_CURSOR_UPDATE_PENDING__SHIFT 0x4
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_CURSOR_UPDATE_TAKEN__SHIFT 0x5
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_SURFACE_UPDATE_PENDING_MASK 0x00000001L
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_SURFACE_UPDATE_TAKEN_MASK 0x00000002L
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_CONFIG_UPDATE_PENDING_MASK 0x00000004L
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_CONFIG_UPDATE_TAKEN_MASK 0x00000008L
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_CURSOR_UPDATE_PENDING_MASK 0x00000010L
+#define MPC_PENDING_TAKEN_STATUS_REG2__IN_DPP5_CURSOR_UPDATE_TAKEN_MASK 0x00000020L
+//MPC_PENDING_TAKEN_STATUS_REG3
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT 0x0
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN__SHIFT 0x1
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT 0x2
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN__SHIFT 0x3
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT 0x4
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN__SHIFT 0x5
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT 0x6
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN__SHIFT 0x7
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP4_CONFIG_UPDATE_PENDING__SHIFT 0x8
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP4_CONFIG_UPDATE_TAKEN__SHIFT 0x9
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP5_CONFIG_UPDATE_PENDING__SHIFT 0xa
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP5_CONFIG_UPDATE_TAKEN__SHIFT 0xb
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING__SHIFT 0xc
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN__SHIFT 0xd
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING__SHIFT 0xe
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN__SHIFT 0xf
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING__SHIFT 0x10
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN__SHIFT 0x11
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING__SHIFT 0x12
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN__SHIFT 0x13
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC4_CONFIG_UPDATE_PENDING__SHIFT 0x14
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC4_CONFIG_UPDATE_TAKEN__SHIFT 0x15
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC5_CONFIG_UPDATE_PENDING__SHIFT 0x16
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC5_CONFIG_UPDATE_TAKEN__SHIFT 0x17
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK 0x00000001L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN_MASK 0x00000002L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK 0x00000004L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN_MASK 0x00000008L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK 0x00000010L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN_MASK 0x00000020L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK 0x00000040L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN_MASK 0x00000080L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP4_CONFIG_UPDATE_PENDING_MASK 0x00000100L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP4_CONFIG_UPDATE_TAKEN_MASK 0x00000200L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP5_CONFIG_UPDATE_PENDING_MASK 0x00000400L
+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP5_CONFIG_UPDATE_TAKEN_MASK 0x00000800L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING_MASK 0x00001000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN_MASK 0x00002000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING_MASK 0x00004000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN_MASK 0x00008000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING_MASK 0x00010000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN_MASK 0x00020000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING_MASK 0x00040000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN_MASK 0x00080000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC4_CONFIG_UPDATE_PENDING_MASK 0x00100000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC4_CONFIG_UPDATE_TAKEN_MASK 0x00200000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC5_CONFIG_UPDATE_PENDING_MASK 0x00400000L
+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC5_CONFIG_UPDATE_TAKEN_MASK 0x00800000L
+//MPC_UPDATE_ACK_REG5
+#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK__SHIFT 0x0
+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK__SHIFT 0x1
+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK__SHIFT 0x2
+#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK__SHIFT 0x3
+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK__SHIFT 0x4
+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK__SHIFT 0x5
+#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK__SHIFT 0x6
+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK__SHIFT 0x7
+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK__SHIFT 0x8
+#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK__SHIFT 0x9
+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK__SHIFT 0xa
+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK__SHIFT 0xb
+#define MPC_UPDATE_ACK_REG5__IN_DPP4_SURFACE_UPDATE_ACK__SHIFT 0xc
+#define MPC_UPDATE_ACK_REG5__IN_DPP4_CONFIG_UPDATE_ACK__SHIFT 0xd
+#define MPC_UPDATE_ACK_REG5__IN_DPP4_CURSOR_UPDATE_ACK__SHIFT 0xe
+#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK__SHIFT 0xf
+#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK__SHIFT 0x10
+#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK__SHIFT 0x11
+#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK__SHIFT 0x12
+#define MPC_UPDATE_ACK_REG5__MPCC4_CONFIG_UPDATE_ACK__SHIFT 0x13
+#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK__SHIFT 0x14
+#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK__SHIFT 0x15
+#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK__SHIFT 0x16
+#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK__SHIFT 0x17
+#define MPC_UPDATE_ACK_REG5__OUT_OPP4_CONFIG_UPDATE_ACK__SHIFT 0x18
+#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK_MASK 0x00000001L
+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK_MASK 0x00000002L
+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK_MASK 0x00000004L
+#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK_MASK 0x00000008L
+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK_MASK 0x00000010L
+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK_MASK 0x00000020L
+#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK_MASK 0x00000040L
+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK_MASK 0x00000080L
+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK_MASK 0x00000100L
+#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK_MASK 0x00000200L
+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK_MASK 0x00000400L
+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK_MASK 0x00000800L
+#define MPC_UPDATE_ACK_REG5__IN_DPP4_SURFACE_UPDATE_ACK_MASK 0x00001000L
+#define MPC_UPDATE_ACK_REG5__IN_DPP4_CONFIG_UPDATE_ACK_MASK 0x00002000L
+#define MPC_UPDATE_ACK_REG5__IN_DPP4_CURSOR_UPDATE_ACK_MASK 0x00004000L
+#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK_MASK 0x00008000L
+#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK_MASK 0x00010000L
+#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK_MASK 0x00020000L
+#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK_MASK 0x00040000L
+#define MPC_UPDATE_ACK_REG5__MPCC4_CONFIG_UPDATE_ACK_MASK 0x00080000L
+#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK_MASK 0x00100000L
+#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK_MASK 0x00200000L
+#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK_MASK 0x00400000L
+#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK_MASK 0x00800000L
+#define MPC_UPDATE_ACK_REG5__OUT_OPP4_CONFIG_UPDATE_ACK_MASK 0x01000000L
+//MPC_UPDATE_ACK_REG6
+#define MPC_UPDATE_ACK_REG6__IN_DPP5_SURFACE_UPDATE_ACK__SHIFT 0x0
+#define MPC_UPDATE_ACK_REG6__IN_DPP5_CONFIG_UPDATE_ACK__SHIFT 0x1
+#define MPC_UPDATE_ACK_REG6__IN_DPP5_CURSOR_UPDATE_ACK__SHIFT 0x2
+#define MPC_UPDATE_ACK_REG6__MPCC5_CONFIG_UPDATE_ACK__SHIFT 0x9
+#define MPC_UPDATE_ACK_REG6__OUT_OPP5_CONFIG_UPDATE_ACK__SHIFT 0xc
+#define MPC_UPDATE_ACK_REG6__IN_DPP5_SURFACE_UPDATE_ACK_MASK 0x00000001L
+#define MPC_UPDATE_ACK_REG6__IN_DPP5_CONFIG_UPDATE_ACK_MASK 0x00000002L
+#define MPC_UPDATE_ACK_REG6__IN_DPP5_CURSOR_UPDATE_ACK_MASK 0x00000004L
+#define MPC_UPDATE_ACK_REG6__MPCC5_CONFIG_UPDATE_ACK_MASK 0x00000200L
+#define MPC_UPDATE_ACK_REG6__OUT_OPP5_CONFIG_UPDATE_ACK_MASK 0x00001000L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_VUPDATE_LOCK_SET0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CFG_VUPDATE_LOCK_SET0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CUR_VUPDATE_LOCK_SET0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET1
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET1
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_VUPDATE_LOCK_SET1
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CFG_VUPDATE_LOCK_SET1
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CUR_VUPDATE_LOCK_SET1
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET2
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET2
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_VUPDATE_LOCK_SET2
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CFG_VUPDATE_LOCK_SET2
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CUR_VUPDATE_LOCK_SET2
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET3
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET3
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_VUPDATE_LOCK_SET3
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CFG_VUPDATE_LOCK_SET3
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CUR_VUPDATE_LOCK_SET3
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET4
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET4__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET4__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET4
+#define ADR_CFG_VUPDATE_LOCK_SET4__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_VUPDATE_LOCK_SET4__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_VUPDATE_LOCK_SET4
+#define ADR_VUPDATE_LOCK_SET4__ADR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_VUPDATE_LOCK_SET4__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CFG_VUPDATE_LOCK_SET4
+#define CFG_VUPDATE_LOCK_SET4__CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CFG_VUPDATE_LOCK_SET4__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CUR_VUPDATE_LOCK_SET4
+#define CUR_VUPDATE_LOCK_SET4__CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CUR_VUPDATE_LOCK_SET4__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET5
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET5__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET5__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET5
+#define ADR_CFG_VUPDATE_LOCK_SET5__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_CFG_VUPDATE_LOCK_SET5__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//ADR_VUPDATE_LOCK_SET5
+#define ADR_VUPDATE_LOCK_SET5__ADR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define ADR_VUPDATE_LOCK_SET5__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CFG_VUPDATE_LOCK_SET5
+#define CFG_VUPDATE_LOCK_SET5__CFG_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CFG_VUPDATE_LOCK_SET5__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L
+//CUR_VUPDATE_LOCK_SET5
+#define CUR_VUPDATE_LOCK_SET5__CUR_VUPDATE_LOCK_SET__SHIFT 0x0
+#define CUR_VUPDATE_LOCK_SET5__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L
+//MPC_OUT0_MUX
+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0
+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL
+//MPC_OUT0_DENORM_CONTROL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L
+//MPC_OUT0_DENORM_CLAMP_G_Y
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L
+//MPC_OUT0_DENORM_CLAMP_B_CB
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L
+//MPC_OUT1_MUX
+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0
+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL
+//MPC_OUT1_DENORM_CONTROL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L
+//MPC_OUT1_DENORM_CLAMP_G_Y
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L
+//MPC_OUT1_DENORM_CLAMP_B_CB
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L
+//MPC_OUT2_MUX
+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0
+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL
+//MPC_OUT2_DENORM_CONTROL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L
+//MPC_OUT2_DENORM_CLAMP_G_Y
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L
+//MPC_OUT2_DENORM_CLAMP_B_CB
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L
+//MPC_OUT3_MUX
+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0
+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL
+//MPC_OUT3_DENORM_CONTROL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L
+//MPC_OUT3_DENORM_CLAMP_G_Y
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L
+//MPC_OUT3_DENORM_CLAMP_B_CB
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L
+//MPC_OUT4_MUX
+#define MPC_OUT4_MUX__MPC_OUT_MUX__SHIFT 0x0
+#define MPC_OUT4_MUX__MPC_OUT_MUX_MASK 0x0000000FL
+//MPC_OUT4_DENORM_CONTROL
+#define MPC_OUT4_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0
+#define MPC_OUT4_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc
+#define MPC_OUT4_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18
+#define MPC_OUT4_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL
+#define MPC_OUT4_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L
+#define MPC_OUT4_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L
+//MPC_OUT4_DENORM_CLAMP_G_Y
+#define MPC_OUT4_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0
+#define MPC_OUT4_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc
+#define MPC_OUT4_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL
+#define MPC_OUT4_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L
+//MPC_OUT4_DENORM_CLAMP_B_CB
+#define MPC_OUT4_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0
+#define MPC_OUT4_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc
+#define MPC_OUT4_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL
+#define MPC_OUT4_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L
+//MPC_OUT5_MUX
+#define MPC_OUT5_MUX__MPC_OUT_MUX__SHIFT 0x0
+#define MPC_OUT5_MUX__MPC_OUT_MUX_MASK 0x0000000FL
+//MPC_OUT5_DENORM_CONTROL
+#define MPC_OUT5_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0
+#define MPC_OUT5_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc
+#define MPC_OUT5_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18
+#define MPC_OUT5_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL
+#define MPC_OUT5_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L
+#define MPC_OUT5_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L
+//MPC_OUT5_DENORM_CLAMP_G_Y
+#define MPC_OUT5_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0
+#define MPC_OUT5_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc
+#define MPC_OUT5_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL
+#define MPC_OUT5_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L
+//MPC_OUT5_DENORM_CLAMP_B_CB
+#define MPC_OUT5_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0
+#define MPC_OUT5_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc
+#define MPC_OUT5_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL
+#define MPC_OUT5_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+//MPCC_OGAM0_MPCC_OGAM_MODE
+#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L
+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3
+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4
+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+//MPCC_OGAM1_MPCC_OGAM_MODE
+#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L
+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3
+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4
+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+//MPCC_OGAM2_MPCC_OGAM_MODE
+#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L
+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3
+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4
+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+//MPCC_OGAM3_MPCC_OGAM_MODE
+#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L
+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3
+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4
+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
+//MPCC_OGAM4_MPCC_OGAM_MODE
+#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L
+//MPCC_OGAM4_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL
+//MPCC_OGAM4_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL
+//MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL
+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3
+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4
+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L
+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec
+//MPCC_OGAM5_MPCC_OGAM_MODE
+#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L
+//MPCC_OGAM5_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL
+//MPCC_OGAM5_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL
+//MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL
+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3
+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4
+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L
+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec
+//MPCC_OGAM6_MPCC_OGAM_MODE
+#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L
+//MPCC_OGAM6_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL
+//MPCC_OGAM6_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL
+//MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL
+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3
+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4
+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L
+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec
+//MPCC_OGAM7_MPCC_OGAM_MODE
+#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L
+//MPCC_OGAM7_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL
+//MPCC_OGAM7_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL
+//MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL
+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3
+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4
+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L
+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+//MPC_OUT_CSC_COEF_FORMAT
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT 0x0
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT 0x1
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT 0x2
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT 0x3
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC4_COEF_FORMAT__SHIFT 0x4
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC5_COEF_FORMAT__SHIFT 0x5
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK 0x00000001L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK 0x00000002L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK 0x00000004L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK 0x00000008L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC4_COEF_FORMAT_MASK 0x00000010L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC5_COEF_FORMAT_MASK 0x00000020L
+//MPC_OUT0_CSC_MODE
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L
+//MPC_OUT0_CSC_C11_C12_A
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_A
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_A
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_A
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_A
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_A
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C11_C12_B
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_B
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_B
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_B
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_B
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_B
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_MODE
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L
+//MPC_OUT1_CSC_C11_C12_A
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_A
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_A
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_A
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_A
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_A
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C11_C12_B
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_B
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_B
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_B
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_B
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_B
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_MODE
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L
+//MPC_OUT2_CSC_C11_C12_A
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_A
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_A
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_A
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_A
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_A
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C11_C12_B
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_B
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_B
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_B
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_B
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_B
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_MODE
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L
+//MPC_OUT3_CSC_C11_C12_A
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_A
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_A
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_A
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_A
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_A
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C11_C12_B
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_B
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_B
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_B
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_B
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_B
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_MODE
+#define MPC_OUT4_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0
+#define MPC_OUT4_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L
+//MPC_OUT4_CSC_C11_C12_A
+#define MPC_OUT4_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0
+#define MPC_OUT4_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10
+#define MPC_OUT4_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C13_C14_A
+#define MPC_OUT4_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0
+#define MPC_OUT4_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10
+#define MPC_OUT4_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C21_C22_A
+#define MPC_OUT4_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0
+#define MPC_OUT4_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10
+#define MPC_OUT4_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C23_C24_A
+#define MPC_OUT4_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0
+#define MPC_OUT4_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10
+#define MPC_OUT4_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C31_C32_A
+#define MPC_OUT4_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0
+#define MPC_OUT4_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10
+#define MPC_OUT4_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C33_C34_A
+#define MPC_OUT4_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0
+#define MPC_OUT4_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10
+#define MPC_OUT4_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C11_C12_B
+#define MPC_OUT4_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0
+#define MPC_OUT4_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10
+#define MPC_OUT4_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C13_C14_B
+#define MPC_OUT4_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0
+#define MPC_OUT4_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10
+#define MPC_OUT4_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C21_C22_B
+#define MPC_OUT4_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0
+#define MPC_OUT4_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10
+#define MPC_OUT4_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C23_C24_B
+#define MPC_OUT4_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0
+#define MPC_OUT4_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10
+#define MPC_OUT4_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C31_C32_B
+#define MPC_OUT4_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0
+#define MPC_OUT4_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10
+#define MPC_OUT4_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L
+//MPC_OUT4_CSC_C33_C34_B
+#define MPC_OUT4_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0
+#define MPC_OUT4_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10
+#define MPC_OUT4_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL
+#define MPC_OUT4_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_MODE
+#define MPC_OUT5_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0
+#define MPC_OUT5_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L
+//MPC_OUT5_CSC_C11_C12_A
+#define MPC_OUT5_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0
+#define MPC_OUT5_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10
+#define MPC_OUT5_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C13_C14_A
+#define MPC_OUT5_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0
+#define MPC_OUT5_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10
+#define MPC_OUT5_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C21_C22_A
+#define MPC_OUT5_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0
+#define MPC_OUT5_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10
+#define MPC_OUT5_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C23_C24_A
+#define MPC_OUT5_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0
+#define MPC_OUT5_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10
+#define MPC_OUT5_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C31_C32_A
+#define MPC_OUT5_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0
+#define MPC_OUT5_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10
+#define MPC_OUT5_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C33_C34_A
+#define MPC_OUT5_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0
+#define MPC_OUT5_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10
+#define MPC_OUT5_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C11_C12_B
+#define MPC_OUT5_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0
+#define MPC_OUT5_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10
+#define MPC_OUT5_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C13_C14_B
+#define MPC_OUT5_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0
+#define MPC_OUT5_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10
+#define MPC_OUT5_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C21_C22_B
+#define MPC_OUT5_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0
+#define MPC_OUT5_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10
+#define MPC_OUT5_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C23_C24_B
+#define MPC_OUT5_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0
+#define MPC_OUT5_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10
+#define MPC_OUT5_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C31_C32_B
+#define MPC_OUT5_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0
+#define MPC_OUT5_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10
+#define MPC_OUT5_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L
+//MPC_OUT5_CSC_C33_C34_B
+#define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0
+#define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10
+#define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL
+#define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON17_PERFCOUNTER_CNTL
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON17_PERFCOUNTER_CNTL2
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON17_PERFCOUNTER_STATE
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON17_PERFMON_CNTL
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON17_PERFMON_CNTL2
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON17_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON17_PERFMON_CVALUE_LOW
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON17_PERFMON_HI
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON17_PERFMON_LOW
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+//BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL
+//BL1_PWM_USER_LEVEL
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL
+//BL1_PWM_TARGET_ABM_LEVEL
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL
+//BL1_PWM_CURRENT_ABM_LEVEL
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL
+//BL1_PWM_FINAL_DUTY_CYCLE
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL
+//BL1_PWM_MINIMUM_DUTY_CYCLE
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL
+//BL1_PWM_ABM_CNTL
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L
+//BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//BL1_PWM_GRP2_REG_LOCK
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
+//DC_ABM1_CNTL
+#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
+#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
+#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L
+#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L
+//DC_ABM1_IPCSC_COEFF_SEL
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_0
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_1
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_2
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_3
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_OFFSET_SLOPE_4
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_THRES_12
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_THRES_34
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L
+//DC_ABM1_ACE_CNTL_MISC
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L
+//DC_ABM1_HGLS_REG_READ_PROGRESS
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L
+//DC_ABM1_HG_MISC_CTRL
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_LS_SUM_OF_LUMA
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL
+//DC_ABM1_LS_MIN_MAX_LUMA
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L
+//DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L
+//DC_ABM1_LS_PIXEL_COUNT
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L
+//DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL
+//DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL
+//DC_ABM1_HG_SAMPLE_RATE
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_LS_SAMPLE_RATE
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
+//DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_1
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_2
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_3
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_4
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_5
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_6
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_7
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_8
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_9
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_10
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_11
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_12
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_13
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_14
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_15
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_16
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_17
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_18
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_19
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_20
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_21
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_22
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_23
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL
+//DC_ABM1_HG_RESULT_24
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL
+//DC_ABM1_BL_MASTER_LOCK
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+//FMT0_FMT_CLAMP_COMPONENT_R
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_G
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_B
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT0_FMT_DYNAMIC_EXP_CNTL
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT0_FMT_CONTROL
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L
+//FMT0_FMT_BIT_DEPTH_CONTROL
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT0_FMT_DITHER_RAND_R_SEED
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_G_SEED
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_B_SEED
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT0_FMT_CLAMP_CNTL
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT0_FMT_MAP420_MEMORY_CONTROL
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L
+//FMT0_FMT_422_CONTROL
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+//DPG0_DPG_CONTROL
+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0
+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT 0x4
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc
+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT 0x10
+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT 0x14
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18
+#define DPG0_DPG_CONTROL__DPG_EN_MASK 0x00000001L
+#define DPG0_DPG_CONTROL__DPG_MODE_MASK 0x00000070L
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L
+#define DPG0_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L
+#define DPG0_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L
+//DPG0_DPG_RAMP_CONTROL
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L
+//DPG0_DPG_DIMENSIONS
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L
+//DPG0_DPG_COLOUR_R_CR
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L
+//DPG0_DPG_COLOUR_G_Y
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L
+//DPG0_DPG_COLOUR_B_CB
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L
+//DPG0_DPG_OFFSET_SEGMENT
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L
+//DPG0_DPG_STATUS
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+//OPPBUF0_OPPBUF_CONTROL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L
+//OPPBUF0_OPPBUF_CONTROL1
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+//OPP_PIPE0_OPP_PIPE_CONTROL
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+//FMT1_FMT_CLAMP_COMPONENT_R
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_G
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_B
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT1_FMT_DYNAMIC_EXP_CNTL
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT1_FMT_CONTROL
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L
+//FMT1_FMT_BIT_DEPTH_CONTROL
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT1_FMT_DITHER_RAND_R_SEED
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_G_SEED
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_B_SEED
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT1_FMT_CLAMP_CNTL
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT1_FMT_MAP420_MEMORY_CONTROL
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L
+//FMT1_FMT_422_CONTROL
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+//DPG1_DPG_CONTROL
+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT 0x0
+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT 0x4
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc
+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT 0x10
+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT 0x14
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18
+#define DPG1_DPG_CONTROL__DPG_EN_MASK 0x00000001L
+#define DPG1_DPG_CONTROL__DPG_MODE_MASK 0x00000070L
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L
+#define DPG1_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L
+#define DPG1_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L
+//DPG1_DPG_RAMP_CONTROL
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L
+//DPG1_DPG_DIMENSIONS
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L
+//DPG1_DPG_COLOUR_R_CR
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L
+//DPG1_DPG_COLOUR_G_Y
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L
+//DPG1_DPG_COLOUR_B_CB
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L
+//DPG1_DPG_OFFSET_SEGMENT
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L
+//DPG1_DPG_STATUS
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+//OPPBUF1_OPPBUF_CONTROL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L
+//OPPBUF1_OPPBUF_CONTROL1
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+//OPP_PIPE1_OPP_PIPE_CONTROL
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+//FMT2_FMT_CLAMP_COMPONENT_R
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_G
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_B
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT2_FMT_DYNAMIC_EXP_CNTL
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT2_FMT_CONTROL
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L
+//FMT2_FMT_BIT_DEPTH_CONTROL
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT2_FMT_DITHER_RAND_R_SEED
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_G_SEED
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_B_SEED
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT2_FMT_CLAMP_CNTL
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT2_FMT_MAP420_MEMORY_CONTROL
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L
+//FMT2_FMT_422_CONTROL
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+//DPG2_DPG_CONTROL
+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT 0x0
+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT 0x4
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc
+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT 0x10
+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT 0x14
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18
+#define DPG2_DPG_CONTROL__DPG_EN_MASK 0x00000001L
+#define DPG2_DPG_CONTROL__DPG_MODE_MASK 0x00000070L
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L
+#define DPG2_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L
+#define DPG2_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L
+//DPG2_DPG_RAMP_CONTROL
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L
+//DPG2_DPG_DIMENSIONS
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L
+//DPG2_DPG_COLOUR_R_CR
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L
+//DPG2_DPG_COLOUR_G_Y
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L
+//DPG2_DPG_COLOUR_B_CB
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L
+//DPG2_DPG_OFFSET_SEGMENT
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L
+//DPG2_DPG_STATUS
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+//OPPBUF2_OPPBUF_CONTROL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L
+//OPPBUF2_OPPBUF_CONTROL1
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+//OPP_PIPE2_OPP_PIPE_CONTROL
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+//FMT3_FMT_CLAMP_COMPONENT_R
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_G
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_B
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT3_FMT_DYNAMIC_EXP_CNTL
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT3_FMT_CONTROL
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L
+//FMT3_FMT_BIT_DEPTH_CONTROL
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT3_FMT_DITHER_RAND_R_SEED
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_G_SEED
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_B_SEED
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT3_FMT_CLAMP_CNTL
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT3_FMT_MAP420_MEMORY_CONTROL
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L
+//FMT3_FMT_422_CONTROL
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+//DPG3_DPG_CONTROL
+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT 0x0
+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT 0x4
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc
+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT 0x10
+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT 0x14
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18
+#define DPG3_DPG_CONTROL__DPG_EN_MASK 0x00000001L
+#define DPG3_DPG_CONTROL__DPG_MODE_MASK 0x00000070L
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L
+#define DPG3_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L
+#define DPG3_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L
+//DPG3_DPG_RAMP_CONTROL
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L
+//DPG3_DPG_DIMENSIONS
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L
+//DPG3_DPG_COLOUR_R_CR
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L
+//DPG3_DPG_COLOUR_G_Y
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L
+//DPG3_DPG_COLOUR_B_CB
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L
+//DPG3_DPG_OFFSET_SEGMENT
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L
+//DPG3_DPG_STATUS
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+//OPPBUF3_OPPBUF_CONTROL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L
+//OPPBUF3_OPPBUF_CONTROL1
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+//OPP_PIPE3_OPP_PIPE_CONTROL
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_fmt4_dispdec
+//FMT4_FMT_CLAMP_COMPONENT_R
+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT4_FMT_CLAMP_COMPONENT_G
+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT4_FMT_CLAMP_COMPONENT_B
+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT4_FMT_DYNAMIC_EXP_CNTL
+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT4_FMT_CONTROL
+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4
+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c
+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L
+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L
+//FMT4_FMT_BIT_DEPTH_CONTROL
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT4_FMT_DITHER_RAND_R_SEED
+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT4_FMT_DITHER_RAND_G_SEED
+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT4_FMT_DITHER_RAND_B_SEED
+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT4_FMT_CLAMP_CNTL
+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT4_FMT_MAP420_MEMORY_CONTROL
+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0
+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4
+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8
+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc
+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L
+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L
+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L
+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L
+//FMT4_FMT_422_CONTROL
+#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0
+#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg4_dispdec
+//DPG4_DPG_CONTROL
+#define DPG4_DPG_CONTROL__DPG_EN__SHIFT 0x0
+#define DPG4_DPG_CONTROL__DPG_MODE__SHIFT 0x4
+#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8
+#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc
+#define DPG4_DPG_CONTROL__DPG_VRES__SHIFT 0x10
+#define DPG4_DPG_CONTROL__DPG_HRES__SHIFT 0x14
+#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18
+#define DPG4_DPG_CONTROL__DPG_EN_MASK 0x00000001L
+#define DPG4_DPG_CONTROL__DPG_MODE_MASK 0x00000070L
+#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L
+#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L
+#define DPG4_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L
+#define DPG4_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L
+#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L
+//DPG4_DPG_RAMP_CONTROL
+#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0
+#define DPG4_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18
+#define DPG4_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c
+#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL
+#define DPG4_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L
+#define DPG4_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L
+//DPG4_DPG_DIMENSIONS
+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0
+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10
+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL
+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L
+//DPG4_DPG_COLOUR_R_CR
+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0
+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10
+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL
+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L
+//DPG4_DPG_COLOUR_G_Y
+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0
+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10
+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL
+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L
+//DPG4_DPG_COLOUR_B_CB
+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0
+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10
+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL
+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L
+//DPG4_DPG_OFFSET_SEGMENT
+#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0
+#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10
+#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL
+#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L
+//DPG4_DPG_STATUS
+#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0
+#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf4_dispdec
+//OPPBUF4_OPPBUF_CONTROL
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L
+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L
+//OPPBUF4_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L
+//OPPBUF4_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL
+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L
+//OPPBUF4_OPPBUF_CONTROL1
+#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0
+#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe4_dispdec
+//OPP_PIPE4_OPP_PIPE_CONTROL
+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0
+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1
+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4
+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L
+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L
+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
+//OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L
+//OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL
+//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L
+//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L
+//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0
+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_fmt5_dispdec
+//FMT5_FMT_CLAMP_COMPONENT_R
+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL
+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L
+//FMT5_FMT_CLAMP_COMPONENT_G
+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL
+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L
+//FMT5_FMT_CLAMP_COMPONENT_B
+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL
+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L
+//FMT5_FMT_DYNAMIC_EXP_CNTL
+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
+//FMT5_FMT_CONTROL
+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4
+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12
+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14
+#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15
+#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c
+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
+#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L
+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L
+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L
+#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L
+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L
+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L
+#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L
+#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L
+//FMT5_FMT_BIT_DEPTH_CONTROL
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L
+//FMT5_FMT_DITHER_RAND_R_SEED
+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL
+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L
+//FMT5_FMT_DITHER_RAND_G_SEED
+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL
+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L
+//FMT5_FMT_DITHER_RAND_B_SEED
+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL
+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L
+//FMT5_FMT_CLAMP_CNTL
+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
+//FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0
+#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL
+//FMT5_FMT_MAP420_MEMORY_CONTROL
+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0
+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4
+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8
+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc
+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L
+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L
+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L
+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L
+//FMT5_FMT_422_CONTROL
+#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0
+#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg5_dispdec
+//DPG5_DPG_CONTROL
+#define DPG5_DPG_CONTROL__DPG_EN__SHIFT 0x0
+#define DPG5_DPG_CONTROL__DPG_MODE__SHIFT 0x4
+#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8
+#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc
+#define DPG5_DPG_CONTROL__DPG_VRES__SHIFT 0x10
+#define DPG5_DPG_CONTROL__DPG_HRES__SHIFT 0x14
+#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18
+#define DPG5_DPG_CONTROL__DPG_EN_MASK 0x00000001L
+#define DPG5_DPG_CONTROL__DPG_MODE_MASK 0x00000070L
+#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L
+#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L
+#define DPG5_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L
+#define DPG5_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L
+#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L
+//DPG5_DPG_RAMP_CONTROL
+#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0
+#define DPG5_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18
+#define DPG5_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c
+#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL
+#define DPG5_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L
+#define DPG5_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L
+//DPG5_DPG_DIMENSIONS
+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0
+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10
+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL
+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L
+//DPG5_DPG_COLOUR_R_CR
+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0
+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10
+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL
+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L
+//DPG5_DPG_COLOUR_G_Y
+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0
+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10
+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL
+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L
+//DPG5_DPG_COLOUR_B_CB
+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0
+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10
+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL
+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L
+//DPG5_DPG_OFFSET_SEGMENT
+#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0
+#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10
+#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL
+#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L
+//DPG5_DPG_STATUS
+#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0
+#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf5_dispdec
+//OPPBUF5_OPPBUF_CONTROL
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L
+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L
+//OPPBUF5_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L
+//OPPBUF5_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL
+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L
+//OPPBUF5_OPPBUF_CONTROL1
+#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0
+#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe5_dispdec
+//OPP_PIPE5_OPP_PIPE_CONTROL
+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0
+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1
+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4
+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L
+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L
+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
+//OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L
+//OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL
+//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L
+//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L
+//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0
+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+//OPP_TOP_CLK_CONTROL
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm3_dispdec
+//DSCRM3_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm4_dispdec
+//DSCRM4_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0
+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4
+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8
+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc
+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L
+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L
+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L
+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm5_dispdec
+//DSCRM5_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0
+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4
+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8
+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc
+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L
+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L
+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L
+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON18_PERFCOUNTER_CNTL
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON18_PERFCOUNTER_CNTL2
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON18_PERFCOUNTER_STATE
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON18_PERFMON_CNTL
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON18_PERFMON_CNTL2
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON18_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON18_PERFMON_CVALUE_LOW
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON18_PERFMON_HI
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON18_PERFMON_LOW
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+//ODM0_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L
+//ODM0_OPTC_DATA_SOURCE_SELECT
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L
+//ODM0_OPTC_DATA_FORMAT_CONTROL
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L
+//ODM0_OPTC_BYTES_PER_PIXEL
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//ODM0_OPTC_WIDTH_CONTROL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//ODM0_OPTC_INPUT_CLOCK_CONTROL
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L
+//ODM0_OPTC_MEMORY_CONFIG
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL
+//ODM0_OPTC_INPUT_SPARE_REGISTER
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+//ODM1_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L
+//ODM1_OPTC_DATA_SOURCE_SELECT
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L
+//ODM1_OPTC_DATA_FORMAT_CONTROL
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L
+//ODM1_OPTC_BYTES_PER_PIXEL
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//ODM1_OPTC_WIDTH_CONTROL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//ODM1_OPTC_INPUT_CLOCK_CONTROL
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L
+//ODM1_OPTC_MEMORY_CONFIG
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL
+//ODM1_OPTC_INPUT_SPARE_REGISTER
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+//ODM2_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L
+//ODM2_OPTC_DATA_SOURCE_SELECT
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L
+//ODM2_OPTC_DATA_FORMAT_CONTROL
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L
+//ODM2_OPTC_BYTES_PER_PIXEL
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//ODM2_OPTC_WIDTH_CONTROL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//ODM2_OPTC_INPUT_CLOCK_CONTROL
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L
+//ODM2_OPTC_MEMORY_CONFIG
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL
+//ODM2_OPTC_INPUT_SPARE_REGISTER
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+//ODM3_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L
+//ODM3_OPTC_DATA_SOURCE_SELECT
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L
+//ODM3_OPTC_DATA_FORMAT_CONTROL
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L
+//ODM3_OPTC_BYTES_PER_PIXEL
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//ODM3_OPTC_WIDTH_CONTROL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//ODM3_OPTC_INPUT_CLOCK_CONTROL
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L
+//ODM3_OPTC_MEMORY_CONFIG
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL
+//ODM3_OPTC_INPUT_SPARE_REGISTER
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm4_dispdec
+//ODM4_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L
+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L
+//ODM4_OPTC_DATA_SOURCE_SELECT
+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0
+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2
+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8
+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc
+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L
+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL
+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L
+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L
+//ODM4_OPTC_DATA_FORMAT_CONTROL
+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0
+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4
+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L
+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L
+//ODM4_OPTC_BYTES_PER_PIXEL
+#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//ODM4_OPTC_WIDTH_CONTROL
+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0
+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10
+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL
+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//ODM4_OPTC_INPUT_CLOCK_CONTROL
+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0
+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1
+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2
+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L
+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L
+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L
+//ODM4_OPTC_MEMORY_CONFIG
+#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0
+#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL
+//ODM4_OPTC_INPUT_SPARE_REGISTER
+#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
+#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm5_dispdec
+//ODM5_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L
+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L
+//ODM5_OPTC_DATA_SOURCE_SELECT
+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0
+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2
+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8
+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc
+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L
+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL
+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L
+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L
+//ODM5_OPTC_DATA_FORMAT_CONTROL
+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0
+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4
+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L
+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L
+//ODM5_OPTC_BYTES_PER_PIXEL
+#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//ODM5_OPTC_WIDTH_CONTROL
+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0
+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10
+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL
+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//ODM5_OPTC_INPUT_CLOCK_CONTROL
+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0
+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1
+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2
+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L
+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L
+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L
+//ODM5_OPTC_MEMORY_CONFIG
+#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0
+#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL
+//ODM5_OPTC_INPUT_SPARE_REGISTER
+#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0
+#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+//OTG0_OTG_H_TOTAL
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL
+//OTG0_OTG_H_BLANK_START_END
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L
+//OTG0_OTG_H_SYNC_A
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L
+//OTG0_OTG_H_SYNC_A_CNTL
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//OTG0_OTG_H_TIMING_CNTL
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L
+//OTG0_OTG_V_TOTAL
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL
+//OTG0_OTG_V_TOTAL_MIN
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL
+//OTG0_OTG_V_TOTAL_MAX
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL
+//OTG0_OTG_V_TOTAL_MID
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL
+//OTG0_OTG_V_TOTAL_CONTROL
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//OTG0_OTG_V_TOTAL_INT_STATUS
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//OTG0_OTG_VSYNC_NOM_INT_STATUS
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//OTG0_OTG_V_BLANK_START_END
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L
+//OTG0_OTG_V_SYNC_A
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L
+//OTG0_OTG_V_SYNC_A_CNTL
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L
+//OTG0_OTG_TRIGA_CNTL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L
+//OTG0_OTG_TRIGA_MANUAL_TRIG
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//OTG0_OTG_TRIGB_CNTL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L
+//OTG0_OTG_TRIGB_MANUAL_TRIG
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//OTG0_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//OTG0_OTG_FLOW_CONTROL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//OTG0_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//OTG0_OTG_CONTROL
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0
+#define OTG0_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT 0x4
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L
+#define OTG0_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK 0x00000010L
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L
+#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//OTG0_OTG_BLANK_CONTROL
+#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0
+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8
+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10
+#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L
+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L
+//OTG0_OTG_PIPE_ABORT_CONTROL
+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0
+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8
+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L
+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L
+//OTG0_OTG_INTERLACE_CONTROL
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//OTG0_OTG_INTERLACE_STATUS
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//OTG0_OTG_PIXEL_DATA_READBACK0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L
+//OTG0_OTG_PIXEL_DATA_READBACK1
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL
+//OTG0_OTG_STATUS
+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2
+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12
+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L
+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L
+//OTG0_OTG_STATUS_POSITION
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG0_OTG_NOM_VERT_POSITION
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL
+//OTG0_OTG_STATUS_FRAME_COUNT
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG0_OTG_STATUS_VF_COUNT
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL
+//OTG0_OTG_STATUS_HV_COUNT
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL
+//OTG0_OTG_COUNT_CONTROL
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//OTG0_OTG_COUNT_RESET
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L
+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//OTG0_OTG_VERT_SYNC_CONTROL
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//OTG0_OTG_STEREO_STATUS
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L
+//OTG0_OTG_STEREO_CONTROL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L
+//OTG0_OTG_SNAPSHOT_STATUS
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//OTG0_OTG_SNAPSHOT_CONTROL
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//OTG0_OTG_SNAPSHOT_POSITION
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG0_OTG_SNAPSHOT_FRAME
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG0_OTG_INTERRUPT_CONTROL
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//OTG0_OTG_UPDATE_LOCK
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L
+//OTG0_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L
+//OTG0_OTG_MASTER_EN
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L
+//OTG0_OTG_BLANK_DATA_COLOR
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//OTG0_OTG_BLANK_DATA_COLOR_EXT
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L
+//OTG0_OTG_BLACK_COLOR
+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0
+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa
+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14
+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//OTG0_OTG_BLACK_COLOR_EXT
+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL
+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L
+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//OTG0_OTG_CRC_CNTL
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L
+//OTG0_OTG_CRC_CNTL2
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L
+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG0_OTG_CRC0_DATA_RG
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//OTG0_OTG_CRC0_DATA_B
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L
+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG0_OTG_CRC1_DATA_RG
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//OTG0_OTG_CRC1_DATA_B
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_RG
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_B
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_RG
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_B
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L
+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//OTG0_OTG_STATIC_SCREEN_CONTROL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//OTG0_OTG_3D_STRUCTURE_CONTROL
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//OTG0_OTG_GSL_VSYNC_GAP
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L
+//OTG0_OTG_MASTER_UPDATE_MODE
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L
+//OTG0_OTG_CLOCK_CONTROL
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L
+//OTG0_OTG_VSTARTUP_PARAM
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL
+//OTG0_OTG_VUPDATE_PARAM
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L
+//OTG0_OTG_VREADY_PARAM
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL
+//OTG0_OTG_GLOBAL_SYNC_STATUS
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L
+//OTG0_OTG_MASTER_UPDATE_LOCK
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L
+//OTG0_OTG_GSL_CONTROL
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L
+//OTG0_OTG_GSL_WINDOW_X
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L
+//OTG0_OTG_GSL_WINDOW_Y
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L
+//OTG0_OTG_VUPDATE_KEEPOUT
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL0
+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0
+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8
+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19
+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL
+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L
+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L
+//OTG0_OTG_GLOBAL_CONTROL1
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL2
+#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f
+#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL3
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L
+//OTG0_OTG_TRIG_MANUAL_CONTROL
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L
+//OTG0_OTG_MANUAL_FLOW_CONTROL
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L
+//OTG0_OTG_RANGE_TIMING_INT_STATUS
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//OTG0_OTG_DRR_CONTROL
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L
+//OTG0_OTG_REQUEST_CONTROL
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L
+//OTG0_OTG_DSC_START_POSITION
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L
+//OTG0_OTG_PIPE_UPDATE_STATUS
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L
+//OTG0_OTG_SPARE_REGISTER
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+//OTG1_OTG_H_TOTAL
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL
+//OTG1_OTG_H_BLANK_START_END
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L
+//OTG1_OTG_H_SYNC_A
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L
+//OTG1_OTG_H_SYNC_A_CNTL
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//OTG1_OTG_H_TIMING_CNTL
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L
+//OTG1_OTG_V_TOTAL
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL
+//OTG1_OTG_V_TOTAL_MIN
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL
+//OTG1_OTG_V_TOTAL_MAX
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL
+//OTG1_OTG_V_TOTAL_MID
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL
+//OTG1_OTG_V_TOTAL_CONTROL
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//OTG1_OTG_V_TOTAL_INT_STATUS
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//OTG1_OTG_VSYNC_NOM_INT_STATUS
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//OTG1_OTG_V_BLANK_START_END
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L
+//OTG1_OTG_V_SYNC_A
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L
+//OTG1_OTG_V_SYNC_A_CNTL
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L
+//OTG1_OTG_TRIGA_CNTL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L
+//OTG1_OTG_TRIGA_MANUAL_TRIG
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//OTG1_OTG_TRIGB_CNTL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L
+//OTG1_OTG_TRIGB_MANUAL_TRIG
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//OTG1_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//OTG1_OTG_FLOW_CONTROL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//OTG1_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//OTG1_OTG_CONTROL
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0
+#define OTG1_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT 0x4
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L
+#define OTG1_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK 0x00000010L
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L
+#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//OTG1_OTG_BLANK_CONTROL
+#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0
+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8
+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10
+#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L
+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L
+//OTG1_OTG_PIPE_ABORT_CONTROL
+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0
+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8
+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L
+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L
+//OTG1_OTG_INTERLACE_CONTROL
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//OTG1_OTG_INTERLACE_STATUS
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//OTG1_OTG_PIXEL_DATA_READBACK0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L
+//OTG1_OTG_PIXEL_DATA_READBACK1
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL
+//OTG1_OTG_STATUS
+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2
+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12
+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L
+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L
+//OTG1_OTG_STATUS_POSITION
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG1_OTG_NOM_VERT_POSITION
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL
+//OTG1_OTG_STATUS_FRAME_COUNT
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG1_OTG_STATUS_VF_COUNT
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL
+//OTG1_OTG_STATUS_HV_COUNT
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL
+//OTG1_OTG_COUNT_CONTROL
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//OTG1_OTG_COUNT_RESET
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L
+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//OTG1_OTG_VERT_SYNC_CONTROL
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//OTG1_OTG_STEREO_STATUS
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L
+//OTG1_OTG_STEREO_CONTROL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L
+//OTG1_OTG_SNAPSHOT_STATUS
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//OTG1_OTG_SNAPSHOT_CONTROL
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//OTG1_OTG_SNAPSHOT_POSITION
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG1_OTG_SNAPSHOT_FRAME
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG1_OTG_INTERRUPT_CONTROL
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//OTG1_OTG_UPDATE_LOCK
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L
+//OTG1_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L
+//OTG1_OTG_MASTER_EN
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L
+//OTG1_OTG_BLANK_DATA_COLOR
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//OTG1_OTG_BLANK_DATA_COLOR_EXT
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L
+//OTG1_OTG_BLACK_COLOR
+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0
+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa
+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14
+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//OTG1_OTG_BLACK_COLOR_EXT
+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL
+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L
+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//OTG1_OTG_CRC_CNTL
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L
+//OTG1_OTG_CRC_CNTL2
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L
+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG1_OTG_CRC0_DATA_RG
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//OTG1_OTG_CRC0_DATA_B
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L
+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG1_OTG_CRC1_DATA_RG
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//OTG1_OTG_CRC1_DATA_B
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_RG
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_B
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_RG
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_B
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L
+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//OTG1_OTG_STATIC_SCREEN_CONTROL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//OTG1_OTG_3D_STRUCTURE_CONTROL
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//OTG1_OTG_GSL_VSYNC_GAP
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L
+//OTG1_OTG_MASTER_UPDATE_MODE
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L
+//OTG1_OTG_CLOCK_CONTROL
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L
+//OTG1_OTG_VSTARTUP_PARAM
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL
+//OTG1_OTG_VUPDATE_PARAM
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L
+//OTG1_OTG_VREADY_PARAM
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL
+//OTG1_OTG_GLOBAL_SYNC_STATUS
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L
+//OTG1_OTG_MASTER_UPDATE_LOCK
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L
+//OTG1_OTG_GSL_CONTROL
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L
+//OTG1_OTG_GSL_WINDOW_X
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L
+//OTG1_OTG_GSL_WINDOW_Y
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L
+//OTG1_OTG_VUPDATE_KEEPOUT
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL0
+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0
+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8
+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19
+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL
+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L
+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L
+//OTG1_OTG_GLOBAL_CONTROL1
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL2
+#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f
+#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL3
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L
+//OTG1_OTG_TRIG_MANUAL_CONTROL
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L
+//OTG1_OTG_MANUAL_FLOW_CONTROL
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L
+//OTG1_OTG_RANGE_TIMING_INT_STATUS
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//OTG1_OTG_DRR_CONTROL
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L
+//OTG1_OTG_REQUEST_CONTROL
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L
+//OTG1_OTG_DSC_START_POSITION
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L
+//OTG1_OTG_PIPE_UPDATE_STATUS
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L
+//OTG1_OTG_SPARE_REGISTER
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+//OTG2_OTG_H_TOTAL
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL
+//OTG2_OTG_H_BLANK_START_END
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L
+//OTG2_OTG_H_SYNC_A
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L
+//OTG2_OTG_H_SYNC_A_CNTL
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//OTG2_OTG_H_TIMING_CNTL
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L
+//OTG2_OTG_V_TOTAL
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL
+//OTG2_OTG_V_TOTAL_MIN
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL
+//OTG2_OTG_V_TOTAL_MAX
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL
+//OTG2_OTG_V_TOTAL_MID
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL
+//OTG2_OTG_V_TOTAL_CONTROL
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//OTG2_OTG_V_TOTAL_INT_STATUS
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//OTG2_OTG_VSYNC_NOM_INT_STATUS
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//OTG2_OTG_V_BLANK_START_END
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L
+//OTG2_OTG_V_SYNC_A
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L
+//OTG2_OTG_V_SYNC_A_CNTL
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L
+//OTG2_OTG_TRIGA_CNTL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L
+//OTG2_OTG_TRIGA_MANUAL_TRIG
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//OTG2_OTG_TRIGB_CNTL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L
+//OTG2_OTG_TRIGB_MANUAL_TRIG
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//OTG2_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//OTG2_OTG_FLOW_CONTROL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//OTG2_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//OTG2_OTG_CONTROL
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0
+#define OTG2_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT 0x4
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L
+#define OTG2_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK 0x00000010L
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L
+#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//OTG2_OTG_BLANK_CONTROL
+#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0
+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8
+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10
+#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L
+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L
+//OTG2_OTG_PIPE_ABORT_CONTROL
+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0
+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8
+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L
+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L
+//OTG2_OTG_INTERLACE_CONTROL
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//OTG2_OTG_INTERLACE_STATUS
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//OTG2_OTG_PIXEL_DATA_READBACK0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L
+//OTG2_OTG_PIXEL_DATA_READBACK1
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL
+//OTG2_OTG_STATUS
+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2
+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12
+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L
+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L
+//OTG2_OTG_STATUS_POSITION
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG2_OTG_NOM_VERT_POSITION
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL
+//OTG2_OTG_STATUS_FRAME_COUNT
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG2_OTG_STATUS_VF_COUNT
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL
+//OTG2_OTG_STATUS_HV_COUNT
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL
+//OTG2_OTG_COUNT_CONTROL
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//OTG2_OTG_COUNT_RESET
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L
+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//OTG2_OTG_VERT_SYNC_CONTROL
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//OTG2_OTG_STEREO_STATUS
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L
+//OTG2_OTG_STEREO_CONTROL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L
+//OTG2_OTG_SNAPSHOT_STATUS
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//OTG2_OTG_SNAPSHOT_CONTROL
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//OTG2_OTG_SNAPSHOT_POSITION
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG2_OTG_SNAPSHOT_FRAME
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG2_OTG_INTERRUPT_CONTROL
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//OTG2_OTG_UPDATE_LOCK
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L
+//OTG2_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L
+//OTG2_OTG_MASTER_EN
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L
+//OTG2_OTG_BLANK_DATA_COLOR
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//OTG2_OTG_BLANK_DATA_COLOR_EXT
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L
+//OTG2_OTG_BLACK_COLOR
+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0
+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa
+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14
+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//OTG2_OTG_BLACK_COLOR_EXT
+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL
+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L
+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L
+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L
+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//OTG2_OTG_CRC_CNTL
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L
+//OTG2_OTG_CRC_CNTL2
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L
+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG2_OTG_CRC0_DATA_RG
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//OTG2_OTG_CRC0_DATA_B
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L
+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG2_OTG_CRC1_DATA_RG
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//OTG2_OTG_CRC1_DATA_B
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_RG
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_B
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_RG
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_B
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L
+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//OTG2_OTG_STATIC_SCREEN_CONTROL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//OTG2_OTG_3D_STRUCTURE_CONTROL
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//OTG2_OTG_GSL_VSYNC_GAP
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L
+//OTG2_OTG_MASTER_UPDATE_MODE
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L
+//OTG2_OTG_CLOCK_CONTROL
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L
+//OTG2_OTG_VSTARTUP_PARAM
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL
+//OTG2_OTG_VUPDATE_PARAM
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L
+//OTG2_OTG_VREADY_PARAM
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL
+//OTG2_OTG_GLOBAL_SYNC_STATUS
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L
+//OTG2_OTG_MASTER_UPDATE_LOCK
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L
+//OTG2_OTG_GSL_CONTROL
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L
+//OTG2_OTG_GSL_WINDOW_X
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L
+//OTG2_OTG_GSL_WINDOW_Y
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L
+//OTG2_OTG_VUPDATE_KEEPOUT
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL0
+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0
+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8
+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19
+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL
+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L
+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L
+//OTG2_OTG_GLOBAL_CONTROL1
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL2
+#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f
+#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL3
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L
+//OTG2_OTG_TRIG_MANUAL_CONTROL
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L
+//OTG2_OTG_MANUAL_FLOW_CONTROL
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L
+//OTG2_OTG_RANGE_TIMING_INT_STATUS
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//OTG2_OTG_DRR_CONTROL
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L
+//OTG2_OTG_REQUEST_CONTROL
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L
+//OTG2_OTG_DSC_START_POSITION
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L
+//OTG2_OTG_PIPE_UPDATE_STATUS
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L
+//OTG2_OTG_SPARE_REGISTER
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+//OTG3_OTG_H_TOTAL
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL
+//OTG3_OTG_H_BLANK_START_END
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L
+//OTG3_OTG_H_SYNC_A
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L
+//OTG3_OTG_H_SYNC_A_CNTL
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//OTG3_OTG_H_TIMING_CNTL
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L
+//OTG3_OTG_V_TOTAL
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL
+//OTG3_OTG_V_TOTAL_MIN
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL
+//OTG3_OTG_V_TOTAL_MAX
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL
+//OTG3_OTG_V_TOTAL_MID
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL
+//OTG3_OTG_V_TOTAL_CONTROL
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//OTG3_OTG_V_TOTAL_INT_STATUS
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//OTG3_OTG_VSYNC_NOM_INT_STATUS
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//OTG3_OTG_V_BLANK_START_END
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L
+//OTG3_OTG_V_SYNC_A
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L
+//OTG3_OTG_V_SYNC_A_CNTL
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L
+//OTG3_OTG_TRIGA_CNTL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L
+//OTG3_OTG_TRIGA_MANUAL_TRIG
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//OTG3_OTG_TRIGB_CNTL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L
+//OTG3_OTG_TRIGB_MANUAL_TRIG
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//OTG3_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//OTG3_OTG_FLOW_CONTROL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//OTG3_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//OTG3_OTG_CONTROL
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0
+#define OTG3_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT 0x4
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L
+#define OTG3_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK 0x00000010L
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L
+#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//OTG3_OTG_BLANK_CONTROL
+#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0
+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8
+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10
+#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L
+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L
+//OTG3_OTG_PIPE_ABORT_CONTROL
+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0
+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8
+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L
+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L
+//OTG3_OTG_INTERLACE_CONTROL
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//OTG3_OTG_INTERLACE_STATUS
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//OTG3_OTG_PIXEL_DATA_READBACK0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L
+//OTG3_OTG_PIXEL_DATA_READBACK1
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL
+//OTG3_OTG_STATUS
+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2
+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12
+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L
+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L
+//OTG3_OTG_STATUS_POSITION
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG3_OTG_NOM_VERT_POSITION
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL
+//OTG3_OTG_STATUS_FRAME_COUNT
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG3_OTG_STATUS_VF_COUNT
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL
+//OTG3_OTG_STATUS_HV_COUNT
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL
+//OTG3_OTG_COUNT_CONTROL
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//OTG3_OTG_COUNT_RESET
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L
+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//OTG3_OTG_VERT_SYNC_CONTROL
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//OTG3_OTG_STEREO_STATUS
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L
+//OTG3_OTG_STEREO_CONTROL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L
+//OTG3_OTG_SNAPSHOT_STATUS
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//OTG3_OTG_SNAPSHOT_CONTROL
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//OTG3_OTG_SNAPSHOT_POSITION
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG3_OTG_SNAPSHOT_FRAME
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG3_OTG_INTERRUPT_CONTROL
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//OTG3_OTG_UPDATE_LOCK
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L
+//OTG3_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L
+//OTG3_OTG_MASTER_EN
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L
+//OTG3_OTG_BLANK_DATA_COLOR
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//OTG3_OTG_BLANK_DATA_COLOR_EXT
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L
+//OTG3_OTG_BLACK_COLOR
+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0
+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa
+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14
+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//OTG3_OTG_BLACK_COLOR_EXT
+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL
+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L
+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L
+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L
+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//OTG3_OTG_CRC_CNTL
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L
+//OTG3_OTG_CRC_CNTL2
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L
+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG3_OTG_CRC0_DATA_RG
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//OTG3_OTG_CRC0_DATA_B
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L
+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG3_OTG_CRC1_DATA_RG
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//OTG3_OTG_CRC1_DATA_B
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_RG
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_B
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_RG
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_B
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L
+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//OTG3_OTG_STATIC_SCREEN_CONTROL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//OTG3_OTG_3D_STRUCTURE_CONTROL
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//OTG3_OTG_GSL_VSYNC_GAP
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L
+//OTG3_OTG_MASTER_UPDATE_MODE
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L
+//OTG3_OTG_CLOCK_CONTROL
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L
+//OTG3_OTG_VSTARTUP_PARAM
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL
+//OTG3_OTG_VUPDATE_PARAM
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L
+//OTG3_OTG_VREADY_PARAM
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL
+//OTG3_OTG_GLOBAL_SYNC_STATUS
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L
+//OTG3_OTG_MASTER_UPDATE_LOCK
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L
+//OTG3_OTG_GSL_CONTROL
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L
+//OTG3_OTG_GSL_WINDOW_X
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L
+//OTG3_OTG_GSL_WINDOW_Y
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L
+//OTG3_OTG_VUPDATE_KEEPOUT
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL0
+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0
+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8
+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19
+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL
+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L
+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L
+//OTG3_OTG_GLOBAL_CONTROL1
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL2
+#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f
+#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL3
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L
+//OTG3_OTG_TRIG_MANUAL_CONTROL
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L
+//OTG3_OTG_MANUAL_FLOW_CONTROL
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L
+//OTG3_OTG_RANGE_TIMING_INT_STATUS
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//OTG3_OTG_DRR_CONTROL
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L
+//OTG3_OTG_REQUEST_CONTROL
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L
+//OTG3_OTG_DSC_START_POSITION
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L
+//OTG3_OTG_PIPE_UPDATE_STATUS
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L
+//OTG3_OTG_SPARE_REGISTER
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg4_dispdec
+//OTG4_OTG_H_TOTAL
+#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0
+#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL
+//OTG4_OTG_H_BLANK_START_END
+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0
+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10
+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL
+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L
+//OTG4_OTG_H_SYNC_A
+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0
+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10
+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL
+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L
+//OTG4_OTG_H_SYNC_A_CNTL
+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0
+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10
+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L
+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L
+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//OTG4_OTG_H_TIMING_CNTL
+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0
+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8
+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L
+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L
+//OTG4_OTG_V_TOTAL
+#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0
+#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL
+//OTG4_OTG_V_TOTAL_MIN
+#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0
+#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL
+//OTG4_OTG_V_TOTAL_MAX
+#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0
+#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL
+//OTG4_OTG_V_TOTAL_MID
+#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0
+#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL
+//OTG4_OTG_V_TOTAL_CONTROL
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L
+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//OTG4_OTG_V_TOTAL_INT_STATUS
+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//OTG4_OTG_VSYNC_NOM_INT_STATUS
+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0
+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L
+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//OTG4_OTG_V_BLANK_START_END
+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0
+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10
+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL
+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L
+//OTG4_OTG_V_SYNC_A
+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0
+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10
+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL
+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L
+//OTG4_OTG_V_SYNC_A_CNTL
+#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0
+#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L
+//OTG4_OTG_TRIGA_CNTL
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L
+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L
+//OTG4_OTG_TRIGA_MANUAL_TRIG
+#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//OTG4_OTG_TRIGB_CNTL
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L
+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L
+//OTG4_OTG_TRIGB_MANUAL_TRIG
+#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//OTG4_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//OTG4_OTG_FLOW_CONTROL
+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//OTG4_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//OTG4_OTG_CONTROL
+#define OTG4_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0
+#define OTG4_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT 0x4
+#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8
+#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc
+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define OTG4_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L
+#define OTG4_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK 0x00000010L
+#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L
+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L
+#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//OTG4_OTG_BLANK_CONTROL
+#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0
+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8
+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10
+#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L
+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L
+//OTG4_OTG_PIPE_ABORT_CONTROL
+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0
+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8
+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L
+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L
+//OTG4_OTG_INTERLACE_CONTROL
+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0
+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L
+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//OTG4_OTG_INTERLACE_STATUS
+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//OTG4_OTG_PIXEL_DATA_READBACK0
+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL
+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L
+//OTG4_OTG_PIXEL_DATA_READBACK1
+#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL
+//OTG4_OTG_STATUS
+#define OTG4_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0
+#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1
+#define OTG4_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2
+#define OTG4_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3
+#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define OTG4_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10
+#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11
+#define OTG4_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12
+#define OTG4_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L
+#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L
+#define OTG4_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L
+#define OTG4_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L
+#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define OTG4_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L
+#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L
+#define OTG4_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L
+//OTG4_OTG_STATUS_POSITION
+#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0
+#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10
+#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL
+#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG4_OTG_NOM_VERT_POSITION
+#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0
+#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL
+//OTG4_OTG_STATUS_FRAME_COUNT
+#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0
+#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG4_OTG_STATUS_VF_COUNT
+#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0
+#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL
+//OTG4_OTG_STATUS_HV_COUNT
+#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0
+#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL
+//OTG4_OTG_COUNT_CONTROL
+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//OTG4_OTG_COUNT_RESET
+#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0
+#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L
+//OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//OTG4_OTG_VERT_SYNC_CONTROL
+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//OTG4_OTG_STEREO_STATUS
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e
+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L
+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L
+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L
+//OTG4_OTG_STEREO_CONTROL
+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13
+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18
+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL
+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L
+//OTG4_OTG_SNAPSHOT_STATUS
+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1
+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//OTG4_OTG_SNAPSHOT_CONTROL
+#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//OTG4_OTG_SNAPSHOT_POSITION
+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL
+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG4_OTG_SNAPSHOT_FRAME
+#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG4_OTG_INTERRUPT_CONTROL
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//OTG4_OTG_UPDATE_LOCK
+#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0
+#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L
+//OTG4_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L
+//OTG4_OTG_MASTER_EN
+#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0
+#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L
+//OTG4_OTG_BLANK_DATA_COLOR
+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//OTG4_OTG_BLANK_DATA_COLOR_EXT
+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL
+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L
+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L
+//OTG4_OTG_BLACK_COLOR
+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0
+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa
+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14
+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//OTG4_OTG_BLACK_COLOR_EXT
+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL
+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L
+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L
+//OTG4_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL
+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L
+//OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//OTG4_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL
+//OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//OTG4_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL
+//OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//OTG4_OTG_CRC_CNTL
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13
+#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14
+#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18
+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c
+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d
+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e
+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L
+#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L
+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L
+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L
+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L
+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L
+//OTG4_OTG_CRC_CNTL2
+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0
+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1
+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4
+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8
+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L
+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L
+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L
+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L
+//OTG4_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG4_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG4_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG4_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG4_OTG_CRC0_DATA_RG
+#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//OTG4_OTG_CRC0_DATA_B
+#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define OTG4_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10
+#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L
+//OTG4_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG4_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG4_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG4_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG4_OTG_CRC1_DATA_RG
+#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//OTG4_OTG_CRC1_DATA_B
+#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define OTG4_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10
+#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L
+//OTG4_OTG_CRC2_DATA_RG
+#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0
+#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10
+#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L
+//OTG4_OTG_CRC2_DATA_B
+#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0
+#define OTG4_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10
+#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L
+//OTG4_OTG_CRC3_DATA_RG
+#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0
+#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10
+#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L
+//OTG4_OTG_CRC3_DATA_B
+#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0
+#define OTG4_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10
+#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L
+//OTG4_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0
+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//OTG4_OTG_STATIC_SCREEN_CONTROL
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//OTG4_OTG_3D_STRUCTURE_CONTROL
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//OTG4_OTG_GSL_VSYNC_GAP
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L
+//OTG4_OTG_MASTER_UPDATE_MODE
+#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0
+#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L
+//OTG4_OTG_CLOCK_CONTROL
+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0
+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1
+#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4
+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8
+#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10
+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L
+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L
+#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L
+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L
+#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L
+//OTG4_OTG_VSTARTUP_PARAM
+#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0
+#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL
+//OTG4_OTG_VUPDATE_PARAM
+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0
+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10
+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L
+//OTG4_OTG_VREADY_PARAM
+#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0
+#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL
+//OTG4_OTG_GLOBAL_SYNC_STATUS
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L
+#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L
+//OTG4_OTG_MASTER_UPDATE_LOCK
+#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0
+#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8
+#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L
+//OTG4_OTG_GSL_CONTROL
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L
+//OTG4_OTG_GSL_WINDOW_X
+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0
+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10
+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL
+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L
+//OTG4_OTG_GSL_WINDOW_Y
+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0
+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10
+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL
+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L
+//OTG4_OTG_VUPDATE_KEEPOUT
+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0
+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10
+#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f
+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL
+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L
+#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L
+//OTG4_OTG_GLOBAL_CONTROL0
+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0
+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8
+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19
+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL
+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L
+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L
+//OTG4_OTG_GLOBAL_CONTROL1
+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0
+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10
+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f
+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL
+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L
+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L
+//OTG4_OTG_GLOBAL_CONTROL2
+#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0
+#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa
+#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10
+#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f
+#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL
+#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L
+#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L
+#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L
+//OTG4_OTG_GLOBAL_CONTROL3
+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0
+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4
+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8
+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L
+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L
+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L
+//OTG4_OTG_TRIG_MANUAL_CONTROL
+#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0
+#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L
+//OTG4_OTG_MANUAL_FLOW_CONTROL
+#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0
+#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L
+//OTG4_OTG_RANGE_TIMING_INT_STATUS
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//OTG4_OTG_DRR_CONTROL
+#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0
+#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10
+#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L
+#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L
+//OTG4_OTG_REQUEST_CONTROL
+#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0
+#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L
+//OTG4_OTG_DSC_START_POSITION
+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0
+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10
+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL
+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L
+//OTG4_OTG_PIPE_UPDATE_STATUS
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L
+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L
+//OTG4_OTG_SPARE_REGISTER
+#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0
+#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg5_dispdec
+//OTG5_OTG_H_TOTAL
+#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0
+#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL
+//OTG5_OTG_H_BLANK_START_END
+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0
+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10
+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL
+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L
+//OTG5_OTG_H_SYNC_A
+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0
+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10
+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL
+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L
+//OTG5_OTG_H_SYNC_A_CNTL
+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0
+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10
+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L
+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L
+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L
+//OTG5_OTG_H_TIMING_CNTL
+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0
+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8
+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L
+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L
+//OTG5_OTG_V_TOTAL
+#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0
+#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL
+//OTG5_OTG_V_TOTAL_MIN
+#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0
+#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL
+//OTG5_OTG_V_TOTAL_MAX
+#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0
+#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL
+//OTG5_OTG_V_TOTAL_MID
+#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0
+#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL
+//OTG5_OTG_V_TOTAL_CONTROL
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L
+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L
+//OTG5_OTG_V_TOTAL_INT_STATUS
+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
+//OTG5_OTG_VSYNC_NOM_INT_STATUS
+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0
+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L
+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
+//OTG5_OTG_V_BLANK_START_END
+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0
+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10
+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL
+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L
+//OTG5_OTG_V_SYNC_A
+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0
+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10
+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL
+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L
+//OTG5_OTG_V_SYNC_A_CNTL
+#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0
+#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L
+//OTG5_OTG_TRIGA_CNTL
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L
+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L
+//OTG5_OTG_TRIGA_MANUAL_TRIG
+#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L
+//OTG5_OTG_TRIGB_CNTL
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L
+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L
+//OTG5_OTG_TRIGB_MANUAL_TRIG
+#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L
+//OTG5_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
+//OTG5_OTG_FLOW_CONTROL
+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL
+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L
+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
+//OTG5_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L
+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L
+//OTG5_OTG_CONTROL
+#define OTG5_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0
+#define OTG5_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT 0x4
+#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8
+#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc
+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define OTG5_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L
+#define OTG5_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK 0x00000010L
+#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L
+#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L
+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L
+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L
+#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
+#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L
+#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L
+#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L
+//OTG5_OTG_BLANK_CONTROL
+#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0
+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8
+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10
+#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L
+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L
+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L
+//OTG5_OTG_PIPE_ABORT_CONTROL
+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0
+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8
+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L
+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L
+//OTG5_OTG_INTERLACE_CONTROL
+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0
+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L
+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
+//OTG5_OTG_INTERLACE_STATUS
+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L
+//OTG5_OTG_PIXEL_DATA_READBACK0
+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL
+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L
+//OTG5_OTG_PIXEL_DATA_READBACK1
+#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL
+//OTG5_OTG_STATUS
+#define OTG5_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0
+#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1
+#define OTG5_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2
+#define OTG5_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3
+#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define OTG5_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10
+#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11
+#define OTG5_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12
+#define OTG5_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L
+#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L
+#define OTG5_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L
+#define OTG5_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L
+#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
+#define OTG5_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L
+#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L
+#define OTG5_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L
+//OTG5_OTG_STATUS_POSITION
+#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0
+#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10
+#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL
+#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG5_OTG_NOM_VERT_POSITION
+#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0
+#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL
+//OTG5_OTG_STATUS_FRAME_COUNT
+#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0
+#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG5_OTG_STATUS_VF_COUNT
+#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0
+#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL
+//OTG5_OTG_STATUS_HV_COUNT
+#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0
+#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL
+//OTG5_OTG_COUNT_CONTROL
+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L
+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL
+//OTG5_OTG_COUNT_RESET
+#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0
+#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L
+//OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
+//OTG5_OTG_VERT_SYNC_CONTROL
+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
+//OTG5_OTG_STEREO_STATUS
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e
+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L
+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L
+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L
+//OTG5_OTG_STEREO_CONTROL
+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13
+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18
+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL
+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L
+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L
+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L
+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L
+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L
+//OTG5_OTG_SNAPSHOT_STATUS
+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1
+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L
+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L
+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
+//OTG5_OTG_SNAPSHOT_CONTROL
+#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
+//OTG5_OTG_SNAPSHOT_POSITION
+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL
+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L
+//OTG5_OTG_SNAPSHOT_FRAME
+#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL
+//OTG5_OTG_INTERRUPT_CONTROL
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
+//OTG5_OTG_UPDATE_LOCK
+#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0
+#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L
+//OTG5_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L
+//OTG5_OTG_MASTER_EN
+#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0
+#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L
+//OTG5_OTG_BLANK_DATA_COLOR
+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL
+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L
+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L
+//OTG5_OTG_BLANK_DATA_COLOR_EXT
+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL
+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L
+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L
+//OTG5_OTG_BLACK_COLOR
+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0
+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa
+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14
+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL
+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L
+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L
+//OTG5_OTG_BLACK_COLOR_EXT
+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL
+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L
+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L
+//OTG5_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL
+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L
+//OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L
+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L
+//OTG5_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL
+//OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L
+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L
+//OTG5_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL
+//OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L
+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L
+//OTG5_OTG_CRC_CNTL
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13
+#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14
+#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18
+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c
+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d
+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e
+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L
+#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L
+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L
+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L
+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L
+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L
+//OTG5_OTG_CRC_CNTL2
+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0
+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1
+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4
+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8
+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L
+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L
+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L
+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L
+//OTG5_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG5_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG5_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG5_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG5_OTG_CRC0_DATA_RG
+#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L
+//OTG5_OTG_CRC0_DATA_B
+#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define OTG5_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10
+#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L
+//OTG5_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL
+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L
+//OTG5_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL
+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L
+//OTG5_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL
+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L
+//OTG5_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL
+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L
+//OTG5_OTG_CRC1_DATA_RG
+#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L
+//OTG5_OTG_CRC1_DATA_B
+#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define OTG5_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10
+#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L
+//OTG5_OTG_CRC2_DATA_RG
+#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0
+#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10
+#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L
+//OTG5_OTG_CRC2_DATA_B
+#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0
+#define OTG5_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10
+#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L
+//OTG5_OTG_CRC3_DATA_RG
+#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0
+#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10
+#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L
+//OTG5_OTG_CRC3_DATA_B
+#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0
+#define OTG5_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10
+#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L
+//OTG5_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0
+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L
+//OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL
+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L
+//OTG5_OTG_STATIC_SCREEN_CONTROL
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L
+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L
+//OTG5_OTG_3D_STRUCTURE_CONTROL
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L
+//OTG5_OTG_GSL_VSYNC_GAP
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L
+//OTG5_OTG_MASTER_UPDATE_MODE
+#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0
+#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L
+//OTG5_OTG_CLOCK_CONTROL
+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0
+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1
+#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4
+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8
+#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10
+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L
+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L
+#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L
+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L
+#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L
+//OTG5_OTG_VSTARTUP_PARAM
+#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0
+#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL
+//OTG5_OTG_VUPDATE_PARAM
+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0
+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10
+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL
+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L
+//OTG5_OTG_VREADY_PARAM
+#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0
+#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL
+//OTG5_OTG_GLOBAL_SYNC_STATUS
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L
+#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L
+//OTG5_OTG_MASTER_UPDATE_LOCK
+#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0
+#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8
+#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L
+#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L
+//OTG5_OTG_GSL_CONTROL
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L
+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
+#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L
+//OTG5_OTG_GSL_WINDOW_X
+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0
+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10
+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL
+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L
+//OTG5_OTG_GSL_WINDOW_Y
+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0
+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10
+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL
+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L
+//OTG5_OTG_VUPDATE_KEEPOUT
+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0
+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10
+#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f
+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL
+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L
+#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L
+//OTG5_OTG_GLOBAL_CONTROL0
+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0
+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8
+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19
+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL
+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L
+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L
+//OTG5_OTG_GLOBAL_CONTROL1
+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0
+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10
+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f
+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL
+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L
+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L
+//OTG5_OTG_GLOBAL_CONTROL2
+#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0
+#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa
+#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10
+#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f
+#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL
+#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L
+#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L
+#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L
+//OTG5_OTG_GLOBAL_CONTROL3
+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0
+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4
+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8
+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L
+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L
+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L
+//OTG5_OTG_TRIG_MANUAL_CONTROL
+#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0
+#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L
+//OTG5_OTG_MANUAL_FLOW_CONTROL
+#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0
+#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L
+//OTG5_OTG_RANGE_TIMING_INT_STATUS
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L
+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L
+//OTG5_OTG_DRR_CONTROL
+#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0
+#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10
+#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L
+#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L
+//OTG5_OTG_REQUEST_CONTROL
+#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0
+#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L
+//OTG5_OTG_DSC_START_POSITION
+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0
+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10
+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL
+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L
+//OTG5_OTG_PIPE_UPDATE_STATUS
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L
+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L
+//OTG5_OTG_SPARE_REGISTER
+#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0
+#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+//DWB_SOURCE_SELECT
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT 0x0
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT 0x3
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT 0x6
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK 0x00000007L
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK 0x00000038L
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK 0x000001C0L
+//GSL_SOURCE_SELECT
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L
+//OPTC_CLOCK_CONTROL
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L
+//ODM_MEM_PWR_CTRL
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT 0x0
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT 0x2
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT 0x4
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT 0x6
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT 0x8
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT 0xa
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT 0xc
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT 0xe
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT 0x10
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT 0x12
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT 0x14
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT 0x16
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT 0x18
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT 0x1a
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT 0x1c
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT 0x1e
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK 0x00000003L
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK 0x00000004L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK 0x00000030L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK 0x00000040L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK 0x00000300L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK 0x00000400L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK 0x00003000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK 0x00004000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK 0x00030000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK 0x00040000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK 0x00300000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK 0x00400000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK 0x03000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK 0x04000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK 0x30000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK 0x40000000L
+//ODM_MEM_PWR_CTRL2
+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE__SHIFT 0x0
+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS__SHIFT 0x2
+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE__SHIFT 0x4
+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS__SHIFT 0x6
+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE__SHIFT 0x8
+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS__SHIFT 0xa
+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE__SHIFT 0xc
+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS__SHIFT 0xe
+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE_MASK 0x00000003L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS_MASK 0x00000004L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE_MASK 0x00000030L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS_MASK 0x00000040L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE_MASK 0x00000300L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS_MASK 0x00000400L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE_MASK 0x00003000L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS_MASK 0x00004000L
+//ODM_MEM_PWR_CTRL3
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT 0x0
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT 0x2
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK 0x00000003L
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK 0x0000000CL
+//ODM_MEM_PWR_STATUS
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT 0x0
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT 0x2
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT 0x4
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT 0x6
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT 0x8
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT 0xa
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT 0xc
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT 0xe
+#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE__SHIFT 0x10
+#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE__SHIFT 0x12
+#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE__SHIFT 0x14
+#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE__SHIFT 0x16
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK 0x00000003L
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 0x0000000CL
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK 0x00000030L
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK 0x000000C0L
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK 0x00000300L
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK 0x00000C00L
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK 0x00003000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK 0x0000C000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE_MASK 0x00030000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE_MASK 0x000C0000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE_MASK 0x00300000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE_MASK 0x00C00000L
+//OPTC_MISC_SPARE_REGISTER
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON19_PERFCOUNTER_CNTL
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON19_PERFCOUNTER_CNTL2
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON19_PERFCOUNTER_STATE
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON19_PERFMON_CNTL
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON19_PERFMON_CNTL2
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON19_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON19_PERFMON_CVALUE_LOW
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON19_PERFMON_HI
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON19_PERFMON_LOW
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+//DC_I2C_CONTROL
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L
+//DC_I2C_ARBITRATION
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L
+//DC_I2C_INTERRUPT_CONTROL
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L
+//DC_I2C_SW_STATUS
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L
+//DC_I2C_DDC1_HW_STATUS
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC2_HW_STATUS
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC3_HW_STATUS
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC4_HW_STATUS
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC5_HW_STATUS
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC6_HW_STATUS
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L
+//DC_I2C_DDC1_SPEED
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC1_SETUP
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT 0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK 0x00000004L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC2_SPEED
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC2_SETUP
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT 0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK 0x00000004L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC3_SPEED
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC3_SETUP
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT 0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK 0x00000004L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC4_SPEED
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC4_SETUP
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT 0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK 0x00000004L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC5_SPEED
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC5_SETUP
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT 0x2
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK 0x00000004L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_DDC6_SPEED
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x00000300L
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xFFFF0000L
+//DC_I2C_DDC6_SETUP
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_SEND_RESET_LENGTH__SHIFT 0x2
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_SEND_RESET_LENGTH_MASK 0x00000004L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000FF00L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xFF000000L
+//DC_I2C_TRANSACTION0
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L
+//DC_I2C_TRANSACTION1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L
+//DC_I2C_TRANSACTION2
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L
+//DC_I2C_TRANSACTION3
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L
+//DC_I2C_DATA
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L
+#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L
+//DC_I2C_EDID_DETECT_CTRL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L
+//DC_I2C_READ_REQUEST_INTERRUPT
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+//DIO_SCRATCH0
+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT 0x0
+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK 0xFFFFFFFFL
+//DIO_SCRATCH1
+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT 0x0
+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK 0xFFFFFFFFL
+//DIO_SCRATCH2
+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT 0x0
+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK 0xFFFFFFFFL
+//DIO_SCRATCH3
+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT 0x0
+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK 0xFFFFFFFFL
+//DIO_SCRATCH4
+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT 0x0
+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK 0xFFFFFFFFL
+//DIO_SCRATCH5
+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT 0x0
+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK 0xFFFFFFFFL
+//DIO_SCRATCH6
+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT 0x0
+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK 0xFFFFFFFFL
+//DIO_SCRATCH7
+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT 0x0
+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK 0xFFFFFFFFL
+//DCE_VCE_CONTROL
+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L
+//DIO_MEM_PWR_STATUS
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9
+#define DIO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa
+#define DIO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc
+#define DIO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe
+#define DIO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10
+#define DIO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12
+#define DIO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14
+#define DIO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L
+#define DIO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0x00000C00L
+#define DIO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x00003000L
+#define DIO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0x0000C000L
+#define DIO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x00030000L
+#define DIO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0x000C0000L
+#define DIO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x00300000L
+#define DIO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0x00C00000L
+//DIO_MEM_PWR_CTRL
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa
+#define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb
+#define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd
+#define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe
+#define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10
+#define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11
+#define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13
+#define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14
+#define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16
+#define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17
+#define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19
+#define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a
+#define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c
+#define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d
+#define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L
+#define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x00001800L
+#define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x00002000L
+#define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0x0000C000L
+#define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x00010000L
+#define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x00060000L
+#define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x00080000L
+#define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x00300000L
+#define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x00400000L
+#define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x01800000L
+#define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x02000000L
+#define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0x0C000000L
+#define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000L
+#define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000L
+#define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000L
+//DIO_MEM_PWR_CTRL2
+#define DIO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_DIS__SHIFT 0x4
+#define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_FORCE__SHIFT 0x5
+#define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_DIS__SHIFT 0x6
+#define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_FORCE__SHIFT 0x7
+#define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_DIS__SHIFT 0x8
+#define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_FORCE__SHIFT 0x9
+#define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_DIS__SHIFT 0xa
+#define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_FORCE__SHIFT 0xb
+#define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_DIS__SHIFT 0xc
+#define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_FORCE__SHIFT 0xd
+#define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_DIS__SHIFT 0xe
+#define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_FORCE__SHIFT 0xf
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT 0x18
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT 0x19
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT 0x1a
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT 0x1b
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT 0x1c
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT 0x1d
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT 0x1e
+#define DIO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x00000003L
+#define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_DIS_MASK 0x00000010L
+#define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_FORCE_MASK 0x00000020L
+#define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_DIS_MASK 0x00000040L
+#define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_FORCE_MASK 0x00000080L
+#define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_DIS_MASK 0x00000100L
+#define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_FORCE_MASK 0x00000200L
+#define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_DIS_MASK 0x00000400L
+#define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_FORCE_MASK 0x00000800L
+#define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_DIS_MASK 0x00001000L
+#define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_FORCE_MASK 0x00002000L
+#define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_DIS_MASK 0x00004000L
+#define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_FORCE_MASK 0x00008000L
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK 0x01000000L
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK 0x02000000L
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK 0x04000000L
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK 0x08000000L
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK 0x10000000L
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK 0x20000000L
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK 0x40000000L
+//DIO_CLK_CNTL
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT 0x5
+#define DIO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT 0xa
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK 0x00000020L
+#define DIO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK 0x00000400L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L
+//DIO_MEM_PWR_CTRL3
+#define DIO_MEM_PWR_CTRL3__DME0_MEM_PWR_DIS__SHIFT 0x0
+#define DIO_MEM_PWR_CTRL3__DME0_MEM_PWR_FORCE__SHIFT 0x1
+#define DIO_MEM_PWR_CTRL3__DME1_MEM_PWR_DIS__SHIFT 0x3
+#define DIO_MEM_PWR_CTRL3__DME1_MEM_PWR_FORCE__SHIFT 0x4
+#define DIO_MEM_PWR_CTRL3__DME2_MEM_PWR_DIS__SHIFT 0x6
+#define DIO_MEM_PWR_CTRL3__DME2_MEM_PWR_FORCE__SHIFT 0x7
+#define DIO_MEM_PWR_CTRL3__DME3_MEM_PWR_DIS__SHIFT 0x9
+#define DIO_MEM_PWR_CTRL3__DME3_MEM_PWR_FORCE__SHIFT 0xa
+#define DIO_MEM_PWR_CTRL3__DME4_MEM_PWR_DIS__SHIFT 0xc
+#define DIO_MEM_PWR_CTRL3__DME4_MEM_PWR_FORCE__SHIFT 0xd
+#define DIO_MEM_PWR_CTRL3__DME5_MEM_PWR_DIS__SHIFT 0xf
+#define DIO_MEM_PWR_CTRL3__DME5_MEM_PWR_FORCE__SHIFT 0x10
+#define DIO_MEM_PWR_CTRL3__DME0_MEM_PWR_DIS_MASK 0x00000001L
+#define DIO_MEM_PWR_CTRL3__DME0_MEM_PWR_FORCE_MASK 0x00000006L
+#define DIO_MEM_PWR_CTRL3__DME1_MEM_PWR_DIS_MASK 0x00000008L
+#define DIO_MEM_PWR_CTRL3__DME1_MEM_PWR_FORCE_MASK 0x00000030L
+#define DIO_MEM_PWR_CTRL3__DME2_MEM_PWR_DIS_MASK 0x00000040L
+#define DIO_MEM_PWR_CTRL3__DME2_MEM_PWR_FORCE_MASK 0x00000180L
+#define DIO_MEM_PWR_CTRL3__DME3_MEM_PWR_DIS_MASK 0x00000200L
+#define DIO_MEM_PWR_CTRL3__DME3_MEM_PWR_FORCE_MASK 0x00000C00L
+#define DIO_MEM_PWR_CTRL3__DME4_MEM_PWR_DIS_MASK 0x00001000L
+#define DIO_MEM_PWR_CTRL3__DME4_MEM_PWR_FORCE_MASK 0x00006000L
+#define DIO_MEM_PWR_CTRL3__DME5_MEM_PWR_DIS_MASK 0x00008000L
+#define DIO_MEM_PWR_CTRL3__DME5_MEM_PWR_FORCE_MASK 0x00030000L
+//DIO_POWER_MANAGEMENT_CNTL
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L
+//DIG_SOFT_RESET
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L
+//DIO_MEM_PWR_STATUS1
+#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE__SHIFT 0x0
+#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE__SHIFT 0x2
+#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE__SHIFT 0x4
+#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE__SHIFT 0x6
+#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE__SHIFT 0x8
+#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE__SHIFT 0xa
+#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE__SHIFT 0x10
+#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE__SHIFT 0x12
+#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE__SHIFT 0x14
+#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE__SHIFT 0x16
+#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE__SHIFT 0x18
+#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE__SHIFT 0x1a
+#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE_MASK 0x00000001L
+#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE_MASK 0x00000004L
+#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE_MASK 0x00000010L
+#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE_MASK 0x00000040L
+#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE_MASK 0x00000100L
+#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE_MASK 0x00000400L
+#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE_MASK 0x00030000L
+#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE_MASK 0x000C0000L
+#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE_MASK 0x00300000L
+#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE_MASK 0x00C00000L
+#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE_MASK 0x03000000L
+#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE_MASK 0x0C000000L
+//DIO_CLK_CNTL2
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT 0x0
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT 0x7
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT 0x8
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT 0x9
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT 0xa
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT 0xb
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT 0xc
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT 0xd
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK 0x0000007FL
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L
+//DIO_CLK_CNTL3
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L
+//DIO_HDMI_RXSTATUS_TIMER_CONTROL
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L
+//DIO_PSP_INTERRUPT_STATUS
+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT 0x0
+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1
+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK 0x00000001L
+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL
+//DIO_PSP_INTERRUPT_CLEAR
+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT 0x0
+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L
+//DIO_GENERIC_INTERRUPT_MESSAGE
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL
+//DIO_GENERIC_INTERRUPT_CLEAR
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+//HPD0_DC_HPD_INT_STATUS
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD0_DC_HPD_INT_CONTROL
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD0_DC_HPD_CONTROL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD0_DC_HPD_FAST_TRAIN_CNTL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+//HPD1_DC_HPD_INT_STATUS
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD1_DC_HPD_INT_CONTROL
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD1_DC_HPD_CONTROL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD1_DC_HPD_FAST_TRAIN_CNTL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+//HPD2_DC_HPD_INT_STATUS
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD2_DC_HPD_INT_CONTROL
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD2_DC_HPD_CONTROL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD2_DC_HPD_FAST_TRAIN_CNTL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD2_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+//HPD3_DC_HPD_INT_STATUS
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD3_DC_HPD_INT_CONTROL
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD3_DC_HPD_CONTROL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD3_DC_HPD_FAST_TRAIN_CNTL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD3_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd4_dispdec
+//HPD4_DC_HPD_INT_STATUS
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD4_DC_HPD_INT_CONTROL
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD4_DC_HPD_CONTROL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD4_DC_HPD_FAST_TRAIN_CNTL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD4_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd5_dispdec
+//HPD5_DC_HPD_INT_STATUS
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L
+#define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L
+//HPD5_DC_HPD_INT_CONTROL
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L
+#define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L
+//HPD5_DC_HPD_CONTROL
+#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define HPD5_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL
+#define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L
+#define HPD5_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
+//HPD5_DC_HPD_FAST_TRAIN_CNTL
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L
+#define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
+//HPD5_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL
+#define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON20_PERFCOUNTER_CNTL
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON20_PERFCOUNTER_CNTL2
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON20_PERFCOUNTER_STATE
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON20_PERFMON_CNTL
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON20_PERFMON_CNTL2
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON20_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON20_PERFMON_CVALUE_LOW
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON20_PERFMON_HI
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON20_PERFMON_LOW
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+//DP_AUX0_AUX_CONTROL
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX0_AUX_SW_CONTROL
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX0_AUX_ARB_CONTROL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX0_AUX_INTERRUPT_CONTROL
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX0_AUX_SW_STATUS
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L
+//DP_AUX0_AUX_LS_STATUS
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX0_AUX_SW_DATA
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX0_AUX_LS_DATA
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX0_AUX_DPHY_TX_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL1
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L
+//DP_AUX0_AUX_DPHY_TX_STATUS
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX0_AUX_DPHY_RX_STATUS
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+//DP_AUX0_AUX_PHY_WAKE_CNTL
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+//DP_AUX1_AUX_CONTROL
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX1_AUX_SW_CONTROL
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX1_AUX_ARB_CONTROL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX1_AUX_INTERRUPT_CONTROL
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX1_AUX_SW_STATUS
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L
+//DP_AUX1_AUX_LS_STATUS
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX1_AUX_SW_DATA
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX1_AUX_LS_DATA
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX1_AUX_DPHY_TX_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL1
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L
+//DP_AUX1_AUX_DPHY_TX_STATUS
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX1_AUX_DPHY_RX_STATUS
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+//DP_AUX1_AUX_PHY_WAKE_CNTL
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+//DP_AUX2_AUX_CONTROL
+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX2_AUX_SW_CONTROL
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX2_AUX_ARB_CONTROL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX2_AUX_INTERRUPT_CONTROL
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX2_AUX_SW_STATUS
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L
+//DP_AUX2_AUX_LS_STATUS
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX2_AUX_SW_DATA
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX2_AUX_LS_DATA
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX2_AUX_DPHY_TX_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL1
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L
+//DP_AUX2_AUX_DPHY_TX_STATUS
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX2_AUX_DPHY_RX_STATUS
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+//DP_AUX2_AUX_PHY_WAKE_CNTL
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+//DP_AUX3_AUX_CONTROL
+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX3_AUX_SW_CONTROL
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX3_AUX_ARB_CONTROL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX3_AUX_INTERRUPT_CONTROL
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX3_AUX_SW_STATUS
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L
+//DP_AUX3_AUX_LS_STATUS
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX3_AUX_SW_DATA
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX3_AUX_LS_DATA
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX3_AUX_DPHY_TX_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL1
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L
+//DP_AUX3_AUX_DPHY_TX_STATUS
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX3_AUX_DPHY_RX_STATUS
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+//DP_AUX3_AUX_PHY_WAKE_CNTL
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux4_dispdec
+//DP_AUX4_AUX_CONTROL
+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX4_AUX_SW_CONTROL
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX4_AUX_ARB_CONTROL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX4_AUX_INTERRUPT_CONTROL
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX4_AUX_SW_STATUS
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L
+//DP_AUX4_AUX_LS_STATUS
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX4_AUX_SW_DATA
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX4_AUX_LS_DATA
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX4_AUX_DPHY_TX_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL1
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L
+//DP_AUX4_AUX_DPHY_TX_STATUS
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX4_AUX_DPHY_RX_STATUS
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+//DP_AUX4_AUX_PHY_WAKE_CNTL
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux5_dispdec
+//DP_AUX5_AUX_CONTROL
+#define DP_AUX5_AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define DP_AUX5_AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define DP_AUX5_AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define DP_AUX5_AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define DP_AUX5_AUX_CONTROL__AUX_EN_MASK 0x00000001L
+#define DP_AUX5_AUX_CONTROL__AUX_RESET_MASK 0x00000010L
+#define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L
+#define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
+#define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
+#define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
+#define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
+#define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
+#define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
+#define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
+#define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
+#define DP_AUX5_AUX_CONTROL__SPARE_0_MASK 0x40000000L
+#define DP_AUX5_AUX_CONTROL__SPARE_1_MASK 0x80000000L
+//DP_AUX5_AUX_SW_CONTROL
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
+#define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L
+#define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L
+//DP_AUX5_AUX_ARB_CONTROL
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
+#define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
+//DP_AUX5_AUX_INTERRUPT_CONTROL
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L
+#define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L
+//DP_AUX5_AUX_SW_STATUS
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L
+//DP_AUX5_AUX_LS_STATUS
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
+#define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
+//DP_AUX5_AUX_SW_DATA
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L
+#define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
+//DP_AUX5_AUX_LS_DATA
+#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L
+#define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L
+//DP_AUX5_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
+#define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L
+//DP_AUX5_AUX_DPHY_TX_CONTROL
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L
+#define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L
+//DP_AUX5_AUX_DPHY_RX_CONTROL0
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
+//DP_AUX5_AUX_DPHY_RX_CONTROL1
+#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8
+#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf
+#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL
+#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L
+#define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L
+//DP_AUX5_AUX_DPHY_TX_STATUS
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
+#define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L
+//DP_AUX5_AUX_DPHY_RX_STATUS
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L
+#define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L
+//DP_AUX5_AUX_GTC_SYNC_CONTROL
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L
+//DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L
+#define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L
+//DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L
+#define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L
+//DP_AUX5_AUX_GTC_SYNC_STATUS
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L
+#define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L
+//DP_AUX5_AUX_PHY_WAKE_CNTL
+#define DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0
+#define DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1
+#define DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2
+#define DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3
+#define DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L
+#define DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L
+#define DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L
+#define DP_AUX5_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+//DIG0_DIG_FE_CNTL
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG0_DIG_OUTPUT_CRC_CNTL
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG0_DIG_OUTPUT_CRC_RESULT
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG0_DIG_CLOCK_PATTERN
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG0_DIG_TEST_PATTERN
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG0_DIG_RANDOM_PATTERN_SEED
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG0_DIG_FIFO_STATUS
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG0_HDMI_METADATA_PACKET_CONTROL
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L
+//DIG0_HDMI_CONTROL
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG0_HDMI_STATUS
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG0_HDMI_AUDIO_PACKET_CONTROL
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG0_HDMI_ACR_PACKET_CONTROL
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG0_HDMI_VBI_PACKET_CONTROL
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG0_HDMI_INFOFRAME_CONTROL0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG0_HDMI_INFOFRAME_CONTROL1
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L
+//DIG0_HDMI_GC
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG0_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG0_AFMT_ISRC1_0
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG0_AFMT_ISRC1_1
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG0_AFMT_ISRC1_2
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG0_AFMT_ISRC1_3
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG0_AFMT_ISRC1_4
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG0_AFMT_ISRC2_0
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG0_AFMT_ISRC2_1
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG0_AFMT_ISRC2_2
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG0_AFMT_ISRC2_3
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L
+//DIG0_HDMI_DB_CONTROL
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DIG0_DME_CONTROL
+#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0
+#define DIG0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4
+#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8
+#define DIG0_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc
+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd
+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10
+#define DIG0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14
+#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L
+#define DIG0_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L
+#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L
+#define DIG0_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L
+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L
+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L
+#define DIG0_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L
+//DIG0_AFMT_MPEG_INFO0
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG0_AFMT_MPEG_INFO1
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG0_AFMT_GENERIC_HDR
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_0
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_1
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_2
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_3
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_4
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_5
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_6
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG0_AFMT_GENERIC_7
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L
+//DIG0_HDMI_ACR_32_0
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG0_HDMI_ACR_32_1
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG0_HDMI_ACR_44_0
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG0_HDMI_ACR_44_1
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG0_HDMI_ACR_48_0
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG0_HDMI_ACR_48_1
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG0_HDMI_ACR_STATUS_0
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG0_HDMI_ACR_STATUS_1
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG0_AFMT_AUDIO_INFO0
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG0_AFMT_AUDIO_INFO1
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG0_AFMT_60958_0
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG0_AFMT_60958_1
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG0_AFMT_AUDIO_CRC_CONTROL
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG0_AFMT_RAMP_CONTROL0
+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG0_AFMT_RAMP_CONTROL1
+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG0_AFMT_RAMP_CONTROL2
+#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG0_AFMT_RAMP_CONTROL3
+#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG0_AFMT_60958_2
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG0_AFMT_AUDIO_CRC_RESULT
+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG0_AFMT_STATUS
+#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG0_AFMT_AUDIO_PACKET_CONTROL
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L
+//DIG0_AFMT_VBI_PACKET_CONTROL
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L
+//DIG0_AFMT_INFOFRAME_CONTROL0
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG0_AFMT_AUDIO_SRC_CONTROL
+#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG0_DIG_BE_CNTL
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG0_DIG_BE_EN_CNTL
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG0_TMDS_CNTL
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG0_TMDS_CONTROL_CHAR
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG0_TMDS_CONTROL0_FEEDBACK
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG0_TMDS_STEREOSYNC_CTL_SEL
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG0_TMDS_CTL_BITS
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG0_TMDS_DCBALANCER_CONTROL
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG0_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L
+//DIG0_TMDS_CTL0_1_GEN_CNTL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG0_TMDS_CTL2_3_GEN_CNTL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG0_DIG_VERSION
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG0_DIG_LANE_ENABLE
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG0_AFMT_CNTL
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+//DIG0_AFMT_VBI_PACKET_CONTROL1
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L
+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L
+//DIG0_FORCE_DIG_DISABLE
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+//DP0_DP_LINK_CNTL
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP0_DP_PIXEL_FORMAT
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L
+//DP0_DP_MSA_COLORIMETRY
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L
+//DP0_DP_CONFIG
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP0_DP_VID_STREAM_CNTL
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP0_DP_STEER_FIFO
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP0_DP_MSA_MISC
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP0_DP_VID_TIMING
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP0_DP_VID_N
+#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP0_DP_VID_M
+#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP0_DP_LINK_FRAMING_CNTL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP0_DP_HBR2_EYE_PATTERN
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP0_DP_VID_MSA_VBID
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP0_DP_VID_INTERRUPT_CNTL
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP0_DP_DPHY_CNTL
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP0_DP_DPHY_SYM0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP0_DP_DPHY_SYM1
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP0_DP_DPHY_SYM2
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP0_DP_DPHY_8B10B_CNTL
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP0_DP_DPHY_PRBS_CNTL
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP0_DP_DPHY_SCRAM_CNTL
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP0_DP_DPHY_CRC_EN
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP0_DP_DPHY_CRC_CNTL
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP0_DP_DPHY_CRC_RESULT
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP0_DP_DPHY_CRC_MST_CNTL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP0_DP_DPHY_CRC_MST_STATUS
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP0_DP_DPHY_FAST_TRAINING
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP0_DP_DPHY_FAST_TRAINING_STATUS
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP0_DP_SEC_CNTL
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP0_DP_SEC_CNTL1
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP0_DP_SEC_FRAMING1
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP0_DP_SEC_FRAMING2
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP0_DP_SEC_FRAMING3
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP0_DP_SEC_FRAMING4
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP0_DP_SEC_AUD_N
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP0_DP_SEC_AUD_N_READBACK
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M_READBACK
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP0_DP_SEC_TIMESTAMP
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP0_DP_SEC_PACKET_CNTL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP0_DP_MSE_RATE_CNTL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP0_DP_MSE_RATE_UPDATE
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP0_DP_MSE_SAT0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP0_DP_MSE_SAT1
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP0_DP_MSE_SAT2
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP0_DP_MSE_SAT_UPDATE
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP0_DP_MSE_LINK_TIMING
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP0_DP_MSE_MISC_CNTL
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP0_DP_MSE_SAT0_STATUS
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP0_DP_MSE_SAT1_STATUS
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP0_DP_MSE_SAT2_STATUS
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+//DP0_DP_MSA_TIMING_PARAM1
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM2
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM3
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L
+//DP0_DP_MSA_TIMING_PARAM4
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L
+//DP0_DP_MSO_CNTL
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L
+//DP0_DP_MSO_CNTL1
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L
+//DP0_DP_DSC_CNTL
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//DP0_DP_SEC_CNTL2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L
+//DP0_DP_SEC_CNTL3
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L
+//DP0_DP_SEC_CNTL4
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L
+//DP0_DP_SEC_CNTL5
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L
+//DP0_DP_SEC_CNTL6
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL
+//DP0_DP_SEC_CNTL7
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L
+//DP0_DP_DB_CNTL
+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5
+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L
+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DP0_DP_MSA_VBID_MISC
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L
+//DP0_DP_SEC_METADATA_TRANSMISSION
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DP0_DP_DSC_BYTES_PER_PIXEL
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//DP0_DP_ALPM_CNTL
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+//DIG1_DIG_FE_CNTL
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG1_DIG_OUTPUT_CRC_CNTL
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG1_DIG_OUTPUT_CRC_RESULT
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG1_DIG_CLOCK_PATTERN
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG1_DIG_TEST_PATTERN
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG1_DIG_RANDOM_PATTERN_SEED
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG1_DIG_FIFO_STATUS
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG1_HDMI_METADATA_PACKET_CONTROL
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L
+//DIG1_HDMI_CONTROL
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG1_HDMI_STATUS
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG1_HDMI_AUDIO_PACKET_CONTROL
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG1_HDMI_ACR_PACKET_CONTROL
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG1_HDMI_VBI_PACKET_CONTROL
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG1_HDMI_INFOFRAME_CONTROL0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG1_HDMI_INFOFRAME_CONTROL1
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L
+//DIG1_HDMI_GC
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG1_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG1_AFMT_ISRC1_0
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG1_AFMT_ISRC1_1
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG1_AFMT_ISRC1_2
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG1_AFMT_ISRC1_3
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG1_AFMT_ISRC1_4
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG1_AFMT_ISRC2_0
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG1_AFMT_ISRC2_1
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG1_AFMT_ISRC2_2
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG1_AFMT_ISRC2_3
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L
+//DIG1_HDMI_DB_CONTROL
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DIG1_DME_CONTROL
+#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0
+#define DIG1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4
+#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8
+#define DIG1_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc
+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd
+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10
+#define DIG1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14
+#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L
+#define DIG1_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L
+#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L
+#define DIG1_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L
+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L
+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L
+#define DIG1_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L
+//DIG1_AFMT_MPEG_INFO0
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG1_AFMT_MPEG_INFO1
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG1_AFMT_GENERIC_HDR
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_0
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_1
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_2
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_3
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_4
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_5
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_6
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG1_AFMT_GENERIC_7
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L
+//DIG1_HDMI_ACR_32_0
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG1_HDMI_ACR_32_1
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG1_HDMI_ACR_44_0
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG1_HDMI_ACR_44_1
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG1_HDMI_ACR_48_0
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG1_HDMI_ACR_48_1
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG1_HDMI_ACR_STATUS_0
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG1_HDMI_ACR_STATUS_1
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG1_AFMT_AUDIO_INFO0
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG1_AFMT_AUDIO_INFO1
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG1_AFMT_60958_0
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG1_AFMT_60958_1
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG1_AFMT_AUDIO_CRC_CONTROL
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG1_AFMT_RAMP_CONTROL0
+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG1_AFMT_RAMP_CONTROL1
+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG1_AFMT_RAMP_CONTROL2
+#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG1_AFMT_RAMP_CONTROL3
+#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG1_AFMT_60958_2
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG1_AFMT_AUDIO_CRC_RESULT
+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG1_AFMT_STATUS
+#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG1_AFMT_AUDIO_PACKET_CONTROL
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L
+//DIG1_AFMT_VBI_PACKET_CONTROL
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L
+//DIG1_AFMT_INFOFRAME_CONTROL0
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG1_AFMT_AUDIO_SRC_CONTROL
+#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG1_DIG_BE_CNTL
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG1_DIG_BE_EN_CNTL
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG1_TMDS_CNTL
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG1_TMDS_CONTROL_CHAR
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG1_TMDS_CONTROL0_FEEDBACK
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG1_TMDS_STEREOSYNC_CTL_SEL
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG1_TMDS_CTL_BITS
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG1_TMDS_DCBALANCER_CONTROL
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG1_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L
+//DIG1_TMDS_CTL0_1_GEN_CNTL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG1_TMDS_CTL2_3_GEN_CNTL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG1_DIG_VERSION
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG1_DIG_LANE_ENABLE
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG1_AFMT_CNTL
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+//DIG1_AFMT_VBI_PACKET_CONTROL1
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L
+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L
+//DIG1_FORCE_DIG_DISABLE
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+//DP1_DP_LINK_CNTL
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP1_DP_PIXEL_FORMAT
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L
+//DP1_DP_MSA_COLORIMETRY
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L
+//DP1_DP_CONFIG
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP1_DP_VID_STREAM_CNTL
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP1_DP_STEER_FIFO
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP1_DP_MSA_MISC
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP1_DP_VID_TIMING
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP1_DP_VID_N
+#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP1_DP_VID_M
+#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP1_DP_LINK_FRAMING_CNTL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP1_DP_HBR2_EYE_PATTERN
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP1_DP_VID_MSA_VBID
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP1_DP_VID_INTERRUPT_CNTL
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP1_DP_DPHY_CNTL
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP1_DP_DPHY_SYM0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP1_DP_DPHY_SYM1
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP1_DP_DPHY_SYM2
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP1_DP_DPHY_8B10B_CNTL
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP1_DP_DPHY_PRBS_CNTL
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP1_DP_DPHY_SCRAM_CNTL
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP1_DP_DPHY_CRC_EN
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP1_DP_DPHY_CRC_CNTL
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP1_DP_DPHY_CRC_RESULT
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP1_DP_DPHY_CRC_MST_CNTL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP1_DP_DPHY_CRC_MST_STATUS
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP1_DP_DPHY_FAST_TRAINING
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP1_DP_DPHY_FAST_TRAINING_STATUS
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP1_DP_SEC_CNTL
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP1_DP_SEC_CNTL1
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP1_DP_SEC_FRAMING1
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP1_DP_SEC_FRAMING2
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP1_DP_SEC_FRAMING3
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP1_DP_SEC_FRAMING4
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP1_DP_SEC_AUD_N
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP1_DP_SEC_AUD_N_READBACK
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M_READBACK
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP1_DP_SEC_TIMESTAMP
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP1_DP_SEC_PACKET_CNTL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP1_DP_MSE_RATE_CNTL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP1_DP_MSE_RATE_UPDATE
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP1_DP_MSE_SAT0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP1_DP_MSE_SAT1
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP1_DP_MSE_SAT2
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP1_DP_MSE_SAT_UPDATE
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP1_DP_MSE_LINK_TIMING
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP1_DP_MSE_MISC_CNTL
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP1_DP_MSE_SAT0_STATUS
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP1_DP_MSE_SAT1_STATUS
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP1_DP_MSE_SAT2_STATUS
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+//DP1_DP_MSA_TIMING_PARAM1
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM2
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM3
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L
+//DP1_DP_MSA_TIMING_PARAM4
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L
+//DP1_DP_MSO_CNTL
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L
+//DP1_DP_MSO_CNTL1
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L
+//DP1_DP_DSC_CNTL
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//DP1_DP_SEC_CNTL2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L
+//DP1_DP_SEC_CNTL3
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L
+//DP1_DP_SEC_CNTL4
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L
+//DP1_DP_SEC_CNTL5
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L
+//DP1_DP_SEC_CNTL6
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL
+//DP1_DP_SEC_CNTL7
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L
+//DP1_DP_DB_CNTL
+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5
+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L
+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DP1_DP_MSA_VBID_MISC
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L
+//DP1_DP_SEC_METADATA_TRANSMISSION
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DP1_DP_DSC_BYTES_PER_PIXEL
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//DP1_DP_ALPM_CNTL
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+//DIG2_DIG_FE_CNTL
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG2_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG2_DIG_OUTPUT_CRC_CNTL
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG2_DIG_OUTPUT_CRC_RESULT
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG2_DIG_CLOCK_PATTERN
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG2_DIG_TEST_PATTERN
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG2_DIG_RANDOM_PATTERN_SEED
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG2_DIG_FIFO_STATUS
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG2_HDMI_METADATA_PACKET_CONTROL
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L
+//DIG2_HDMI_CONTROL
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG2_HDMI_STATUS
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG2_HDMI_AUDIO_PACKET_CONTROL
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG2_HDMI_ACR_PACKET_CONTROL
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG2_HDMI_VBI_PACKET_CONTROL
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG2_HDMI_INFOFRAME_CONTROL0
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG2_HDMI_INFOFRAME_CONTROL1
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L
+//DIG2_HDMI_GC
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG2_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG2_AFMT_ISRC1_0
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG2_AFMT_ISRC1_1
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG2_AFMT_ISRC1_2
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG2_AFMT_ISRC1_3
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG2_AFMT_ISRC1_4
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG2_AFMT_ISRC2_0
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG2_AFMT_ISRC2_1
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG2_AFMT_ISRC2_2
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG2_AFMT_ISRC2_3
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L
+//DIG2_HDMI_DB_CONTROL
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DIG2_DME_CONTROL
+#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0
+#define DIG2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4
+#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8
+#define DIG2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc
+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd
+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10
+#define DIG2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14
+#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L
+#define DIG2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L
+#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L
+#define DIG2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L
+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L
+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L
+#define DIG2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L
+//DIG2_AFMT_MPEG_INFO0
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG2_AFMT_MPEG_INFO1
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG2_AFMT_GENERIC_HDR
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_0
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_1
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_2
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_3
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_4
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_5
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_6
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG2_AFMT_GENERIC_7
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L
+//DIG2_HDMI_ACR_32_0
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG2_HDMI_ACR_32_1
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG2_HDMI_ACR_44_0
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG2_HDMI_ACR_44_1
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG2_HDMI_ACR_48_0
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG2_HDMI_ACR_48_1
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG2_HDMI_ACR_STATUS_0
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG2_HDMI_ACR_STATUS_1
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG2_AFMT_AUDIO_INFO0
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG2_AFMT_AUDIO_INFO1
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG2_AFMT_60958_0
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG2_AFMT_60958_1
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG2_AFMT_AUDIO_CRC_CONTROL
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG2_AFMT_RAMP_CONTROL0
+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG2_AFMT_RAMP_CONTROL1
+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG2_AFMT_RAMP_CONTROL2
+#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG2_AFMT_RAMP_CONTROL3
+#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG2_AFMT_60958_2
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG2_AFMT_AUDIO_CRC_RESULT
+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG2_AFMT_STATUS
+#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG2_AFMT_AUDIO_PACKET_CONTROL
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L
+//DIG2_AFMT_VBI_PACKET_CONTROL
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L
+//DIG2_AFMT_INFOFRAME_CONTROL0
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG2_AFMT_AUDIO_SRC_CONTROL
+#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG2_DIG_BE_CNTL
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG2_DIG_BE_EN_CNTL
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG2_TMDS_CNTL
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG2_TMDS_CONTROL_CHAR
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG2_TMDS_CONTROL0_FEEDBACK
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG2_TMDS_STEREOSYNC_CTL_SEL
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG2_TMDS_CTL_BITS
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG2_TMDS_DCBALANCER_CONTROL
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG2_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L
+//DIG2_TMDS_CTL0_1_GEN_CNTL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG2_TMDS_CTL2_3_GEN_CNTL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG2_DIG_VERSION
+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG2_DIG_LANE_ENABLE
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG2_AFMT_CNTL
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+//DIG2_AFMT_VBI_PACKET_CONTROL1
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L
+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L
+//DIG2_FORCE_DIG_DISABLE
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+//DP2_DP_LINK_CNTL
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP2_DP_PIXEL_FORMAT
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L
+//DP2_DP_MSA_COLORIMETRY
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L
+//DP2_DP_CONFIG
+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP2_DP_VID_STREAM_CNTL
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP2_DP_STEER_FIFO
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP2_DP_MSA_MISC
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP2_DP_VID_TIMING
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP2_DP_VID_N
+#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP2_DP_VID_M
+#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP2_DP_LINK_FRAMING_CNTL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP2_DP_HBR2_EYE_PATTERN
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP2_DP_VID_MSA_VBID
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP2_DP_VID_INTERRUPT_CNTL
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP2_DP_DPHY_CNTL
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP2_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP2_DP_DPHY_SYM0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP2_DP_DPHY_SYM1
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP2_DP_DPHY_SYM2
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP2_DP_DPHY_8B10B_CNTL
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP2_DP_DPHY_PRBS_CNTL
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP2_DP_DPHY_SCRAM_CNTL
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP2_DP_DPHY_CRC_EN
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP2_DP_DPHY_CRC_CNTL
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP2_DP_DPHY_CRC_RESULT
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP2_DP_DPHY_CRC_MST_CNTL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP2_DP_DPHY_CRC_MST_STATUS
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP2_DP_DPHY_FAST_TRAINING
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP2_DP_DPHY_FAST_TRAINING_STATUS
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP2_DP_SEC_CNTL
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP2_DP_SEC_CNTL1
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP2_DP_SEC_FRAMING1
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP2_DP_SEC_FRAMING2
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP2_DP_SEC_FRAMING3
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP2_DP_SEC_FRAMING4
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP2_DP_SEC_AUD_N
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP2_DP_SEC_AUD_N_READBACK
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M_READBACK
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP2_DP_SEC_TIMESTAMP
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP2_DP_SEC_PACKET_CNTL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP2_DP_MSE_RATE_CNTL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP2_DP_MSE_RATE_UPDATE
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP2_DP_MSE_SAT0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP2_DP_MSE_SAT1
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP2_DP_MSE_SAT2
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP2_DP_MSE_SAT_UPDATE
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP2_DP_MSE_LINK_TIMING
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP2_DP_MSE_MISC_CNTL
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP2_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP2_DP_MSE_SAT0_STATUS
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP2_DP_MSE_SAT1_STATUS
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP2_DP_MSE_SAT2_STATUS
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+//DP2_DP_MSA_TIMING_PARAM1
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM2
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM3
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L
+//DP2_DP_MSA_TIMING_PARAM4
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L
+//DP2_DP_MSO_CNTL
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L
+//DP2_DP_MSO_CNTL1
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L
+//DP2_DP_DSC_CNTL
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0
+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L
+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//DP2_DP_SEC_CNTL2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L
+//DP2_DP_SEC_CNTL3
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L
+//DP2_DP_SEC_CNTL4
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L
+//DP2_DP_SEC_CNTL5
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L
+//DP2_DP_SEC_CNTL6
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL
+//DP2_DP_SEC_CNTL7
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L
+//DP2_DP_DB_CNTL
+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5
+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L
+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DP2_DP_MSA_VBID_MISC
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L
+//DP2_DP_SEC_METADATA_TRANSMISSION
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DP2_DP_DSC_BYTES_PER_PIXEL
+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//DP2_DP_ALPM_CNTL
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+//DIG3_DIG_FE_CNTL
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG3_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG3_DIG_OUTPUT_CRC_CNTL
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG3_DIG_OUTPUT_CRC_RESULT
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG3_DIG_CLOCK_PATTERN
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG3_DIG_TEST_PATTERN
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG3_DIG_RANDOM_PATTERN_SEED
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG3_DIG_FIFO_STATUS
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG3_HDMI_METADATA_PACKET_CONTROL
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L
+//DIG3_HDMI_CONTROL
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG3_HDMI_STATUS
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG3_HDMI_AUDIO_PACKET_CONTROL
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG3_HDMI_ACR_PACKET_CONTROL
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG3_HDMI_VBI_PACKET_CONTROL
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG3_HDMI_INFOFRAME_CONTROL0
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG3_HDMI_INFOFRAME_CONTROL1
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L
+//DIG3_HDMI_GC
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG3_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG3_AFMT_ISRC1_0
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG3_AFMT_ISRC1_1
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG3_AFMT_ISRC1_2
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG3_AFMT_ISRC1_3
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG3_AFMT_ISRC1_4
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG3_AFMT_ISRC2_0
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG3_AFMT_ISRC2_1
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG3_AFMT_ISRC2_2
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG3_AFMT_ISRC2_3
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L
+//DIG3_HDMI_DB_CONTROL
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DIG3_DME_CONTROL
+#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0
+#define DIG3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4
+#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8
+#define DIG3_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc
+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd
+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10
+#define DIG3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14
+#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L
+#define DIG3_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L
+#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L
+#define DIG3_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L
+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L
+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L
+#define DIG3_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L
+//DIG3_AFMT_MPEG_INFO0
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG3_AFMT_MPEG_INFO1
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG3_AFMT_GENERIC_HDR
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_0
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_1
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_2
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_3
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_4
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_5
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_6
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG3_AFMT_GENERIC_7
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L
+//DIG3_HDMI_ACR_32_0
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG3_HDMI_ACR_32_1
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG3_HDMI_ACR_44_0
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG3_HDMI_ACR_44_1
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG3_HDMI_ACR_48_0
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG3_HDMI_ACR_48_1
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG3_HDMI_ACR_STATUS_0
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG3_HDMI_ACR_STATUS_1
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG3_AFMT_AUDIO_INFO0
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG3_AFMT_AUDIO_INFO1
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG3_AFMT_60958_0
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG3_AFMT_60958_1
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG3_AFMT_AUDIO_CRC_CONTROL
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG3_AFMT_RAMP_CONTROL0
+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG3_AFMT_RAMP_CONTROL1
+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG3_AFMT_RAMP_CONTROL2
+#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG3_AFMT_RAMP_CONTROL3
+#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG3_AFMT_60958_2
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG3_AFMT_AUDIO_CRC_RESULT
+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG3_AFMT_STATUS
+#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG3_AFMT_AUDIO_PACKET_CONTROL
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L
+//DIG3_AFMT_VBI_PACKET_CONTROL
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L
+//DIG3_AFMT_INFOFRAME_CONTROL0
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG3_AFMT_AUDIO_SRC_CONTROL
+#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG3_DIG_BE_CNTL
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG3_DIG_BE_EN_CNTL
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG3_TMDS_CNTL
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG3_TMDS_CONTROL_CHAR
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG3_TMDS_CONTROL0_FEEDBACK
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG3_TMDS_STEREOSYNC_CTL_SEL
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG3_TMDS_CTL_BITS
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG3_TMDS_DCBALANCER_CONTROL
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG3_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L
+//DIG3_TMDS_CTL0_1_GEN_CNTL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG3_TMDS_CTL2_3_GEN_CNTL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG3_DIG_VERSION
+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG3_DIG_LANE_ENABLE
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG3_AFMT_CNTL
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+//DIG3_AFMT_VBI_PACKET_CONTROL1
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L
+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L
+//DIG3_FORCE_DIG_DISABLE
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+//DP3_DP_LINK_CNTL
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP3_DP_PIXEL_FORMAT
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L
+//DP3_DP_MSA_COLORIMETRY
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L
+//DP3_DP_CONFIG
+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP3_DP_VID_STREAM_CNTL
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP3_DP_STEER_FIFO
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP3_DP_MSA_MISC
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP3_DP_VID_TIMING
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP3_DP_VID_N
+#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP3_DP_VID_M
+#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP3_DP_LINK_FRAMING_CNTL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP3_DP_HBR2_EYE_PATTERN
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP3_DP_VID_MSA_VBID
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP3_DP_VID_INTERRUPT_CNTL
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP3_DP_DPHY_CNTL
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP3_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP3_DP_DPHY_SYM0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP3_DP_DPHY_SYM1
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP3_DP_DPHY_SYM2
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP3_DP_DPHY_8B10B_CNTL
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP3_DP_DPHY_PRBS_CNTL
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP3_DP_DPHY_SCRAM_CNTL
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP3_DP_DPHY_CRC_EN
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP3_DP_DPHY_CRC_CNTL
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP3_DP_DPHY_CRC_RESULT
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP3_DP_DPHY_CRC_MST_CNTL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP3_DP_DPHY_CRC_MST_STATUS
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP3_DP_DPHY_FAST_TRAINING
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP3_DP_DPHY_FAST_TRAINING_STATUS
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP3_DP_SEC_CNTL
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP3_DP_SEC_CNTL1
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP3_DP_SEC_FRAMING1
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP3_DP_SEC_FRAMING2
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP3_DP_SEC_FRAMING3
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP3_DP_SEC_FRAMING4
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP3_DP_SEC_AUD_N
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP3_DP_SEC_AUD_N_READBACK
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M_READBACK
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP3_DP_SEC_TIMESTAMP
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP3_DP_SEC_PACKET_CNTL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP3_DP_MSE_RATE_CNTL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP3_DP_MSE_RATE_UPDATE
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP3_DP_MSE_SAT0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP3_DP_MSE_SAT1
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP3_DP_MSE_SAT2
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP3_DP_MSE_SAT_UPDATE
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP3_DP_MSE_LINK_TIMING
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP3_DP_MSE_MISC_CNTL
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP3_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP3_DP_MSE_SAT0_STATUS
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP3_DP_MSE_SAT1_STATUS
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP3_DP_MSE_SAT2_STATUS
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+//DP3_DP_MSA_TIMING_PARAM1
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM2
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM3
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L
+//DP3_DP_MSA_TIMING_PARAM4
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L
+//DP3_DP_MSO_CNTL
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L
+//DP3_DP_MSO_CNTL1
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L
+//DP3_DP_DSC_CNTL
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0
+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L
+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//DP3_DP_SEC_CNTL2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L
+//DP3_DP_SEC_CNTL3
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L
+//DP3_DP_SEC_CNTL4
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L
+//DP3_DP_SEC_CNTL5
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L
+//DP3_DP_SEC_CNTL6
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL
+//DP3_DP_SEC_CNTL7
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L
+//DP3_DP_DB_CNTL
+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5
+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L
+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DP3_DP_MSA_VBID_MISC
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L
+//DP3_DP_SEC_METADATA_TRANSMISSION
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DP3_DP_DSC_BYTES_PER_PIXEL
+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//DP3_DP_ALPM_CNTL
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig4_dispdec
+//DIG4_DIG_FE_CNTL
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG4_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG4_DIG_OUTPUT_CRC_CNTL
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG4_DIG_OUTPUT_CRC_RESULT
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG4_DIG_CLOCK_PATTERN
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG4_DIG_TEST_PATTERN
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG4_DIG_RANDOM_PATTERN_SEED
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG4_DIG_FIFO_STATUS
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG4_HDMI_METADATA_PACKET_CONTROL
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L
+//DIG4_HDMI_CONTROL
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG4_HDMI_STATUS
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG4_HDMI_AUDIO_PACKET_CONTROL
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG4_HDMI_ACR_PACKET_CONTROL
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG4_HDMI_VBI_PACKET_CONTROL
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG4_HDMI_INFOFRAME_CONTROL0
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG4_HDMI_INFOFRAME_CONTROL1
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L
+//DIG4_HDMI_GC
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG4_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG4_AFMT_ISRC1_0
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG4_AFMT_ISRC1_1
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG4_AFMT_ISRC1_2
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG4_AFMT_ISRC1_3
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG4_AFMT_ISRC1_4
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG4_AFMT_ISRC2_0
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG4_AFMT_ISRC2_1
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG4_AFMT_ISRC2_2
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG4_AFMT_ISRC2_3
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L
+//DIG4_HDMI_DB_CONTROL
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DIG4_DME_CONTROL
+#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0
+#define DIG4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4
+#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8
+#define DIG4_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc
+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd
+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10
+#define DIG4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14
+#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L
+#define DIG4_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L
+#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L
+#define DIG4_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L
+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L
+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L
+#define DIG4_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L
+//DIG4_AFMT_MPEG_INFO0
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG4_AFMT_MPEG_INFO1
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG4_AFMT_GENERIC_HDR
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_0
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_1
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_2
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_3
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_4
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_5
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_6
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG4_AFMT_GENERIC_7
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L
+//DIG4_HDMI_ACR_32_0
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG4_HDMI_ACR_32_1
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG4_HDMI_ACR_44_0
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG4_HDMI_ACR_44_1
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG4_HDMI_ACR_48_0
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG4_HDMI_ACR_48_1
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG4_HDMI_ACR_STATUS_0
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG4_HDMI_ACR_STATUS_1
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG4_AFMT_AUDIO_INFO0
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG4_AFMT_AUDIO_INFO1
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG4_AFMT_60958_0
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG4_AFMT_60958_1
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG4_AFMT_AUDIO_CRC_CONTROL
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG4_AFMT_RAMP_CONTROL0
+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG4_AFMT_RAMP_CONTROL1
+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG4_AFMT_RAMP_CONTROL2
+#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG4_AFMT_RAMP_CONTROL3
+#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG4_AFMT_60958_2
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG4_AFMT_AUDIO_CRC_RESULT
+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG4_AFMT_STATUS
+#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG4_AFMT_AUDIO_PACKET_CONTROL
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L
+//DIG4_AFMT_VBI_PACKET_CONTROL
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L
+//DIG4_AFMT_INFOFRAME_CONTROL0
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG4_AFMT_AUDIO_SRC_CONTROL
+#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG4_DIG_BE_CNTL
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG4_DIG_BE_EN_CNTL
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG4_TMDS_CNTL
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG4_TMDS_CONTROL_CHAR
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG4_TMDS_CONTROL0_FEEDBACK
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG4_TMDS_STEREOSYNC_CTL_SEL
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG4_TMDS_CTL_BITS
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG4_TMDS_DCBALANCER_CONTROL
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG4_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L
+//DIG4_TMDS_CTL0_1_GEN_CNTL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG4_TMDS_CTL2_3_GEN_CNTL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG4_DIG_VERSION
+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG4_DIG_LANE_ENABLE
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG4_AFMT_CNTL
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+//DIG4_AFMT_VBI_PACKET_CONTROL1
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L
+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L
+//DIG4_FORCE_DIG_DISABLE
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp4_dispdec
+//DP4_DP_LINK_CNTL
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP4_DP_PIXEL_FORMAT
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L
+//DP4_DP_MSA_COLORIMETRY
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L
+//DP4_DP_CONFIG
+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP4_DP_VID_STREAM_CNTL
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP4_DP_STEER_FIFO
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP4_DP_MSA_MISC
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP4_DP_VID_TIMING
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP4_DP_VID_N
+#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP4_DP_VID_M
+#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP4_DP_LINK_FRAMING_CNTL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP4_DP_HBR2_EYE_PATTERN
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP4_DP_VID_MSA_VBID
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP4_DP_VID_INTERRUPT_CNTL
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP4_DP_DPHY_CNTL
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP4_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP4_DP_DPHY_SYM0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP4_DP_DPHY_SYM1
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP4_DP_DPHY_SYM2
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP4_DP_DPHY_8B10B_CNTL
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP4_DP_DPHY_PRBS_CNTL
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP4_DP_DPHY_SCRAM_CNTL
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP4_DP_DPHY_CRC_EN
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP4_DP_DPHY_CRC_CNTL
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP4_DP_DPHY_CRC_RESULT
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP4_DP_DPHY_CRC_MST_CNTL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP4_DP_DPHY_CRC_MST_STATUS
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP4_DP_DPHY_FAST_TRAINING
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP4_DP_DPHY_FAST_TRAINING_STATUS
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP4_DP_SEC_CNTL
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP4_DP_SEC_CNTL1
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP4_DP_SEC_FRAMING1
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP4_DP_SEC_FRAMING2
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP4_DP_SEC_FRAMING3
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP4_DP_SEC_FRAMING4
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP4_DP_SEC_AUD_N
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP4_DP_SEC_AUD_N_READBACK
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP4_DP_SEC_AUD_M
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP4_DP_SEC_AUD_M_READBACK
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP4_DP_SEC_TIMESTAMP
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP4_DP_SEC_PACKET_CNTL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP4_DP_MSE_RATE_CNTL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP4_DP_MSE_RATE_UPDATE
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP4_DP_MSE_SAT0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP4_DP_MSE_SAT1
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP4_DP_MSE_SAT2
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP4_DP_MSE_SAT_UPDATE
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP4_DP_MSE_LINK_TIMING
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP4_DP_MSE_MISC_CNTL
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP4_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP4_DP_MSE_SAT0_STATUS
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP4_DP_MSE_SAT1_STATUS
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP4_DP_MSE_SAT2_STATUS
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+//DP4_DP_MSA_TIMING_PARAM1
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM2
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM3
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L
+//DP4_DP_MSA_TIMING_PARAM4
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L
+//DP4_DP_MSO_CNTL
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L
+//DP4_DP_MSO_CNTL1
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L
+//DP4_DP_DSC_CNTL
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0
+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L
+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//DP4_DP_SEC_CNTL2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L
+//DP4_DP_SEC_CNTL3
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L
+//DP4_DP_SEC_CNTL4
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L
+//DP4_DP_SEC_CNTL5
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L
+//DP4_DP_SEC_CNTL6
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL
+//DP4_DP_SEC_CNTL7
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L
+//DP4_DP_DB_CNTL
+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5
+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L
+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DP4_DP_MSA_VBID_MISC
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L
+//DP4_DP_SEC_METADATA_TRANSMISSION
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DP4_DP_DSC_BYTES_PER_PIXEL
+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//DP4_DP_ALPM_CNTL
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dio_dig5_dispdec
+//DIG5_DIG_FE_CNTL
+#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG5_DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG5_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc
+#define DIG5_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10
+#define DIG5_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12
+#define DIG5_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13
+#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
+#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
+#define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
+#define DIG5_DIG_FE_CNTL__DIG_START_MASK 0x00000400L
+#define DIG5_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L
+#define DIG5_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L
+#define DIG5_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L
+#define DIG5_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L
+#define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
+#define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L
+#define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L
+//DIG5_DIG_OUTPUT_CRC_CNTL
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
+#define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
+//DIG5_DIG_OUTPUT_CRC_RESULT
+#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL
+//DIG5_DIG_CLOCK_PATTERN
+#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL
+//DIG5_DIG_TEST_PATTERN
+#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
+#define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
+#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
+#define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
+#define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
+#define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L
+//DIG5_DIG_RANDOM_PATTERN_SEED
+#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL
+#define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
+//DIG5_DIG_FIFO_STATUS
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
+#define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
+//DIG5_HDMI_METADATA_PACKET_CONTROL
+#define DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4
+#define DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8
+#define DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10
+#define DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L
+#define DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L
+#define DIG5_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DIG5_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L
+//DIG5_HDMI_CONTROL
+#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
+#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
+#define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L
+#define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L
+#define DIG5_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L
+#define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
+#define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
+#define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
+#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
+#define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
+//DIG5_HDMI_STATUS
+#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define DIG5_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
+#define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
+#define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
+#define DIG5_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
+//DIG5_HDMI_AUDIO_PACKET_CONTROL
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L
+#define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L
+//DIG5_HDMI_ACR_PACKET_CONTROL
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
+#define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
+//DIG5_HDMI_VBI_PACKET_CONTROL
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
+#define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L
+//DIG5_HDMI_INFOFRAME_CONTROL0
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
+#define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
+//DIG5_HDMI_INFOFRAME_CONTROL1
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L
+#define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L
+//DIG5_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L
+//DIG5_HDMI_GC
+#define DIG5_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define DIG5_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
+#define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
+#define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
+#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L
+#define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
+//DIG5_AFMT_AUDIO_PACKET_CONTROL2
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
+//DIG5_AFMT_ISRC1_0
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
+#define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
+//DIG5_AFMT_ISRC1_1
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L
+//DIG5_AFMT_ISRC1_2
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L
+//DIG5_AFMT_ISRC1_3
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L
+//DIG5_AFMT_ISRC1_4
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L
+//DIG5_AFMT_ISRC2_0
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L
+//DIG5_AFMT_ISRC2_1
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L
+//DIG5_AFMT_ISRC2_2
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L
+//DIG5_AFMT_ISRC2_3
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L
+#define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L
+//DIG5_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L
+//DIG5_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L
+//DIG5_HDMI_DB_CONTROL
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc
+#define DIG5_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf
+#define DIG5_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DIG5_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L
+#define DIG5_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L
+#define DIG5_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DIG5_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DIG5_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DIG5_DME_CONTROL
+#define DIG5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0
+#define DIG5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4
+#define DIG5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8
+#define DIG5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc
+#define DIG5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd
+#define DIG5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10
+#define DIG5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14
+#define DIG5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L
+#define DIG5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L
+#define DIG5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L
+#define DIG5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L
+#define DIG5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L
+#define DIG5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L
+#define DIG5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L
+//DIG5_AFMT_MPEG_INFO0
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L
+#define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L
+//DIG5_AFMT_MPEG_INFO1
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
+#define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
+//DIG5_AFMT_GENERIC_HDR
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_0
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_1
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_2
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_3
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_4
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_5
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_6
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L
+//DIG5_AFMT_GENERIC_7
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L
+#define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L
+//DIG5_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L
+//DIG5_HDMI_ACR_32_0
+#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L
+//DIG5_HDMI_ACR_32_1
+#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL
+//DIG5_HDMI_ACR_44_0
+#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L
+//DIG5_HDMI_ACR_44_1
+#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL
+//DIG5_HDMI_ACR_48_0
+#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L
+//DIG5_HDMI_ACR_48_1
+#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL
+//DIG5_HDMI_ACR_STATUS_0
+#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L
+//DIG5_HDMI_ACR_STATUS_1
+#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL
+//DIG5_AFMT_AUDIO_INFO0
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L
+#define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L
+//DIG5_AFMT_AUDIO_INFO1
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
+#define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
+//DIG5_AFMT_60958_0
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L
+#define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
+//DIG5_AFMT_60958_1
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L
+#define DIG5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
+#define DIG5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
+#define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L
+//DIG5_AFMT_AUDIO_CRC_CONTROL
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L
+#define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L
+//DIG5_AFMT_RAMP_CONTROL0
+#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL
+#define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
+//DIG5_AFMT_RAMP_CONTROL1
+#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL
+#define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L
+//DIG5_AFMT_RAMP_CONTROL2
+#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL
+//DIG5_AFMT_RAMP_CONTROL3
+#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL
+//DIG5_AFMT_60958_2
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L
+#define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L
+//DIG5_AFMT_AUDIO_CRC_RESULT
+#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
+#define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L
+//DIG5_AFMT_STATUS
+#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
+#define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
+#define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
+#define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
+//DIG5_AFMT_AUDIO_PACKET_CONTROL
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
+#define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L
+//DIG5_AFMT_VBI_PACKET_CONTROL
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L
+//DIG5_AFMT_INFOFRAME_CONTROL0
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
+#define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
+//DIG5_AFMT_AUDIO_SRC_CONTROL
+#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
+//DIG5_DIG_BE_CNTL
+#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG5_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG5_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
+#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG5_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L
+#define DIG5_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L
+#define DIG5_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L
+#define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L
+#define DIG5_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
+#define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
+//DIG5_DIG_BE_EN_CNTL
+#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
+#define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
+//DIG5_TMDS_CNTL
+#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
+//DIG5_TMDS_CONTROL_CHAR
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
+#define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
+//DIG5_TMDS_CONTROL0_FEEDBACK
+#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
+#define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
+//DIG5_TMDS_STEREOSYNC_CTL_SEL
+#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
+//DIG5_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L
+//DIG5_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL
+#define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L
+//DIG5_TMDS_CTL_BITS
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
+#define DIG5_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
+//DIG5_TMDS_DCBALANCER_CONTROL
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L
+#define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
+//DIG5_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG5_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0
+#define DIG5_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10
+#define DIG5_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL
+#define DIG5_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L
+//DIG5_TMDS_CTL0_1_GEN_CNTL
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
+#define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
+//DIG5_TMDS_CTL2_3_GEN_CNTL
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
+#define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
+//DIG5_DIG_VERSION
+#define DIG5_DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG5_DIG_VERSION__DIG_TYPE_MASK 0x00000001L
+//DIG5_DIG_LANE_ENABLE
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
+#define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
+#define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
+//DIG5_AFMT_CNTL
+#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L
+#define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L
+//DIG5_AFMT_VBI_PACKET_CONTROL1
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L
+#define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L
+//DIG5_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L
+#define DIG5_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L
+//DIG5_FORCE_DIG_DISABLE
+#define DIG5_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0
+#define DIG5_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp5_dispdec
+//DP5_DP_LINK_CNTL
+#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP5_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
+#define DP5_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
+#define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
+//DP5_DP_PIXEL_FORMAT
+#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c
+#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L
+#define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
+#define DP5_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L
+//DP5_DP_MSA_COLORIMETRY
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18
+#define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L
+//DP5_DP_CONFIG
+#define DP5_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP5_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
+//DP5_DP_VID_STREAM_CNTL
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
+#define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
+//DP5_DP_STEER_FIFO
+#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
+#define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
+#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
+#define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
+//DP5_DP_MSA_MISC
+#define DP5_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0
+#define DP5_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP5_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP5_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP5_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL
+#define DP5_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L
+#define DP5_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L
+#define DP5_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L
+//DP5_DP_VID_TIMING
+#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP5_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa
+#define DP5_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc
+#define DP5_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L
+#define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
+#define DP5_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L
+#define DP5_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L
+#define DP5_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L
+//DP5_DP_VID_N
+#define DP5_DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP5_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL
+//DP5_DP_VID_M
+#define DP5_DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP5_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL
+//DP5_DP_LINK_FRAMING_CNTL
+#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL
+#define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
+#define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
+//DP5_DP_HBR2_EYE_PATTERN
+#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
+//DP5_DP_VID_MSA_VBID
+#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL
+#define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
+//DP5_DP_VID_INTERRUPT_CNTL
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
+#define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
+//DP5_DP_DPHY_CNTL
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP5_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4
+#define DP5_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5
+#define DP5_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6
+#define DP5_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
+#define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
+#define DP5_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L
+#define DP5_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L
+#define DP5_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L
+#define DP5_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
+#define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
+//DP5_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
+//DP5_DP_DPHY_SYM0
+#define DP5_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP5_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP5_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP5_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL
+#define DP5_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L
+#define DP5_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L
+//DP5_DP_DPHY_SYM1
+#define DP5_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP5_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP5_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP5_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL
+#define DP5_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L
+#define DP5_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L
+//DP5_DP_DPHY_SYM2
+#define DP5_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP5_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP5_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL
+#define DP5_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L
+//DP5_DP_DPHY_8B10B_CNTL
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
+#define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
+//DP5_DP_DPHY_PRBS_CNTL
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
+#define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L
+//DP5_DP_DPHY_SCRAM_CNTL
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L
+#define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L
+//DP5_DP_DPHY_CRC_EN
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
+#define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
+//DP5_DP_DPHY_CRC_CNTL
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
+#define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L
+//DP5_DP_DPHY_CRC_RESULT
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L
+#define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L
+//DP5_DP_DPHY_CRC_MST_CNTL
+#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL
+#define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L
+//DP5_DP_DPHY_CRC_MST_STATUS
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
+#define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
+//DP5_DP_DPHY_FAST_TRAINING
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L
+#define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L
+//DP5_DP_DPHY_FAST_TRAINING_STATUS
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
+#define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
+//DP5_DP_SEC_CNTL
+#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b
+#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
+#define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
+#define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
+#define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
+#define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L
+#define DP5_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L
+#define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
+//DP5_DP_SEC_CNTL1
+#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L
+#define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L
+//DP5_DP_SEC_FRAMING1
+#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL
+#define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP5_DP_SEC_FRAMING2
+#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL
+#define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP5_DP_SEC_FRAMING3
+#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL
+#define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L
+//DP5_DP_SEC_FRAMING4
+#define DP5_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0
+#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP5_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L
+#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
+#define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
+#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
+#define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
+//DP5_DP_SEC_AUD_N
+#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL
+//DP5_DP_SEC_AUD_N_READBACK
+#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL
+//DP5_DP_SEC_AUD_M
+#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL
+//DP5_DP_SEC_AUD_M_READBACK
+#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL
+//DP5_DP_SEC_TIMESTAMP
+#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
+//DP5_DP_SEC_PACKET_CNTL
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L
+#define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
+//DP5_DP_MSE_RATE_CNTL
+#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL
+#define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L
+//DP5_DP_MSE_RATE_UPDATE
+#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
+//DP5_DP_MSE_SAT0
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
+#define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L
+//DP5_DP_MSE_SAT1
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
+#define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L
+//DP5_DP_MSE_SAT2
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
+#define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L
+//DP5_DP_MSE_SAT_UPDATE
+#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
+#define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
+//DP5_DP_MSE_LINK_TIMING
+#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL
+#define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
+//DP5_DP_MSE_MISC_CNTL
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
+#define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
+//DP5_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L
+#define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L
+//DP5_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L
+//DP5_DP_MSE_SAT0_STATUS
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L
+#define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L
+//DP5_DP_MSE_SAT1_STATUS
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L
+#define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L
+//DP5_DP_MSE_SAT2_STATUS
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L
+#define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L
+//DP5_DP_MSA_TIMING_PARAM1
+#define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0
+#define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10
+#define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL
+#define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L
+//DP5_DP_MSA_TIMING_PARAM2
+#define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0
+#define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10
+#define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL
+#define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L
+//DP5_DP_MSA_TIMING_PARAM3
+#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0
+#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf
+#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10
+#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f
+#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL
+#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L
+#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L
+#define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L
+//DP5_DP_MSA_TIMING_PARAM4
+#define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0
+#define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10
+#define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL
+#define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L
+//DP5_DP_MSO_CNTL
+#define DP5_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c
+#define DP5_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L
+#define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L
+//DP5_DP_MSO_CNTL1
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L
+#define DP5_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L
+//DP5_DP_DSC_CNTL
+#define DP5_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0
+#define DP5_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10
+#define DP5_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L
+#define DP5_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L
+//DP5_DP_SEC_CNTL2
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L
+#define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L
+//DP5_DP_SEC_CNTL3
+#define DP5_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0
+#define DP5_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10
+#define DP5_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL
+#define DP5_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L
+//DP5_DP_SEC_CNTL4
+#define DP5_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0
+#define DP5_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10
+#define DP5_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL
+#define DP5_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L
+//DP5_DP_SEC_CNTL5
+#define DP5_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0
+#define DP5_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10
+#define DP5_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL
+#define DP5_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L
+//DP5_DP_SEC_CNTL6
+#define DP5_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0
+#define DP5_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL
+//DP5_DP_SEC_CNTL7
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L
+#define DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L
+//DP5_DP_DB_CNTL
+#define DP5_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0
+#define DP5_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4
+#define DP5_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5
+#define DP5_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8
+#define DP5_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc
+#define DP5_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf
+#define DP5_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10
+#define DP5_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11
+#define DP5_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L
+#define DP5_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L
+#define DP5_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L
+#define DP5_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L
+#define DP5_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L
+#define DP5_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L
+#define DP5_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L
+#define DP5_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L
+//DP5_DP_MSA_VBID_MISC
+#define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4
+#define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8
+#define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9
+#define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc
+#define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd
+#define DP5_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf
+#define DP5_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10
+#define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L
+#define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L
+#define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L
+#define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L
+#define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L
+#define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L
+#define DP5_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L
+#define DP5_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L
+//DP5_DP_SEC_METADATA_TRANSMISSION
+#define DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0
+#define DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1
+#define DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4
+#define DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10
+#define DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L
+#define DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L
+#define DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L
+#define DP5_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L
+//DP5_DP_DSC_BYTES_PER_PIXEL
+#define DP5_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0
+#define DP5_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL
+//DP5_DP_ALPM_CNTL
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4
+#define DP5_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L
+#define DP5_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L
+#define DP5_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L
+//UNIPHYA_LINK_CNTL
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYB_LINK_CNTL
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYC_LINK_CNTL
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYD_LINK_CNTL
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYE_LINK_CNTL
+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYE_CHANNEL_XBAR_CNTL
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//UNIPHYF_LINK_CNTL
+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L
+//UNIPHYF_CHANNEL_XBAR_CNTL
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4
+#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc
+#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18
+#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0x000000F0L
+#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0x00000F00L
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L
+#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0x000E0000L
+//LVTMA_PWRSEQ_CNTL
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L
+//LVTMA_PWRSEQ_STATE
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000F00L
+//LVTMA_PWRSEQ_REF_DIV
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000FFFL
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xFFFF0000L
+//LVTMA_PWRSEQ_DELAY1
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000FFL
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000FF00L
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00FF0000L
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xFF000000L
+//LVTMA_PWRSEQ_DELAY2
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000FFL
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000FF00L
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00FF0000L
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L
+//BL_PWM_CNTL
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L
+#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L
+//BL_PWM_CNTL2
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L
+//BL_PWM_PERIOD_CNTL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L
+//BL_PWM_GRP1_REG_LOCK
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000E0000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd
+#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14
+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18
+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L
+#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00010000L
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x00100000L
+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x01000000L
+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x04000000L
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC5_MASK
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC5_A
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC5_EN
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC5_Y
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDC6_MASK
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
+#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L
+#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDC6_A
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L
+//DC_GPIO_DDC6_EN
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L
+//DC_GPIO_DDC6_Y
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x00000002L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x00000004L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x00000008L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x00000008L
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x00000010L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x00000080L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L
+//DC_GPIO_PWRSEQ_MASK
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x000000C0L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00C00000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x01000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x02000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x04000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000L
+//DC_GPIO_PWRSEQ_A
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x01000000L
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000L
+//DC_GPIO_PWRSEQ_EN
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x01000000L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000L
+//DC_GPIO_PWRSEQ_Y
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x01000000L
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0x00000F00L
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0x0000F000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0x8
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14
+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT 0x17
+#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT 0x18
+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT 0x1c
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x00000001L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x00000002L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x00000004L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x00000008L
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x00000010L
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x00000020L
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x00000040L
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x00000080L
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x00000100L
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L
+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK 0x00800000L
+#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK 0x03000000L
+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK 0x70000000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x00000001L
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x00000004L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xc
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00001000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0x40000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13
+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT 0x14
+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT 0x15
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT 0x16
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L
+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L
+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT 0x14
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT 0x15
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT 0x16
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK 0x00100000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK 0x00200000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK 0x00400000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy5_dispdec
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy6_dispdec
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+//DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+//DSC_TOP0_DSC_TOP_CONTROL
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L
+//DSC_TOP0_DSC_DEBUG_CONTROL
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+//DSCCIF0_DSCCIF_CONFIG0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+//DSCCIF0_DSCCIF_CONFIG1
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+//DSCC0_DSCC_CONFIG0
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L
+//DSCC0_DSCC_CONFIG1
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L
+//DSCC0_DSCC_STATUS
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L
+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L
+//DSCC0_DSCC_PPS_CONFIG0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG1
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG2
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG3
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG4
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG5
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG6
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L
+//DSCC0_DSCC_PPS_CONFIG7
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG8
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG9
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG11
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG12
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG13
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG14
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG15
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG16
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG17
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG18
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG19
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG20
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG21
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG22
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L
+//DSCC0_DSCC_MEM_POWER_CONTROL
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC0_DSCC_MAX_ABS_ERROR0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L
+//DSCC0_DSCC_MAX_ABS_ERROR1
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL
+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON21_PERFCOUNTER_CNTL
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON21_PERFCOUNTER_CNTL2
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON21_PERFCOUNTER_STATE
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON21_PERFMON_CNTL
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON21_PERFMON_CNTL2
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON21_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON21_PERFMON_CVALUE_LOW
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON21_PERFMON_HI
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON21_PERFMON_LOW
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+//DSC_TOP1_DSC_TOP_CONTROL
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L
+//DSC_TOP1_DSC_DEBUG_CONTROL
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+//DSCCIF1_DSCCIF_CONFIG0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+//DSCCIF1_DSCCIF_CONFIG1
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+//DSCC1_DSCC_CONFIG0
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L
+//DSCC1_DSCC_CONFIG1
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L
+//DSCC1_DSCC_STATUS
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L
+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L
+//DSCC1_DSCC_PPS_CONFIG0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG1
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG2
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG3
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG4
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG5
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG6
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L
+//DSCC1_DSCC_PPS_CONFIG7
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG8
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG9
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG11
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG12
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG13
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG14
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG15
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG16
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG17
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG18
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG19
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG20
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG21
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG22
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L
+//DSCC1_DSCC_MEM_POWER_CONTROL
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC1_DSCC_MAX_ABS_ERROR0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L
+//DSCC1_DSCC_MAX_ABS_ERROR1
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL
+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON22_PERFCOUNTER_CNTL
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON22_PERFCOUNTER_CNTL2
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON22_PERFCOUNTER_STATE
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON22_PERFMON_CNTL
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON22_PERFMON_CNTL2
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON22_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON22_PERFMON_CVALUE_LOW
+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON22_PERFMON_HI
+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON22_PERFMON_LOW
+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+//DSC_TOP2_DSC_TOP_CONTROL
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L
+//DSC_TOP2_DSC_DEBUG_CONTROL
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+//DSCCIF2_DSCCIF_CONFIG0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+//DSCCIF2_DSCCIF_CONFIG1
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+//DSCC2_DSCC_CONFIG0
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L
+//DSCC2_DSCC_CONFIG1
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L
+//DSCC2_DSCC_STATUS
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L
+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L
+//DSCC2_DSCC_PPS_CONFIG0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG1
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG2
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG3
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG4
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG5
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG6
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L
+//DSCC2_DSCC_PPS_CONFIG7
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG8
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG9
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG11
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG12
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG13
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG14
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG15
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG16
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG17
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG18
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG19
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG20
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG21
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG22
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L
+//DSCC2_DSCC_MEM_POWER_CONTROL
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC2_DSCC_MAX_ABS_ERROR0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L
+//DSCC2_DSCC_MAX_ABS_ERROR1
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL
+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON23_PERFCOUNTER_CNTL
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON23_PERFCOUNTER_CNTL2
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON23_PERFCOUNTER_STATE
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON23_PERFMON_CNTL
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON23_PERFMON_CNTL2
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON23_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON23_PERFMON_CVALUE_LOW
+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON23_PERFMON_HI
+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON23_PERFMON_LOW
+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
+//DSC_TOP3_DSC_TOP_CONTROL
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L
+//DSC_TOP3_DSC_DEBUG_CONTROL
+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4
+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L
+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
+//DSCCIF3_DSCCIF_CONFIG0
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+//DSCCIF3_DSCCIF_CONFIG1
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
+//DSCC3_DSCC_CONFIG0
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L
+//DSCC3_DSCC_CONFIG1
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L
+//DSCC3_DSCC_STATUS
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L
+//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L
+//DSCC3_DSCC_PPS_CONFIG0
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L
+//DSCC3_DSCC_PPS_CONFIG1
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG2
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG3
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG4
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG5
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG6
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L
+//DSCC3_DSCC_PPS_CONFIG7
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG8
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG9
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG10
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG11
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L
+//DSCC3_DSCC_PPS_CONFIG12
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG13
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG14
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG15
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG16
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG17
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG18
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG19
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG20
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG21
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG22
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L
+//DSCC3_DSCC_MEM_POWER_CONTROL
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L
+//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC3_DSCC_MAX_ABS_ERROR0
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L
+//DSCC3_DSCC_MAX_ABS_ERROR1
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL
+//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0
+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8
+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10
+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18
+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL
+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L
+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L
+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON24_PERFCOUNTER_CNTL
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON24_PERFCOUNTER_CNTL2
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON24_PERFCOUNTER_STATE
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON24_PERFMON_CNTL
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON24_PERFMON_CNTL2
+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON24_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON24_PERFMON_CVALUE_LOW
+#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON24_PERFMON_HI
+#define DC_PERFMON24_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON24_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON24_PERFMON_LOW
+#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
+//DSC_TOP4_DSC_TOP_CONTROL
+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0
+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8
+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L
+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L
+//DSC_TOP4_DSC_DEBUG_CONTROL
+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4
+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L
+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L
+
+
+// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
+//DSCCIF4_DSCCIF_CONFIG0
+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0
+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4
+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8
+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc
+#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10
+#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L
+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L
+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L
+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L
+#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L
+#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+//DSCCIF4_DSCCIF_CONFIG1
+#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0
+#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10
+#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
+//DSCC4_DSCC_CONFIG0
+#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4
+#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8
+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10
+#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L
+#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L
+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L
+//DSCC4_DSCC_CONFIG1
+#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0
+#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18
+#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL
+#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L
+//DSCC4_DSCC_STATUS
+#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0
+#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L
+//DSCC4_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L
+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L
+//DSCC4_DSCC_PPS_CONFIG0
+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4
+#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8
+#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18
+#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c
+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL
+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L
+#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L
+#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L
+#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L
+//DSCC4_DSCC_PPS_CONFIG1
+#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa
+#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb
+#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc
+#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd
+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe
+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf
+#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL
+#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L
+#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L
+#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L
+#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L
+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L
+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L
+#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L
+//DSCC4_DSCC_PPS_CONFIG2
+#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L
+//DSCC4_DSCC_PPS_CONFIG3
+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL
+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L
+//DSCC4_DSCC_PPS_CONFIG4
+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL
+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L
+//DSCC4_DSCC_PPS_CONFIG5
+#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL
+#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L
+//DSCC4_DSCC_PPS_CONFIG6
+#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18
+#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL
+#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L
+//DSCC4_DSCC_PPS_CONFIG7
+#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L
+//DSCC4_DSCC_PPS_CONFIG8
+#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L
+//DSCC4_DSCC_PPS_CONFIG9
+#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL
+#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L
+//DSCC4_DSCC_PPS_CONFIG10
+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8
+#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL
+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L
+#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L
+//DSCC4_DSCC_PPS_CONFIG11
+#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8
+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18
+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c
+#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL
+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L
+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L
+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L
+//DSCC4_DSCC_PPS_CONFIG12
+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8
+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18
+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL
+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L
+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L
+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L
+//DSCC4_DSCC_PPS_CONFIG13
+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8
+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18
+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL
+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L
+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L
+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L
+//DSCC4_DSCC_PPS_CONFIG14
+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8
+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18
+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL
+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L
+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L
+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L
+//DSCC4_DSCC_PPS_CONFIG15
+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8
+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15
+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a
+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL
+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L
+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L
+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L
+//DSCC4_DSCC_PPS_CONFIG16
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L
+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L
+//DSCC4_DSCC_PPS_CONFIG17
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L
+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L
+//DSCC4_DSCC_PPS_CONFIG18
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L
+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L
+//DSCC4_DSCC_PPS_CONFIG19
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L
+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L
+//DSCC4_DSCC_PPS_CONFIG20
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L
+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L
+//DSCC4_DSCC_PPS_CONFIG21
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L
+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L
+//DSCC4_DSCC_PPS_CONFIG22
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L
+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L
+//DSCC4_DSCC_MEM_POWER_CONTROL
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L
+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L
+//DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC4_DSCC_MAX_ABS_ERROR0
+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10
+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL
+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L
+//DSCC4_DSCC_MAX_ABS_ERROR1
+#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL
+//DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0
+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8
+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10
+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18
+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL
+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L
+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L
+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L
+
+
+// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON25_PERFCOUNTER_CNTL
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON25_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON25_PERFCOUNTER_CNTL2
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON25_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON25_PERFCOUNTER_STATE
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON25_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON25_PERFMON_CNTL
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON25_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON25_PERFMON_CNTL2
+#define DC_PERFMON25_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON25_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON25_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON25_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON25_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON25_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON25_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON25_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON25_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON25_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON25_PERFMON_CVALUE_LOW
+#define DC_PERFMON25_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON25_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON25_PERFMON_HI
+#define DC_PERFMON25_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON25_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON25_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON25_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON25_PERFMON_LOW
+#define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec
+//DSC_TOP5_DSC_TOP_CONTROL
+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0
+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4
+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8
+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L
+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L
+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L
+//DSC_TOP5_DSC_DEBUG_CONTROL
+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0
+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4
+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L
+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L
+
+
+// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec
+//DSCCIF5_DSCCIF_CONFIG0
+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0
+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4
+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8
+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc
+#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10
+#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18
+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L
+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L
+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L
+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L
+#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L
+#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L
+//DSCCIF5_DSCCIF_CONFIG1
+#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0
+#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10
+#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec
+//DSCC5_DSCC_CONFIG0
+#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4
+#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8
+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10
+#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L
+#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L
+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L
+//DSCC5_DSCC_CONFIG1
+#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0
+#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18
+#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL
+#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L
+//DSCC5_DSCC_STATUS
+#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0
+#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L
+//DSCC5_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L
+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L
+//DSCC5_DSCC_PPS_CONFIG0
+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4
+#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8
+#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18
+#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c
+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL
+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L
+#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L
+#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L
+#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L
+//DSCC5_DSCC_PPS_CONFIG1
+#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa
+#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb
+#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc
+#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd
+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe
+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf
+#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL
+#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L
+#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L
+#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L
+#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L
+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L
+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L
+#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L
+//DSCC5_DSCC_PPS_CONFIG2
+#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL
+#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L
+//DSCC5_DSCC_PPS_CONFIG3
+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL
+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L
+//DSCC5_DSCC_PPS_CONFIG4
+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL
+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L
+//DSCC5_DSCC_PPS_CONFIG5
+#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL
+#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L
+//DSCC5_DSCC_PPS_CONFIG6
+#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18
+#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL
+#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L
+//DSCC5_DSCC_PPS_CONFIG7
+#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L
+//DSCC5_DSCC_PPS_CONFIG8
+#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL
+#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L
+//DSCC5_DSCC_PPS_CONFIG9
+#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL
+#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L
+//DSCC5_DSCC_PPS_CONFIG10
+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8
+#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL
+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L
+#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L
+//DSCC5_DSCC_PPS_CONFIG11
+#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8
+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18
+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c
+#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL
+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L
+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L
+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L
+//DSCC5_DSCC_PPS_CONFIG12
+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8
+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18
+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL
+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L
+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L
+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L
+//DSCC5_DSCC_PPS_CONFIG13
+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8
+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18
+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL
+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L
+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L
+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L
+//DSCC5_DSCC_PPS_CONFIG14
+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8
+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18
+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL
+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L
+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L
+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L
+//DSCC5_DSCC_PPS_CONFIG15
+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8
+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15
+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a
+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL
+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L
+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L
+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L
+//DSCC5_DSCC_PPS_CONFIG16
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L
+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L
+//DSCC5_DSCC_PPS_CONFIG17
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L
+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L
+//DSCC5_DSCC_PPS_CONFIG18
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L
+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L
+//DSCC5_DSCC_PPS_CONFIG19
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L
+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L
+//DSCC5_DSCC_PPS_CONFIG20
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L
+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L
+//DSCC5_DSCC_PPS_CONFIG21
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L
+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L
+//DSCC5_DSCC_PPS_CONFIG22
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L
+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L
+//DSCC5_DSCC_MEM_POWER_CONTROL
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L
+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L
+//DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0
+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL
+//DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0
+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL
+//DSCC5_DSCC_MAX_ABS_ERROR0
+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10
+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL
+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L
+//DSCC5_DSCC_MAX_ABS_ERROR1
+#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0
+#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL
+//DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0
+#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL
+//DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0
+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8
+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10
+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18
+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL
+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L
+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L
+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L
+
+
+// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON26_PERFCOUNTER_CNTL
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON26_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON26_PERFCOUNTER_CNTL2
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON26_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON26_PERFCOUNTER_STATE
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON26_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON26_PERFMON_CNTL
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON26_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON26_PERFMON_CNTL2
+#define DC_PERFMON26_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON26_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON26_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON26_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON26_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON26_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON26_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON26_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON26_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON26_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON26_PERFMON_CVALUE_LOW
+#define DC_PERFMON26_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON26_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON26_PERFMON_HI
+#define DC_PERFMON26_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON26_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON26_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON26_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON26_PERFMON_LOW
+#define DC_PERFMON26_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON26_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+//DMCUB_REGION0_OFFSET
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT 0x8
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION0_OFFSET_HIGH
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION1_OFFSET
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT 0x8
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION1_OFFSET_HIGH
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION2_OFFSET
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT 0x8
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION2_OFFSET_HIGH
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION4_OFFSET
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT 0x8
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION4_OFFSET_HIGH
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION5_OFFSET
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT 0x8
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION5_OFFSET_HIGH
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION6_OFFSET
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT 0x8
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION6_OFFSET_HIGH
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION7_OFFSET
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT 0x8
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION7_OFFSET_HIGH
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION0_TOP_ADDRESS
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK 0x80000000L
+//DMCUB_REGION1_TOP_ADDRESS
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK 0x80000000L
+//DMCUB_REGION2_TOP_ADDRESS
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK 0x80000000L
+//DMCUB_REGION4_TOP_ADDRESS
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK 0x80000000L
+//DMCUB_REGION5_TOP_ADDRESS
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK 0x80000000L
+//DMCUB_REGION6_TOP_ADDRESS
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK 0x80000000L
+//DMCUB_REGION7_TOP_ADDRESS
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK 0x80000000L
+//DMCUB_REGION3_CW0_BASE_ADDRESS
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK 0x1FFFFFFFL
+//DMCUB_REGION3_CW1_BASE_ADDRESS
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK 0x1FFFFFFFL
+//DMCUB_REGION3_CW2_BASE_ADDRESS
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK 0x1FFFFFFFL
+//DMCUB_REGION3_CW3_BASE_ADDRESS
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK 0x1FFFFFFFL
+//DMCUB_REGION3_CW4_BASE_ADDRESS
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK 0x1FFFFFFFL
+//DMCUB_REGION3_CW5_BASE_ADDRESS
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK 0x1FFFFFFFL
+//DMCUB_REGION3_CW6_BASE_ADDRESS
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK 0x1FFFFFFFL
+//DMCUB_REGION3_CW7_BASE_ADDRESS
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK 0x1FFFFFFFL
+//DMCUB_REGION3_CW0_TOP_ADDRESS
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK 0x80000000L
+//DMCUB_REGION3_CW1_TOP_ADDRESS
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK 0x80000000L
+//DMCUB_REGION3_CW2_TOP_ADDRESS
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK 0x80000000L
+//DMCUB_REGION3_CW3_TOP_ADDRESS
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK 0x80000000L
+//DMCUB_REGION3_CW4_TOP_ADDRESS
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK 0x80000000L
+//DMCUB_REGION3_CW5_TOP_ADDRESS
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK 0x80000000L
+//DMCUB_REGION3_CW6_TOP_ADDRESS
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK 0x80000000L
+//DMCUB_REGION3_CW7_TOP_ADDRESS
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT 0x0
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT 0x1f
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK 0x1FFFFFFFL
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK 0x80000000L
+//DMCUB_REGION3_CW0_OFFSET
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT 0x8
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION3_CW0_OFFSET_HIGH
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION3_CW1_OFFSET
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT 0x8
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION3_CW1_OFFSET_HIGH
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION3_CW2_OFFSET
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT 0x8
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION3_CW2_OFFSET_HIGH
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION3_CW3_OFFSET
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT 0x8
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION3_CW3_OFFSET_HIGH
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION3_CW4_OFFSET
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT 0x8
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION3_CW4_OFFSET_HIGH
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION3_CW5_OFFSET
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT 0x8
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION3_CW5_OFFSET_HIGH
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION3_CW6_OFFSET
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT 0x8
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION3_CW6_OFFSET_HIGH
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_REGION3_CW7_OFFSET
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT 0x8
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK 0xFFFFFF00L
+//DMCUB_REGION3_CW7_OFFSET_HIGH
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT 0x0
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK 0x0000FFFFL
+//DMCUB_INTERRUPT_ENABLE
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT 0x0
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT 0x1
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT 0x2
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT 0x3
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT 0x4
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT 0x5
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT 0x6
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT 0x7
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT 0x8
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT 0x9
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT 0xa
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0xd
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK 0x00000008L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK 0x00000010L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK 0x00000020L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK 0x00000040L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK 0x00000080L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK 0x00000100L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK 0x00000200L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK 0x00000400L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00002000L
+//DMCUB_INTERRUPT_ACK
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT 0x2
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT 0x3
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT 0x4
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT 0x5
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT 0x6
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT 0x7
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT 0x8
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT 0x9
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT 0xa
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0xd
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK 0x00000008L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK 0x00000010L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK 0x00000020L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK 0x00000040L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK 0x00000080L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK 0x00000100L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK 0x00000200L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK 0x00000400L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00002000L
+//DMCUB_INTERRUPT_STATUS
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT 0x2
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT 0x3
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT 0x4
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT 0x5
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT 0x6
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT 0x7
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT 0x8
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT 0x9
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT 0xa
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT 0xb
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT 0xc
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT 0xd
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT 0xe
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT 0xf
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK 0x00000001L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK 0x00000002L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK 0x00000004L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK 0x00000008L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK 0x00000010L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK 0x00000020L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK 0x00000040L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK 0x00000080L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK 0x00000100L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK 0x00000200L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK 0x00000400L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK 0x00000800L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK 0x00001000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK 0x00002000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK 0x00004000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK 0x00008000L
+//DMCUB_INTERRUPT_TYPE
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT 0x0
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT 0x1
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT 0x2
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT 0x3
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT 0x4
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT 0x5
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT 0x6
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT 0x7
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT 0x8
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT 0x9
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT 0xa
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT 0xb
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT 0xc
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT 0xd
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK 0x00000001L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK 0x00000002L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK 0x00000004L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK 0x00000008L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK 0x00000010L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK 0x00000020L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK 0x00000040L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK 0x00000080L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK 0x00000100L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK 0x00000200L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK 0x00000400L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK 0x00000800L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK 0x00001000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK 0x00002000L
+//DMCUB_EXT_INTERRUPT_STATUS
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT 0x0
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT 0x8
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK 0x000000FFL
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK 0x0000FF00L
+//DMCUB_EXT_INTERRUPT_CTXID
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT 0x0
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK 0x0FFFFFFFL
+//DMCUB_EXT_INTERRUPT_ACK
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT 0x0
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK 0x00000001L
+//DMCUB_INST_FETCH_FAULT_ADDR
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT 0x0
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK 0xFFFFFFFFL
+//DMCUB_DATA_WRITE_FAULT_ADDR
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT 0x0
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK 0xFFFFFFFFL
+//DMCUB_SEC_CNTL
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT 0x0
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT 0x8
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT 0x10
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT 0x11
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT 0x14
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT 0x15
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT 0x18
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT 0x19
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK 0x00000007L
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK 0x00003F00L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK 0x00010000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK 0x00020000L
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK 0x00100000L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK 0x00200000L
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK 0x01000000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK 0x02000000L
+//DMCUB_MEM_CNTL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT 0x0
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT 0x4
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE__SHIFT 0x8
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE__SHIFT 0xc
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK 0x0000000FL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK 0x000000F0L
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE_MASK 0x00000700L
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE_MASK 0x00007000L
+//DMCUB_INBOX0_BASE_ADDRESS
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//DMCUB_INBOX0_SIZE
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT 0x0
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK 0xFFFFFFFFL
+//DMCUB_INBOX0_WPTR
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT 0x0
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK 0xFFFFFFFFL
+//DMCUB_INBOX0_RPTR
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT 0x0
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK 0xFFFFFFFFL
+//DMCUB_INBOX1_BASE_ADDRESS
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//DMCUB_INBOX1_SIZE
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT 0x0
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK 0xFFFFFFFFL
+//DMCUB_INBOX1_WPTR
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT 0x0
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK 0xFFFFFFFFL
+//DMCUB_INBOX1_RPTR
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT 0x0
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK 0xFFFFFFFFL
+//DMCUB_OUTBOX0_BASE_ADDRESS
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//DMCUB_OUTBOX0_SIZE
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT 0x0
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK 0xFFFFFFFFL
+//DMCUB_OUTBOX0_WPTR
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT 0x0
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK 0xFFFFFFFFL
+//DMCUB_OUTBOX0_RPTR
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT 0x0
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK 0xFFFFFFFFL
+//DMCUB_OUTBOX1_BASE_ADDRESS
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT 0x0
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//DMCUB_OUTBOX1_SIZE
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT 0x0
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK 0xFFFFFFFFL
+//DMCUB_OUTBOX1_WPTR
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT 0x0
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK 0xFFFFFFFFL
+//DMCUB_OUTBOX1_RPTR
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT 0x0
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK 0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT 0x0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK 0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER1
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT 0x0
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK 0xFFFFFFFFL
+//DMCUB_TIMER_WINDOW
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT 0x0
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK 0x00000007L
+//DMCUB_SCRATCH0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT 0x0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH1
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT 0x0
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH2
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT 0x0
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH3
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT 0x0
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH4
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT 0x0
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH5
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT 0x0
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH6
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT 0x0
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH7
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT 0x0
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH8
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT 0x0
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH9
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT 0x0
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH10
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT 0x0
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH11
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT 0x0
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH12
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT 0x0
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH13
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT 0x0
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH14
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT 0x0
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK 0xFFFFFFFFL
+//DMCUB_SCRATCH15
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT 0x0
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK 0xFFFFFFFFL
+//DMCUB_CNTL
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT 0x0
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT 0x8
+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT 0x10
+#define DMCUB_CNTL__DMCUB_SOFT_RESET__SHIFT 0x11
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT 0x12
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT 0x13
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT 0x14
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK 0x000000FFL
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK 0x00000100L
+#define DMCUB_CNTL__DMCUB_ENABLE_MASK 0x00010000L
+#define DMCUB_CNTL__DMCUB_SOFT_RESET_MASK 0x00020000L
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK 0x00040000L
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK 0x00080000L
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK 0x00100000L
+//DMCUB_GPINT_DATAIN0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT 0x0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK 0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN1
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT 0x0
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK 0xFFFFFFFFL
+//DMCUB_GPINT_DATAOUT
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT 0x0
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK 0xFFFFFFFFL
+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT 0x0
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK 0xFFFFFFFFL
+//DMCUB_LS_WAKE_INT_ENABLE
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT 0x0
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK 0xFFFFFFFFL
+//DMCUB_MEM_PWR_CNTL
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT 0x1
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT 0x3
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT 0x4
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK 0x00000006L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK 0x00000008L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK 0x00000030L
+//DMCUB_TIMER_CURRENT
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT 0x0
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK 0xFFFFFFFFL
+//DMCUB_PROC_ID
+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT 0x0
+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK 0x0000FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec
+//MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L
+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L
+//MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R
+#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL
+//MCIF_WB2_MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L
+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L
+//MCIF_WB2_MCIF_WB_BUF_PITCH
+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L
+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L
+//MCIF_WB2_MCIF_WB_BUF_1_STATUS
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB2_MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB2_MCIF_WB_BUF_2_STATUS
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB2_MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB2_MCIF_WB_BUF_3_STATUS
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB2_MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB2_MCIF_WB_BUF_4_STATUS
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L
+//MCIF_WB2_MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L
+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L
+//MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16
+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L
+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L
+//MCIF_WB2_MCIF_WB_SCLK_CHANGE
+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL
+//MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX
+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA
+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL
+//MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L
+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L
+//MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0007FFFFL
+//MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L
+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L
+//MCIF_WB2_MCIF_WB_WATERMARK
+#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL
+//MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L
+//MCIF_WB2_MCIF_WB_WARM_UP_CNTL
+#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8
+#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L
+//MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1
+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L
+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L
+//MCIF_WB2_MULTI_LEVEL_QOS_CTRL
+#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
+#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+//MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
+//MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL
+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL
+//MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+//MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+//MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+//MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0
+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10
+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL
+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp0_dispdec
+//XFCP0_MMHUBBUB_XFC_CNTL
+#define XFCP0_MMHUBBUB_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define XFCP0_MMHUBBUB_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define XFCP0_MMHUBBUB_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define XFCP0_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define XFCP0_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define XFCP0_MMHUBBUB_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define XFCP0_MMHUBBUB_XFC_CNTL__MY_GPUID__SHIFT 0x10
+#define XFCP0_MMHUBBUB_XFC_CNTL__TARGET_PID__SHIFT 0x14
+#define XFCP0_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID__SHIFT 0x18
+#define XFCP0_MMHUBBUB_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define XFCP0_MMHUBBUB_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define XFCP0_MMHUBBUB_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define XFCP0_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define XFCP0_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define XFCP0_MMHUBBUB_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define XFCP0_MMHUBBUB_XFC_CNTL__MY_GPUID_MASK 0x00070000L
+#define XFCP0_MMHUBBUB_XFC_CNTL__TARGET_PID_MASK 0x00F00000L
+#define XFCP0_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID_MASK 0x07000000L
+//XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB
+#define XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB__SHIFT 0x0
+#define XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB
+#define XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB__SHIFT 0x0
+#define XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB
+#define XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB__SHIFT 0x0
+#define XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB
+#define XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB__SHIFT 0x0
+#define XFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP0_MMHUBBUB_XFC_XBUF_CONFIG
+#define XFCP0_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE__SHIFT 0x0
+#define XFCP0_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH__SHIFT 0x10
+#define XFCP0_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE_MASK 0x0000001FL
+#define XFCP0_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH_MASK 0x3FFF0000L
+//XFCP0_MMHUBBUB_XFC_XBUF_SIZE
+#define XFCP0_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH__SHIFT 0x0
+#define XFCP0_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT__SHIFT 0x10
+#define XFCP0_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH_MASK 0x00003FFFL
+#define XFCP0_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT_MASK 0x3FFF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp1_dispdec
+//XFCP1_MMHUBBUB_XFC_CNTL
+#define XFCP1_MMHUBBUB_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define XFCP1_MMHUBBUB_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define XFCP1_MMHUBBUB_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define XFCP1_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define XFCP1_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define XFCP1_MMHUBBUB_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define XFCP1_MMHUBBUB_XFC_CNTL__MY_GPUID__SHIFT 0x10
+#define XFCP1_MMHUBBUB_XFC_CNTL__TARGET_PID__SHIFT 0x14
+#define XFCP1_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID__SHIFT 0x18
+#define XFCP1_MMHUBBUB_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define XFCP1_MMHUBBUB_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define XFCP1_MMHUBBUB_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define XFCP1_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define XFCP1_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define XFCP1_MMHUBBUB_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define XFCP1_MMHUBBUB_XFC_CNTL__MY_GPUID_MASK 0x00070000L
+#define XFCP1_MMHUBBUB_XFC_CNTL__TARGET_PID_MASK 0x00F00000L
+#define XFCP1_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID_MASK 0x07000000L
+//XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB
+#define XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB__SHIFT 0x0
+#define XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB
+#define XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB__SHIFT 0x0
+#define XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB
+#define XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB__SHIFT 0x0
+#define XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB
+#define XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB__SHIFT 0x0
+#define XFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP1_MMHUBBUB_XFC_XBUF_CONFIG
+#define XFCP1_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE__SHIFT 0x0
+#define XFCP1_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH__SHIFT 0x10
+#define XFCP1_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE_MASK 0x0000001FL
+#define XFCP1_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH_MASK 0x3FFF0000L
+//XFCP1_MMHUBBUB_XFC_XBUF_SIZE
+#define XFCP1_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH__SHIFT 0x0
+#define XFCP1_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT__SHIFT 0x10
+#define XFCP1_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH_MASK 0x00003FFFL
+#define XFCP1_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT_MASK 0x3FFF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp2_dispdec
+//XFCP2_MMHUBBUB_XFC_CNTL
+#define XFCP2_MMHUBBUB_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define XFCP2_MMHUBBUB_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define XFCP2_MMHUBBUB_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define XFCP2_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define XFCP2_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define XFCP2_MMHUBBUB_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define XFCP2_MMHUBBUB_XFC_CNTL__MY_GPUID__SHIFT 0x10
+#define XFCP2_MMHUBBUB_XFC_CNTL__TARGET_PID__SHIFT 0x14
+#define XFCP2_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID__SHIFT 0x18
+#define XFCP2_MMHUBBUB_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define XFCP2_MMHUBBUB_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define XFCP2_MMHUBBUB_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define XFCP2_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define XFCP2_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define XFCP2_MMHUBBUB_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define XFCP2_MMHUBBUB_XFC_CNTL__MY_GPUID_MASK 0x00070000L
+#define XFCP2_MMHUBBUB_XFC_CNTL__TARGET_PID_MASK 0x00F00000L
+#define XFCP2_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID_MASK 0x07000000L
+//XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB
+#define XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB__SHIFT 0x0
+#define XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB
+#define XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB__SHIFT 0x0
+#define XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB
+#define XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB__SHIFT 0x0
+#define XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB
+#define XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB__SHIFT 0x0
+#define XFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP2_MMHUBBUB_XFC_XBUF_CONFIG
+#define XFCP2_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE__SHIFT 0x0
+#define XFCP2_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH__SHIFT 0x10
+#define XFCP2_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE_MASK 0x0000001FL
+#define XFCP2_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH_MASK 0x3FFF0000L
+//XFCP2_MMHUBBUB_XFC_XBUF_SIZE
+#define XFCP2_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH__SHIFT 0x0
+#define XFCP2_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT__SHIFT 0x10
+#define XFCP2_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH_MASK 0x00003FFFL
+#define XFCP2_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT_MASK 0x3FFF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp3_dispdec
+//XFCP3_MMHUBBUB_XFC_CNTL
+#define XFCP3_MMHUBBUB_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define XFCP3_MMHUBBUB_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define XFCP3_MMHUBBUB_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define XFCP3_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define XFCP3_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define XFCP3_MMHUBBUB_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define XFCP3_MMHUBBUB_XFC_CNTL__MY_GPUID__SHIFT 0x10
+#define XFCP3_MMHUBBUB_XFC_CNTL__TARGET_PID__SHIFT 0x14
+#define XFCP3_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID__SHIFT 0x18
+#define XFCP3_MMHUBBUB_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define XFCP3_MMHUBBUB_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define XFCP3_MMHUBBUB_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define XFCP3_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define XFCP3_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define XFCP3_MMHUBBUB_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define XFCP3_MMHUBBUB_XFC_CNTL__MY_GPUID_MASK 0x00070000L
+#define XFCP3_MMHUBBUB_XFC_CNTL__TARGET_PID_MASK 0x00F00000L
+#define XFCP3_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID_MASK 0x07000000L
+//XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB
+#define XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB__SHIFT 0x0
+#define XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB
+#define XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB__SHIFT 0x0
+#define XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB
+#define XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB__SHIFT 0x0
+#define XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB
+#define XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB__SHIFT 0x0
+#define XFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP3_MMHUBBUB_XFC_XBUF_CONFIG
+#define XFCP3_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE__SHIFT 0x0
+#define XFCP3_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH__SHIFT 0x10
+#define XFCP3_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE_MASK 0x0000001FL
+#define XFCP3_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH_MASK 0x3FFF0000L
+//XFCP3_MMHUBBUB_XFC_XBUF_SIZE
+#define XFCP3_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH__SHIFT 0x0
+#define XFCP3_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT__SHIFT 0x10
+#define XFCP3_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH_MASK 0x00003FFFL
+#define XFCP3_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT_MASK 0x3FFF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp4_dispdec
+//XFCP4_MMHUBBUB_XFC_CNTL
+#define XFCP4_MMHUBBUB_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define XFCP4_MMHUBBUB_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define XFCP4_MMHUBBUB_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define XFCP4_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define XFCP4_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define XFCP4_MMHUBBUB_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define XFCP4_MMHUBBUB_XFC_CNTL__MY_GPUID__SHIFT 0x10
+#define XFCP4_MMHUBBUB_XFC_CNTL__TARGET_PID__SHIFT 0x14
+#define XFCP4_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID__SHIFT 0x18
+#define XFCP4_MMHUBBUB_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define XFCP4_MMHUBBUB_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define XFCP4_MMHUBBUB_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define XFCP4_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define XFCP4_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define XFCP4_MMHUBBUB_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define XFCP4_MMHUBBUB_XFC_CNTL__MY_GPUID_MASK 0x00070000L
+#define XFCP4_MMHUBBUB_XFC_CNTL__TARGET_PID_MASK 0x00F00000L
+#define XFCP4_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID_MASK 0x07000000L
+//XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB
+#define XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB__SHIFT 0x0
+#define XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB
+#define XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB__SHIFT 0x0
+#define XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB
+#define XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB__SHIFT 0x0
+#define XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB
+#define XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB__SHIFT 0x0
+#define XFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP4_MMHUBBUB_XFC_XBUF_CONFIG
+#define XFCP4_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE__SHIFT 0x0
+#define XFCP4_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH__SHIFT 0x10
+#define XFCP4_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE_MASK 0x0000001FL
+#define XFCP4_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH_MASK 0x3FFF0000L
+//XFCP4_MMHUBBUB_XFC_XBUF_SIZE
+#define XFCP4_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH__SHIFT 0x0
+#define XFCP4_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT__SHIFT 0x10
+#define XFCP4_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH_MASK 0x00003FFFL
+#define XFCP4_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT_MASK 0x3FFF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_xfcp5_dispdec
+//XFCP5_MMHUBBUB_XFC_CNTL
+#define XFCP5_MMHUBBUB_XFC_CNTL__MXFC_ENABLE__SHIFT 0x0
+#define XFCP5_MMHUBBUB_XFC_CNTL__SXFC_ENABLE__SHIFT 0x1
+#define XFCP5_MMHUBBUB_XFC_CNTL__PIXEL_64BPP__SHIFT 0x4
+#define XFCP5_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT 0x5
+#define XFCP5_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE__SHIFT 0x6
+#define XFCP5_MMHUBBUB_XFC_CNTL__ALPHA_POSITION__SHIFT 0x7
+#define XFCP5_MMHUBBUB_XFC_CNTL__MY_GPUID__SHIFT 0x10
+#define XFCP5_MMHUBBUB_XFC_CNTL__TARGET_PID__SHIFT 0x14
+#define XFCP5_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID__SHIFT 0x18
+#define XFCP5_MMHUBBUB_XFC_CNTL__MXFC_ENABLE_MASK 0x00000001L
+#define XFCP5_MMHUBBUB_XFC_CNTL__SXFC_ENABLE_MASK 0x00000002L
+#define XFCP5_MMHUBBUB_XFC_CNTL__PIXEL_64BPP_MASK 0x00000010L
+#define XFCP5_MMHUBBUB_XFC_CNTL__XBUF_FULL_ENABLE_MASK 0x00000020L
+#define XFCP5_MMHUBBUB_XFC_CNTL__BW_REDUCTION_MODE_MASK 0x00000040L
+#define XFCP5_MMHUBBUB_XFC_CNTL__ALPHA_POSITION_MASK 0x00000080L
+#define XFCP5_MMHUBBUB_XFC_CNTL__MY_GPUID_MASK 0x00070000L
+#define XFCP5_MMHUBBUB_XFC_CNTL__TARGET_PID_MASK 0x00F00000L
+#define XFCP5_MMHUBBUB_XFC_CNTL__SLV2MST_GPUID_MASK 0x07000000L
+//XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB
+#define XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB__SHIFT 0x0
+#define XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB__XBUF_WR_BASE0_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB
+#define XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB__SHIFT 0x0
+#define XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB__XBUF_WR_BASE0_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB
+#define XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB__SHIFT 0x0
+#define XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB__XBUF_WR_BASE1_ADDR_LSB_MASK 0xFFFFFFFFL
+//XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB
+#define XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB__SHIFT 0x0
+#define XFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB__XBUF_WR_BASE1_ADDR_MSB_MASK 0x0000FFFFL
+//XFCP5_MMHUBBUB_XFC_XBUF_CONFIG
+#define XFCP5_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE__SHIFT 0x0
+#define XFCP5_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH__SHIFT 0x10
+#define XFCP5_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_SW_MODE_MASK 0x0000001FL
+#define XFCP5_MMHUBBUB_XFC_XBUF_CONFIG__XBUF_WR_PITCH_MASK 0x3FFF0000L
+//XFCP5_MMHUBBUB_XFC_XBUF_SIZE
+#define XFCP5_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH__SHIFT 0x0
+#define XFCP5_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT__SHIFT 0x10
+#define XFCP5_MMHUBBUB_XFC_XBUF_SIZE__XBUF_WIDTH_MASK 0x00003FFFL
+#define XFCP5_MMHUBBUB_XFC_XBUF_SIZE__XBUF_HEIGHT_MASK 0x3FFF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_xfc_dispdec
+//XFC_MEM_PWR_CNTL
+#define XFC_MEM_PWR_CNTL__XFC_MEM_PWR_FORCE__SHIFT 0x0
+#define XFC_MEM_PWR_CNTL__XFC_MEM_PWR_DIS__SHIFT 0x2
+#define XFC_MEM_PWR_CNTL__XFC_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define XFC_MEM_PWR_CNTL__XFC_MEM_PWR_STATE__SHIFT 0x1e
+#define XFC_MEM_PWR_CNTL__XFC_MEM_PWR_FORCE_MASK 0x00000003L
+#define XFC_MEM_PWR_CNTL__XFC_MEM_PWR_DIS_MASK 0x00000004L
+#define XFC_MEM_PWR_CNTL__XFC_MEM_PWR_MODE_SEL_MASK 0x00000030L
+#define XFC_MEM_PWR_CNTL__XFC_MEM_PWR_STATE_MASK 0xC0000000L
+//MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_NUM_SE__SHIFT 0x0
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_NUM_PIPE__SHIFT 0x4
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_NUM_BANK__SHIFT 0x8
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_PIPE_INTERLEAVE__SHIFT 0xc
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_DIM_TYPE__SHIFT 0x10
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_NUM_SE_MASK 0x00000003L
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_NUM_PIPE_MASK 0x00000070L
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_NUM_BANK_MASK 0x00000700L
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_PIPE_INTERLEAVE_MASK 0x00003000L
+#define MMHUBBUB_XFC_XBUF_WR_SURF_CONFIG__XBUF_SW_DIM_TYPE_MASK 0x00030000L
+//MMHUBBUB_XFC_XBUF_WR_CONFIG
+#define MMHUBBUB_XFC_XBUF_WR_CONFIG__XBUF_WR_VMID__SHIFT 0x0
+#define MMHUBBUB_XFC_XBUF_WR_CONFIG__XBUF_WR_AWCACHE__SHIFT 0x4
+#define MMHUBBUB_XFC_XBUF_WR_CONFIG__XBUF_WR_URG_WATERMARK__SHIFT 0x10
+#define MMHUBBUB_XFC_XBUF_WR_CONFIG__XBUF_WR_STALL_TIMER__SHIFT 0x18
+#define MMHUBBUB_XFC_XBUF_WR_CONFIG__XBUF_WR_VMID_MASK 0x0000000FL
+#define MMHUBBUB_XFC_XBUF_WR_CONFIG__XBUF_WR_AWCACHE_MASK 0x000000F0L
+#define MMHUBBUB_XFC_XBUF_WR_CONFIG__XBUF_WR_URG_WATERMARK_MASK 0x00FF0000L
+#define MMHUBBUB_XFC_XBUF_WR_CONFIG__XBUF_WR_STALL_TIMER_MASK 0xFF000000L
+//MMHUBBUB_XFC_IO_BACKPRESSURE_RELEASE_TIMER
+#define MMHUBBUB_XFC_IO_BACKPRESSURE_RELEASE_TIMER__XFC_IO_BACKPRESSURE_RELEASE_TIMER__SHIFT 0x0
+#define MMHUBBUB_XFC_IO_BACKPRESSURE_RELEASE_TIMER__XFC_IO_BACKPRESSURE_RELEASE_TIMER_MASK 0x0000FFFFL
+//MMHUBBUB_XFC_GPU_CTRL
+#define MMHUBBUB_XFC_GPU_CTRL__GPU_WR_QOS__SHIFT 0x0
+#define MMHUBBUB_XFC_GPU_CTRL__GPU_WR_CACHE__SHIFT 0x4
+#define MMHUBBUB_XFC_GPU_CTRL__GPU_WR_USER__SHIFT 0x8
+#define MMHUBBUB_XFC_GPU_CTRL__XIOARB_TERMINATE_ON_BUBBLE__SHIFT 0x9
+#define MMHUBBUB_XFC_GPU_CTRL__XFC_LOOPBACK_ENABLE__SHIFT 0xc
+#define MMHUBBUB_XFC_GPU_CTRL__XFC_LOOPBACK_MODE__SHIFT 0xd
+#define MMHUBBUB_XFC_GPU_CTRL__XFC_SYSHUB_BRESP_FLAG__SHIFT 0x10
+#define MMHUBBUB_XFC_GPU_CTRL__XFC_SYSHUB_BRESP_ACK__SHIFT 0x14
+#define MMHUBBUB_XFC_GPU_CTRL__SYSHUB_SLVWR_RESP_THLD__SHIFT 0x18
+#define MMHUBBUB_XFC_GPU_CTRL__GPU_WR_QOS_MASK 0x0000000FL
+#define MMHUBBUB_XFC_GPU_CTRL__GPU_WR_CACHE_MASK 0x000000F0L
+#define MMHUBBUB_XFC_GPU_CTRL__GPU_WR_USER_MASK 0x00000100L
+#define MMHUBBUB_XFC_GPU_CTRL__XIOARB_TERMINATE_ON_BUBBLE_MASK 0x00000200L
+#define MMHUBBUB_XFC_GPU_CTRL__XFC_LOOPBACK_ENABLE_MASK 0x00001000L
+#define MMHUBBUB_XFC_GPU_CTRL__XFC_LOOPBACK_MODE_MASK 0x00002000L
+#define MMHUBBUB_XFC_GPU_CTRL__XFC_SYSHUB_BRESP_FLAG_MASK 0x00070000L
+#define MMHUBBUB_XFC_GPU_CTRL__XFC_SYSHUB_BRESP_ACK_MASK 0x00700000L
+#define MMHUBBUB_XFC_GPU_CTRL__SYSHUB_SLVWR_RESP_THLD_MASK 0xFF000000L
+//MMHUBBUB_XFC_XBUF_VM_CTRL
+#define MMHUBBUB_XFC_XBUF_VM_CTRL__XBUF_VM_INIT_ENABLE__SHIFT 0x0
+#define MMHUBBUB_XFC_XBUF_VM_CTRL__XBUF_VM_INIT_FAST_ENABLE__SHIFT 0x1
+#define MMHUBBUB_XFC_XBUF_VM_CTRL__XBUF_VM_INIT_DONE__SHIFT 0x4
+#define MMHUBBUB_XFC_XBUF_VM_CTRL__XBUF_VM_INIT_SIZE__SHIFT 0x10
+#define MMHUBBUB_XFC_XBUF_VM_CTRL__XBUF_VM_INIT_ENABLE_MASK 0x00000001L
+#define MMHUBBUB_XFC_XBUF_VM_CTRL__XBUF_VM_INIT_FAST_ENABLE_MASK 0x00000002L
+#define MMHUBBUB_XFC_XBUF_VM_CTRL__XBUF_VM_INIT_DONE_MASK 0x00000010L
+#define MMHUBBUB_XFC_XBUF_VM_CTRL__XBUF_VM_INIT_SIZE_MASK 0x3FFF0000L
+//MMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_LSB
+#define MMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_LSB__XBUF_VM_INIT_BASE_ADDR_LSB__SHIFT 0x0
+#define MMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_LSB__XBUF_VM_INIT_BASE_ADDR_LSB_MASK 0xFFFFFFFFL
+//MMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_MSB
+#define MMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_MSB__XBUF_VM_INIT_BASE_ADDR_MSB__SHIFT 0x0
+#define MMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_MSB__XBUF_VM_INIT_BASE_ADDR_MSB_MASK 0x0000FFFFL
+//MMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_LSB
+#define MMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_LSB__XBUF_VM_INIT_PIXEL_VALUE_LSB__SHIFT 0x0
+#define MMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_LSB__XBUF_VM_INIT_PIXEL_VALUE_LSB_MASK 0xFFFFFFFFL
+//MMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_MSB
+#define MMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_MSB__XBUF_VM_INIT_PIXEL_VALUE_MSB__SHIFT 0x0
+#define MMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_MSB__XBUF_VM_INIT_PIXEL_VALUE_MSB_MASK 0xFFFFFFFFL
+//MMHUBBUB_XFC_GPU0_BASE_ADDR
+#define MMHUBBUB_XFC_GPU0_BASE_ADDR__GPU0_BASE_ADDR__SHIFT 0x0
+#define MMHUBBUB_XFC_GPU0_BASE_ADDR__GPU0_BASE_ADDR_MASK 0xFFFFFFFFL
+//MMHUBBUB_XFC_GPU1_BASE_ADDR
+#define MMHUBBUB_XFC_GPU1_BASE_ADDR__GPU1_BASE_ADDR__SHIFT 0x0
+#define MMHUBBUB_XFC_GPU1_BASE_ADDR__GPU1_BASE_ADDR_MASK 0xFFFFFFFFL
+//MMHUBBUB_XFC_GPU2_BASE_ADDR
+#define MMHUBBUB_XFC_GPU2_BASE_ADDR__GPU2_BASE_ADDR__SHIFT 0x0
+#define MMHUBBUB_XFC_GPU2_BASE_ADDR__GPU2_BASE_ADDR_MASK 0xFFFFFFFFL
+//MMHUBBUB_XFC_GPU3_BASE_ADDR
+#define MMHUBBUB_XFC_GPU3_BASE_ADDR__GPU3_BASE_ADDR__SHIFT 0x0
+#define MMHUBBUB_XFC_GPU3_BASE_ADDR__GPU3_BASE_ADDR_MASK 0xFFFFFFFFL
+//MMHUBBUB_XFCMON_CTRL
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_ENABLE__SHIFT 0x0
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_MMHUB_SUPPRESSION_ENABLE__SHIFT 0x1
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_MODE__SHIFT 0x2
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_INTERFACE_SEL__SHIFT 0x4
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_MONITOR_PERIODS__SHIFT 0x8
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_STATS_VALID__SHIFT 0x1e
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_STATS_VALID_ACK__SHIFT 0x1f
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_ENABLE_MASK 0x00000001L
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_MMHUB_SUPPRESSION_ENABLE_MASK 0x00000002L
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_MODE_MASK 0x0000000CL
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_INTERFACE_SEL_MASK 0x00000010L
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_MONITOR_PERIODS_MASK 0x00001F00L
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_STATS_VALID_MASK 0x40000000L
+#define MMHUBBUB_XFCMON_CTRL__XFCMON_STATS_VALID_ACK_MASK 0x80000000L
+//MMHUBBUB_XFCMON_TIMER
+#define MMHUBBUB_XFCMON_TIMER__XFCMON_TIMER__SHIFT 0x0
+#define MMHUBBUB_XFCMON_TIMER__XFCMON_TIMER_MASK 0x00FFFFFFL
+//MMHUBBUB_XFCMON_STAT_REQUESTS
+#define MMHUBBUB_XFCMON_STAT_REQUESTS__XFCMON_REQUESTS__SHIFT 0x0
+#define MMHUBBUB_XFCMON_STAT_REQUESTS__XFCMON_REQUESTS_MASK 0x00FFFFFFL
+//MMHUBBUB_XFCMON_STAT_BACKPRESSURE
+#define MMHUBBUB_XFCMON_STAT_BACKPRESSURE__XFCMON_BACKPRESSURE__SHIFT 0x0
+#define MMHUBBUB_XFCMON_STAT_BACKPRESSURE__XFCMON_BACKPRESSURE_MASK 0x00FFFFFFL
+//MMHUBBUB_XFCMON_STAT_MAX_REQUESTS
+#define MMHUBBUB_XFCMON_STAT_MAX_REQUESTS__XFCMON_MAX_REQUESTS__SHIFT 0x0
+#define MMHUBBUB_XFCMON_STAT_MAX_REQUESTS__XFCMON_MAX_REQUESTS_MASK 0x00FFFFFFL
+//MMHUBBUB_XFCMON_STAT_BACKPRESSURE_AT_MAX_REQUESTS
+#define MMHUBBUB_XFCMON_STAT_BACKPRESSURE_AT_MAX_REQUESTS__XFCMON_BACKPRESSURE_AT_MAX_REQUESTS__SHIFT 0x0
+#define MMHUBBUB_XFCMON_STAT_BACKPRESSURE_AT_MAX_REQUESTS__XFCMON_BACKPRESSURE_AT_MAX_REQUESTS_MASK 0x00FFFFFFL
+//MMHUBBUB_XFCMON_STAT_MAX_BACKPRESSURE
+#define MMHUBBUB_XFCMON_STAT_MAX_BACKPRESSURE__XFCMON_MAX_BACKPRESSURE__SHIFT 0x0
+#define MMHUBBUB_XFCMON_STAT_MAX_BACKPRESSURE__XFCMON_MAX_BACKPRESSURE_MASK 0x00FFFFFFL
+//MMHUBBUB_XFCMON_STAT_REQUESTS_AT_MAX_BACKPRESSURE
+#define MMHUBBUB_XFCMON_STAT_REQUESTS_AT_MAX_BACKPRESSURE__XFCMON_REQUESTS_AT_MAX_BACKPRESSURE__SHIFT 0x0
+#define MMHUBBUB_XFCMON_STAT_REQUESTS_AT_MAX_BACKPRESSURE__XFCMON_REQUESTS_AT_MAX_BACKPRESSURE_MASK 0x00FFFFFFL
+
+
+// addressBlock: dce_dc_dpp4_dispdec_dpp_top_dispdec
+//DPP_TOP4_DPP_CONTROL
+#define DPP_TOP4_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10
+#define DPP_TOP4_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12
+#define DPP_TOP4_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14
+#define DPP_TOP4_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c
+#define DPP_TOP4_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L
+#define DPP_TOP4_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L
+#define DPP_TOP4_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L
+#define DPP_TOP4_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L
+#define DPP_TOP4_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L
+//DPP_TOP4_DPP_SOFT_RESET
+#define DPP_TOP4_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0
+#define DPP_TOP4_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4
+#define DPP_TOP4_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8
+#define DPP_TOP4_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc
+#define DPP_TOP4_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L
+#define DPP_TOP4_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L
+#define DPP_TOP4_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L
+#define DPP_TOP4_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L
+//DPP_TOP4_DPP_CRC_VAL_R_G
+#define DPP_TOP4_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0
+#define DPP_TOP4_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10
+#define DPP_TOP4_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL
+#define DPP_TOP4_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L
+//DPP_TOP4_DPP_CRC_VAL_B_A
+#define DPP_TOP4_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0
+#define DPP_TOP4_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10
+#define DPP_TOP4_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL
+#define DPP_TOP4_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L
+//DPP_TOP4_DPP_CRC_CTRL
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L
+#define DPP_TOP4_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L
+//DPP_TOP4_HOST_READ_CONTROL
+#define DPP_TOP4_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0
+#define DPP_TOP4_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL
+
+
+// addressBlock: dce_dc_dpp4_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define CNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+//CNVC_CFG4_FORMAT_CONTROL
+#define CNVC_CFG4_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0
+#define CNVC_CFG4_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4
+#define CNVC_CFG4_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8
+#define CNVC_CFG4_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc
+#define CNVC_CFG4_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd
+#define CNVC_CFG4_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10
+#define CNVC_CFG4_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11
+#define CNVC_CFG4_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14
+#define CNVC_CFG4_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L
+#define CNVC_CFG4_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L
+#define CNVC_CFG4_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L
+#define CNVC_CFG4_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L
+#define CNVC_CFG4_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L
+#define CNVC_CFG4_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L
+#define CNVC_CFG4_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L
+#define CNVC_CFG4_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L
+//CNVC_CFG4_FCNV_FP_BIAS_R
+#define CNVC_CFG4_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0
+#define CNVC_CFG4_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL
+//CNVC_CFG4_FCNV_FP_BIAS_G
+#define CNVC_CFG4_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0
+#define CNVC_CFG4_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL
+//CNVC_CFG4_FCNV_FP_BIAS_B
+#define CNVC_CFG4_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0
+#define CNVC_CFG4_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL
+//CNVC_CFG4_FCNV_FP_SCALE_R
+#define CNVC_CFG4_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0
+#define CNVC_CFG4_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL
+//CNVC_CFG4_FCNV_FP_SCALE_G
+#define CNVC_CFG4_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0
+#define CNVC_CFG4_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL
+//CNVC_CFG4_FCNV_FP_SCALE_B
+#define CNVC_CFG4_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0
+#define CNVC_CFG4_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL
+//CNVC_CFG4_COLOR_KEYER_CONTROL
+#define CNVC_CFG4_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0
+#define CNVC_CFG4_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4
+#define CNVC_CFG4_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L
+#define CNVC_CFG4_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L
+//CNVC_CFG4_COLOR_KEYER_ALPHA
+#define CNVC_CFG4_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0
+#define CNVC_CFG4_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10
+#define CNVC_CFG4_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG4_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG4_COLOR_KEYER_RED
+#define CNVC_CFG4_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0
+#define CNVC_CFG4_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10
+#define CNVC_CFG4_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG4_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG4_COLOR_KEYER_GREEN
+#define CNVC_CFG4_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0
+#define CNVC_CFG4_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10
+#define CNVC_CFG4_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG4_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG4_COLOR_KEYER_BLUE
+#define CNVC_CFG4_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0
+#define CNVC_CFG4_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10
+#define CNVC_CFG4_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG4_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG4_ALPHA_2BIT_LUT
+#define CNVC_CFG4_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0
+#define CNVC_CFG4_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8
+#define CNVC_CFG4_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10
+#define CNVC_CFG4_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18
+#define CNVC_CFG4_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL
+#define CNVC_CFG4_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L
+#define CNVC_CFG4_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L
+#define CNVC_CFG4_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L
+
+
+// addressBlock: dce_dc_dpp4_dispdec_cnvc_cur_dispdec
+//CNVC_CUR4_CURSOR0_CONTROL
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L
+#define CNVC_CUR4_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L
+//CNVC_CUR4_CURSOR0_COLOR0
+#define CNVC_CUR4_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0
+#define CNVC_CUR4_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL
+//CNVC_CUR4_CURSOR0_COLOR1
+#define CNVC_CUR4_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0
+#define CNVC_CUR4_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL
+//CNVC_CUR4_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR4_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0
+#define CNVC_CUR4_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10
+#define CNVC_CUR4_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL
+#define CNVC_CUR4_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp4_dispdec_dscl_dispdec
+//DSCL4_SCL_COEF_RAM_TAP_SELECT
+#define DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8
+#define DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+#define DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+#define DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L
+#define DSCL4_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L
+//DSCL4_SCL_COEF_RAM_TAP_DATA
+#define DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define DSCL4_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//DSCL4_SCL_MODE
+#define DSCL4_SCL_MODE__DSCL_MODE__SHIFT 0x0
+#define DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8
+#define DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc
+#define DSCL4_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10
+#define DSCL4_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14
+#define DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18
+#define DSCL4_SCL_MODE__DSCL_MODE_MASK 0x00000007L
+#define DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L
+#define DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L
+#define DSCL4_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L
+#define DSCL4_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L
+#define DSCL4_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L
+//DSCL4_SCL_TAP_CONTROL
+#define DSCL4_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0
+#define DSCL4_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4
+#define DSCL4_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8
+#define DSCL4_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc
+#define DSCL4_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L
+#define DSCL4_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L
+#define DSCL4_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L
+#define DSCL4_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L
+//DSCL4_DSCL_CONTROL
+#define DSCL4_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define DSCL4_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+//DSCL4_DSCL_2TAP_CONTROL
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L
+#define DSCL4_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L
+//DSCL4_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define DSCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define DSCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define DSCL4_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//DSCL4_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define DSCL4_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL4_SCL_HORZ_FILTER_INIT
+#define DSCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define DSCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define DSCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL4_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//DSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL4_SCL_HORZ_FILTER_INIT_C
+#define DSCL4_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define DSCL4_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define DSCL4_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL4_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+//DSCL4_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define DSCL4_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL4_SCL_VERT_FILTER_INIT
+#define DSCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define DSCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define DSCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL4_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L
+//DSCL4_SCL_VERT_FILTER_INIT_BOT
+#define DSCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define DSCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define DSCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define DSCL4_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L
+//DSCL4_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL4_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL4_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL4_SCL_VERT_FILTER_INIT_C
+#define DSCL4_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define DSCL4_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define DSCL4_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL4_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L
+//DSCL4_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL4_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define DSCL4_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define DSCL4_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define DSCL4_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L
+//DSCL4_SCL_BLACK_OFFSET
+#define DSCL4_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0
+#define DSCL4_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10
+#define DSCL4_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define DSCL4_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L
+//DSCL4_DSCL_UPDATE
+#define DSCL4_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define DSCL4_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+//DSCL4_DSCL_AUTOCAL
+#define DSCL4_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0
+#define DSCL4_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8
+#define DSCL4_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc
+#define DSCL4_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L
+#define DSCL4_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L
+#define DSCL4_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L
+//DSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define DSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define DSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define DSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//DSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define DSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define DSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define DSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//DSCL4_OTG_H_BLANK
+#define DSCL4_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0
+#define DSCL4_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10
+#define DSCL4_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL
+#define DSCL4_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L
+//DSCL4_OTG_V_BLANK
+#define DSCL4_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0
+#define DSCL4_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10
+#define DSCL4_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL
+#define DSCL4_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L
+//DSCL4_RECOUT_START
+#define DSCL4_RECOUT_START__RECOUT_START_X__SHIFT 0x0
+#define DSCL4_RECOUT_START__RECOUT_START_Y__SHIFT 0x10
+#define DSCL4_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL
+#define DSCL4_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L
+//DSCL4_RECOUT_SIZE
+#define DSCL4_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0
+#define DSCL4_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10
+#define DSCL4_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL
+#define DSCL4_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L
+//DSCL4_MPC_SIZE
+#define DSCL4_MPC_SIZE__MPC_WIDTH__SHIFT 0x0
+#define DSCL4_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10
+#define DSCL4_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL
+#define DSCL4_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L
+//DSCL4_LB_DATA_FORMAT
+#define DSCL4_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0
+#define DSCL4_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4
+#define DSCL4_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L
+#define DSCL4_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L
+//DSCL4_LB_MEMORY_CTRL
+#define DSCL4_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0
+#define DSCL4_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8
+#define DSCL4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define DSCL4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18
+#define DSCL4_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L
+#define DSCL4_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L
+#define DSCL4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L
+#define DSCL4_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L
+//DSCL4_LB_V_COUNTER
+#define DSCL4_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define DSCL4_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10
+#define DSCL4_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL
+#define DSCL4_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L
+//DSCL4_DSCL_MEM_PWR_CTRL
+#define DSCL4_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL4_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c
+#define DSCL4_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L
+#define DSCL4_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L
+//DSCL4_DSCL_MEM_PWR_STATUS
+#define DSCL4_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc
+#define DSCL4_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L
+#define DSCL4_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L
+//DSCL4_OBUF_CONTROL
+#define DSCL4_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0
+#define DSCL4_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4
+#define DSCL4_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc
+#define DSCL4_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c
+#define DSCL4_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L
+#define DSCL4_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L
+#define DSCL4_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L
+#define DSCL4_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L
+//DSCL4_OBUF_MEM_PWR_CTRL
+#define DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8
+#define DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10
+#define DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L
+#define DSCL4_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L
+
+
+// addressBlock: dce_dc_dpp4_dispdec_cm_dispdec
+//CM4_CM_CONTROL
+#define CM4_CM_CONTROL__CM_BYPASS__SHIFT 0x0
+#define CM4_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8
+#define CM4_CM_CONTROL__CM_BYPASS_MASK 0x00000001L
+#define CM4_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L
+//CM4_CM_ICSC_CONTROL
+#define CM4_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0
+#define CM4_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L
+//CM4_CM_ICSC_C11_C12
+#define CM4_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0
+#define CM4_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10
+#define CM4_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L
+//CM4_CM_ICSC_C13_C14
+#define CM4_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0
+#define CM4_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10
+#define CM4_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L
+//CM4_CM_ICSC_C21_C22
+#define CM4_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0
+#define CM4_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10
+#define CM4_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L
+//CM4_CM_ICSC_C23_C24
+#define CM4_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0
+#define CM4_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10
+#define CM4_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L
+//CM4_CM_ICSC_C31_C32
+#define CM4_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0
+#define CM4_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10
+#define CM4_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L
+//CM4_CM_ICSC_C33_C34
+#define CM4_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0
+#define CM4_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10
+#define CM4_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L
+//CM4_CM_ICSC_B_C11_C12
+#define CM4_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0
+#define CM4_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10
+#define CM4_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L
+//CM4_CM_ICSC_B_C13_C14
+#define CM4_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0
+#define CM4_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10
+#define CM4_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L
+//CM4_CM_ICSC_B_C21_C22
+#define CM4_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0
+#define CM4_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10
+#define CM4_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L
+//CM4_CM_ICSC_B_C23_C24
+#define CM4_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0
+#define CM4_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10
+#define CM4_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L
+//CM4_CM_ICSC_B_C31_C32
+#define CM4_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0
+#define CM4_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10
+#define CM4_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L
+//CM4_CM_ICSC_B_C33_C34
+#define CM4_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0
+#define CM4_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10
+#define CM4_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL
+#define CM4_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_CONTROL
+#define CM4_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L
+//CM4_CM_GAMUT_REMAP_C11_C12
+#define CM4_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_C13_C14
+#define CM4_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_C21_C22
+#define CM4_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_C23_C24
+#define CM4_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_C31_C32
+#define CM4_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_C33_C34
+#define CM4_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_B_C11_C12
+#define CM4_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_B_C13_C14
+#define CM4_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_B_C21_C22
+#define CM4_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_B_C23_C24
+#define CM4_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_B_C31_C32
+#define CM4_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L
+//CM4_CM_GAMUT_REMAP_B_C33_C34
+#define CM4_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0
+#define CM4_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10
+#define CM4_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL
+#define CM4_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L
+//CM4_CM_BIAS_CR_R
+#define CM4_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0
+#define CM4_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL
+//CM4_CM_BIAS_Y_G_CB_B
+#define CM4_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0
+#define CM4_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10
+#define CM4_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL
+#define CM4_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L
+//CM4_CM_DGAM_CONTROL
+#define CM4_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0
+#define CM4_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L
+//CM4_CM_DGAM_LUT_INDEX
+#define CM4_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0
+#define CM4_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL
+//CM4_CM_DGAM_LUT_DATA
+#define CM4_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0
+#define CM4_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM4_CM_DGAM_LUT_WRITE_EN_MASK
+#define CM4_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM4_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM4_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM4_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc
+#define CM4_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM4_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM4_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L
+#define CM4_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L
+//CM4_CM_DGAM_RAMA_START_CNTL_B
+#define CM4_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM4_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM4_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM4_CM_DGAM_RAMA_START_CNTL_G
+#define CM4_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM4_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM4_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM4_CM_DGAM_RAMA_START_CNTL_R
+#define CM4_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM4_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM4_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM4_CM_DGAM_RAMA_SLOPE_CNTL_B
+#define CM4_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM4_CM_DGAM_RAMA_SLOPE_CNTL_G
+#define CM4_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM4_CM_DGAM_RAMA_SLOPE_CNTL_R
+#define CM4_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM4_CM_DGAM_RAMA_END_CNTL1_B
+#define CM4_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM4_CM_DGAM_RAMA_END_CNTL2_B
+#define CM4_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM4_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM4_CM_DGAM_RAMA_END_CNTL1_G
+#define CM4_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM4_CM_DGAM_RAMA_END_CNTL2_G
+#define CM4_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM4_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM4_CM_DGAM_RAMA_END_CNTL1_R
+#define CM4_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM4_CM_DGAM_RAMA_END_CNTL2_R
+#define CM4_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM4_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM4_CM_DGAM_RAMA_REGION_0_1
+#define CM4_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMA_REGION_2_3
+#define CM4_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMA_REGION_4_5
+#define CM4_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMA_REGION_6_7
+#define CM4_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMA_REGION_8_9
+#define CM4_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMA_REGION_10_11
+#define CM4_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMA_REGION_12_13
+#define CM4_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMA_REGION_14_15
+#define CM4_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMB_START_CNTL_B
+#define CM4_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM4_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM4_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM4_CM_DGAM_RAMB_START_CNTL_G
+#define CM4_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM4_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM4_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM4_CM_DGAM_RAMB_START_CNTL_R
+#define CM4_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM4_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM4_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM4_CM_DGAM_RAMB_SLOPE_CNTL_B
+#define CM4_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM4_CM_DGAM_RAMB_SLOPE_CNTL_G
+#define CM4_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM4_CM_DGAM_RAMB_SLOPE_CNTL_R
+#define CM4_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM4_CM_DGAM_RAMB_END_CNTL1_B
+#define CM4_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM4_CM_DGAM_RAMB_END_CNTL2_B
+#define CM4_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM4_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM4_CM_DGAM_RAMB_END_CNTL1_G
+#define CM4_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM4_CM_DGAM_RAMB_END_CNTL2_G
+#define CM4_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM4_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM4_CM_DGAM_RAMB_END_CNTL1_R
+#define CM4_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM4_CM_DGAM_RAMB_END_CNTL2_R
+#define CM4_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM4_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM4_CM_DGAM_RAMB_REGION_0_1
+#define CM4_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMB_REGION_2_3
+#define CM4_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMB_REGION_4_5
+#define CM4_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMB_REGION_6_7
+#define CM4_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMB_REGION_8_9
+#define CM4_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMB_REGION_10_11
+#define CM4_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMB_REGION_12_13
+#define CM4_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_DGAM_RAMB_REGION_14_15
+#define CM4_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_CONTROL
+#define CM4_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0
+#define CM4_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L
+//CM4_CM_BLNDGAM_LUT_INDEX
+#define CM4_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0
+#define CM4_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL
+//CM4_CM_BLNDGAM_LUT_DATA
+#define CM4_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0
+#define CM4_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM4_CM_BLNDGAM_LUT_WRITE_EN_MASK
+#define CM4_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM4_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM4_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM4_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM4_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM4_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L
+//CM4_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM4_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM4_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM4_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
+#define CM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
+#define CM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
+#define CM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM4_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM4_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM4_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM4_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM4_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM4_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM4_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM4_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM4_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM4_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM4_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM4_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM4_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM4_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM4_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM4_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM4_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM4_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM4_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM4_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM4_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM4_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM4_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM4_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM4_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM4_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM4_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM4_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
+#define CM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
+#define CM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
+#define CM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM4_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM4_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM4_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM4_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM4_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM4_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM4_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM4_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM4_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM4_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM4_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM4_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM4_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM4_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM4_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM4_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM4_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM4_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM4_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM4_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM4_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM4_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM4_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM4_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM4_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_HDR_MULT_COEF
+#define CM4_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0
+#define CM4_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL
+//CM4_CM_MEM_PWR_CTRL
+#define CM4_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0
+#define CM4_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2
+#define CM4_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4
+#define CM4_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6
+#define CM4_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L
+#define CM4_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L
+#define CM4_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L
+#define CM4_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L
+//CM4_CM_MEM_PWR_STATUS
+#define CM4_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0
+#define CM4_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2
+#define CM4_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
+#define CM4_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL
+//CM4_CM_DEALPHA
+#define CM4_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0
+#define CM4_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L
+//CM4_CM_COEF_FORMAT
+#define CM4_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0
+#define CM4_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4
+#define CM4_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8
+#define CM4_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L
+#define CM4_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L
+#define CM4_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L
+//CM4_CM_SHAPER_CONTROL
+#define CM4_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0
+#define CM4_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L
+//CM4_CM_SHAPER_OFFSET_R
+#define CM4_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0
+#define CM4_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL
+//CM4_CM_SHAPER_OFFSET_G
+#define CM4_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0
+#define CM4_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL
+//CM4_CM_SHAPER_OFFSET_B
+#define CM4_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0
+#define CM4_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL
+//CM4_CM_SHAPER_SCALE_R
+#define CM4_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0
+#define CM4_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL
+//CM4_CM_SHAPER_SCALE_G_B
+#define CM4_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0
+#define CM4_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10
+#define CM4_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL
+#define CM4_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L
+//CM4_CM_SHAPER_LUT_INDEX
+#define CM4_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0
+#define CM4_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL
+//CM4_CM_SHAPER_LUT_DATA
+#define CM4_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0
+#define CM4_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL
+//CM4_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM4_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM4_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4
+#define CM4_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8
+#define CM4_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM4_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM4_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L
+//CM4_CM_SHAPER_RAMA_START_CNTL_B
+#define CM4_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM4_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM4_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM4_CM_SHAPER_RAMA_START_CNTL_G
+#define CM4_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM4_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM4_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM4_CM_SHAPER_RAMA_START_CNTL_R
+#define CM4_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM4_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM4_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM4_CM_SHAPER_RAMA_END_CNTL_B
+#define CM4_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM4_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM4_CM_SHAPER_RAMA_END_CNTL_G
+#define CM4_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM4_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM4_CM_SHAPER_RAMA_END_CNTL_R
+#define CM4_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM4_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM4_CM_SHAPER_RAMA_REGION_0_1
+#define CM4_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_2_3
+#define CM4_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_4_5
+#define CM4_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_6_7
+#define CM4_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_8_9
+#define CM4_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_10_11
+#define CM4_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_12_13
+#define CM4_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_14_15
+#define CM4_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_16_17
+#define CM4_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_18_19
+#define CM4_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_20_21
+#define CM4_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_22_23
+#define CM4_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_24_25
+#define CM4_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_26_27
+#define CM4_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_28_29
+#define CM4_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_30_31
+#define CM4_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMA_REGION_32_33
+#define CM4_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_START_CNTL_B
+#define CM4_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM4_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM4_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM4_CM_SHAPER_RAMB_START_CNTL_G
+#define CM4_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM4_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM4_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM4_CM_SHAPER_RAMB_START_CNTL_R
+#define CM4_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM4_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM4_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM4_CM_SHAPER_RAMB_END_CNTL_B
+#define CM4_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM4_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM4_CM_SHAPER_RAMB_END_CNTL_G
+#define CM4_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM4_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM4_CM_SHAPER_RAMB_END_CNTL_R
+#define CM4_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM4_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM4_CM_SHAPER_RAMB_REGION_0_1
+#define CM4_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_2_3
+#define CM4_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_4_5
+#define CM4_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_6_7
+#define CM4_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_8_9
+#define CM4_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_10_11
+#define CM4_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_12_13
+#define CM4_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_14_15
+#define CM4_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_16_17
+#define CM4_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_18_19
+#define CM4_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_20_21
+#define CM4_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_22_23
+#define CM4_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_24_25
+#define CM4_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_26_27
+#define CM4_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_28_29
+#define CM4_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_30_31
+#define CM4_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_SHAPER_RAMB_REGION_32_33
+#define CM4_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM4_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM4_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM4_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM4_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM4_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM4_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM4_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM4_CM_MEM_PWR_CTRL2
+#define CM4_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8
+#define CM4_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa
+#define CM4_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc
+#define CM4_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe
+#define CM4_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L
+#define CM4_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L
+#define CM4_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L
+#define CM4_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L
+//CM4_CM_MEM_PWR_STATUS2
+#define CM4_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4
+#define CM4_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6
+#define CM4_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L
+#define CM4_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L
+//CM4_CM_3DLUT_MODE
+#define CM4_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0
+#define CM4_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4
+#define CM4_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L
+#define CM4_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L
+//CM4_CM_3DLUT_INDEX
+#define CM4_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0
+#define CM4_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL
+//CM4_CM_3DLUT_DATA
+#define CM4_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0
+#define CM4_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10
+#define CM4_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL
+#define CM4_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L
+//CM4_CM_3DLUT_DATA_30BIT
+#define CM4_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2
+#define CM4_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL
+//CM4_CM_3DLUT_READ_WRITE_CONTROL
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L
+#define CM4_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L
+//CM4_CM_3DLUT_OUT_NORM_FACTOR
+#define CM4_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0
+#define CM4_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL
+//CM4_CM_3DLUT_OUT_OFFSET_R
+#define CM4_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0
+#define CM4_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10
+#define CM4_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL
+#define CM4_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L
+//CM4_CM_3DLUT_OUT_OFFSET_G
+#define CM4_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0
+#define CM4_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10
+#define CM4_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL
+#define CM4_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L
+//CM4_CM_3DLUT_OUT_OFFSET_B
+#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0
+#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
+#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
+#define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
+//CM4_CM_TEST_DEBUG_INDEX
+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//CM4_CM_TEST_DEBUG_DATA
+#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON27_PERFCOUNTER_CNTL
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON27_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON27_PERFCOUNTER_CNTL2
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON27_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON27_PERFCOUNTER_STATE
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON27_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON27_PERFMON_CNTL
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON27_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON27_PERFMON_CNTL2
+#define DC_PERFMON27_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON27_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON27_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON27_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON27_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON27_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON27_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON27_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON27_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON27_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON27_PERFMON_CVALUE_LOW
+#define DC_PERFMON27_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON27_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON27_PERFMON_HI
+#define DC_PERFMON27_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON27_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON27_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON27_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON27_PERFMON_LOW
+#define DC_PERFMON27_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON27_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp5_dispdec_dpp_top_dispdec
+//DPP_TOP5_DPP_CONTROL
+#define DPP_TOP5_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10
+#define DPP_TOP5_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12
+#define DPP_TOP5_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14
+#define DPP_TOP5_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c
+#define DPP_TOP5_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L
+#define DPP_TOP5_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L
+#define DPP_TOP5_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L
+#define DPP_TOP5_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L
+#define DPP_TOP5_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L
+//DPP_TOP5_DPP_SOFT_RESET
+#define DPP_TOP5_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0
+#define DPP_TOP5_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4
+#define DPP_TOP5_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8
+#define DPP_TOP5_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc
+#define DPP_TOP5_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L
+#define DPP_TOP5_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L
+#define DPP_TOP5_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L
+#define DPP_TOP5_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L
+//DPP_TOP5_DPP_CRC_VAL_R_G
+#define DPP_TOP5_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0
+#define DPP_TOP5_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10
+#define DPP_TOP5_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL
+#define DPP_TOP5_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L
+//DPP_TOP5_DPP_CRC_VAL_B_A
+#define DPP_TOP5_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0
+#define DPP_TOP5_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10
+#define DPP_TOP5_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL
+#define DPP_TOP5_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L
+//DPP_TOP5_DPP_CRC_CTRL
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L
+#define DPP_TOP5_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L
+//DPP_TOP5_HOST_READ_CONTROL
+#define DPP_TOP5_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0
+#define DPP_TOP5_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL
+
+
+// addressBlock: dce_dc_dpp5_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0
+#define CNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL
+//CNVC_CFG5_FORMAT_CONTROL
+#define CNVC_CFG5_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0
+#define CNVC_CFG5_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4
+#define CNVC_CFG5_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8
+#define CNVC_CFG5_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc
+#define CNVC_CFG5_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd
+#define CNVC_CFG5_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10
+#define CNVC_CFG5_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11
+#define CNVC_CFG5_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14
+#define CNVC_CFG5_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L
+#define CNVC_CFG5_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L
+#define CNVC_CFG5_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L
+#define CNVC_CFG5_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L
+#define CNVC_CFG5_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L
+#define CNVC_CFG5_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L
+#define CNVC_CFG5_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L
+#define CNVC_CFG5_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L
+//CNVC_CFG5_FCNV_FP_BIAS_R
+#define CNVC_CFG5_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0
+#define CNVC_CFG5_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL
+//CNVC_CFG5_FCNV_FP_BIAS_G
+#define CNVC_CFG5_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0
+#define CNVC_CFG5_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL
+//CNVC_CFG5_FCNV_FP_BIAS_B
+#define CNVC_CFG5_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0
+#define CNVC_CFG5_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL
+//CNVC_CFG5_FCNV_FP_SCALE_R
+#define CNVC_CFG5_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0
+#define CNVC_CFG5_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL
+//CNVC_CFG5_FCNV_FP_SCALE_G
+#define CNVC_CFG5_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0
+#define CNVC_CFG5_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL
+//CNVC_CFG5_FCNV_FP_SCALE_B
+#define CNVC_CFG5_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0
+#define CNVC_CFG5_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL
+//CNVC_CFG5_COLOR_KEYER_CONTROL
+#define CNVC_CFG5_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0
+#define CNVC_CFG5_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4
+#define CNVC_CFG5_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L
+#define CNVC_CFG5_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L
+//CNVC_CFG5_COLOR_KEYER_ALPHA
+#define CNVC_CFG5_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0
+#define CNVC_CFG5_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10
+#define CNVC_CFG5_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG5_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG5_COLOR_KEYER_RED
+#define CNVC_CFG5_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0
+#define CNVC_CFG5_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10
+#define CNVC_CFG5_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG5_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG5_COLOR_KEYER_GREEN
+#define CNVC_CFG5_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0
+#define CNVC_CFG5_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10
+#define CNVC_CFG5_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG5_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG5_COLOR_KEYER_BLUE
+#define CNVC_CFG5_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0
+#define CNVC_CFG5_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10
+#define CNVC_CFG5_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL
+#define CNVC_CFG5_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L
+//CNVC_CFG5_ALPHA_2BIT_LUT
+#define CNVC_CFG5_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0
+#define CNVC_CFG5_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8
+#define CNVC_CFG5_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10
+#define CNVC_CFG5_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18
+#define CNVC_CFG5_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL
+#define CNVC_CFG5_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L
+#define CNVC_CFG5_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L
+#define CNVC_CFG5_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L
+
+
+// addressBlock: dce_dc_dpp5_dispdec_cnvc_cur_dispdec
+//CNVC_CUR5_CURSOR0_CONTROL
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L
+#define CNVC_CUR5_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L
+//CNVC_CUR5_CURSOR0_COLOR0
+#define CNVC_CUR5_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0
+#define CNVC_CUR5_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL
+//CNVC_CUR5_CURSOR0_COLOR1
+#define CNVC_CUR5_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0
+#define CNVC_CUR5_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL
+//CNVC_CUR5_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR5_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0
+#define CNVC_CUR5_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10
+#define CNVC_CUR5_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL
+#define CNVC_CUR5_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp5_dispdec_dscl_dispdec
+//DSCL5_SCL_COEF_RAM_TAP_SELECT
+#define DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8
+#define DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+#define DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L
+#define DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L
+#define DSCL5_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L
+//DSCL5_SCL_COEF_RAM_TAP_DATA
+#define DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL
+#define DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
+#define DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L
+#define DSCL5_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
+//DSCL5_SCL_MODE
+#define DSCL5_SCL_MODE__DSCL_MODE__SHIFT 0x0
+#define DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8
+#define DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc
+#define DSCL5_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10
+#define DSCL5_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14
+#define DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18
+#define DSCL5_SCL_MODE__DSCL_MODE_MASK 0x00000007L
+#define DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L
+#define DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L
+#define DSCL5_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L
+#define DSCL5_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L
+#define DSCL5_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L
+//DSCL5_SCL_TAP_CONTROL
+#define DSCL5_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0
+#define DSCL5_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4
+#define DSCL5_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8
+#define DSCL5_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc
+#define DSCL5_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L
+#define DSCL5_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L
+#define DSCL5_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L
+#define DSCL5_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L
+//DSCL5_DSCL_CONTROL
+#define DSCL5_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define DSCL5_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L
+//DSCL5_DSCL_2TAP_CONTROL
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L
+#define DSCL5_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L
+//DSCL5_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define DSCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define DSCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL
+#define DSCL5_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L
+//DSCL5_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define DSCL5_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL5_SCL_HORZ_FILTER_INIT
+#define DSCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define DSCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define DSCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL5_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L
+//DSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL5_SCL_HORZ_FILTER_INIT_C
+#define DSCL5_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define DSCL5_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define DSCL5_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL5_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L
+//DSCL5_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define DSCL5_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL
+//DSCL5_SCL_VERT_FILTER_INIT
+#define DSCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define DSCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define DSCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL
+#define DSCL5_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L
+//DSCL5_SCL_VERT_FILTER_INIT_BOT
+#define DSCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define DSCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define DSCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL
+#define DSCL5_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L
+//DSCL5_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL5_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define DSCL5_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL
+//DSCL5_SCL_VERT_FILTER_INIT_C
+#define DSCL5_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define DSCL5_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define DSCL5_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL
+#define DSCL5_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L
+//DSCL5_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL5_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define DSCL5_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define DSCL5_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL
+#define DSCL5_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L
+//DSCL5_SCL_BLACK_OFFSET
+#define DSCL5_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0
+#define DSCL5_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10
+#define DSCL5_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL
+#define DSCL5_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L
+//DSCL5_DSCL_UPDATE
+#define DSCL5_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define DSCL5_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
+//DSCL5_DSCL_AUTOCAL
+#define DSCL5_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0
+#define DSCL5_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8
+#define DSCL5_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc
+#define DSCL5_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L
+#define DSCL5_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L
+#define DSCL5_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L
+//DSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define DSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define DSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL
+#define DSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L
+//DSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define DSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define DSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL
+#define DSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L
+//DSCL5_OTG_H_BLANK
+#define DSCL5_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0
+#define DSCL5_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10
+#define DSCL5_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL
+#define DSCL5_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L
+//DSCL5_OTG_V_BLANK
+#define DSCL5_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0
+#define DSCL5_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10
+#define DSCL5_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL
+#define DSCL5_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L
+//DSCL5_RECOUT_START
+#define DSCL5_RECOUT_START__RECOUT_START_X__SHIFT 0x0
+#define DSCL5_RECOUT_START__RECOUT_START_Y__SHIFT 0x10
+#define DSCL5_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL
+#define DSCL5_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L
+//DSCL5_RECOUT_SIZE
+#define DSCL5_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0
+#define DSCL5_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10
+#define DSCL5_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL
+#define DSCL5_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L
+//DSCL5_MPC_SIZE
+#define DSCL5_MPC_SIZE__MPC_WIDTH__SHIFT 0x0
+#define DSCL5_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10
+#define DSCL5_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL
+#define DSCL5_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L
+//DSCL5_LB_DATA_FORMAT
+#define DSCL5_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0
+#define DSCL5_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4
+#define DSCL5_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L
+#define DSCL5_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L
+//DSCL5_LB_MEMORY_CTRL
+#define DSCL5_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0
+#define DSCL5_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8
+#define DSCL5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define DSCL5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18
+#define DSCL5_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L
+#define DSCL5_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L
+#define DSCL5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L
+#define DSCL5_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L
+//DSCL5_LB_V_COUNTER
+#define DSCL5_LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define DSCL5_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10
+#define DSCL5_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL
+#define DSCL5_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L
+//DSCL5_DSCL_MEM_PWR_CTRL
+#define DSCL5_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL5_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c
+#define DSCL5_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L
+#define DSCL5_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L
+//DSCL5_DSCL_MEM_PWR_STATUS
+#define DSCL5_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc
+#define DSCL5_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L
+#define DSCL5_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L
+//DSCL5_OBUF_CONTROL
+#define DSCL5_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0
+#define DSCL5_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4
+#define DSCL5_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc
+#define DSCL5_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c
+#define DSCL5_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L
+#define DSCL5_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L
+#define DSCL5_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L
+#define DSCL5_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L
+//DSCL5_OBUF_MEM_PWR_CTRL
+#define DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0
+#define DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2
+#define DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8
+#define DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10
+#define DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L
+#define DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L
+#define DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L
+#define DSCL5_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L
+
+
+// addressBlock: dce_dc_dpp5_dispdec_cm_dispdec
+//CM5_CM_CONTROL
+#define CM5_CM_CONTROL__CM_BYPASS__SHIFT 0x0
+#define CM5_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8
+#define CM5_CM_CONTROL__CM_BYPASS_MASK 0x00000001L
+#define CM5_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L
+//CM5_CM_ICSC_CONTROL
+#define CM5_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0
+#define CM5_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L
+//CM5_CM_ICSC_C11_C12
+#define CM5_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0
+#define CM5_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10
+#define CM5_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L
+//CM5_CM_ICSC_C13_C14
+#define CM5_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0
+#define CM5_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10
+#define CM5_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L
+//CM5_CM_ICSC_C21_C22
+#define CM5_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0
+#define CM5_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10
+#define CM5_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L
+//CM5_CM_ICSC_C23_C24
+#define CM5_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0
+#define CM5_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10
+#define CM5_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L
+//CM5_CM_ICSC_C31_C32
+#define CM5_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0
+#define CM5_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10
+#define CM5_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L
+//CM5_CM_ICSC_C33_C34
+#define CM5_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0
+#define CM5_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10
+#define CM5_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L
+//CM5_CM_ICSC_B_C11_C12
+#define CM5_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0
+#define CM5_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10
+#define CM5_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L
+//CM5_CM_ICSC_B_C13_C14
+#define CM5_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0
+#define CM5_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10
+#define CM5_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L
+//CM5_CM_ICSC_B_C21_C22
+#define CM5_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0
+#define CM5_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10
+#define CM5_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L
+//CM5_CM_ICSC_B_C23_C24
+#define CM5_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0
+#define CM5_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10
+#define CM5_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L
+//CM5_CM_ICSC_B_C31_C32
+#define CM5_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0
+#define CM5_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10
+#define CM5_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L
+//CM5_CM_ICSC_B_C33_C34
+#define CM5_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0
+#define CM5_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10
+#define CM5_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL
+#define CM5_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_CONTROL
+#define CM5_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L
+//CM5_CM_GAMUT_REMAP_C11_C12
+#define CM5_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_C13_C14
+#define CM5_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_C21_C22
+#define CM5_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_C23_C24
+#define CM5_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_C31_C32
+#define CM5_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_C33_C34
+#define CM5_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_B_C11_C12
+#define CM5_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_B_C13_C14
+#define CM5_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_B_C21_C22
+#define CM5_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_B_C23_C24
+#define CM5_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_B_C31_C32
+#define CM5_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L
+//CM5_CM_GAMUT_REMAP_B_C33_C34
+#define CM5_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0
+#define CM5_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10
+#define CM5_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL
+#define CM5_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L
+//CM5_CM_BIAS_CR_R
+#define CM5_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0
+#define CM5_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL
+//CM5_CM_BIAS_Y_G_CB_B
+#define CM5_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0
+#define CM5_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10
+#define CM5_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL
+#define CM5_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L
+//CM5_CM_DGAM_CONTROL
+#define CM5_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0
+#define CM5_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L
+//CM5_CM_DGAM_LUT_INDEX
+#define CM5_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0
+#define CM5_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL
+//CM5_CM_DGAM_LUT_DATA
+#define CM5_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0
+#define CM5_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM5_CM_DGAM_LUT_WRITE_EN_MASK
+#define CM5_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM5_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM5_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM5_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc
+#define CM5_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM5_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM5_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L
+#define CM5_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L
+//CM5_CM_DGAM_RAMA_START_CNTL_B
+#define CM5_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM5_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM5_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM5_CM_DGAM_RAMA_START_CNTL_G
+#define CM5_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM5_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM5_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM5_CM_DGAM_RAMA_START_CNTL_R
+#define CM5_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM5_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM5_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM5_CM_DGAM_RAMA_SLOPE_CNTL_B
+#define CM5_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM5_CM_DGAM_RAMA_SLOPE_CNTL_G
+#define CM5_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM5_CM_DGAM_RAMA_SLOPE_CNTL_R
+#define CM5_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM5_CM_DGAM_RAMA_END_CNTL1_B
+#define CM5_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM5_CM_DGAM_RAMA_END_CNTL2_B
+#define CM5_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM5_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM5_CM_DGAM_RAMA_END_CNTL1_G
+#define CM5_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM5_CM_DGAM_RAMA_END_CNTL2_G
+#define CM5_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM5_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM5_CM_DGAM_RAMA_END_CNTL1_R
+#define CM5_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM5_CM_DGAM_RAMA_END_CNTL2_R
+#define CM5_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM5_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM5_CM_DGAM_RAMA_REGION_0_1
+#define CM5_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMA_REGION_2_3
+#define CM5_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMA_REGION_4_5
+#define CM5_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMA_REGION_6_7
+#define CM5_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMA_REGION_8_9
+#define CM5_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMA_REGION_10_11
+#define CM5_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMA_REGION_12_13
+#define CM5_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMA_REGION_14_15
+#define CM5_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMB_START_CNTL_B
+#define CM5_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM5_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM5_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM5_CM_DGAM_RAMB_START_CNTL_G
+#define CM5_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM5_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM5_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM5_CM_DGAM_RAMB_START_CNTL_R
+#define CM5_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM5_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM5_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM5_CM_DGAM_RAMB_SLOPE_CNTL_B
+#define CM5_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM5_CM_DGAM_RAMB_SLOPE_CNTL_G
+#define CM5_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM5_CM_DGAM_RAMB_SLOPE_CNTL_R
+#define CM5_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM5_CM_DGAM_RAMB_END_CNTL1_B
+#define CM5_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM5_CM_DGAM_RAMB_END_CNTL2_B
+#define CM5_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM5_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM5_CM_DGAM_RAMB_END_CNTL1_G
+#define CM5_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM5_CM_DGAM_RAMB_END_CNTL2_G
+#define CM5_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM5_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM5_CM_DGAM_RAMB_END_CNTL1_R
+#define CM5_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM5_CM_DGAM_RAMB_END_CNTL2_R
+#define CM5_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM5_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM5_CM_DGAM_RAMB_REGION_0_1
+#define CM5_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMB_REGION_2_3
+#define CM5_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMB_REGION_4_5
+#define CM5_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMB_REGION_6_7
+#define CM5_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMB_REGION_8_9
+#define CM5_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMB_REGION_10_11
+#define CM5_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMB_REGION_12_13
+#define CM5_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_DGAM_RAMB_REGION_14_15
+#define CM5_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_CONTROL
+#define CM5_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0
+#define CM5_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L
+//CM5_CM_BLNDGAM_LUT_INDEX
+#define CM5_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0
+#define CM5_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL
+//CM5_CM_BLNDGAM_LUT_DATA
+#define CM5_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0
+#define CM5_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL
+//CM5_CM_BLNDGAM_LUT_WRITE_EN_MASK
+#define CM5_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM5_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4
+#define CM5_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8
+#define CM5_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM5_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM5_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L
+//CM5_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM5_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM5_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM5_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
+#define CM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
+#define CM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
+#define CM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM5_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM5_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM5_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM5_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM5_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM5_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM5_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM5_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM5_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM5_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM5_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM5_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM5_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM5_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM5_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM5_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM5_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM5_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM5_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM5_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM5_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM5_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM5_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM5_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM5_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM5_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM5_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM5_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
+#define CM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL
+//CM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
+#define CM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL
+//CM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
+#define CM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL
+//CM5_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+//CM5_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L
+//CM5_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+//CM5_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L
+//CM5_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+//CM5_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL
+#define CM5_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L
+//CM5_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM5_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM5_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM5_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM5_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM5_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM5_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM5_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM5_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM5_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM5_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM5_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM5_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM5_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM5_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM5_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM5_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM5_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_HDR_MULT_COEF
+#define CM5_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0
+#define CM5_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL
+//CM5_CM_MEM_PWR_CTRL
+#define CM5_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0
+#define CM5_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2
+#define CM5_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4
+#define CM5_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6
+#define CM5_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L
+#define CM5_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L
+#define CM5_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L
+#define CM5_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L
+//CM5_CM_MEM_PWR_STATUS
+#define CM5_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0
+#define CM5_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2
+#define CM5_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L
+#define CM5_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL
+//CM5_CM_DEALPHA
+#define CM5_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0
+#define CM5_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L
+//CM5_CM_COEF_FORMAT
+#define CM5_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0
+#define CM5_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4
+#define CM5_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8
+#define CM5_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L
+#define CM5_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L
+#define CM5_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L
+//CM5_CM_SHAPER_CONTROL
+#define CM5_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0
+#define CM5_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L
+//CM5_CM_SHAPER_OFFSET_R
+#define CM5_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0
+#define CM5_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL
+//CM5_CM_SHAPER_OFFSET_G
+#define CM5_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0
+#define CM5_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL
+//CM5_CM_SHAPER_OFFSET_B
+#define CM5_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0
+#define CM5_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL
+//CM5_CM_SHAPER_SCALE_R
+#define CM5_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0
+#define CM5_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL
+//CM5_CM_SHAPER_SCALE_G_B
+#define CM5_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0
+#define CM5_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10
+#define CM5_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL
+#define CM5_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L
+//CM5_CM_SHAPER_LUT_INDEX
+#define CM5_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0
+#define CM5_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL
+//CM5_CM_SHAPER_LUT_DATA
+#define CM5_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0
+#define CM5_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL
+//CM5_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM5_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM5_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4
+#define CM5_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8
+#define CM5_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L
+#define CM5_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L
+#define CM5_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L
+//CM5_CM_SHAPER_RAMA_START_CNTL_B
+#define CM5_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM5_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM5_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM5_CM_SHAPER_RAMA_START_CNTL_G
+#define CM5_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM5_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM5_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM5_CM_SHAPER_RAMA_START_CNTL_R
+#define CM5_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM5_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM5_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM5_CM_SHAPER_RAMA_END_CNTL_B
+#define CM5_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM5_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM5_CM_SHAPER_RAMA_END_CNTL_G
+#define CM5_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM5_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM5_CM_SHAPER_RAMA_END_CNTL_R
+#define CM5_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM5_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM5_CM_SHAPER_RAMA_REGION_0_1
+#define CM5_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_2_3
+#define CM5_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_4_5
+#define CM5_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_6_7
+#define CM5_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_8_9
+#define CM5_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_10_11
+#define CM5_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_12_13
+#define CM5_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_14_15
+#define CM5_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_16_17
+#define CM5_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_18_19
+#define CM5_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_20_21
+#define CM5_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_22_23
+#define CM5_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_24_25
+#define CM5_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_26_27
+#define CM5_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_28_29
+#define CM5_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_30_31
+#define CM5_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMA_REGION_32_33
+#define CM5_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_START_CNTL_B
+#define CM5_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14
+#define CM5_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL
+#define CM5_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L
+//CM5_CM_SHAPER_RAMB_START_CNTL_G
+#define CM5_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14
+#define CM5_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL
+#define CM5_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L
+//CM5_CM_SHAPER_RAMB_START_CNTL_R
+#define CM5_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14
+#define CM5_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL
+#define CM5_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L
+//CM5_CM_SHAPER_RAMB_END_CNTL_B
+#define CM5_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL
+#define CM5_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L
+//CM5_CM_SHAPER_RAMB_END_CNTL_G
+#define CM5_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL
+#define CM5_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L
+//CM5_CM_SHAPER_RAMB_END_CNTL_R
+#define CM5_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL
+#define CM5_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L
+//CM5_CM_SHAPER_RAMB_REGION_0_1
+#define CM5_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_2_3
+#define CM5_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_4_5
+#define CM5_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_6_7
+#define CM5_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_8_9
+#define CM5_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_10_11
+#define CM5_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_12_13
+#define CM5_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_14_15
+#define CM5_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_16_17
+#define CM5_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_18_19
+#define CM5_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_20_21
+#define CM5_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_22_23
+#define CM5_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_24_25
+#define CM5_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_26_27
+#define CM5_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_28_29
+#define CM5_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_30_31
+#define CM5_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_SHAPER_RAMB_REGION_32_33
+#define CM5_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0
+#define CM5_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc
+#define CM5_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10
+#define CM5_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c
+#define CM5_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL
+#define CM5_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L
+#define CM5_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L
+#define CM5_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L
+//CM5_CM_MEM_PWR_CTRL2
+#define CM5_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8
+#define CM5_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa
+#define CM5_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc
+#define CM5_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe
+#define CM5_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L
+#define CM5_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L
+#define CM5_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L
+#define CM5_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L
+//CM5_CM_MEM_PWR_STATUS2
+#define CM5_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4
+#define CM5_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6
+#define CM5_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L
+#define CM5_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L
+//CM5_CM_3DLUT_MODE
+#define CM5_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0
+#define CM5_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4
+#define CM5_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L
+#define CM5_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L
+//CM5_CM_3DLUT_INDEX
+#define CM5_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0
+#define CM5_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL
+//CM5_CM_3DLUT_DATA
+#define CM5_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0
+#define CM5_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10
+#define CM5_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL
+#define CM5_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L
+//CM5_CM_3DLUT_DATA_30BIT
+#define CM5_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2
+#define CM5_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL
+//CM5_CM_3DLUT_READ_WRITE_CONTROL
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L
+#define CM5_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L
+//CM5_CM_3DLUT_OUT_NORM_FACTOR
+#define CM5_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0
+#define CM5_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL
+//CM5_CM_3DLUT_OUT_OFFSET_R
+#define CM5_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0
+#define CM5_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10
+#define CM5_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL
+#define CM5_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L
+//CM5_CM_3DLUT_OUT_OFFSET_G
+#define CM5_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0
+#define CM5_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10
+#define CM5_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL
+#define CM5_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L
+//CM5_CM_3DLUT_OUT_OFFSET_B
+#define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0
+#define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10
+#define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL
+#define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L
+//CM5_CM_TEST_DEBUG_INDEX
+#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL
+#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
+//CM5_CM_TEST_DEBUG_DATA
+#define CM5_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CM5_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp5_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON28_PERFCOUNTER_CNTL
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L
+#define DC_PERFMON28_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L
+//DC_PERFMON28_PERFCOUNTER_CNTL2
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L
+#define DC_PERFMON28_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L
+//DC_PERFMON28_PERFCOUNTER_STATE
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L
+#define DC_PERFMON28_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L
+//DC_PERFMON28_PERFMON_CNTL
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L
+#define DC_PERFMON28_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L
+//DC_PERFMON28_PERFMON_CNTL2
+#define DC_PERFMON28_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define DC_PERFMON28_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define DC_PERFMON28_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2
+#define DC_PERFMON28_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
+#define DC_PERFMON28_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L
+#define DC_PERFMON28_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L
+#define DC_PERFMON28_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL
+#define DC_PERFMON28_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L
+//DC_PERFMON28_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L
+#define DC_PERFMON28_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L
+//DC_PERFMON28_PERFMON_CVALUE_LOW
+#define DC_PERFMON28_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define DC_PERFMON28_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL
+//DC_PERFMON28_PERFMON_HI
+#define DC_PERFMON28_PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define DC_PERFMON28_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define DC_PERFMON28_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL
+#define DC_PERFMON28_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L
+//DC_PERFMON28_PERFMON_LOW
+#define DC_PERFMON28_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define DC_PERFMON28_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+//CORB_WRITE_POINTER
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
+//CORB_READ_POINTER
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
+//CORB_CONTROL
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L
+//CORB_STATUS
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L
+//CORB_SIZE
+#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
+#define CORB_SIZE__CORB_SIZE_MASK 0x0003L
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L
+//RIRB_LOWER_BASE_ADDRESS
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//RIRB_UPPER_BASE_ADDRESS
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//RIRB_WRITE_POINTER
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L
+//RESPONSE_INTERRUPT_COUNT
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL
+//RIRB_CONTROL
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L
+//RIRB_STATUS
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L
+//RIRB_SIZE
+#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
+#define RIRB_SIZE__RIRB_SIZE_MASK 0x0003L
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL
+//IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL
+//IMMEDIATE_COMMAND_STATUS
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L
+//DMA_POSITION_LOWER_BASE_ADDRESS
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//DMA_POSITION_UPPER_BASE_ADDRESS
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//WALL_CLOCK_COUNTER_ALIAS
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azroot_azdec
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azstream0_azdec
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream1_azdec
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream2_azdec
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream3_azdec
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream4_azdec
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream5_azdec
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream6_azdec
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azstream7_azdec
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL
+
+
+
+
+// addressBlock: vga_vgaseqind
+//SEQ00
+#define SEQ00__SEQ_RST0B__SHIFT 0x0
+#define SEQ00__SEQ_RST1B__SHIFT 0x1
+#define SEQ00__SEQ_RST0B_MASK 0x01L
+#define SEQ00__SEQ_RST1B_MASK 0x02L
+//SEQ01
+#define SEQ01__SEQ_DOT8__SHIFT 0x0
+#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
+#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
+#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
+#define SEQ01__SEQ_MAXBW__SHIFT 0x5
+#define SEQ01__SEQ_DOT8_MASK 0x01L
+#define SEQ01__SEQ_SHIFT2_MASK 0x04L
+#define SEQ01__SEQ_PCLKBY2_MASK 0x08L
+#define SEQ01__SEQ_SHIFT4_MASK 0x10L
+#define SEQ01__SEQ_MAXBW_MASK 0x20L
+//SEQ02
+#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
+#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
+#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
+#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
+#define SEQ02__SEQ_MAP0_EN_MASK 0x01L
+#define SEQ02__SEQ_MAP1_EN_MASK 0x02L
+#define SEQ02__SEQ_MAP2_EN_MASK 0x04L
+#define SEQ02__SEQ_MAP3_EN_MASK 0x08L
+//SEQ03
+#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
+#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
+#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
+#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
+#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
+#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
+#define SEQ03__SEQ_FONT_B1_MASK 0x01L
+#define SEQ03__SEQ_FONT_B2_MASK 0x02L
+#define SEQ03__SEQ_FONT_A1_MASK 0x04L
+#define SEQ03__SEQ_FONT_A2_MASK 0x08L
+#define SEQ03__SEQ_FONT_B0_MASK 0x10L
+#define SEQ03__SEQ_FONT_A0_MASK 0x20L
+//SEQ04
+#define SEQ04__SEQ_256K__SHIFT 0x1
+#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
+#define SEQ04__SEQ_CHAIN__SHIFT 0x3
+#define SEQ04__SEQ_256K_MASK 0x02L
+#define SEQ04__SEQ_ODDEVEN_MASK 0x04L
+#define SEQ04__SEQ_CHAIN_MASK 0x08L
+
+
+// addressBlock: vga_vgacrtind
+//CRT00
+#define CRT00__H_TOTAL__SHIFT 0x0
+#define CRT00__H_TOTAL_MASK 0xFFL
+//CRT01
+#define CRT01__H_DISP_END__SHIFT 0x0
+#define CRT01__H_DISP_END_MASK 0xFFL
+//CRT02
+#define CRT02__H_BLANK_START__SHIFT 0x0
+#define CRT02__H_BLANK_START_MASK 0xFFL
+//CRT03
+#define CRT03__H_BLANK_END__SHIFT 0x0
+#define CRT03__H_DE_SKEW__SHIFT 0x5
+#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
+#define CRT03__H_BLANK_END_MASK 0x1FL
+#define CRT03__H_DE_SKEW_MASK 0x60L
+#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L
+//CRT04
+#define CRT04__H_SYNC_START__SHIFT 0x0
+#define CRT04__H_SYNC_START_MASK 0xFFL
+//CRT05
+#define CRT05__H_SYNC_END__SHIFT 0x0
+#define CRT05__H_SYNC_SKEW__SHIFT 0x5
+#define CRT05__H_BLANK_END_B5__SHIFT 0x7
+#define CRT05__H_SYNC_END_MASK 0x1FL
+#define CRT05__H_SYNC_SKEW_MASK 0x60L
+#define CRT05__H_BLANK_END_B5_MASK 0x80L
+//CRT06
+#define CRT06__V_TOTAL__SHIFT 0x0
+#define CRT06__V_TOTAL_MASK 0xFFL
+//CRT07
+#define CRT07__V_TOTAL_B8__SHIFT 0x0
+#define CRT07__V_DISP_END_B8__SHIFT 0x1
+#define CRT07__V_SYNC_START_B8__SHIFT 0x2
+#define CRT07__V_BLANK_START_B8__SHIFT 0x3
+#define CRT07__LINE_CMP_B8__SHIFT 0x4
+#define CRT07__V_TOTAL_B9__SHIFT 0x5
+#define CRT07__V_DISP_END_B9__SHIFT 0x6
+#define CRT07__V_SYNC_START_B9__SHIFT 0x7
+#define CRT07__V_TOTAL_B8_MASK 0x01L
+#define CRT07__V_DISP_END_B8_MASK 0x02L
+#define CRT07__V_SYNC_START_B8_MASK 0x04L
+#define CRT07__V_BLANK_START_B8_MASK 0x08L
+#define CRT07__LINE_CMP_B8_MASK 0x10L
+#define CRT07__V_TOTAL_B9_MASK 0x20L
+#define CRT07__V_DISP_END_B9_MASK 0x40L
+#define CRT07__V_SYNC_START_B9_MASK 0x80L
+//CRT08
+#define CRT08__ROW_SCAN_START__SHIFT 0x0
+#define CRT08__BYTE_PAN__SHIFT 0x5
+#define CRT08__ROW_SCAN_START_MASK 0x1FL
+#define CRT08__BYTE_PAN_MASK 0x60L
+//CRT09
+#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
+#define CRT09__V_BLANK_START_B9__SHIFT 0x5
+#define CRT09__LINE_CMP_B9__SHIFT 0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
+#define CRT09__MAX_ROW_SCAN_MASK 0x1FL
+#define CRT09__V_BLANK_START_B9_MASK 0x20L
+#define CRT09__LINE_CMP_B9_MASK 0x40L
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L
+//CRT0A
+#define CRT0A__CURSOR_START__SHIFT 0x0
+#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
+#define CRT0A__CURSOR_START_MASK 0x1FL
+#define CRT0A__CURSOR_DISABLE_MASK 0x20L
+//CRT0B
+#define CRT0B__CURSOR_END__SHIFT 0x0
+#define CRT0B__CURSOR_SKEW__SHIFT 0x5
+#define CRT0B__CURSOR_END_MASK 0x1FL
+#define CRT0B__CURSOR_SKEW_MASK 0x60L
+//CRT0C
+#define CRT0C__DISP_START__SHIFT 0x0
+#define CRT0C__DISP_START_MASK 0xFFL
+//CRT0D
+#define CRT0D__DISP_START__SHIFT 0x0
+#define CRT0D__DISP_START_MASK 0xFFL
+//CRT0E
+#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
+#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL
+//CRT0F
+#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
+#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL
+//CRT10
+#define CRT10__V_SYNC_START__SHIFT 0x0
+#define CRT10__V_SYNC_START_MASK 0xFFL
+//CRT11
+#define CRT11__V_SYNC_END__SHIFT 0x0
+#define CRT11__V_INTR_CLR__SHIFT 0x4
+#define CRT11__V_INTR_EN__SHIFT 0x5
+#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
+#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
+#define CRT11__V_SYNC_END_MASK 0x0FL
+#define CRT11__V_INTR_CLR_MASK 0x10L
+#define CRT11__V_INTR_EN_MASK 0x20L
+#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L
+#define CRT11__C0T7_WR_ONLY_MASK 0x80L
+//CRT12
+#define CRT12__V_DISP_END__SHIFT 0x0
+#define CRT12__V_DISP_END_MASK 0xFFL
+//CRT13
+#define CRT13__DISP_PITCH__SHIFT 0x0
+#define CRT13__DISP_PITCH_MASK 0xFFL
+//CRT14
+#define CRT14__UNDRLN_LOC__SHIFT 0x0
+#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
+#define CRT14__DOUBLE_WORD__SHIFT 0x6
+#define CRT14__UNDRLN_LOC_MASK 0x1FL
+#define CRT14__ADDR_CNT_BY4_MASK 0x20L
+#define CRT14__DOUBLE_WORD_MASK 0x40L
+//CRT15
+#define CRT15__V_BLANK_START__SHIFT 0x0
+#define CRT15__V_BLANK_START_MASK 0xFFL
+//CRT16
+#define CRT16__V_BLANK_END__SHIFT 0x0
+#define CRT16__V_BLANK_END_MASK 0xFFL
+//CRT17
+#define CRT17__RA0_AS_A13B__SHIFT 0x0
+#define CRT17__RA1_AS_A14B__SHIFT 0x1
+#define CRT17__VCOUNT_BY2__SHIFT 0x2
+#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
+#define CRT17__WRAP_A15TOA0__SHIFT 0x5
+#define CRT17__BYTE_MODE__SHIFT 0x6
+#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
+#define CRT17__RA0_AS_A13B_MASK 0x01L
+#define CRT17__RA1_AS_A14B_MASK 0x02L
+#define CRT17__VCOUNT_BY2_MASK 0x04L
+#define CRT17__ADDR_CNT_BY2_MASK 0x08L
+#define CRT17__WRAP_A15TOA0_MASK 0x20L
+#define CRT17__BYTE_MODE_MASK 0x40L
+#define CRT17__CRTC_SYNC_EN_MASK 0x80L
+//CRT18
+#define CRT18__LINE_CMP__SHIFT 0x0
+#define CRT18__LINE_CMP_MASK 0xFFL
+//CRT1E
+#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
+#define CRT1E__GRPH_DEC_RD1_MASK 0x02L
+//CRT1F
+#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
+#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL
+//CRT22
+#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
+#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL
+
+
+// addressBlock: vga_vgagrphind
+//GRA00
+#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
+#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
+#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
+#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
+#define GRA00__GRPH_SET_RESET0_MASK 0x01L
+#define GRA00__GRPH_SET_RESET1_MASK 0x02L
+#define GRA00__GRPH_SET_RESET2_MASK 0x04L
+#define GRA00__GRPH_SET_RESET3_MASK 0x08L
+//GRA01
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L
+#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L
+#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L
+#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L
+//GRA02
+#define GRA02__GRPH_CCOMP__SHIFT 0x0
+#define GRA02__GRPH_CCOMP_MASK 0x0FL
+//GRA03
+#define GRA03__GRPH_ROTATE__SHIFT 0x0
+#define GRA03__GRPH_FN_SEL__SHIFT 0x3
+#define GRA03__GRPH_ROTATE_MASK 0x07L
+#define GRA03__GRPH_FN_SEL_MASK 0x18L
+//GRA04
+#define GRA04__GRPH_RMAP__SHIFT 0x0
+#define GRA04__GRPH_RMAP_MASK 0x03L
+//GRA05
+#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
+#define GRA05__GRPH_READ1__SHIFT 0x3
+#define GRA05__CGA_ODDEVEN__SHIFT 0x4
+#define GRA05__GRPH_OES__SHIFT 0x5
+#define GRA05__GRPH_PACK__SHIFT 0x6
+#define GRA05__GRPH_WRITE_MODE_MASK 0x03L
+#define GRA05__GRPH_READ1_MASK 0x08L
+#define GRA05__CGA_ODDEVEN_MASK 0x10L
+#define GRA05__GRPH_OES_MASK 0x20L
+#define GRA05__GRPH_PACK_MASK 0x40L
+//GRA06
+#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
+#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
+#define GRA06__GRPH_ADRSEL__SHIFT 0x2
+#define GRA06__GRPH_GRAPHICS_MASK 0x01L
+#define GRA06__GRPH_ODDEVEN_MASK 0x02L
+#define GRA06__GRPH_ADRSEL_MASK 0x0CL
+//GRA07
+#define GRA07__GRPH_XCARE0__SHIFT 0x0
+#define GRA07__GRPH_XCARE1__SHIFT 0x1
+#define GRA07__GRPH_XCARE2__SHIFT 0x2
+#define GRA07__GRPH_XCARE3__SHIFT 0x3
+#define GRA07__GRPH_XCARE0_MASK 0x01L
+#define GRA07__GRPH_XCARE1_MASK 0x02L
+#define GRA07__GRPH_XCARE2_MASK 0x04L
+#define GRA07__GRPH_XCARE3_MASK 0x08L
+//GRA08
+#define GRA08__GRPH_BMSK__SHIFT 0x0
+#define GRA08__GRPH_BMSK_MASK 0xFFL
+
+
+// addressBlock: vga_vgaattrind
+//ATTR00
+#define ATTR00__ATTR_PAL__SHIFT 0x0
+#define ATTR00__ATTR_PAL_MASK 0x3FL
+//ATTR01
+#define ATTR01__ATTR_PAL__SHIFT 0x0
+#define ATTR01__ATTR_PAL_MASK 0x3FL
+//ATTR02
+#define ATTR02__ATTR_PAL__SHIFT 0x0
+#define ATTR02__ATTR_PAL_MASK 0x3FL
+//ATTR03
+#define ATTR03__ATTR_PAL__SHIFT 0x0
+#define ATTR03__ATTR_PAL_MASK 0x3FL
+//ATTR04
+#define ATTR04__ATTR_PAL__SHIFT 0x0
+#define ATTR04__ATTR_PAL_MASK 0x3FL
+//ATTR05
+#define ATTR05__ATTR_PAL__SHIFT 0x0
+#define ATTR05__ATTR_PAL_MASK 0x3FL
+//ATTR06
+#define ATTR06__ATTR_PAL__SHIFT 0x0
+#define ATTR06__ATTR_PAL_MASK 0x3FL
+//ATTR07
+#define ATTR07__ATTR_PAL__SHIFT 0x0
+#define ATTR07__ATTR_PAL_MASK 0x3FL
+//ATTR08
+#define ATTR08__ATTR_PAL__SHIFT 0x0
+#define ATTR08__ATTR_PAL_MASK 0x3FL
+//ATTR09
+#define ATTR09__ATTR_PAL__SHIFT 0x0
+#define ATTR09__ATTR_PAL_MASK 0x3FL
+//ATTR0A
+#define ATTR0A__ATTR_PAL__SHIFT 0x0
+#define ATTR0A__ATTR_PAL_MASK 0x3FL
+//ATTR0B
+#define ATTR0B__ATTR_PAL__SHIFT 0x0
+#define ATTR0B__ATTR_PAL_MASK 0x3FL
+//ATTR0C
+#define ATTR0C__ATTR_PAL__SHIFT 0x0
+#define ATTR0C__ATTR_PAL_MASK 0x3FL
+//ATTR0D
+#define ATTR0D__ATTR_PAL__SHIFT 0x0
+#define ATTR0D__ATTR_PAL_MASK 0x3FL
+//ATTR0E
+#define ATTR0E__ATTR_PAL__SHIFT 0x0
+#define ATTR0E__ATTR_PAL_MASK 0x3FL
+//ATTR0F
+#define ATTR0F__ATTR_PAL__SHIFT 0x0
+#define ATTR0F__ATTR_PAL_MASK 0x3FL
+//ATTR10
+#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
+#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
+#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
+#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
+#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
+#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
+#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
+#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L
+#define ATTR10__ATTR_MONO_EN_MASK 0x02L
+#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L
+#define ATTR10__ATTR_BLINK_EN_MASK 0x08L
+#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L
+#define ATTR10__ATTR_PCLKBY2_MASK 0x40L
+#define ATTR10__ATTR_CSEL_EN_MASK 0x80L
+//ATTR11
+#define ATTR11__ATTR_OVSC__SHIFT 0x0
+#define ATTR11__ATTR_OVSC_MASK 0xFFL
+//ATTR12
+#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
+#define ATTR12__ATTR_VSMUX__SHIFT 0x4
+#define ATTR12__ATTR_MAP_EN_MASK 0x0FL
+#define ATTR12__ATTR_VSMUX_MASK 0x30L
+//ATTR13
+#define ATTR13__ATTR_PPAN__SHIFT 0x0
+#define ATTR13__ATTR_PPAN_MASK 0x0FL
+//ATTR14
+#define ATTR14__ATTR_CSEL1__SHIFT 0x0
+#define ATTR14__ATTR_CSEL2__SHIFT 0x2
+#define ATTR14__ATTR_CSEL1_MASK 0x03L
+#define ATTR14__ATTR_CSEL2_MASK 0x0CL
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+// addressBlock: azendpoint_f2codecind
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL
+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L
+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azendpoint_descriptorind
+//AUDIO_DESCRIPTOR0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR1
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR2
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR3
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR4
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR5
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR6
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR8
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR9
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR10
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR11
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR12
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AUDIO_DESCRIPTOR13
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+
+
+// addressBlock: azendpoint_sinkinfoind
+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL
+//SINK_DESCRIPTION0
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION1
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION2
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION3
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION4
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION5
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION6
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION7
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION8
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION9
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION10
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION11
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION12
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION13
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION14
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION15
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION16
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL
+//SINK_DESCRIPTION17
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+//AZALIA_INPUT_CRC0_CHANNEL0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL1
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL2
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL3
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL4
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL5
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL6
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL7
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+//AZALIA_INPUT_CRC1_CHANNEL0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL1
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL2
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL3
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL4
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL5
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL6
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL7
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc0resultind
+//AZALIA_CRC0_CHANNEL0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL1
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL2
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL3
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL4
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL5
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL6
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL7
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc1resultind
+//AZALIA_CRC1_CHANNEL0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL1
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL2
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL3
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL4
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL5
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL6
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL7
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azinputendpoint_f2codecind
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+
+
+// addressBlock: azroot_f2codecind
+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
+
+
+// addressBlock: azf0stream0_streamind
+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream1_streamind
+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream2_streamind
+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream3_streamind
+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream4_streamind
+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream5_streamind
+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream6_streamind
+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream7_streamind
+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream8_streamind
+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream9_streamind
+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream10_streamind
+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream11_streamind
+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream12_streamind
+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream13_streamind
+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream14_streamind
+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0stream15_streamind
+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L
+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: azf0endpoint0_endpointind
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint1_endpointind
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint2_endpointind
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint3_endpointind
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint4_endpointind
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint5_endpointind
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint6_endpointind
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0endpoint7_endpointind
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
index a9575db8d7aa..6efcaa93e17b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
@@ -30,4 +30,22 @@
#define mmDF_CS_UMC_AON0_DramBaseAddress0 0x0044
#define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX 0
+#define smnPerfMonCtlLo0 0x01d440UL
+#define smnPerfMonCtlHi0 0x01d444UL
+#define smnPerfMonCtlLo1 0x01d450UL
+#define smnPerfMonCtlHi1 0x01d454UL
+#define smnPerfMonCtlLo2 0x01d460UL
+#define smnPerfMonCtlHi2 0x01d464UL
+#define smnPerfMonCtlLo3 0x01d470UL
+#define smnPerfMonCtlHi3 0x01d474UL
+
+#define smnPerfMonCtrLo0 0x01d448UL
+#define smnPerfMonCtrHi0 0x01d44cUL
+#define smnPerfMonCtrLo1 0x01d458UL
+#define smnPerfMonCtrHi1 0x01d45cUL
+#define smnPerfMonCtrLo2 0x01d468UL
+#define smnPerfMonCtrHi2 0x01d46cUL
+#define smnPerfMonCtrLo3 0x01d478UL
+#define smnPerfMonCtrHi3 0x01d47cUL
+
#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
new file mode 100644
index 000000000000..320e1ee5df1a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
@@ -0,0 +1,6028 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _gc_10_1_0_DEFAULT_HEADER
+#define _gc_10_1_0_DEFAULT_HEADER
+
+
+// addressBlock: gc_sdma0_sdma0dec
+#define mmSDMA0_DEC_START_DEFAULT 0x00000000
+#define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
+#define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
+#define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
+#define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
+#define mmSDMA0_CNTL_DEFAULT 0x000000c2
+#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
+#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
+#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000044
+#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
+#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000
+#define mmSDMA0_PROGRAM_DEFAULT 0x00000000
+#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557
+#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff
+#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000002
+#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000
+#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000
+#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001
+#define mmSDMA0_FREEZE_DEFAULT 0x00000000
+#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA_POWER_GATING_DEFAULT 0x00000000
+#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000
+#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000
+#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000
+#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002
+#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff
+#define mmSDMA0_ID_DEFAULT 0x00000001
+#define mmSDMA0_VERSION_DEFAULT 0x00000500
+#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000
+#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
+#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000
+#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200
+#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0000191
+#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbd9fb
+#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x01011555
+#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x51011555
+#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000800
+#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00000000
+#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000c5c20
+#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x00000000
+#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
+#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005
+#define mmSDMA0_STATUS3_REG_DEFAULT 0x03f00000
+#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000
+#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000
+#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd
+#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
+#define mmSDMA0_CRD_CNTL_DEFAULT 0x1668c640
+#define mmSDMA0_AQL_STATUS_DEFAULT 0x00000003
+#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
+#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
+#define mmSDMA0_TLBI_GCR_CNTL_DEFAULT 0x40180454
+#define mmSDMA0_TILING_CONFIG_DEFAULT 0x00000000
+#define mmSDMA0_HASH_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmSDMA0_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmSDMA0_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmSDMA0_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmSDMA0_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmSDMA0_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmSDMA0_INT_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG2_DEFAULT 0x00000000
+#define mmSDMA0_HOLE_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_HOLE_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
+#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_RLC2_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC2_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC2_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC2_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC2_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_RLC3_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC3_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC3_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC3_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC3_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_RLC4_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC4_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC4_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC4_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC4_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_RLC5_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC5_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC5_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC5_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC5_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_RLC6_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC6_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC6_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC6_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC6_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA0_RLC7_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA0_RLC7_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA0_RLC7_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_STATUS_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA0_RLC7_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA0_RLC7_MIDCMD_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_sdma1_sdma1dec
+#define mmSDMA1_DEC_START_DEFAULT 0x00000000
+#define mmSDMA1_PG_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_PG_CTX_LO_DEFAULT 0x00000000
+#define mmSDMA1_PG_CTX_HI_DEFAULT 0x00000000
+#define mmSDMA1_PG_CTX_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_POWER_CNTL_DEFAULT 0x40000050
+#define mmSDMA1_CLK_CTRL_DEFAULT 0x00000100
+#define mmSDMA1_CNTL_DEFAULT 0x000000c2
+#define mmSDMA1_CHICKEN_BITS_DEFAULT 0x01af0107
+#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00000044
+#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00000044
+#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000
+#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000
+#define mmSDMA1_PROGRAM_DEFAULT 0x00000000
+#define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557
+#define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff
+#define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000002
+#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000
+#define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000
+#define mmSDMA1_F32_CNTL_DEFAULT 0x00000001
+#define mmSDMA1_FREEZE_DEFAULT 0x00000000
+#define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002
+#define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff
+#define mmSDMA1_ID_DEFAULT 0x00000001
+#define mmSDMA1_VERSION_DEFAULT 0x00000500
+#define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000
+#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
+#define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001
+#define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200
+#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0000191
+#define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbd9fb
+#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x01011555
+#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x51011555
+#define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000800
+#define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00000000
+#define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000c5c20
+#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x00000000
+#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
+#define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005
+#define mmSDMA1_STATUS3_REG_DEFAULT 0x03f00000
+#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002
+#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000
+#define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000
+#define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd
+#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
+#define mmSDMA1_CRD_CNTL_DEFAULT 0x1668c640
+#define mmSDMA1_AQL_STATUS_DEFAULT 0x00000003
+#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
+#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
+#define mmSDMA1_TLBI_GCR_CNTL_DEFAULT 0x40180454
+#define mmSDMA1_TILING_CONFIG_DEFAULT 0x00000000
+#define mmSDMA1_HASH_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmSDMA1_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmSDMA1_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmSDMA1_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmSDMA1_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmSDMA1_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmSDMA1_INT_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG2_DEFAULT 0x00000000
+#define mmSDMA1_HOLE_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_HOLE_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
+#define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_RLC2_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC2_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC2_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC2_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC2_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_RLC3_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC3_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC3_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC3_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC3_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_RLC4_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC4_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC4_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC4_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC4_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_RLC5_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC5_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC5_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC5_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC5_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_RLC6_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC6_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC6_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC6_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC6_MIDCMD_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_CNTL_DEFAULT 0x80840000
+#define mmSDMA1_RLC7_RB_BASE_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_RPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_WPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
+#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_IB_CNTL_DEFAULT 0x00000100
+#define mmSDMA1_RLC7_IB_RPTR_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_IB_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_IB_BASE_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_IB_BASE_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_IB_SIZE_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_SKIP_CNTL_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_CONTEXT_STATUS_DEFAULT 0x00000004
+#define mmSDMA1_RLC7_DOORBELL_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_STATUS_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_WATERMARK_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_DOORBELL_OFFSET_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_CSA_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_CSA_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_IB_SUB_REMAIN_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_PREEMPT_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_DUMMY_REG_DEFAULT 0x0000000f
+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_RB_AQL_CNTL_DEFAULT 0x00004000
+#define mmSDMA1_RLC7_MINOR_PTR_UPDATE_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_DATA0_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_DATA1_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_DATA2_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_DATA3_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_DATA4_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_DATA5_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_DATA6_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_DATA7_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_DATA8_DEFAULT 0x00000000
+#define mmSDMA1_RLC7_MIDCMD_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_grbmdec
+#define mmGRBM_CNTL_DEFAULT 0x00000018
+#define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
+#define mmGRBM_STATUS2_DEFAULT 0x00000000
+#define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
+#define mmGRBM_STATUS_DEFAULT 0x00000000
+#define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
+#define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
+#define mmGRBM_STATUS3_DEFAULT 0x00000000
+#define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
+#define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
+#define mmGRBM_WAIT_IDLE_CLOCKS_DEFAULT 0x00000030
+#define mmGRBM_STATUS_SE2_DEFAULT 0x00000000
+#define mmGRBM_STATUS_SE3_DEFAULT 0x00000000
+#define mmGRBM_PM_CNTL_DEFAULT 0x00000000
+#define mmGRBM_READ_ERROR_DEFAULT 0x00000000
+#define mmGRBM_READ_ERROR2_DEFAULT 0x00000000
+#define mmGRBM_INT_CNTL_DEFAULT 0x00000000
+#define mmGRBM_TRAP_OP_DEFAULT 0x00000000
+#define mmGRBM_TRAP_ADDR_DEFAULT 0x00000000
+#define mmGRBM_TRAP_ADDR_MSK_DEFAULT 0x0003ffff
+#define mmGRBM_TRAP_WD_DEFAULT 0x00000000
+#define mmGRBM_TRAP_WD_MSK_DEFAULT 0xffffffff
+#define mmGRBM_DSM_BYPASS_DEFAULT 0x00000000
+#define mmGRBM_WRITE_ERROR_DEFAULT 0x00000000
+#define mmGRBM_IOV_ERROR_DEFAULT 0x00000000
+#define mmGRBM_CHIP_REVISION_DEFAULT 0x00000000
+#define mmGRBM_GFX_CNTL_DEFAULT 0x00000000
+#define mmGRBM_IH_CREDIT_DEFAULT 0x00010000
+#define mmGRBM_PWR_CNTL2_DEFAULT 0x00010000
+#define mmGRBM_UTCL2_INVAL_RANGE_START_DEFAULT 0x00002891
+#define mmGRBM_UTCL2_INVAL_RANGE_END_DEFAULT 0x000028ea
+#define mmGRBM_IOV_READ_ERROR_DEFAULT 0x00000000
+#define mmGRBM_FENCE_RANGE0_DEFAULT 0x00000000
+#define mmGRBM_FENCE_RANGE1_DEFAULT 0x00000000
+#define mmGRBM_NOWHERE_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG0_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG1_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG2_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG3_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG4_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG5_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG6_DEFAULT 0x00000000
+#define mmGRBM_SCRATCH_REG7_DEFAULT 0x00000000
+
+
+// addressBlock: gc_cpdec
+#define mmCP_CPC_STATUS_DEFAULT 0x00000000
+#define mmCP_CPC_BUSY_STAT_DEFAULT 0x00000000
+#define mmCP_CPC_STALLED_STAT1_DEFAULT 0x00000000
+#define mmCP_CPF_STATUS_DEFAULT 0x00000000
+#define mmCP_CPF_BUSY_STAT_DEFAULT 0x00000000
+#define mmCP_CPF_STALLED_STAT1_DEFAULT 0x00000000
+#define mmCP_CPC_BUSY_STAT2_DEFAULT 0x00000000
+#define mmCP_CPC_GRBM_FREE_COUNT_DEFAULT 0x00000008
+#define mmCP_MEC_CNTL_DEFAULT 0x50000000
+#define mmCP_MEC_ME1_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_MEC_ME2_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_CPC_SCRATCH_INDEX_DEFAULT 0x00000000
+#define mmCP_CPC_SCRATCH_DATA_DEFAULT 0x00000000
+#define mmCP_CPF_GRBM_FREE_COUNT_DEFAULT 0x00000002
+#define mmCP_CPF_BUSY_STAT2_DEFAULT 0x00000000
+#define mmCP_CPC_HALT_HYST_COUNT_DEFAULT 0x00000002
+#define mmCP_CE_COMPARE_COUNT_DEFAULT 0x00000000
+#define mmCP_CE_DE_COUNT_DEFAULT 0x00000000
+#define mmCP_DE_CE_COUNT_DEFAULT 0x00000000
+#define mmCP_DE_LAST_INVAL_COUNT_DEFAULT 0x00000000
+#define mmCP_DE_DE_COUNT_DEFAULT 0x00000000
+#define mmCP_STALLED_STAT3_DEFAULT 0x00000000
+#define mmCP_STALLED_STAT1_DEFAULT 0x00000000
+#define mmCP_STALLED_STAT2_DEFAULT 0x00000000
+#define mmCP_BUSY_STAT_DEFAULT 0x00000000
+#define mmCP_STAT_DEFAULT 0x00000000
+#define mmCP_ME_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_PFP_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_GRBM_FREE_COUNT_DEFAULT 0x00080808
+#define mmCP_CE_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_PFP_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_ME_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_CE_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_MEC1_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_MEC2_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_CSF_STAT_DEFAULT 0x00000000
+#define mmCP_ME_CNTL_DEFAULT 0x15000000
+#define mmCP_CNTX_STAT_DEFAULT 0x00000000
+#define mmCP_ME_PREEMPTION_DEFAULT 0x00000000
+#define mmCP_ROQ_THRESHOLDS_DEFAULT 0x00003010
+#define mmCP_MEQ_STQ_THRESHOLD_DEFAULT 0x00000010
+#define mmCP_RB2_RPTR_DEFAULT 0x00000000
+#define mmCP_RB1_RPTR_DEFAULT 0x00000000
+#define mmCP_RB0_RPTR_DEFAULT 0x00000000
+#define mmCP_RB_RPTR_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_DELAY_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_POLL_CNTL_DEFAULT 0x00400100
+#define mmCP_ROQ1_THRESHOLDS_DEFAULT 0x06008010
+#define mmCP_ROQ2_THRESHOLDS_DEFAULT 0x000380a0
+#define mmCP_STQ_THRESHOLDS_DEFAULT 0x00804000
+#define mmCP_QUEUE_THRESHOLDS_DEFAULT 0x00002b16
+#define mmCP_MEQ_THRESHOLDS_DEFAULT 0x00008040
+#define mmCP_ROQ_AVAIL_DEFAULT 0x00000000
+#define mmCP_STQ_AVAIL_DEFAULT 0x00000000
+#define mmCP_ROQ2_AVAIL_DEFAULT 0x00000000
+#define mmCP_MEQ_AVAIL_DEFAULT 0x00000000
+#define mmCP_CMD_INDEX_DEFAULT 0x00000000
+#define mmCP_CMD_DATA_DEFAULT 0x00000000
+#define mmCP_ROQ_RB_STAT_DEFAULT 0x00000000
+#define mmCP_ROQ_IB1_STAT_DEFAULT 0x00000000
+#define mmCP_ROQ_IB2_STAT_DEFAULT 0x00000000
+#define mmCP_STQ_STAT_DEFAULT 0x00000000
+#define mmCP_STQ_WR_STAT_DEFAULT 0x00000000
+#define mmCP_MEQ_STAT_DEFAULT 0x00000000
+#define mmCP_CEQ1_AVAIL_DEFAULT 0x00000000
+#define mmCP_CEQ2_AVAIL_DEFAULT 0x00000000
+#define mmCP_CE_ROQ_RB_STAT_DEFAULT 0x00000000
+#define mmCP_CE_ROQ_IB1_STAT_DEFAULT 0x00000000
+#define mmCP_CE_ROQ_IB2_STAT_DEFAULT 0x00000000
+#define mmCP_CE_ROQ_DB_STAT_DEFAULT 0x00000000
+#define mmCP_ROQ3_THRESHOLDS_DEFAULT 0x0004c120
+#define mmCP_ROQ_DB_STAT_DEFAULT 0x00000000
+
+
+// addressBlock: gc_padec
+#define mmVGT_VTX_VECT_EJECT_REG_DEFAULT 0x0000007d
+#define mmVGT_DMA_DATA_FIFO_DEPTH_DEFAULT 0x00000200
+#define mmVGT_DMA_REQ_FIFO_DEPTH_DEFAULT 0x00000020
+#define mmVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT 0x00000020
+#define mmVGT_LAST_COPY_STATE_DEFAULT 0x00000000
+#define mmVGT_CACHE_INVALIDATION_DEFAULT 0x09000000
+#define mmVGT_ESGS_RING_SIZE_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_SIZE_DEFAULT 0x00000000
+#define mmVGT_FIFO_DEPTHS_DEFAULT 0x10100040
+#define mmVGT_GS_VERTEX_REUSE_DEFAULT 0x00000010
+#define mmVGT_MC_LAT_CNTL_DEFAULT 0x000000fe
+#define mmIA_UTCL1_STATUS_2_DEFAULT 0x00000000
+#define mmVGT_CNTL_STATUS_DEFAULT 0x00000000
+#define mmWD_CNTL_STATUS_DEFAULT 0x00000000
+#define mmCC_GC_PRIM_CONFIG_DEFAULT 0x00000000
+#define mmGC_USER_PRIM_CONFIG_DEFAULT 0x00000000
+#define mmWD_QOS_DEFAULT 0x00000000
+#define mmWD_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmWD_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmGE_PC_CNTL_DEFAULT 0x00000400
+#define mmIA_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmIA_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmGE_FAST_CLKS_DEFAULT 0x00000000
+#define mmVGT_TF_RING_SIZE_DEFAULT 0x0000c000
+#define mmVGT_SYS_CONFIG_DEFAULT 0x00000011
+#define mmGE_PRIV_CONTROL_DEFAULT 0x000000fe
+#define mmGE_STATUS_DEFAULT 0x00000000
+#define mmVGT_VS_MAX_WAVE_ID_DEFAULT 0x000001ff
+#define mmVGT_GS_MAX_WAVE_ID_DEFAULT 0x000003ff
+#define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_DEFAULT 0x00000000
+#define mmVGT_HS_OFFCHIP_PARAM_DEFAULT 0x00000000
+#define mmGFX_PIPE_CONTROL_DEFAULT 0x00000000
+#define mmVGT_TF_MEMORY_BASE_DEFAULT 0x00000000
+#define mmCC_GC_SHADER_ARRAY_CONFIG_DEFAULT 0xffe00000
+#define mmGC_USER_SHADER_ARRAY_CONFIG_DEFAULT 0x00000000
+#define mmVGT_DMA_PRIMITIVE_TYPE_DEFAULT 0x00000000
+#define mmVGT_DMA_CONTROL_DEFAULT 0x00000000
+#define mmVGT_DMA_LS_HS_CONFIG_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_DELAY_DEFAULT 0x00092400
+#define mmWD_BUF_RESOURCE_1_DEFAULT 0x00000000
+#define mmWD_BUF_RESOURCE_2_DEFAULT 0x00000000
+#define mmVGT_TF_MEMORY_BASE_HI_DEFAULT 0x00000000
+#define mmPA_CL_CNTL_STATUS_DEFAULT 0x00000000
+#define mmPA_CL_ENHANCE_DEFAULT 0x00a00007
+#define mmPA_SU_CNTL_STATUS_DEFAULT 0x00000000
+#define mmPA_SC_FIFO_DEPTH_CNTL_DEFAULT 0x00000100
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000
+#define mmPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT 0x00ffffff
+#define mmPA_SC_BINNER_EVENT_CNTL_0_DEFAULT 0x842a4402
+#define mmPA_SC_BINNER_EVENT_CNTL_1_DEFAULT 0x82000008
+#define mmPA_SC_BINNER_EVENT_CNTL_2_DEFAULT 0x9118aab8
+#define mmPA_SC_BINNER_EVENT_CNTL_3_DEFAULT 0xc2400024
+#define mmPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_PERF_CNTL_0_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_PERF_CNTL_1_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_PERF_CNTL_2_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_PERF_CNTL_3_DEFAULT 0x00000000
+#define mmPA_SC_ENHANCE_2_DEFAULT 0x00000020
+#define mmPA_SC_ENHANCE_INTERNAL_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_CNTL_OVERRIDE_DEFAULT 0x08000000
+#define mmPA_SC_PBB_OVERRIDE_FLAG_DEFAULT 0x00000000
+#define mmPA_PH_INTERFACE_FIFO_SIZE_DEFAULT 0x00000100
+#define mmPA_PH_ENHANCE_DEFAULT 0x00001000
+#define mmPA_SC_BC_WAVE_BREAK_DEFAULT 0x00360040
+#define mmPA_SC_FIFO_SIZE_DEFAULT 0x00000000
+#define mmPA_SC_IF_FIFO_SIZE_DEFAULT 0x00000000
+#define mmPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT 0x00000000
+#define mmPA_SIDEBAND_REQUEST_DELAYS_DEFAULT 0x08000020
+#define mmPA_SC_ENHANCE_DEFAULT 0x08000001
+#define mmPA_SC_ENHANCE_1_DEFAULT 0x04040000
+#define mmPA_SC_DSM_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_sqdec
+#define mmSQ_CONFIG_DEFAULT 0x01180000
+#define mmSQC_CONFIG_DEFAULT 0x000a2000
+#define mmLDS_CONFIG_DEFAULT 0x00000000
+#define mmSQ_RANDOM_WAVE_PRI_DEFAULT 0x0000007f
+#define mmSQG_STATUS_DEFAULT 0x00000000
+#define mmSQ_FIFO_SIZES_DEFAULT 0x0000d001
+#define mmSQ_DSM_CNTL_DEFAULT 0x00000000
+#define mmSQ_DSM_CNTL2_DEFAULT 0x00000000
+#define mmSQ_RUNTIME_CONFIG_DEFAULT 0x00000000
+#define mmSH_MEM_BASES_DEFAULT 0x00000000
+#define mmSP_CONFIG_DEFAULT 0x00000001
+#define mmSQ_ARB_CONFIG_DEFAULT 0x00000030
+#define mmSH_MEM_CONFIG_DEFAULT 0x00000000
+#define mmCC_GC_SHADER_RATE_CONFIG_DEFAULT 0x00000000
+#define mmGC_USER_SHADER_RATE_CONFIG_DEFAULT 0x00000000
+#define mmSQ_INTERRUPT_AUTO_MASK_DEFAULT 0x00ffffff
+#define mmSQ_INTERRUPT_MSG_CTRL_DEFAULT 0x00000000
+#define mmSQG_UTCL0_CNTL1_DEFAULT 0x00000580
+#define mmSQG_UTCL0_CNTL2_DEFAULT 0x00000000
+#define mmSQG_UTCL0_STATUS_DEFAULT 0x00000000
+#define mmSQG_CONFIG_DEFAULT 0x00000000
+#define mmSQ_SHADER_TBA_LO_DEFAULT 0x00000000
+#define mmSQ_SHADER_TBA_HI_DEFAULT 0x00000000
+#define mmSQ_SHADER_TMA_LO_DEFAULT 0x00000000
+#define mmSQ_SHADER_TMA_HI_DEFAULT 0x00000000
+#define mmSQ_WATCH0_ADDR_H_DEFAULT 0x00000000
+#define mmSQ_WATCH0_ADDR_L_DEFAULT 0x00000000
+#define mmSQ_WATCH0_CNTL_DEFAULT 0x00000000
+#define mmSQ_WATCH1_ADDR_H_DEFAULT 0x00000000
+#define mmSQ_WATCH1_ADDR_L_DEFAULT 0x00000000
+#define mmSQ_WATCH1_CNTL_DEFAULT 0x00000000
+#define mmSQ_WATCH2_ADDR_H_DEFAULT 0x00000000
+#define mmSQ_WATCH2_ADDR_L_DEFAULT 0x00000000
+#define mmSQ_WATCH2_CNTL_DEFAULT 0x00000000
+#define mmSQ_WATCH3_ADDR_H_DEFAULT 0x00000000
+#define mmSQ_WATCH3_ADDR_L_DEFAULT 0x00000000
+#define mmSQ_WATCH3_CNTL_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_BUF0_BASE_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_BUF0_SIZE_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_BUF1_BASE_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_BUF1_SIZE_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_WPTR_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_MASK_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_CTRL_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_STATUS_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_DROPPED_CNTR_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_DEFAULT 0x00000000
+#define mmSQ_IND_INDEX_DEFAULT 0x00000000
+#define mmSQ_IND_DATA_DEFAULT 0x00000000
+#define mmSQ_CMD_DEFAULT 0x00000000
+#define mmSQ_TIME_HI_DEFAULT 0x00000000
+#define mmSQ_TIME_LO_DEFAULT 0x00000000
+#define mmSQ_LB_CTR_CTRL_DEFAULT 0x00000000
+#define mmSQ_LB_DATA0_DEFAULT 0x00000000
+#define mmSQ_LB_DATA1_DEFAULT 0x00000000
+#define mmSQ_LB_DATA2_DEFAULT 0x00000000
+#define mmSQ_LB_DATA3_DEFAULT 0x00000000
+#define mmSQ_LB_CTR_SEL0_DEFAULT 0x00000000
+#define mmSQ_LB_CTR_SEL1_DEFAULT 0x00000000
+#define mmSQ_EDC_CNT_DEFAULT 0x00000000
+#define mmSQ_EDC_FUE_CNTL_DEFAULT 0x00000000
+#define mmSQ_WREXEC_EXEC_HI_DEFAULT 0x00000000
+#define mmSQ_WREXEC_EXEC_LO_DEFAULT 0x00000000
+#define mmSQC_ICACHE_UTCL0_CNTL1_DEFAULT 0x00000480
+#define mmSQC_ICACHE_UTCL0_CNTL2_DEFAULT 0x00000000
+#define mmSQC_DCACHE_UTCL0_CNTL1_DEFAULT 0x00000500
+#define mmSQC_DCACHE_UTCL0_CNTL2_DEFAULT 0x00000000
+#define mmSQC_ICACHE_UTCL0_STATUS_DEFAULT 0x00000000
+#define mmSQC_DCACHE_UTCL0_STATUS_DEFAULT 0x00000000
+#define mmSQC_MISC_CONFIG_DEFAULT 0x00000000
+
+
+// addressBlock: gc_shsdec
+#define mmSX_DEBUG_1_DEFAULT 0x00000020
+#define mmSPI_PS_MAX_WAVE_ID_DEFAULT 0x020000ff
+#define mmSPI_START_PHASE_DEFAULT 0x00000004
+#define mmSPI_GFX_CNTL_DEFAULT 0x00000000
+#define mmSPI_USER_ACCUM_VMID_CNTL_DEFAULT 0x00000000
+#define mmSPI_CONFIG_CNTL_DEFAULT 0xc062c688
+#define mmSPI_DSM_CNTL_DEFAULT 0x00000000
+#define mmSPI_DSM_CNTL2_DEFAULT 0x00000000
+#define mmSPI_EDC_CNT_DEFAULT 0x00000000
+#define mmSPI_WAVE_LIMIT_CNTL_DEFAULT 0x00000000
+#define mmSPI_CONFIG_CNTL_2_DEFAULT 0x00000011
+#define mmSPI_CONFIG_CNTL_1_DEFAULT 0x000c0104
+#define mmSPI_WF_LIFETIME_CNTL_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_LIMIT_0_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_1_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_2_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_3_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_4_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_5_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_6_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_7_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_8_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_LIMIT_9_DEFAULT 0x00000100
+#define mmSPI_WF_LIFETIME_STATUS_0_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_1_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_2_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_3_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_4_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_5_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_6_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_7_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_8_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_9_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_10_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_11_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_12_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_13_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_14_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_15_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_16_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_17_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_18_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_19_DEFAULT 0x00000000
+#define mmSPI_WF_LIFETIME_STATUS_20_DEFAULT 0x00000000
+#define mmSPI_LB_CTR_CTRL_DEFAULT 0x00000000
+#define mmSPI_LB_WGP_MASK_DEFAULT 0x0000ffff
+#define mmSPI_LB_DATA_REG_DEFAULT 0x00000000
+#define mmSPI_PG_ENABLE_STATIC_WGP_MASK_DEFAULT 0x0000ffff
+#define mmSPI_GDS_CREDITS_DEFAULT 0x0000203c
+#define mmSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT 0x10000400
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT 0x00800040
+#define mmSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_DEFAULT 0x00000000
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_DEFAULT 0x00000000
+#define mmSPI_LB_DATA_WAVES_DEFAULT 0x00000000
+#define mmSPI_LB_DATA_PERWGP_WAVE_HSGS_DEFAULT 0x00000000
+#define mmSPI_LB_DATA_PERWGP_WAVE_VSPS_DEFAULT 0x00000000
+#define mmSPI_LB_DATA_PERWGP_WAVE_CS_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000
+
+
+// addressBlock: gc_tpdec
+#define mmTD_CNTL_DEFAULT 0x00000000
+#define mmTD_STATUS_DEFAULT 0x00000000
+#define mmTD_POWER_CNTL_DEFAULT 0x00000024
+#define mmTD_DSM_CNTL_DEFAULT 0x00000000
+#define mmTD_DSM_CNTL2_DEFAULT 0x00000000
+#define mmTD_SCRATCH_DEFAULT 0x00000000
+#define mmTA_POWER_CNTL_DEFAULT 0x00020002
+#define mmTA_CNTL_DEFAULT 0xa004005a
+#define mmTA_CNTL_AUX_DEFAULT 0x01030000
+#define mmTA_RESERVED_010C_DEFAULT 0x00000000
+#define mmTA_STATUS_DEFAULT 0x00000000
+#define mmTA_SCRATCH_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gdsdec
+#define mmGDS_CONFIG_DEFAULT 0x00000000
+#define mmGDS_CNTL_STATUS_DEFAULT 0x00000000
+#define mmGDS_ENHANCE_DEFAULT 0x00000000
+#define mmGDS_PROTECTION_FAULT_DEFAULT 0x00000000
+#define mmGDS_VM_PROTECTION_FAULT_DEFAULT 0x00000000
+#define mmGDS_EDC_CNT_DEFAULT 0x00000000
+#define mmGDS_EDC_GRBM_CNT_DEFAULT 0x00000000
+#define mmGDS_EDC_OA_DED_DEFAULT 0x00000000
+#define mmGDS_DSM_CNTL_DEFAULT 0x00000000
+#define mmGDS_EDC_OA_PHY_CNT_DEFAULT 0x00000000
+#define mmGDS_EDC_OA_PIPE_CNT_DEFAULT 0x00000000
+#define mmGDS_DSM_CNTL2_DEFAULT 0x00000000
+#define mmGDS_WD_GDS_CSB_DEFAULT 0x00000000
+
+
+// addressBlock: gc_rbdec
+#define mmDB_DEBUG_DEFAULT 0x00000000
+#define mmDB_DEBUG2_DEFAULT 0x00200420
+#define mmDB_DEBUG3_DEFAULT 0x00000000
+#define mmDB_DEBUG4_DEFAULT 0x04000000
+#define mmDB_ETILE_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDB_LTILE_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDB_EQUAD_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDB_LQUAD_STUTTER_CONTROL_DEFAULT 0x00000000
+#define mmDB_CREDIT_LIMIT_DEFAULT 0x00000000
+#define mmDB_WATERMARKS_DEFAULT 0x0a040a04
+#define mmDB_SUBTILE_CONTROL_DEFAULT 0x00000000
+#define mmDB_FREE_CACHELINES_DEFAULT 0x00000000
+#define mmDB_FIFO_DEPTH1_DEFAULT 0x00000000
+#define mmDB_FIFO_DEPTH2_DEFAULT 0x00000000
+#define mmDB_LAST_OF_BURST_CONFIG_DEFAULT 0x02060410
+#define mmDB_RING_CONTROL_DEFAULT 0x00000001
+#define mmDB_MEM_ARB_WATERMARKS_DEFAULT 0x04040404
+#define mmDB_FIFO_DEPTH3_DEFAULT 0x00000000
+#define mmDB_RMI_BC_GL2_CACHE_CONTROL_DEFAULT 0x00150055
+#define mmDB_EXCEPTION_CONTROL_DEFAULT 0x00000000
+#define mmDB_DFSM_CONFIG_DEFAULT 0x00000000
+#define mmDB_DFSM_TILES_IN_FLIGHT_DEFAULT 0x000003e8
+#define mmDB_DFSM_PRIMS_IN_FLIGHT_DEFAULT 0x000000c8
+#define mmDB_DFSM_WATCHDOG_DEFAULT 0x000f4240
+#define mmDB_DFSM_FLUSH_ENABLE_DEFAULT 0x000007ff
+#define mmDB_DFSM_FLUSH_AUX_EVENT_DEFAULT 0x00000000
+#define mmDB_FGCG_SRAMS_CLK_CTRL_DEFAULT 0x00000000
+#define mmDB_FGCG_INTERFACES_CLK_CTRL_DEFAULT 0x00000000
+#define mmCC_RB_REDUNDANCY_DEFAULT 0x00000000
+#define mmCC_RB_BACKEND_DISABLE_DEFAULT 0x00000000
+#define mmGB_ADDR_CONFIG_DEFAULT 0x00000044
+#define mmGB_BACKEND_MAP_DEFAULT 0x00000000
+#define mmGB_GPU_ID_DEFAULT 0x00000000
+#define mmCC_RB_DAISY_CHAIN_DEFAULT 0x76543210
+#define mmGB_ADDR_CONFIG_READ_DEFAULT 0x00000044
+#define mmGB_TILE_MODE0_DEFAULT 0x00000000
+#define mmGB_TILE_MODE1_DEFAULT 0x00000000
+#define mmGB_TILE_MODE2_DEFAULT 0x00000000
+#define mmGB_TILE_MODE3_DEFAULT 0x00000000
+#define mmGB_TILE_MODE4_DEFAULT 0x00000000
+#define mmGB_TILE_MODE5_DEFAULT 0x00000000
+#define mmGB_TILE_MODE6_DEFAULT 0x00000000
+#define mmGB_TILE_MODE7_DEFAULT 0x00000000
+#define mmGB_TILE_MODE8_DEFAULT 0x00000000
+#define mmGB_TILE_MODE9_DEFAULT 0x00000000
+#define mmGB_TILE_MODE10_DEFAULT 0x00000000
+#define mmGB_TILE_MODE11_DEFAULT 0x00000000
+#define mmGB_TILE_MODE12_DEFAULT 0x00000000
+#define mmGB_TILE_MODE13_DEFAULT 0x00000000
+#define mmGB_TILE_MODE14_DEFAULT 0x00000000
+#define mmGB_TILE_MODE15_DEFAULT 0x00000000
+#define mmGB_TILE_MODE16_DEFAULT 0x00000000
+#define mmGB_TILE_MODE17_DEFAULT 0x00000000
+#define mmGB_TILE_MODE18_DEFAULT 0x00000000
+#define mmGB_TILE_MODE19_DEFAULT 0x00000000
+#define mmGB_TILE_MODE20_DEFAULT 0x00000000
+#define mmGB_TILE_MODE21_DEFAULT 0x00000000
+#define mmGB_TILE_MODE22_DEFAULT 0x00000000
+#define mmGB_TILE_MODE23_DEFAULT 0x00000000
+#define mmGB_TILE_MODE24_DEFAULT 0x00000000
+#define mmGB_TILE_MODE25_DEFAULT 0x00000000
+#define mmGB_TILE_MODE26_DEFAULT 0x00000000
+#define mmGB_TILE_MODE27_DEFAULT 0x00000000
+#define mmGB_TILE_MODE28_DEFAULT 0x00000000
+#define mmGB_TILE_MODE29_DEFAULT 0x00000000
+#define mmGB_TILE_MODE30_DEFAULT 0x00000000
+#define mmGB_TILE_MODE31_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE0_DEFAULT 0x000000e8
+#define mmGB_MACROTILE_MODE1_DEFAULT 0x000000d4
+#define mmGB_MACROTILE_MODE2_DEFAULT 0x000000d0
+#define mmGB_MACROTILE_MODE3_DEFAULT 0x000000d0
+#define mmGB_MACROTILE_MODE4_DEFAULT 0x00000080
+#define mmGB_MACROTILE_MODE5_DEFAULT 0x00000040
+#define mmGB_MACROTILE_MODE6_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE7_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE8_DEFAULT 0x000000ec
+#define mmGB_MACROTILE_MODE9_DEFAULT 0x000000e8
+#define mmGB_MACROTILE_MODE10_DEFAULT 0x000000d4
+#define mmGB_MACROTILE_MODE11_DEFAULT 0x000000d0
+#define mmGB_MACROTILE_MODE12_DEFAULT 0x00000080
+#define mmGB_MACROTILE_MODE13_DEFAULT 0x00000040
+#define mmGB_MACROTILE_MODE14_DEFAULT 0x00000000
+#define mmGB_MACROTILE_MODE15_DEFAULT 0x00000000
+#define mmCB_HW_CONTROL_4_DEFAULT 0x00000014
+#define mmCB_HW_CONTROL_3_DEFAULT 0x00000000
+#define mmCB_HW_CONTROL_DEFAULT 0x00040000
+#define mmCB_HW_CONTROL_1_DEFAULT 0x10000000
+#define mmCB_HW_CONTROL_2_DEFAULT 0x24000000
+#define mmCB_DCC_CONFIG_DEFAULT 0x00000000
+#define mmCB_HW_MEM_ARBITER_RD_DEFAULT 0x00029000
+#define mmCB_HW_MEM_ARBITER_WR_DEFAULT 0x00029000
+#define mmCB_RMI_BC_GL2_CACHE_CONTROL_DEFAULT 0x00550055
+#define mmCB_STUTTER_CONTROL_CMASK_RDLAT_DEFAULT 0x00000000
+#define mmCB_STUTTER_CONTROL_FMASK_RDLAT_DEFAULT 0x00000000
+#define mmCB_STUTTER_CONTROL_COLOR_RDLAT_DEFAULT 0x00000000
+#define mmCB_CACHE_EVICT_POINTS_DEFAULT 0x0b101410
+#define mmGC_USER_RB_REDUNDANCY_DEFAULT 0x00000000
+#define mmGC_USER_RB_BACKEND_DISABLE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gceadec2
+#define mmGCEA_SDP_VCD_RESERVE1_DEFAULT 0x00000000
+#define mmGCEA_SDP_REQ_CNTL_DEFAULT 0x0000001f
+#define mmGCEA_MISC_DEFAULT 0x0de03ff0
+#define mmGCEA_LATENCY_SAMPLING_DEFAULT 0x00000000
+#define mmGCEA_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGCEA_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmGCEA_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmGCEA_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmGCEA_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmGCEA_EDC_CNT_DEFAULT 0x00000000
+#define mmGCEA_EDC_CNT2_DEFAULT 0x00000000
+#define mmGCEA_DSM_CNTL_DEFAULT 0x00000000
+#define mmGCEA_DSM_CNTLA_DEFAULT 0x00000000
+#define mmGCEA_DSM_CNTLB_DEFAULT 0x00000000
+#define mmGCEA_DSM_CNTL2_DEFAULT 0x00000000
+#define mmGCEA_DSM_CNTL2A_DEFAULT 0x00000000
+#define mmGCEA_DSM_CNTL2B_DEFAULT 0x00000000
+#define mmGCEA_GL2C_XBR_CREDITS_DEFAULT 0x637f637f
+#define mmGCEA_GL2C_XBR_MAXBURST_DEFAULT 0x00333333
+#define mmGCEA_PROBE_CNTL_DEFAULT 0x00000000
+#define mmGCEA_PROBE_MAP_DEFAULT 0x0000aaaa
+#define mmGCEA_ERR_STATUS_DEFAULT 0x00000300
+#define mmGCEA_MISC2_DEFAULT 0x00000000
+
+
+// addressBlock: gc_spipdec2
+#define mmSPI_PQEV_CTRL_DEFAULT 0x00ff1008
+#define mmSPI_SYS_COMPUTE_DEFAULT 0x00000000
+#define mmSPI_SYS_WIF_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gceadec3
+#define mmGCEA_DRAM_BANK_ARB_DEFAULT 0x00008000
+#define mmGCEA_DRAM_BANK_ARB_RFSH_DEFAULT 0x00000000
+#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_DEFAULT 0x00000000
+#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_DEFAULT 0x00000000
+#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_DEFAULT 0x00000000
+#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_DEFAULT 0x00000000
+#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PACH_DEFAULT 0x00000000
+#define mmGCEA_RRET_MEM_RESERVE_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC_SELECT_DEFAULT 0x00000000
+#define mmGCEA_SDP_ENABLE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_rmi_rmidec
+#define mmRMI_GENERAL_CNTL_DEFAULT 0x00000000
+#define mmRMI_GENERAL_CNTL1_DEFAULT 0x00003203
+#define mmRMI_GENERAL_STATUS_DEFAULT 0x00000000
+#define mmRMI_SUBBLOCK_STATUS0_DEFAULT 0x00000000
+#define mmRMI_SUBBLOCK_STATUS1_DEFAULT 0x00000000
+#define mmRMI_SUBBLOCK_STATUS2_DEFAULT 0x00000000
+#define mmRMI_SUBBLOCK_STATUS3_DEFAULT 0x00000000
+#define mmRMI_XBAR_CONFIG_DEFAULT 0x00000f00
+#define mmRMI_PROBE_POP_LOGIC_CNTL_DEFAULT 0x000340d0
+#define mmRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT 0x00000564
+#define mmRMI_DEMUX_CNTL_DEFAULT 0x02000200
+#define mmRMI_UTCL1_CNTL1_DEFAULT 0x00020000
+#define mmRMI_UTCL1_CNTL2_DEFAULT 0x00010000
+#define mmRMI_UTC_UNIT_CONFIG_DEFAULT 0x00000000
+#define mmRMI_TCIW_FORMATTER0_CNTL_DEFAULT 0x4404001e
+#define mmRMI_TCIW_FORMATTER1_CNTL_DEFAULT 0x4404001e
+#define mmRMI_SCOREBOARD_CNTL_DEFAULT 0x001ffe00
+#define mmRMI_SCOREBOARD_STATUS0_DEFAULT 0x00000000
+#define mmRMI_SCOREBOARD_STATUS1_DEFAULT 0x00000000
+#define mmRMI_SCOREBOARD_STATUS2_DEFAULT 0x00000000
+#define mmRMI_XBAR_ARBITER_CONFIG_DEFAULT 0x08000800
+#define mmRMI_XBAR_ARBITER_CONFIG_1_DEFAULT 0xffffffff
+#define mmRMI_CLOCK_CNTRL_DEFAULT 0x04208822
+#define mmRMI_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmRMI_RB_GLX_CID_MAP_DEFAULT 0xbcaa9987
+#define mmRMI_SPARE_DEFAULT 0xffff3109
+#define mmRMI_SPARE_1_DEFAULT 0x00000a00
+#define mmRMI_SPARE_2_DEFAULT 0x00000000
+#define mmCC_RMI_REDUNDANCY_DEFAULT 0x00000010
+#define mmGC_USER_RMI_REDUNDANCY_DEFAULT 0x00000010
+
+
+// addressBlock: gc_pmmdec
+#define mmPMM_GENERAL_CNTL_DEFAULT 0x00000000
+#define mmGCR_PIO_CNTL_DEFAULT 0x00000000
+#define mmGCR_PIO_DATA_DEFAULT 0x00000000
+#define mmGCR_GENERAL_CNTL_DEFAULT 0x00000400
+#define mmGCR_TARGET_DISABLE_DEFAULT 0x00000000
+#define mmGCR_CMD_STATUS_DEFAULT 0x00000000
+#define mmGCR_SPARE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_utcl1dec
+#define mmUTCL1_CTRL_DEFAULT 0x00000000
+#define mmUTCL1_ALOG_DEFAULT 0x001864a2
+#define mmUTCL1_UTCL0_INVREQ_DISABLE_DEFAULT 0x00000000
+#define mmGCRD_SA_TARGETS_DISABLE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcatcl2dec
+#define mmGC_ATC_L2_CNTL_DEFAULT 0x000001c0
+#define mmGC_ATC_L2_CNTL2_DEFAULT 0x00000100
+#define mmGC_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000
+#define mmGC_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000
+#define mmGC_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000
+#define mmGC_ATC_L2_CNTL3_DEFAULT 0x000001f8
+#define mmGC_ATC_L2_STATUS_DEFAULT 0x00000000
+#define mmGC_ATC_L2_STATUS2_DEFAULT 0x00000000
+#define mmGC_ATC_L2_MISC_CG_DEFAULT 0x00000200
+#define mmGC_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmGC_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+#define mmGC_ATC_L2_SDPPORT_CTRL_DEFAULT 0x000003ff
+
+
+// addressBlock: gc_gcvml2pfdec
+#define mmGCVM_L2_CNTL_DEFAULT 0x00080602
+#define mmGCVM_L2_CNTL2_DEFAULT 0x00000000
+#define mmGCVM_L2_CNTL3_DEFAULT 0x80100007
+#define mmGCVM_L2_STATUS_DEFAULT 0x00000000
+#define mmGCVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090
+#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_CNTL_DEFAULT 0x0000010f
+#define mmGCVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc
+#define mmGCVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000
+#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff
+#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff
+#define mmGCVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000
+#define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000
+#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000
+#define mmGCVM_L2_CNTL4_DEFAULT 0x000000c1
+#define mmGCVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000
+#define mmGCVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000
+#define mmGCVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000
+#define mmGCVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000
+#define mmGCVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+#define mmGCVM_L2_CNTL5_DEFAULT 0x00003fe0
+#define mmGCVM_L2_GCR_CNTL_DEFAULT 0x00000000
+#define mmGCVML2_WALKER_MACRO_THROTTLE_TIME_DEFAULT 0x00000000
+#define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000
+#define mmGCVML2_WALKER_MICRO_THROTTLE_TIME_DEFAULT 0x00000000
+#define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcvml2vcdec
+#define mmGCVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80
+#define mmGCVM_CONTEXTS_DISABLE_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG0_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG1_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG2_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG3_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG4_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG5_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG6_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG7_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG8_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG9_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG10_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG11_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG12_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG13_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG14_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG15_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG16_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG17_REQ_DEFAULT 0x02f80000
+#define mmGCVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcvmsharedpfdec
+#define mmGCMC_VM_NB_MMIOBASE_DEFAULT 0x00000000
+#define mmGCMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000
+#define mmGCMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000
+#define mmGCMC_VM_NB_PCI_ARB_DEFAULT 0x00000008
+#define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000
+#define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000
+#define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_OFFSET_DEFAULT 0x00000000
+#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
+#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
+#define mmGCMC_VM_STEERING_DEFAULT 0x00000001
+#define mmGCMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmGCMC_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000
+#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000
+#define mmGCMC_VM_APT_CNTL_DEFAULT 0x00000000
+#define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000
+#define mmGCMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000
+#define mmGCMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff
+#define mmGCMC_SHARED_VIRT_RESET_REQ2_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcvmsharedvcdec
+#define mmGCMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000
+#define mmGCMC_VM_AGP_TOP_DEFAULT 0x00000000
+#define mmGCMC_VM_AGP_BOT_DEFAULT 0x00000000
+#define mmGCMC_VM_AGP_BASE_DEFAULT 0x00000000
+#define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000
+#define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000
+#define mmGCMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000501
+
+
+// addressBlock: gc_gceadec
+#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0xa9503aaa
+#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0xa9503aaa
+#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0xa9503aaa
+#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0xa9503aaa
+#define mmGCEA_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000924
+#define mmGCEA_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000324
+#define mmGCEA_DRAM_RD_LAZY_DEFAULT 0x78000924
+#define mmGCEA_DRAM_WR_LAZY_DEFAULT 0x78000924
+#define mmGCEA_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444
+#define mmGCEA_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444
+#define mmGCEA_DRAM_PAGE_BURST_DEFAULT 0x20082008
+#define mmGCEA_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249
+#define mmGCEA_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249
+#define mmGCEA_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmGCEA_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmGCEA_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924
+#define mmGCEA_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924
+#define mmGCEA_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6
+#define mmGCEA_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6
+#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmGCEA_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000
+#define mmGCEA_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000
+#define mmGCEA_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000
+#define mmGCEA_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000
+#define mmGCEA_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000
+#define mmGCEA_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000
+#define mmGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef
+#define mmGCEA_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START0_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END0_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START1_DEFAULT 0x00000000
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END1_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe
+#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe
+#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
+#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
+#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408
+#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408
+#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543
+#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543
+#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321
+#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321
+#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543
+#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543
+#define mmGCEA_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe
+#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe
+#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
+#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
+#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408
+#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408
+#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543
+#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543
+#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321
+#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321
+#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543
+#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543
+#define mmGCEA_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000
+#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000
+#define mmGCEA_IO_RD_CLI2GRP_MAP0_DEFAULT 0xa9503aaa
+#define mmGCEA_IO_RD_CLI2GRP_MAP1_DEFAULT 0xa9503aaa
+#define mmGCEA_IO_WR_CLI2GRP_MAP0_DEFAULT 0xa9503aaa
+#define mmGCEA_IO_WR_CLI2GRP_MAP1_DEFAULT 0xa9503aaa
+#define mmGCEA_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777
+#define mmGCEA_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777
+#define mmGCEA_IO_GROUP_BURST_DEFAULT 0x1f031f03
+#define mmGCEA_IO_RD_PRI_AGE_DEFAULT 0x00db6249
+#define mmGCEA_IO_WR_PRI_AGE_DEFAULT 0x00db6249
+#define mmGCEA_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmGCEA_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmGCEA_IO_RD_PRI_FIXED_DEFAULT 0x00000924
+#define mmGCEA_IO_WR_PRI_FIXED_DEFAULT 0x00000924
+#define mmGCEA_IO_RD_PRI_URGENCY_DEFAULT 0x00000492
+#define mmGCEA_IO_WR_PRI_URGENCY_DEFAULT 0x00000492
+#define mmGCEA_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff
+#define mmGCEA_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff
+#define mmGCEA_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmGCEA_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmGCEA_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmGCEA_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmGCEA_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmGCEA_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmGCEA_SDP_ARB_DRAM_DEFAULT 0x00101e7f
+#define mmGCEA_SDP_ARB_FINAL_DEFAULT 0x00007fff
+#define mmGCEA_SDP_DRAM_PRIORITY_DEFAULT 0x00000000
+#define mmGCEA_SDP_IO_PRIORITY_DEFAULT 0x00000000
+#define mmGCEA_SDP_CREDITS_DEFAULT 0x000101bf
+#define mmGCEA_SDP_TAG_RESERVE0_DEFAULT 0x00000000
+#define mmGCEA_SDP_TAG_RESERVE1_DEFAULT 0x00000000
+#define mmGCEA_SDP_VCC_RESERVE0_DEFAULT 0x00000000
+#define mmGCEA_SDP_VCC_RESERVE1_DEFAULT 0x00000000
+#define mmGCEA_SDP_VCD_RESERVE0_DEFAULT 0x00000000
+
+
+// addressBlock: gc_tcdec
+#define mmTCP_INVALIDATE_DEFAULT 0x00000000
+#define mmTCP_STATUS_DEFAULT 0x00000000
+#define mmTCP_CNTL_DEFAULT 0x679c0000
+#define mmTCP_CREDIT_DEFAULT 0x80400000
+#define mmTCP_BUFFER_ADDR_HASH_CNTL_DEFAULT 0x00000000
+#define mmTCP_EDC_CNT_DEFAULT 0x00000000
+#define mmTCI_STATUS_DEFAULT 0x00000000
+#define mmTCI_CNTL_1_DEFAULT 0x40080022
+#define mmTCI_CNTL_2_DEFAULT 0x00000041
+
+
+// addressBlock: gc_shdec
+#define mmSPI_SHADER_PGM_RSRC4_PS_DEFAULT 0x0000ffff
+#define mmSPI_SHADER_PGM_CHKSUM_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC3_PS_DEFAULT 0x0000ffff
+#define mmSPI_SHADER_PGM_LO_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_16_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_17_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_18_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_19_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_20_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_21_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_22_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_23_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_24_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_25_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_26_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_27_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_28_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_29_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_30_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_PS_31_DEFAULT 0x00000000
+#define mmSPI_SHADER_REQ_CTRL_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_PS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_PS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_PS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_PS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_PS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC4_VS_DEFAULT 0x0000ffff
+#define mmSPI_SHADER_PGM_CHKSUM_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC3_VS_DEFAULT 0x0000ffff
+#define mmSPI_SHADER_LATE_ALLOC_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_LO_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_16_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_17_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_18_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_19_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_20_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_21_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_22_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_23_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_24_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_25_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_26_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_27_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_28_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_29_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_30_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_VS_31_DEFAULT 0x00000000
+#define mmSPI_SHADER_REQ_CTRL_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_VS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_VS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_VS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_VS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_GS_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_ES_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_LS_VS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_CHKSUM_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC4_GS_DEFAULT 0x0010ffff
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_LO_ES_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_ES_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC3_GS_DEFAULT 0x0000fffe
+#define mmSPI_SHADER_PGM_LO_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_16_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_17_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_18_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_19_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_20_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_21_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_22_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_23_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_24_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_25_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_26_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_27_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_28_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_29_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_30_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_GS_31_DEFAULT 0x00000000
+#define mmSPI_SHADER_REQ_CTRL_ESGS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_ESGS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_ESGS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_ESGS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_ESGS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_ES_GS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC3_ES_DEFAULT 0x0000fffe
+#define mmSPI_SHADER_PGM_LO_ES_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_ES_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_ES_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_ES_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ES_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_LS_ES_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_CHKSUM_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC4_HS_DEFAULT 0x0000ffff
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_LO_LS_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_LS_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC3_HS_DEFAULT 0xffff0000
+#define mmSPI_SHADER_PGM_LO_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_15_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_16_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_17_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_18_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_19_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_20_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_21_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_22_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_23_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_24_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_25_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_26_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_27_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_28_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_29_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_30_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_HS_31_DEFAULT 0x00000000
+#define mmSPI_SHADER_REQ_CTRL_LSHS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_LSHS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_LSHS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_LSHS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_ACCUM_LSHS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_LS_HS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC3_LS_DEFAULT 0x0000fffc
+#define mmSPI_SHADER_PGM_LO_LS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_HI_LS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC1_LS_DEFAULT 0x00000000
+#define mmSPI_SHADER_PGM_RSRC2_LS_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_0_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_1_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_2_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_3_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_4_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_5_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_6_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_7_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_8_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_9_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_10_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_11_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_12_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_13_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_14_DEFAULT 0x00000000
+#define mmSPI_SHADER_USER_DATA_LS_15_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_INITIATOR_DEFAULT 0x00000000
+#define mmCOMPUTE_DIM_X_DEFAULT 0x00000000
+#define mmCOMPUTE_DIM_Y_DEFAULT 0x00000000
+#define mmCOMPUTE_DIM_Z_DEFAULT 0x00000000
+#define mmCOMPUTE_START_X_DEFAULT 0x00000000
+#define mmCOMPUTE_START_Y_DEFAULT 0x00000000
+#define mmCOMPUTE_START_Z_DEFAULT 0x00000000
+#define mmCOMPUTE_NUM_THREAD_X_DEFAULT 0x00000000
+#define mmCOMPUTE_NUM_THREAD_Y_DEFAULT 0x00000000
+#define mmCOMPUTE_NUM_THREAD_Z_DEFAULT 0x00000000
+#define mmCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT 0x00000001
+#define mmCOMPUTE_PERFCOUNT_ENABLE_DEFAULT 0x00000000
+#define mmCOMPUTE_PGM_LO_DEFAULT 0x00000000
+#define mmCOMPUTE_PGM_HI_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT 0x00000000
+#define mmCOMPUTE_PGM_RSRC1_DEFAULT 0x00000000
+#define mmCOMPUTE_PGM_RSRC2_DEFAULT 0x00000000
+#define mmCOMPUTE_VMID_DEFAULT 0x00000000
+#define mmCOMPUTE_RESOURCE_LIMITS_DEFAULT 0x00000000
+#define mmCOMPUTE_DESTINATION_EN_SE0_DEFAULT 0xffffffff
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT 0xffffffff
+#define mmCOMPUTE_DESTINATION_EN_SE1_DEFAULT 0xffffffff
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT 0xffffffff
+#define mmCOMPUTE_TMPRING_SIZE_DEFAULT 0x00000000
+#define mmCOMPUTE_DESTINATION_EN_SE2_DEFAULT 0xffffffff
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT 0xffffffff
+#define mmCOMPUTE_DESTINATION_EN_SE3_DEFAULT 0xffffffff
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT 0xffffffff
+#define mmCOMPUTE_RESTART_X_DEFAULT 0x00000000
+#define mmCOMPUTE_RESTART_Y_DEFAULT 0x00000000
+#define mmCOMPUTE_RESTART_Z_DEFAULT 0x00000000
+#define mmCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT 0x00000000
+#define mmCOMPUTE_MISC_RESERVED_DEFAULT 0x00000003
+#define mmCOMPUTE_DISPATCH_ID_DEFAULT 0x00000000
+#define mmCOMPUTE_THREADGROUP_ID_DEFAULT 0x00000000
+#define mmCOMPUTE_REQ_CTRL_DEFAULT 0x00000000
+#define mmCOMPUTE_PREF_PRI_ACCUM_0_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_ACCUM_0_DEFAULT 0x00000000
+#define mmCOMPUTE_PREF_PRI_ACCUM_1_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_ACCUM_1_DEFAULT 0x00000000
+#define mmCOMPUTE_PREF_PRI_ACCUM_2_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_ACCUM_2_DEFAULT 0x00000000
+#define mmCOMPUTE_PREF_PRI_ACCUM_3_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_ACCUM_3_DEFAULT 0x00000000
+#define mmCOMPUTE_PGM_RSRC3_DEFAULT 0x00000000
+#define mmCOMPUTE_DDID_INDEX_DEFAULT 0x00000000
+#define mmCOMPUTE_SHADER_CHKSUM_DEFAULT 0x00000000
+#define mmCOMPUTE_RELAUNCH_DEFAULT 0x00000000
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT 0x00000000
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT 0x00000000
+#define mmCOMPUTE_RELAUNCH2_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_0_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_1_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_2_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_3_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_4_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_5_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_6_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_7_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_8_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_9_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_10_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_11_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_12_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_13_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_14_DEFAULT 0x00000000
+#define mmCOMPUTE_USER_DATA_15_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_TUNNEL_DEFAULT 0x00000000
+#define mmCOMPUTE_DISPATCH_END_DEFAULT 0x00000000
+#define mmCOMPUTE_NOWHERE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_cppdec
+#define mmCP_EOPQ_WAIT_TIME_DEFAULT 0x0000052c
+#define mmCP_CPC_MGCG_SYNC_CNTL_DEFAULT 0x00001020
+#define mmCPC_INT_INFO_DEFAULT 0x00000000
+#define mmCP_VIRT_STATUS_DEFAULT 0x00000000
+#define mmCPC_INT_ADDR_DEFAULT 0x00000000
+#define mmCPC_INT_PASID_DEFAULT 0x00000000
+#define mmCP_GFX_ERROR_DEFAULT 0x00000000
+#define mmCPG_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmCPC_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmCPF_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmCP_AQL_SMM_STATUS_DEFAULT 0x00000000
+#define mmCP_RB0_BASE_DEFAULT 0x00000000
+#define mmCP_RB_BASE_DEFAULT 0x00000000
+#define mmCP_RB0_CNTL_DEFAULT 0x00a00000
+#define mmCP_RB_CNTL_DEFAULT 0x00a00000
+#define mmCP_RB_RPTR_WR_DEFAULT 0x00000000
+#define mmCP_RB0_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_RB_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_RB0_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB0_BUFSZ_MASK_DEFAULT 0x00000000
+#define mmCP_RB_BUFSZ_MASK_DEFAULT 0x00000000
+#define mmGC_PRIV_MODE_DEFAULT 0x00000000
+#define mmCP_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_DEVICE_ID_DEFAULT 0x00000000
+#define mmCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
+#define mmCP_RING_PRIORITY_CNTS_DEFAULT 0x08081020
+#define mmCP_ME0_PIPE0_PRIORITY_DEFAULT 0x00000002
+#define mmCP_RING0_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME0_PIPE1_PRIORITY_DEFAULT 0x00000002
+#define mmCP_RING1_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME0_PIPE2_PRIORITY_DEFAULT 0x00000002
+#define mmCP_RING2_PRIORITY_DEFAULT 0x00000002
+#define mmCP_FATAL_ERROR_DEFAULT 0x00000000
+#define mmCP_RB_VMID_DEFAULT 0x00000000
+#define mmCP_ME0_PIPE0_VMID_DEFAULT 0x00000000
+#define mmCP_ME0_PIPE1_VMID_DEFAULT 0x00000000
+#define mmCP_RB0_WPTR_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_DEFAULT 0x00000000
+#define mmCP_RB0_WPTR_HI_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_HI_DEFAULT 0x00000000
+#define mmCP_RB1_WPTR_DEFAULT 0x00000000
+#define mmCP_RB1_WPTR_HI_DEFAULT 0x00000000
+#define mmCP_RB2_WPTR_DEFAULT 0x00000000
+#define mmCP_PROCESS_QUANTUM_DEFAULT 0x00000008
+#define mmCP_RB_DOORBELL_RANGE_LOWER_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_RANGE_UPPER_DEFAULT 0x00000108
+#define mmCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT 0x00000110
+#define mmCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT 0x0ffffffc
+#define mmCPG_UTCL1_ERROR_DEFAULT 0x00000000
+#define mmCPC_UTCL1_ERROR_DEFAULT 0x00000000
+#define mmCP_RB1_BASE_DEFAULT 0x00000000
+#define mmCP_RB1_CNTL_DEFAULT 0x00a00000
+#define mmCP_RB1_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_RB1_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB1_BUFSZ_MASK_DEFAULT 0x00000000
+#define mmCP_RB2_BASE_DEFAULT 0x00000000
+#define mmCP_RB2_CNTL_DEFAULT 0x00a00000
+#define mmCP_RB2_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_RB2_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_INT_CNTL_RING0_DEFAULT 0x00000000
+#define mmCP_INT_CNTL_RING1_DEFAULT 0x00000000
+#define mmCP_INT_CNTL_RING2_DEFAULT 0x00000000
+#define mmCP_INT_STATUS_RING0_DEFAULT 0x00000000
+#define mmCP_INT_STATUS_RING1_DEFAULT 0x00000000
+#define mmCP_INT_STATUS_RING2_DEFAULT 0x00000000
+#define mmCP_PWR_CNTL_DEFAULT 0x00000000
+#define mmCP_MEM_SLP_CNTL_DEFAULT 0x00020200
+#define mmCP_ECC_FIRSTOCCURRENCE_DEFAULT 0x00000000
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT 0x00000000
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT 0x00000000
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2_DEFAULT 0x00000000
+#define mmGB_EDC_MODE_DEFAULT 0x00000000
+#define mmCP_FETCHER_SOURCE_DEFAULT 0x00000000
+#define mmCP_PQ_WPTR_POLL_CNTL_DEFAULT 0x00000001
+#define mmCP_PQ_WPTR_POLL_CNTL1_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE0_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE1_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE2_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE3_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE0_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE1_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE2_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE3_INT_CNTL_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE0_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE1_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE2_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE3_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE0_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE1_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE2_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_ME2_PIPE3_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_GFX_QUEUE_INDEX_DEFAULT 0x00000000
+#define mmCC_GC_EDC_CONFIG_DEFAULT 0x00000000
+#define mmCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
+#define mmCP_ME1_PIPE0_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME1_PIPE1_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME1_PIPE2_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME1_PIPE3_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
+#define mmCP_ME2_PIPE0_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME2_PIPE1_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME2_PIPE2_PRIORITY_DEFAULT 0x00000002
+#define mmCP_ME2_PIPE3_PRIORITY_DEFAULT 0x00000002
+#define mmCP_CE_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_PFP_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_ME_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_MEC1_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_MEC2_PRGRM_CNTR_START_DEFAULT 0x00000000
+#define mmCP_CE_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_PFP_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_ME_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_MEC1_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_MEC2_INTR_ROUTINE_START_DEFAULT 0x00000002
+#define mmCP_CONTEXT_CNTL_DEFAULT 0x00750075
+#define mmCP_MAX_CONTEXT_DEFAULT 0x00000007
+#define mmCP_IQ_WAIT_TIME1_DEFAULT 0x40404040
+#define mmCP_IQ_WAIT_TIME2_DEFAULT 0x40404040
+#define mmCP_RB0_BASE_HI_DEFAULT 0x00000000
+#define mmCP_RB1_BASE_HI_DEFAULT 0x00000000
+#define mmCP_VMID_RESET_DEFAULT 0x00000000
+#define mmCPC_INT_CNTL_DEFAULT 0x00000000
+#define mmCPC_INT_STATUS_DEFAULT 0x00000000
+#define mmCP_VMID_PREEMPT_DEFAULT 0x00000000
+#define mmCPC_INT_CNTX_ID_DEFAULT 0x00000000
+#define mmCP_PQ_STATUS_DEFAULT 0x00000000
+#define mmCP_CE_CS_PARTITION_INDEX_DEFAULT 0x00000000
+#define mmCP_MEC1_F32_INT_DIS_DEFAULT 0x00000000
+#define mmCP_MEC2_F32_INT_DIS_DEFAULT 0x00000000
+#define mmCP_VMID_STATUS_DEFAULT 0x00000000
+#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000
+#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCPC_SUSPEND_CTX_SAVE_CONTROL_DEFAULT 0x00000000
+#define mmCPC_SUSPEND_CNTL_STACK_OFFSET_DEFAULT 0x00000000
+#define mmCPC_SUSPEND_CNTL_STACK_SIZE_DEFAULT 0x00000000
+#define mmCPC_SUSPEND_WG_STATE_OFFSET_DEFAULT 0x00000000
+#define mmCPC_SUSPEND_CTX_SAVE_SIZE_DEFAULT 0x00000000
+#define mmCPC_OS_PIPES_DEFAULT 0x00000000
+#define mmCP_SUSPEND_RESUME_REQ_DEFAULT 0x00000000
+#define mmCP_SUSPEND_CNTL_DEFAULT 0x00000002
+#define mmCP_IQ_WAIT_TIME3_DEFAULT 0x00000040
+#define mmCPC_DDID_BASE_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_DDID_BASE_ADDR_LO_DEFAULT 0x00000000
+#define mmCPC_DDID_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DDID_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCPC_DDID_CNTL_DEFAULT 0x00000080
+#define mmCP_DDID_CNTL_DEFAULT 0x00000080
+#define mmCP_GFX_DDID_INFLIGHT_COUNT_DEFAULT 0x00000000
+#define mmCP_GFX_DDID_WPTR_DEFAULT 0x00000000
+#define mmCP_GFX_DDID_RPTR_DEFAULT 0x00000000
+#define mmCP_GFX_DDID_DELTA_RPT_COUNT_DEFAULT 0x00000000
+#define mmCP_GFX_HPD_STATUS0_DEFAULT 0x01000000
+#define mmCP_GFX_HPD_CONTROL0_DEFAULT 0x00000000
+#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_DEFAULT 0x00000000
+#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_DEFAULT 0x00000000
+#define mmCP_GFX_INDEX_MUTEX_DEFAULT 0x00000000
+#define mmCP_GFX_MQD_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_GFX_MQD_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_ACTIVE_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_VMID_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01
+#define mmCP_GFX_HQD_BASE_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_BASE_HI_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_RPTR_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_OFFSET_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CNTL_DEFAULT 0x00a00000
+#define mmCP_GFX_HQD_CSMD_RPTR_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_WPTR_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_WPTR_HI_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_MAPPED_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_QUE_MGR_CONTROL_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_HQ_STATUS0_DEFAULT 0x40000000
+#define mmCP_GFX_HQD_HQ_CONTROL0_DEFAULT 0x00000000
+#define mmCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
+#define mmCP_HQD_GFX_CONTROL_DEFAULT 0x00000000
+#define mmCP_HQD_GFX_STATUS_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_RPTR_WR_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_BASE_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_BASE_HI_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_RPTR_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_RPTR_ADDR_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_RPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_OFFSET_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_CNTL_DEFAULT 0x08a00000
+#define mmCP_GFX_HQD_CE_CSMD_RPTR_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_WPTR_DEFAULT 0x00000000
+#define mmCP_GFX_HQD_CE_WPTR_HI_DEFAULT 0x00000000
+#define mmCP_CE_DOORBELL_CONTROL_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH0_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH0_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH0_MASK_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH0_CNTL_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH1_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH1_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH1_MASK_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH1_CNTL_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH2_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH2_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH2_MASK_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH2_CNTL_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH3_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH3_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH3_MASK_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH3_CNTL_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH_STAT_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH_STAT_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_WATCH_STAT_DEFAULT 0x00000000
+#define mmCP_PFP_JT_STAT_DEFAULT 0x00000000
+#define mmCP_CE_JT_STAT_DEFAULT 0x00000000
+#define mmCP_MEC_JT_STAT_DEFAULT 0x00000000
+#define mmCP_RB_DOORBELL_CLEAR_DEFAULT 0x00000000
+#define mmCP_RB0_ACTIVE_DEFAULT 0x00000000
+#define mmCP_RB_ACTIVE_DEFAULT 0x00000000
+#define mmCP_RB1_ACTIVE_DEFAULT 0x00000000
+#define mmCP_RB_STATUS_DEFAULT 0x00000000
+#define mmCPG_RCIU_CAM_INDEX_DEFAULT 0x00000000
+#define mmCPG_RCIU_CAM_DATA_DEFAULT 0x00000000
+#define mmCPG_RCIU_CAM_DATA_PHASE0_DEFAULT 0x00000000
+#define mmCPG_RCIU_CAM_DATA_PHASE1_DEFAULT 0x00000000
+#define mmCPG_RCIU_CAM_DATA_PHASE2_DEFAULT 0x00000000
+#define mmCPF_GCR_CNTL_DEFAULT 0x0001c7f0
+#define mmCPG_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmCPC_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmCPF_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmCP_SD_CNTL_DEFAULT 0x0000045f
+#define mmCP_SOFT_RESET_CNTL_DEFAULT 0x00000000
+#define mmCP_CPC_GFX_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_spipdec
+#define mmSPI_ARB_PRIORITY_DEFAULT 0x00000000
+#define mmSPI_ARB_CYCLES_0_DEFAULT 0x00000000
+#define mmSPI_ARB_CYCLES_1_DEFAULT 0x00000000
+#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
+#define mmSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT 0x07c1f07f
+#define mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS1_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS2_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS3_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS4_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f
+#define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f
+#define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_2_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_3_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_4_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_5_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_6_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_7_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_8_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_9_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_10_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_11_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_12_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_13_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_14_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_CU_15_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT 0x00000000
+#define mmSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT 0x00000000
+#define mmSPI_COMPUTE_WF_CTX_SAVE_DEFAULT 0x00000000
+#define mmSPI_ARB_CNTL_0_DEFAULT 0x00000000
+#define mmSPI_FEATURE_CTRL_DEFAULT 0x00000000
+#define mmSPI_SHADER_RSRC_LIMIT_CTRL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_cpphqddec
+#define mmCP_HPD_MES_ROQ_OFFSETS_DEFAULT 0x00400000
+#define mmCP_HPD_ROQ_OFFSETS_DEFAULT 0x00200604
+#define mmCP_HPD_STATUS0_DEFAULT 0x01000000
+#define mmCP_HPD_UTCL1_CNTL_DEFAULT 0x00000000
+#define mmCP_HPD_UTCL1_ERROR_DEFAULT 0x00000000
+#define mmCP_HPD_UTCL1_ERROR_ADDR_DEFAULT 0x00000000
+#define mmCP_MQD_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_MQD_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_ACTIVE_DEFAULT 0x00000000
+#define mmCP_HQD_VMID_DEFAULT 0x00000000
+#define mmCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05301
+#define mmCP_HQD_PIPE_PRIORITY_DEFAULT 0x00000000
+#define mmCP_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
+#define mmCP_HQD_QUANTUM_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_BASE_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_BASE_HI_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_RPTR_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
+#define mmCP_HQD_IB_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_HQD_IB_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_IB_RPTR_DEFAULT 0x00000000
+#define mmCP_HQD_IB_CONTROL_DEFAULT 0x00300000
+#define mmCP_HQD_IQ_TIMER_DEFAULT 0x00000000
+#define mmCP_HQD_IQ_RPTR_DEFAULT 0x00000000
+#define mmCP_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000
+#define mmCP_HQD_DMA_OFFLOAD_DEFAULT 0x00000000
+#define mmCP_HQD_OFFLOAD_DEFAULT 0x00000000
+#define mmCP_HQD_SEMA_CMD_DEFAULT 0x00000000
+#define mmCP_HQD_MSG_TYPE_DEFAULT 0x00000000
+#define mmCP_HQD_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_HQD_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_HQD_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_HQD_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_HQD_HQ_SCHEDULER0_DEFAULT 0x00000000
+#define mmCP_HQD_HQ_STATUS0_DEFAULT 0x40000000
+#define mmCP_HQD_HQ_CONTROL0_DEFAULT 0x00000000
+#define mmCP_HQD_HQ_SCHEDULER1_DEFAULT 0x00000000
+#define mmCP_MQD_CONTROL_DEFAULT 0x00000100
+#define mmCP_HQD_HQ_STATUS1_DEFAULT 0x00000000
+#define mmCP_HQD_HQ_CONTROL1_DEFAULT 0x00000000
+#define mmCP_HQD_EOP_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_HQD_EOP_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
+#define mmCP_HQD_EOP_RPTR_DEFAULT 0x40000000
+#define mmCP_HQD_EOP_WPTR_DEFAULT 0x007f8000
+#define mmCP_HQD_EOP_EVENTS_DEFAULT 0x00000000
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_CTX_SAVE_CONTROL_DEFAULT 0x00000000
+#define mmCP_HQD_CNTL_STACK_OFFSET_DEFAULT 0x00000000
+#define mmCP_HQD_CNTL_STACK_SIZE_DEFAULT 0x00000000
+#define mmCP_HQD_WG_STATE_OFFSET_DEFAULT 0x00000000
+#define mmCP_HQD_CTX_SAVE_SIZE_DEFAULT 0x00000000
+#define mmCP_HQD_GDS_RESOURCE_STATE_DEFAULT 0x00000000
+#define mmCP_HQD_ERROR_DEFAULT 0x00000000
+#define mmCP_HQD_EOP_WPTR_MEM_DEFAULT 0x00000000
+#define mmCP_HQD_AQL_CONTROL_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_WPTR_LO_DEFAULT 0x00000000
+#define mmCP_HQD_PQ_WPTR_HI_DEFAULT 0x00000000
+#define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_DEFAULT 0x00000000
+#define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_DEFAULT 0x00000000
+#define mmCP_HQD_SUSPEND_WG_STATE_OFFSET_DEFAULT 0x00000000
+#define mmCP_HQD_DDID_RPTR_DEFAULT 0x00000000
+#define mmCP_HQD_DDID_WPTR_DEFAULT 0x00000000
+#define mmCP_HQD_DDID_INFLIGHT_COUNT_DEFAULT 0x00000000
+#define mmCP_HQD_DDID_DELTA_RPT_COUNT_DEFAULT 0x00000000
+#define mmCP_HQD_DEQUEUE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: gc_didtdec
+#define mmDIDT_IND_INDEX_DEFAULT 0x00000000
+#define mmDIDT_IND_DATA_DEFAULT 0x00000000
+#define mmDIDT_INDEX_AUTO_INCR_EN_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gccacdec
+#define mmGC_CAC_CTRL_1_DEFAULT 0x01000100
+#define mmGC_CAC_CTRL_2_DEFAULT 0x00000000
+#define mmGC_CAC_AGGR_LOWER_DEFAULT 0x00000000
+#define mmGC_CAC_AGGR_UPPER_DEFAULT 0x00000000
+#define mmGC_CAC_SOFT_CTRL_DEFAULT 0x00000000
+#define mmGC_DIDT_CTRL0_DEFAULT 0x00000000
+#define mmGC_DIDT_CTRL1_DEFAULT 0xffff0000
+#define mmGC_DIDT_CTRL2_DEFAULT 0x1880000f
+#define mmGC_DIDT_WEIGHT_DEFAULT 0x00000000
+#define mmGC_THROTTLE_CTRL_DEFAULT 0x00002000
+#define mmGC_EDC_CTRL_DEFAULT 0x00003c00
+#define mmGC_EDC_THRESHOLD_DEFAULT 0x00000000
+#define mmGC_EDC_STATUS_DEFAULT 0x00000000
+#define mmGC_EDC_OVERFLOW_DEFAULT 0x00000000
+#define mmGC_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define mmGC_THROTTLE_CTRL1_DEFAULT 0x00cc0660
+#define mmGC_THROTTLE_STATUS_DEFAULT 0x00000000
+#define mmEDC_PERF_COUNTER_DEFAULT 0x00000000
+#define mmPCC_PERF_COUNTER_DEFAULT 0x00000000
+#define mmPWRBRK_PERF_COUNTER_DEFAULT 0x00000000
+#define mmGC_CAC_IND_INDEX_DEFAULT 0x00000000
+#define mmGC_CAC_IND_DATA_DEFAULT 0x00000000
+#define mmSE_CAC_IND_INDEX_DEFAULT 0x00000000
+#define mmSE_CAC_IND_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: gc_tcpdec
+#define mmTCP_WATCH0_ADDR_H_DEFAULT 0x00000000
+#define mmTCP_WATCH0_ADDR_L_DEFAULT 0x00000000
+#define mmTCP_WATCH0_CNTL_DEFAULT 0x00000000
+#define mmTCP_WATCH1_ADDR_H_DEFAULT 0x00000000
+#define mmTCP_WATCH1_ADDR_L_DEFAULT 0x00000000
+#define mmTCP_WATCH1_CNTL_DEFAULT 0x00000000
+#define mmTCP_WATCH2_ADDR_H_DEFAULT 0x00000000
+#define mmTCP_WATCH2_ADDR_L_DEFAULT 0x00000000
+#define mmTCP_WATCH2_CNTL_DEFAULT 0x00000000
+#define mmTCP_WATCH3_ADDR_H_DEFAULT 0x00000000
+#define mmTCP_WATCH3_ADDR_L_DEFAULT 0x00000000
+#define mmTCP_WATCH3_CNTL_DEFAULT 0x00000000
+#define mmTCP_CNTL2_DEFAULT 0x0000200a
+#define mmTCP_UTCL0_CNTL1_DEFAULT 0x00800400
+#define mmTCP_UTCL0_CNTL2_DEFAULT 0x00000000
+#define mmTCP_UTCL0_STATUS_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER_FILTER_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER_FILTER_EN_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER_FILTER2_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gdspdec
+#define mmGDS_VMID0_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID0_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID1_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID1_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID2_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID2_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID3_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID3_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID4_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID4_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID5_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID5_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID6_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID6_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID7_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID7_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID8_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID8_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID9_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID9_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID10_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID10_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID11_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID11_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID12_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID12_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID13_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID13_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID14_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID14_SIZE_DEFAULT 0x00010000
+#define mmGDS_VMID15_BASE_DEFAULT 0x00000000
+#define mmGDS_VMID15_SIZE_DEFAULT 0x00010000
+#define mmGDS_GWS_VMID0_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID1_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID2_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID3_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID4_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID5_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID6_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID7_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID8_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID9_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID10_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID11_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID12_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID13_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID14_DEFAULT 0x00400000
+#define mmGDS_GWS_VMID15_DEFAULT 0x00400000
+#define mmGDS_OA_VMID0_DEFAULT 0x00000000
+#define mmGDS_OA_VMID1_DEFAULT 0x00000000
+#define mmGDS_OA_VMID2_DEFAULT 0x00000000
+#define mmGDS_OA_VMID3_DEFAULT 0x00000000
+#define mmGDS_OA_VMID4_DEFAULT 0x00000000
+#define mmGDS_OA_VMID5_DEFAULT 0x00000000
+#define mmGDS_OA_VMID6_DEFAULT 0x00000000
+#define mmGDS_OA_VMID7_DEFAULT 0x00000000
+#define mmGDS_OA_VMID8_DEFAULT 0x00000000
+#define mmGDS_OA_VMID9_DEFAULT 0x00000000
+#define mmGDS_OA_VMID10_DEFAULT 0x00000000
+#define mmGDS_OA_VMID11_DEFAULT 0x00000000
+#define mmGDS_OA_VMID12_DEFAULT 0x00000000
+#define mmGDS_OA_VMID13_DEFAULT 0x00000000
+#define mmGDS_OA_VMID14_DEFAULT 0x00000000
+#define mmGDS_OA_VMID15_DEFAULT 0x00000000
+#define mmGDS_GWS_RESET0_DEFAULT 0x00000000
+#define mmGDS_GWS_RESET1_DEFAULT 0x00000000
+#define mmGDS_GWS_RESOURCE_RESET_DEFAULT 0x00000000
+#define mmGDS_COMPUTE_MAX_WAVE_ID_DEFAULT 0x000004ff
+#define mmGDS_OA_RESET_MASK_DEFAULT 0x00000000
+#define mmGDS_OA_RESET_DEFAULT 0x00000000
+#define mmGDS_ENHANCE2_DEFAULT 0x00000000
+#define mmGDS_OA_CGPG_RESTORE_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_STATUS_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_CS_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_GFX_CTXSW_STATUS_DEFAULT 0x00000000
+#define mmGDS_VS_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_VS_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_VS_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_VS_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_PS_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_PS_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_PS_CTXSW_CNT3_DEFAULT 0x00000000
+#define mmGDS_PS_CTXSW_IDX_DEFAULT 0x00000000
+#define mmGDS_GS_CTXSW_CNT0_DEFAULT 0x00000000
+#define mmGDS_GS_CTXSW_CNT1_DEFAULT 0x00000000
+#define mmGDS_GS_CTXSW_CNT2_DEFAULT 0x00000000
+#define mmGDS_GS_CTXSW_CNT3_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gfxdec0
+#define mmDB_RENDER_CONTROL_DEFAULT 0x00000000
+#define mmDB_COUNT_CONTROL_DEFAULT 0x00000000
+#define mmDB_DEPTH_VIEW_DEFAULT 0x00000000
+#define mmDB_RENDER_OVERRIDE_DEFAULT 0x00000000
+#define mmDB_RENDER_OVERRIDE2_DEFAULT 0x00000000
+#define mmDB_HTILE_DATA_BASE_DEFAULT 0x00000000
+#define mmDB_DEPTH_SIZE_XY_DEFAULT 0x00000000
+#define mmDB_DEPTH_BOUNDS_MIN_DEFAULT 0x00000000
+#define mmDB_DEPTH_BOUNDS_MAX_DEFAULT 0x00000000
+#define mmDB_STENCIL_CLEAR_DEFAULT 0x00000000
+#define mmDB_DEPTH_CLEAR_DEFAULT 0x00000000
+#define mmPA_SC_SCREEN_SCISSOR_TL_DEFAULT 0x00000000
+#define mmPA_SC_SCREEN_SCISSOR_BR_DEFAULT 0x00000000
+#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000
+#define mmDB_RESERVED_REG_2_DEFAULT 0x00000000
+#define mmDB_Z_INFO_DEFAULT 0x00000000
+#define mmDB_STENCIL_INFO_DEFAULT 0x00000000
+#define mmDB_Z_READ_BASE_DEFAULT 0x00000000
+#define mmDB_STENCIL_READ_BASE_DEFAULT 0x00000000
+#define mmDB_Z_WRITE_BASE_DEFAULT 0x00000000
+#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000
+#define mmDB_RESERVED_REG_1_DEFAULT 0x00000000
+#define mmDB_RESERVED_REG_3_DEFAULT 0x00000000
+#define mmDB_Z_READ_BASE_HI_DEFAULT 0x00000000
+#define mmDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000
+#define mmDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000
+#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000
+#define mmDB_HTILE_DATA_BASE_HI_DEFAULT 0x00000000
+#define mmDB_RMI_L2_CACHE_CONTROL_DEFAULT 0x00000000
+#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000
+#define mmTA_BC_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_HI_0_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_HI_1_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_HI_2_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_HI_3_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_2_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_3_DEFAULT 0x00000000
+#define mmPA_SC_WINDOW_OFFSET_DEFAULT 0x00000000
+#define mmPA_SC_WINDOW_SCISSOR_TL_DEFAULT 0x00000000
+#define mmPA_SC_WINDOW_SCISSOR_BR_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_RULE_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_0_TL_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_0_BR_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_1_TL_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_1_BR_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_2_TL_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_2_BR_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_3_TL_DEFAULT 0x00000000
+#define mmPA_SC_CLIPRECT_3_BR_DEFAULT 0x00000000
+#define mmPA_SC_EDGERULE_DEFAULT 0x00000000
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT 0x00000000
+#define mmCB_TARGET_MASK_DEFAULT 0x00000000
+#define mmCB_SHADER_MASK_DEFAULT 0x00000000
+#define mmPA_SC_GENERIC_SCISSOR_TL_DEFAULT 0x00000000
+#define mmPA_SC_GENERIC_SCISSOR_BR_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_0_DEFAULT 0x00000000
+#define mmCOHER_DEST_BASE_1_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_0_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_0_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_1_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_1_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_2_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_2_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_3_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_3_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_4_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_4_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_5_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_5_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_6_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_6_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_7_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_7_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_8_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_8_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_9_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_9_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_10_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_10_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_11_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_11_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_12_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_12_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_13_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_13_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_14_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_14_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_15_TL_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_SCISSOR_15_BR_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_0_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_0_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_1_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_1_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_2_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_2_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_3_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_3_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_4_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_4_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_5_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_5_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_6_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_6_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_7_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_7_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_8_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_8_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_9_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_9_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_10_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_10_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_11_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_11_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_12_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_12_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_13_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_13_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_14_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_14_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMIN_15_DEFAULT 0x00000000
+#define mmPA_SC_VPORT_ZMAX_15_DEFAULT 0x00000000
+#define mmPA_SC_RASTER_CONFIG_DEFAULT 0x00000000
+#define mmPA_SC_RASTER_CONFIG_1_DEFAULT 0x00000000
+#define mmPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT 0x00000000
+#define mmPA_SC_TILE_STEERING_OVERRIDE_DEFAULT 0x00000000
+#define mmCP_PERFMON_CNTX_CNTL_DEFAULT 0x00000000
+#define mmCP_PIPEID_DEFAULT 0x00000000
+#define mmCP_RINGID_DEFAULT 0x00000000
+#define mmCP_VMID_DEFAULT 0x00000000
+#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000
+#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000
+#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000
+#define mmVGT_MAX_VTX_INDX_DEFAULT 0x00000000
+#define mmVGT_MIN_VTX_INDX_DEFAULT 0x00000000
+#define mmVGT_INDX_OFFSET_DEFAULT 0x00000000
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000
+#define mmCB_RMI_GL2_CACHE_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND_RED_DEFAULT 0x00000000
+#define mmCB_BLEND_GREEN_DEFAULT 0x00000000
+#define mmCB_BLEND_BLUE_DEFAULT 0x00000000
+#define mmCB_BLEND_ALPHA_DEFAULT 0x00000000
+#define mmCB_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COVERAGE_OUT_CONTROL_DEFAULT 0x00000000
+#define mmDB_STENCIL_CONTROL_DEFAULT 0x00000000
+#define mmDB_STENCILREFMASK_DEFAULT 0x00000000
+#define mmDB_STENCILREFMASK_BF_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_1_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_2_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_3_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_4_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_5_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_6_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_7_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_8_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_9_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_10_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_11_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_12_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_13_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_14_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XSCALE_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_XOFFSET_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YSCALE_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_YOFFSET_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZSCALE_15_DEFAULT 0x00000000
+#define mmPA_CL_VPORT_ZOFFSET_15_DEFAULT 0x00000000
+#define mmPA_CL_UCP_0_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_0_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_0_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_0_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_1_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_1_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_1_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_1_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_2_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_2_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_2_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_2_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_3_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_3_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_3_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_3_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_4_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_4_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_4_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_4_W_DEFAULT 0x00000000
+#define mmPA_CL_UCP_5_X_DEFAULT 0x00000000
+#define mmPA_CL_UCP_5_Y_DEFAULT 0x00000000
+#define mmPA_CL_UCP_5_Z_DEFAULT 0x00000000
+#define mmPA_CL_UCP_5_W_DEFAULT 0x00000000
+#define mmPA_CL_PROG_NEAR_CLIP_Z_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_0_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_1_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_2_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_3_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_4_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_5_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_6_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_7_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_8_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_9_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_10_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_11_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_12_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_13_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_14_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_15_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_16_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_17_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_18_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_19_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_20_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_21_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_22_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_23_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_24_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_25_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_26_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_27_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_28_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_29_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_30_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_CNTL_31_DEFAULT 0x00000000
+#define mmSPI_VS_OUT_CONFIG_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_ENA_DEFAULT 0x00000000
+#define mmSPI_PS_INPUT_ADDR_DEFAULT 0x00000000
+#define mmSPI_INTERP_CONTROL_0_DEFAULT 0x00000000
+#define mmSPI_PS_IN_CONTROL_DEFAULT 0x00000000
+#define mmSPI_BARYC_CNTL_DEFAULT 0x00000000
+#define mmSPI_TMPRING_SIZE_DEFAULT 0x00000000
+#define mmSPI_SHADER_IDX_FORMAT_DEFAULT 0x00000000
+#define mmSPI_SHADER_POS_FORMAT_DEFAULT 0x00000000
+#define mmSPI_SHADER_Z_FORMAT_DEFAULT 0x00000000
+#define mmSPI_SHADER_COL_FORMAT_DEFAULT 0x00000000
+#define mmSX_PS_DOWNCONVERT_DEFAULT 0x00000000
+#define mmSX_BLEND_OPT_EPSILON_DEFAULT 0x00000000
+#define mmSX_BLEND_OPT_CONTROL_DEFAULT 0x00000000
+#define mmSX_MRT0_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT1_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT2_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT3_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT4_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT5_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT6_BLEND_OPT_DEFAULT 0x00000000
+#define mmSX_MRT7_BLEND_OPT_DEFAULT 0x00000000
+#define mmCB_BLEND0_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND1_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND2_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND3_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND4_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND5_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND6_CONTROL_DEFAULT 0x00000000
+#define mmCB_BLEND7_CONTROL_DEFAULT 0x00000000
+#define mmCS_COPY_STATE_DEFAULT 0x00000000
+#define mmGFX_COPY_STATE_DEFAULT 0x00000000
+#define mmPA_CL_POINT_X_RAD_DEFAULT 0x00000000
+#define mmPA_CL_POINT_Y_RAD_DEFAULT 0x00000000
+#define mmPA_CL_POINT_SIZE_DEFAULT 0x00000000
+#define mmPA_CL_POINT_CULL_RAD_DEFAULT 0x00000000
+#define mmVGT_DMA_BASE_HI_DEFAULT 0x00000000
+#define mmVGT_DMA_BASE_DEFAULT 0x00000000
+#define mmVGT_DRAW_INITIATOR_DEFAULT 0x00000000
+#define mmVGT_IMMED_DATA_DEFAULT 0x00000000
+#define mmVGT_EVENT_ADDRESS_REG_DEFAULT 0x00000000
+#define mmGE_MAX_OUTPUT_PER_SUBGROUP_DEFAULT 0x00000000
+#define mmDB_DEPTH_CONTROL_DEFAULT 0x00000000
+#define mmDB_EQAA_DEFAULT 0x00000000
+#define mmCB_COLOR_CONTROL_DEFAULT 0x00000000
+#define mmDB_SHADER_CONTROL_DEFAULT 0x00000000
+#define mmPA_CL_CLIP_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_SC_MODE_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_VTE_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_VS_OUT_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_NANINF_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_LINE_STIPPLE_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_LINE_STIPPLE_SCALE_DEFAULT 0x00000000
+#define mmPA_SU_PRIM_FILTER_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_OBJPRIM_ID_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_NGG_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000
+#define mmPA_STEREO_CNTL_DEFAULT 0x00000000
+#define mmPA_STATE_STEREO_X_DEFAULT 0x00000000
+#define mmPA_SU_POINT_SIZE_DEFAULT 0x00000000
+#define mmPA_SU_POINT_MINMAX_DEFAULT 0x00000000
+#define mmPA_SU_LINE_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_LINE_STIPPLE_DEFAULT 0x00000000
+#define mmVGT_OUTPUT_PATH_CNTL_DEFAULT 0x00000000
+#define mmVGT_HOS_CNTL_DEFAULT 0x00000000
+#define mmVGT_HOS_MAX_TESS_LEVEL_DEFAULT 0x00000000
+#define mmVGT_HOS_MIN_TESS_LEVEL_DEFAULT 0x00000000
+#define mmVGT_HOS_REUSE_DEPTH_DEFAULT 0x00000000
+#define mmVGT_GROUP_PRIM_TYPE_DEFAULT 0x00000000
+#define mmVGT_GROUP_FIRST_DECR_DEFAULT 0x00000000
+#define mmVGT_GROUP_DECR_DEFAULT 0x00000000
+#define mmVGT_GROUP_VECT_0_CNTL_DEFAULT 0x00000000
+#define mmVGT_GROUP_VECT_1_CNTL_DEFAULT 0x00000000
+#define mmVGT_GROUP_VECT_0_FMT_CNTL_DEFAULT 0x00000000
+#define mmVGT_GROUP_VECT_1_FMT_CNTL_DEFAULT 0x00000000
+#define mmVGT_GS_MODE_DEFAULT 0x00000000
+#define mmVGT_GS_ONCHIP_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_MODE_CNTL_0_DEFAULT 0x00000000
+#define mmPA_SC_MODE_CNTL_1_DEFAULT 0x06000000
+#define mmVGT_ENHANCE_DEFAULT 0x00000000
+#define mmVGT_GS_PER_ES_DEFAULT 0x00000000
+#define mmVGT_ES_PER_GS_DEFAULT 0x00000000
+#define mmVGT_GS_PER_VS_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_OFFSET_1_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_OFFSET_2_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_OFFSET_3_DEFAULT 0x00000000
+#define mmVGT_GS_OUT_PRIM_TYPE_DEFAULT 0x00000000
+#define mmIA_ENHANCE_DEFAULT 0x00000000
+#define mmVGT_DMA_SIZE_DEFAULT 0x00000000
+#define mmVGT_DMA_MAX_SIZE_DEFAULT 0x00000000
+#define mmVGT_DMA_INDEX_TYPE_DEFAULT 0x00000000
+#define mmWD_ENHANCE_DEFAULT 0x00000000
+#define mmVGT_PRIMITIVEID_EN_DEFAULT 0x00000000
+#define mmVGT_DMA_NUM_INSTANCES_DEFAULT 0x00000000
+#define mmVGT_PRIMITIVEID_RESET_DEFAULT 0x00000000
+#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000
+#define mmVGT_MULTI_PRIM_IB_RESET_EN_DEFAULT 0x00000000
+#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000
+#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000
+#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000
+#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x000000ff
+#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_ITEMSIZE_DEFAULT 0x00000000
+#define mmVGT_REUSE_OFF_DEFAULT 0x00000000
+#define mmVGT_VTX_CNT_EN_DEFAULT 0x00000000
+#define mmDB_HTILE_SURFACE_DEFAULT 0x00000000
+#define mmDB_SRESULTS_COMPARE_STATE0_DEFAULT 0x00000000
+#define mmDB_SRESULTS_COMPARE_STATE1_DEFAULT 0x00000000
+#define mmDB_PRELOAD_CONTROL_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_SIZE_0_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_VTX_STRIDE_0_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_SIZE_1_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_VTX_STRIDE_1_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_SIZE_2_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_VTX_STRIDE_2_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_SIZE_3_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_VTX_STRIDE_3_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT 0x00000000
+#define mmVGT_GS_MAX_VERT_OUT_DEFAULT 0x00000000
+#define mmGE_NGG_SUBGRP_CNTL_DEFAULT 0x00000000
+#define mmVGT_TESS_DISTRIBUTION_DEFAULT 0x00000000
+#define mmVGT_SHADER_STAGES_EN_DEFAULT 0x00000000
+#define mmVGT_LS_HS_CONFIG_DEFAULT 0x00000000
+#define mmVGT_GS_VERT_ITEMSIZE_DEFAULT 0x00000000
+#define mmVGT_GS_VERT_ITEMSIZE_1_DEFAULT 0x00000000
+#define mmVGT_GS_VERT_ITEMSIZE_2_DEFAULT 0x00000000
+#define mmVGT_GS_VERT_ITEMSIZE_3_DEFAULT 0x00000000
+#define mmVGT_TF_PARAM_DEFAULT 0x00000000
+#define mmDB_ALPHA_TO_MASK_DEFAULT 0x00000000
+#define mmVGT_DISPATCH_DRAW_INDEX_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_CLAMP_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT 0x00000000
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT 0x00000000
+#define mmVGT_GS_INSTANCE_CNT_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_CONFIG_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_CONFIG_DEFAULT 0x00000000
+#define mmVGT_DMA_EVENT_INITIATOR_DEFAULT 0x00000000
+#define mmPA_SC_CENTROID_PRIORITY_0_DEFAULT 0x00000000
+#define mmPA_SC_CENTROID_PRIORITY_1_DEFAULT 0x00000000
+#define mmPA_SC_LINE_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_AA_CONFIG_DEFAULT 0x00000000
+#define mmPA_SU_VTX_CNTL_DEFAULT 0x00000000
+#define mmPA_CL_GB_VERT_CLIP_ADJ_DEFAULT 0x00000000
+#define mmPA_CL_GB_VERT_DISC_ADJ_DEFAULT 0x00000000
+#define mmPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT 0x00000000
+#define mmPA_CL_GB_HORZ_DISC_ADJ_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT 0x00000000
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT 0x00000000
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT 0x00000000
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT 0x00000000
+#define mmPA_SC_SHADER_CONTROL_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_CNTL_0_DEFAULT 0x00000000
+#define mmPA_SC_BINNER_CNTL_1_DEFAULT 0x00000000
+#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT 0x00000000
+#define mmPA_SC_NGG_MODE_CNTL_DEFAULT 0x00000000
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_DEFAULT 0x00000000
+#define mmVGT_OUT_DEALLOC_CNTL_DEFAULT 0x00000000
+#define mmCB_COLOR0_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR0_PITCH_DEFAULT 0x00000000
+#define mmCB_COLOR0_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR0_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR0_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR0_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR0_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR0_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR0_CMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR0_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR0_FMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR0_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR0_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR0_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR1_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR1_PITCH_DEFAULT 0x00000000
+#define mmCB_COLOR1_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR1_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR1_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR1_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR1_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR1_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR1_CMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR1_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR1_FMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR1_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR1_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR1_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR2_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR2_PITCH_DEFAULT 0x00000000
+#define mmCB_COLOR2_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR2_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR2_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR2_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR2_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR2_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR2_CMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR2_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR2_FMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR2_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR2_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR2_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR3_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR3_PITCH_DEFAULT 0x00000000
+#define mmCB_COLOR3_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR3_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR3_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR3_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR3_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR3_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR3_CMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR3_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR3_FMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR3_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR3_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR3_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR4_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR4_PITCH_DEFAULT 0x00000000
+#define mmCB_COLOR4_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR4_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR4_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR4_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR4_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR4_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR4_CMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR4_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR4_FMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR4_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR4_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR4_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR5_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR5_PITCH_DEFAULT 0x00000000
+#define mmCB_COLOR5_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR5_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR5_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR5_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR5_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR5_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR5_CMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR5_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR5_FMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR5_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR5_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR5_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR6_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR6_PITCH_DEFAULT 0x00000000
+#define mmCB_COLOR6_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR6_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR6_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR6_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR6_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR6_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR6_CMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR6_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR6_FMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR6_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR6_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR6_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR7_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR7_PITCH_DEFAULT 0x00000000
+#define mmCB_COLOR7_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR7_VIEW_DEFAULT 0x00000000
+#define mmCB_COLOR7_INFO_DEFAULT 0x00000000
+#define mmCB_COLOR7_ATTRIB_DEFAULT 0x00000000
+#define mmCB_COLOR7_DCC_CONTROL_DEFAULT 0x00000000
+#define mmCB_COLOR7_CMASK_DEFAULT 0x00000000
+#define mmCB_COLOR7_CMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR7_FMASK_DEFAULT 0x00000000
+#define mmCB_COLOR7_FMASK_SLICE_DEFAULT 0x00000000
+#define mmCB_COLOR7_CLEAR_WORD0_DEFAULT 0x00000000
+#define mmCB_COLOR7_CLEAR_WORD1_DEFAULT 0x00000000
+#define mmCB_COLOR7_DCC_BASE_DEFAULT 0x00000000
+#define mmCB_COLOR0_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR1_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR2_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR3_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR4_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR5_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR6_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR7_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR0_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR1_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR2_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR3_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR4_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR5_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR6_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR7_CMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR0_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR1_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR2_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR3_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR4_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR5_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR6_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR7_FMASK_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR0_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR1_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR2_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR3_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR4_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR5_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR6_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR7_DCC_BASE_EXT_DEFAULT 0x00000000
+#define mmCB_COLOR0_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR1_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR2_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR3_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR4_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR5_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR6_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR7_ATTRIB2_DEFAULT 0x00000000
+#define mmCB_COLOR0_ATTRIB3_DEFAULT 0x00000000
+#define mmCB_COLOR1_ATTRIB3_DEFAULT 0x00000000
+#define mmCB_COLOR2_ATTRIB3_DEFAULT 0x00000000
+#define mmCB_COLOR3_ATTRIB3_DEFAULT 0x00000000
+#define mmCB_COLOR4_ATTRIB3_DEFAULT 0x00000000
+#define mmCB_COLOR5_ATTRIB3_DEFAULT 0x00000000
+#define mmCB_COLOR6_ATTRIB3_DEFAULT 0x00000000
+#define mmCB_COLOR7_ATTRIB3_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gfxudec
+#define mmCP_EOP_DONE_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_DATA_LO_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_DATA_HI_DEFAULT 0x00000000
+#define mmCP_EOP_LAST_FENCE_LO_DEFAULT 0x00000000
+#define mmCP_EOP_LAST_FENCE_HI_DEFAULT 0x00000000
+#define mmCP_STREAM_OUT_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_STREAM_OUT_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_DEFAULT 0x00000000
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_DEFAULT 0x00000000
+#define mmCP_PIPE_STATS_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_PIPE_STATS_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_VGT_IAVERT_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_IAVERT_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_IAPRIM_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_IAPRIM_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_GSPRIM_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_GSPRIM_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_VSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_VSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_GSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_GSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_HSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_HSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_VGT_DSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_DSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_PA_CINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_PA_CINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_PA_CPRIM_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_PA_CPRIM_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_SC_PSINVOC_COUNT0_LO_DEFAULT 0x00000000
+#define mmCP_SC_PSINVOC_COUNT0_HI_DEFAULT 0x00000000
+#define mmCP_SC_PSINVOC_COUNT1_LO_DEFAULT 0x00000000
+#define mmCP_SC_PSINVOC_COUNT1_HI_DEFAULT 0x00000000
+#define mmCP_VGT_CSINVOC_COUNT_LO_DEFAULT 0x00000000
+#define mmCP_VGT_CSINVOC_COUNT_HI_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_DOORBELL_DEFAULT 0x00000000
+#define mmCP_STREAM_OUT_DOORBELL_DEFAULT 0x00000000
+#define mmCP_SEM_DOORBELL_DEFAULT 0x00000000
+#define mmCP_PIPE_STATS_CONTROL_DEFAULT 0x00000000
+#define mmCP_STREAM_OUT_CONTROL_DEFAULT 0x00000000
+#define mmCP_STRMOUT_CNTL_DEFAULT 0x00000000
+#define mmSCRATCH_REG0_DEFAULT 0x00000000
+#define mmSCRATCH_REG1_DEFAULT 0x00000000
+#define mmSCRATCH_REG2_DEFAULT 0x00000000
+#define mmSCRATCH_REG3_DEFAULT 0x00000000
+#define mmSCRATCH_REG4_DEFAULT 0x00000000
+#define mmSCRATCH_REG5_DEFAULT 0x00000000
+#define mmSCRATCH_REG6_DEFAULT 0x00000000
+#define mmSCRATCH_REG7_DEFAULT 0x00000000
+#define mmCP_PIPE_STATS_DOORBELL_DEFAULT 0x00000000
+#define mmCP_APPEND_DDID_CNT_DEFAULT 0x00000000
+#define mmCP_APPEND_DATA_HI_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_CS_FENCE_HI_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_PS_FENCE_HI_DEFAULT 0x00000000
+#define mmSCRATCH_UMSK_DEFAULT 0x00000000
+#define mmSCRATCH_ADDR_DEFAULT 0x00000000
+#define mmCP_PFP_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_PFP_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_APPEND_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_APPEND_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_APPEND_DATA_DEFAULT 0x00000000
+#define mmCP_APPEND_DATA_LO_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_CS_FENCE_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_CS_FENCE_LO_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_PS_FENCE_DEFAULT 0x00000000
+#define mmCP_APPEND_LAST_PS_FENCE_LO_DEFAULT 0x00000000
+#define mmCP_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_ME_ATOMIC_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_ME_ATOMIC_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000
+#define mmCP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000
+#define mmCP_ME_MC_WADDR_LO_DEFAULT 0x00000000
+#define mmCP_ME_MC_WADDR_HI_DEFAULT 0x00000000
+#define mmCP_ME_MC_WDATA_LO_DEFAULT 0x00000000
+#define mmCP_ME_MC_WDATA_HI_DEFAULT 0x00000000
+#define mmCP_ME_MC_RADDR_LO_DEFAULT 0x00000000
+#define mmCP_ME_MC_RADDR_HI_DEFAULT 0x00000000
+#define mmCP_SEM_WAIT_TIMER_DEFAULT 0x00000000
+#define mmCP_SIG_SEM_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_SIG_SEM_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_WAIT_REG_MEM_TIMEOUT_DEFAULT 0x00000000
+#define mmCP_WAIT_SEM_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_WAIT_SEM_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_CONTROL_DEFAULT 0x00000000
+#define mmCP_DMA_ME_CONTROL_DEFAULT 0x00000000
+#define mmCP_COHER_BASE_HI_DEFAULT 0x00000000
+#define mmCP_COHER_START_DELAY_DEFAULT 0x00000020
+#define mmCP_COHER_CNTL_DEFAULT 0x00000000
+#define mmCP_COHER_SIZE_DEFAULT 0x00000000
+#define mmCP_COHER_BASE_DEFAULT 0x00000000
+#define mmCP_COHER_STATUS_DEFAULT 0x00000000
+#define mmCP_DMA_ME_SRC_ADDR_DEFAULT 0x00000000
+#define mmCP_DMA_ME_SRC_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_ME_DST_ADDR_DEFAULT 0x00000000
+#define mmCP_DMA_ME_DST_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_ME_COMMAND_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_SRC_ADDR_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_SRC_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_DST_ADDR_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_DST_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_COMMAND_DEFAULT 0x00000000
+#define mmCP_DMA_CNTL_DEFAULT 0x00100020
+#define mmCP_DMA_READ_TAGS_DEFAULT 0x00000000
+#define mmCP_COHER_SIZE_HI_DEFAULT 0x00000000
+#define mmCP_PFP_IB_CONTROL_DEFAULT 0x00000000
+#define mmCP_PFP_LOAD_CONTROL_DEFAULT 0x00000000
+#define mmCP_SCRATCH_INDEX_DEFAULT 0x00000000
+#define mmCP_SCRATCH_DATA_DEFAULT 0x00000000
+#define mmCP_RB_OFFSET_DEFAULT 0x00000000
+#define mmCP_IB1_OFFSET_DEFAULT 0x00000000
+#define mmCP_IB2_OFFSET_DEFAULT 0x00000000
+#define mmCP_IB1_PREAMBLE_BEGIN_DEFAULT 0x00000000
+#define mmCP_IB1_PREAMBLE_END_DEFAULT 0x00000000
+#define mmCP_IB2_PREAMBLE_BEGIN_DEFAULT 0x00000000
+#define mmCP_IB2_PREAMBLE_END_DEFAULT 0x00000000
+#define mmCP_CE_IB1_OFFSET_DEFAULT 0x00000000
+#define mmCP_CE_IB2_OFFSET_DEFAULT 0x00000000
+#define mmCP_CE_COUNTER_DEFAULT 0x00000000
+#define mmCP_DMA_ME_CMD_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_DMA_ME_CMD_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_CMD_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_DMA_PFP_CMD_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_APPEND_CMD_ADDR_LO_DEFAULT 0x00000000
+#define mmCP_APPEND_CMD_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_CE_INIT_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_IB1_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_IB2_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_IB1_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_IB2_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_ST_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_INIT_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CE_INIT_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CE_INIT_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_IB1_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CE_IB1_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CE_IB1_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_IB2_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CE_IB2_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CE_IB2_BUFSZ_DEFAULT 0x00000000
+#define mmCP_IB1_BASE_LO_DEFAULT 0x00000000
+#define mmCP_IB1_BASE_HI_DEFAULT 0x00000000
+#define mmCP_IB1_BUFSZ_DEFAULT 0x00000000
+#define mmCP_IB2_BASE_LO_DEFAULT 0x00000000
+#define mmCP_IB2_BASE_HI_DEFAULT 0x00000000
+#define mmCP_IB2_BUFSZ_DEFAULT 0x00000000
+#define mmCP_ST_BASE_LO_DEFAULT 0x00000000
+#define mmCP_ST_BASE_HI_DEFAULT 0x00000000
+#define mmCP_ST_BUFSZ_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_EVENT_CNTL_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_DATA_CNTL_DEFAULT 0x00000000
+#define mmCP_EOP_DONE_CNTX_ID_DEFAULT 0x00000000
+#define mmCP_DB_BASE_LO_DEFAULT 0x00000000
+#define mmCP_DB_BASE_HI_DEFAULT 0x00000000
+#define mmCP_DB_BUFSZ_DEFAULT 0x00000000
+#define mmCP_DB_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_DB_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CE_DB_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CE_DB_BUFSZ_DEFAULT 0x00000000
+#define mmCP_CE_DB_CMD_BUFSZ_DEFAULT 0x00000000
+#define mmCP_PFP_COMPLETION_STATUS_DEFAULT 0x00000000
+#define mmCP_CE_COMPLETION_STATUS_DEFAULT 0x00000000
+#define mmCP_PRED_NOT_VISIBLE_DEFAULT 0x00000000
+#define mmCP_PFP_METADATA_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_CE_METADATA_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_CE_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DRAW_INDX_INDR_ADDR_DEFAULT 0x00000000
+#define mmCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_DISPATCH_INDR_ADDR_DEFAULT 0x00000000
+#define mmCP_DISPATCH_INDR_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_INDEX_BASE_ADDR_DEFAULT 0x00000000
+#define mmCP_INDEX_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_INDEX_TYPE_DEFAULT 0x00000000
+#define mmCP_GDS_BKUP_ADDR_DEFAULT 0x00000000
+#define mmCP_GDS_BKUP_ADDR_HI_DEFAULT 0x00000000
+#define mmCP_SAMPLE_STATUS_DEFAULT 0x00000000
+#define mmCP_ME_COHER_CNTL_DEFAULT 0x00000000
+#define mmCP_ME_COHER_SIZE_DEFAULT 0x00000000
+#define mmCP_ME_COHER_SIZE_HI_DEFAULT 0x00000000
+#define mmCP_ME_COHER_BASE_DEFAULT 0x00000000
+#define mmCP_ME_COHER_BASE_HI_DEFAULT 0x00000000
+#define mmCP_ME_COHER_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPM_PERF_COUNT_0_DEFAULT 0x00000000
+#define mmRLC_GPM_PERF_COUNT_1_DEFAULT 0x00000000
+#define mmGRBM_GFX_INDEX_DEFAULT 0xe0000000
+#define mmVGT_ESGS_RING_SIZE_UMD_DEFAULT 0x00000000
+#define mmVGT_GSVS_RING_SIZE_UMD_DEFAULT 0x00000000
+#define mmVGT_PRIMITIVE_TYPE_DEFAULT 0x00000000
+#define mmVGT_INDEX_TYPE_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_DEFAULT 0x00000000
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_DEFAULT 0x00000000
+#define mmGE_MIN_VTX_INDX_DEFAULT 0x00000000
+#define mmGE_INDX_OFFSET_DEFAULT 0x00000000
+#define mmGE_MULTI_PRIM_IB_RESET_EN_DEFAULT 0x00000000
+#define mmVGT_NUM_INDICES_DEFAULT 0x00000000
+#define mmVGT_NUM_INSTANCES_DEFAULT 0x00000000
+#define mmVGT_TF_RING_SIZE_UMD_DEFAULT 0x0000c000
+#define mmVGT_HS_OFFCHIP_PARAM_UMD_DEFAULT 0x00000000
+#define mmVGT_TF_MEMORY_BASE_UMD_DEFAULT 0x00000000
+#define mmGE_DMA_FIRST_INDEX_DEFAULT 0x00000000
+#define mmWD_POS_BUF_BASE_DEFAULT 0x00000000
+#define mmWD_POS_BUF_BASE_HI_DEFAULT 0x00000000
+#define mmWD_CNTL_SB_BUF_BASE_DEFAULT 0x00000000
+#define mmWD_CNTL_SB_BUF_BASE_HI_DEFAULT 0x00000000
+#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000
+#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000
+#define mmIA_MULTI_VGT_PARAM_PIPED_DEFAULT 0x006000ff
+#define mmGE_MAX_VTX_INDX_DEFAULT 0x00000000
+#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000
+#define mmGE_CNTL_DEFAULT 0x00000000
+#define mmGE_USER_VGPR1_DEFAULT 0x00000000
+#define mmGE_USER_VGPR2_DEFAULT 0x00000000
+#define mmGE_USER_VGPR3_DEFAULT 0x00000000
+#define mmGE_STEREO_CNTL_DEFAULT 0x00000000
+#define mmGE_PC_ALLOC_DEFAULT 0x00000000
+#define mmVGT_TF_MEMORY_BASE_HI_UMD_DEFAULT 0x00000000
+#define mmGE_USER_VGPR_EN_DEFAULT 0x00000000
+#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000
+#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000
+#define mmPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT 0x7fff7fff
+#define mmPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT 0x80008000
+#define mmPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT 0x7fff7fff
+#define mmPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT 0x80008000
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
+#define mmPA_SC_P3D_TRAP_SCREEN_H_DEFAULT 0x00000000
+#define mmPA_SC_P3D_TRAP_SCREEN_V_DEFAULT 0x00000000
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_H_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_V_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000
+#define mmPA_SC_TRAP_SCREEN_COUNT_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_0_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_1_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_2_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_3_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_4_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_5_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_6_DEFAULT 0x00000000
+#define mmSQ_THREAD_TRACE_USERDATA_7_DEFAULT 0x00000000
+#define mmSQC_CACHES_DEFAULT 0x00000000
+#define mmSQC_WRITEBACK_DEFAULT 0x00000000
+#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000
+#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT1_HI_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT2_LOW_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT2_HI_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT3_LOW_DEFAULT 0x00000000
+#define mmDB_OCCLUSION_COUNT3_HI_DEFAULT 0x00000000
+#define mmDB_ZPASS_COUNT_LOW_DEFAULT 0x00000000
+#define mmDB_ZPASS_COUNT_HI_DEFAULT 0x00000000
+#define mmGDS_RD_ADDR_DEFAULT 0x00000000
+#define mmGDS_RD_DATA_DEFAULT 0x00000000
+#define mmGDS_RD_BURST_ADDR_DEFAULT 0x00000000
+#define mmGDS_RD_BURST_COUNT_DEFAULT 0x00000000
+#define mmGDS_RD_BURST_DATA_DEFAULT 0x00000000
+#define mmGDS_WR_ADDR_DEFAULT 0x00000000
+#define mmGDS_WR_DATA_DEFAULT 0x00000000
+#define mmGDS_WR_BURST_ADDR_DEFAULT 0x00000000
+#define mmGDS_WR_BURST_DATA_DEFAULT 0x00000000
+#define mmGDS_WRITE_COMPLETE_DEFAULT 0x00000000
+#define mmGDS_ATOM_CNTL_DEFAULT 0x00000000
+#define mmGDS_ATOM_COMPLETE_DEFAULT 0x00000001
+#define mmGDS_ATOM_BASE_DEFAULT 0x00000000
+#define mmGDS_ATOM_SIZE_DEFAULT 0x00000000
+#define mmGDS_ATOM_OFFSET0_DEFAULT 0x00000000
+#define mmGDS_ATOM_OFFSET1_DEFAULT 0x00000000
+#define mmGDS_ATOM_DST_DEFAULT 0x00000000
+#define mmGDS_ATOM_OP_DEFAULT 0x00000000
+#define mmGDS_ATOM_SRC0_DEFAULT 0x00000000
+#define mmGDS_ATOM_SRC0_U_DEFAULT 0x00000000
+#define mmGDS_ATOM_SRC1_DEFAULT 0x00000000
+#define mmGDS_ATOM_SRC1_U_DEFAULT 0x00000000
+#define mmGDS_ATOM_READ0_DEFAULT 0x00000000
+#define mmGDS_ATOM_READ0_U_DEFAULT 0x00000000
+#define mmGDS_ATOM_READ1_DEFAULT 0x00000000
+#define mmGDS_ATOM_READ1_U_DEFAULT 0x00000000
+#define mmGDS_GWS_RESOURCE_CNTL_DEFAULT 0x00000000
+#define mmGDS_GWS_RESOURCE_DEFAULT 0x00000000
+#define mmGDS_GWS_RESOURCE_CNT_DEFAULT 0x00000000
+#define mmGDS_OA_CNTL_DEFAULT 0x00000000
+#define mmGDS_OA_COUNTER_DEFAULT 0x00000000
+#define mmGDS_OA_ADDRESS_DEFAULT 0x00000000
+#define mmGDS_OA_INCDEC_DEFAULT 0x00000000
+#define mmGDS_OA_RING_SIZE_DEFAULT 0x00000000
+#define mmSPI_CONFIG_CNTL_REMAP_DEFAULT 0x00000000
+#define mmSPI_CONFIG_CNTL_1_REMAP_DEFAULT 0x00000000
+#define mmSPI_CONFIG_CNTL_2_REMAP_DEFAULT 0x00000000
+#define mmSPI_WAVE_LIMIT_CNTL_REMAP_DEFAULT 0x00000000
+
+
+// addressBlock: gc_cprs64dec
+#define mmCP_MES_PRGRM_CNTR_START_DEFAULT 0x00000800
+#define mmCP_MES_INTR_ROUTINE_START_DEFAULT 0x00000000
+#define mmCP_MES_MTVEC_LO_DEFAULT 0x00000000
+#define mmCP_MES_MTVEC_HI_DEFAULT 0x00000000
+#define mmCP_MES_CNTL_DEFAULT 0x40000000
+#define mmCP_MES_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020
+#define mmCP_MES_PIPE0_PRIORITY_DEFAULT 0x00000002
+#define mmCP_MES_PIPE1_PRIORITY_DEFAULT 0x00000002
+#define mmCP_MES_PIPE2_PRIORITY_DEFAULT 0x00000002
+#define mmCP_MES_PIPE3_PRIORITY_DEFAULT 0x00000002
+#define mmCP_MES_HEADER_DUMP_DEFAULT 0x00000000
+#define mmCP_MES_MIE_LO_DEFAULT 0x00000000
+#define mmCP_MES_MIE_HI_DEFAULT 0x00000000
+#define mmCP_MES_INTERRUPT_DEFAULT 0x00000000
+#define mmCP_MES_SCRATCH_INDEX_DEFAULT 0x00000000
+#define mmCP_MES_SCRATCH_DATA_DEFAULT 0x00000000
+#define mmCP_MES_INSTR_PNTR_DEFAULT 0x00000000
+#define mmCP_MES_MSCRATCH_HI_DEFAULT 0x00000000
+#define mmCP_MES_MSCRATCH_LO_DEFAULT 0x00000000
+#define mmCP_MES_MSTATUS_LO_DEFAULT 0x00000000
+#define mmCP_MES_MSTATUS_HI_DEFAULT 0x00000000
+#define mmCP_MES_MEPC_LO_DEFAULT 0x00000000
+#define mmCP_MES_MEPC_HI_DEFAULT 0x00000000
+#define mmCP_MES_MCAUSE_LO_DEFAULT 0x00000000
+#define mmCP_MES_MCAUSE_HI_DEFAULT 0x00000000
+#define mmCP_MES_MBADADDR_LO_DEFAULT 0x00000000
+#define mmCP_MES_MBADADDR_HI_DEFAULT 0x00000000
+#define mmCP_MES_MIP_LO_DEFAULT 0x00000000
+#define mmCP_MES_MIP_HI_DEFAULT 0x00000000
+#define mmCP_MES_MCYCLE_LO_DEFAULT 0x00000000
+#define mmCP_MES_MCYCLE_HI_DEFAULT 0x00000000
+#define mmCP_MES_MTIME_LO_DEFAULT 0x00000000
+#define mmCP_MES_MTIME_HI_DEFAULT 0x00000000
+#define mmCP_MES_MINSTRET_LO_DEFAULT 0x00000000
+#define mmCP_MES_MINSTRET_HI_DEFAULT 0x00000000
+#define mmCP_MES_MISA_LO_DEFAULT 0x00000000
+#define mmCP_MES_MISA_HI_DEFAULT 0x00000000
+#define mmCP_MES_MVENDORID_LO_DEFAULT 0x00000000
+#define mmCP_MES_MVENDORID_HI_DEFAULT 0x00000000
+#define mmCP_MES_MARCHID_LO_DEFAULT 0x00000000
+#define mmCP_MES_MARCHID_HI_DEFAULT 0x00000000
+#define mmCP_MES_MIMPID_LO_DEFAULT 0x00000000
+#define mmCP_MES_MIMPID_HI_DEFAULT 0x00000000
+#define mmCP_MES_MHARTID_LO_DEFAULT 0x00000000
+#define mmCP_MES_MHARTID_HI_DEFAULT 0x00000000
+#define mmCP_MES_DC_BASE_CNTL_DEFAULT 0x00000000
+#define mmCP_MES_DC_OP_CNTL_DEFAULT 0x00000000
+#define mmCP_MES_MTIMECMP_LO_DEFAULT 0x00000000
+#define mmCP_MES_MTIMECMP_HI_DEFAULT 0x00000000
+#define mmCP_MES_PROCESS_QUANTUM_PIPE0_DEFAULT 0x00000008
+#define mmCP_MES_PROCESS_QUANTUM_PIPE1_DEFAULT 0x00000008
+#define mmCP_MES_DOORBELL_CONTROL1_DEFAULT 0x00000000
+#define mmCP_MES_DOORBELL_CONTROL2_DEFAULT 0x00000000
+#define mmCP_MES_DOORBELL_CONTROL3_DEFAULT 0x00000000
+#define mmCP_MES_DOORBELL_CONTROL4_DEFAULT 0x00000000
+#define mmCP_MES_DOORBELL_CONTROL5_DEFAULT 0x00000000
+#define mmCP_MES_DOORBELL_CONTROL6_DEFAULT 0x00000000
+#define mmCP_MES_GP0_LO_DEFAULT 0x00000000
+#define mmCP_MES_GP0_HI_DEFAULT 0x00000000
+#define mmCP_MES_GP1_LO_DEFAULT 0x00002001
+#define mmCP_MES_GP1_HI_DEFAULT 0x00000000
+#define mmCP_MES_GP2_LO_DEFAULT 0x00000000
+#define mmCP_MES_GP2_HI_DEFAULT 0x00000000
+#define mmCP_MES_GP3_LO_DEFAULT 0x00000000
+#define mmCP_MES_GP3_HI_DEFAULT 0x00000000
+#define mmCP_MES_GP4_LO_DEFAULT 0x00000000
+#define mmCP_MES_GP4_HI_DEFAULT 0x00000000
+#define mmCP_MES_GP5_LO_DEFAULT 0x00000000
+#define mmCP_MES_GP5_HI_DEFAULT 0x00000000
+#define mmCP_MES_GP6_LO_DEFAULT 0x00000000
+#define mmCP_MES_GP6_HI_DEFAULT 0x00000000
+#define mmCP_MES_GP7_LO_DEFAULT 0x00000000
+#define mmCP_MES_GP7_HI_DEFAULT 0x00000000
+#define mmCP_MES_GP8_LO_DEFAULT 0x00000000
+#define mmCP_MES_GP8_HI_DEFAULT 0x00000000
+#define mmCP_MES_GP9_LO_DEFAULT 0x40000000
+#define mmCP_MES_GP9_HI_DEFAULT 0x40000000
+#define mmCP_MES_DM_INDEX_ADDR_DEFAULT 0x00000000
+#define mmCP_MES_DM_INDEX_DATA_DEFAULT 0x00000000
+#define mmCP_MES_DMCONTROL_DEFAULT 0x00000000
+#define mmCP_MES_DMINFO_DEFAULT 0x00000000
+#define mmCP_MES_SETHALTNOTIFICATION_DEFAULT 0x00000000
+#define mmCP_MES_TSELCT_LOW_DEFAULT 0x00000000
+#define mmCP_MES_TSELCT_HIGH_DEFAULT 0x00000000
+#define mmCP_MES_TDATA1_LOW_DEFAULT 0x00000000
+#define mmCP_MES_TDATA1_HIGH_DEFAULT 0x00000000
+#define mmCP_MES_TDATA2_LOW_DEFAULT 0x00000000
+#define mmCP_MES_TDATA2_HIGH_DEFAULT 0x00000000
+#define mmCP_MES_TDATA3_LOW_DEFAULT 0x00000000
+#define mmCP_MES_TDATA3_HIH_DEFAULT 0x00000000
+#define mmCP_MES_DCSR_DEFAULT 0x00000000
+#define mmCP_MES_DPC_LOW_DEFAULT 0x00000000
+#define mmCP_MES_DPC_HIGH_DEFAULT 0x00000000
+#define mmCP_MES_DSCRATCH_LOW_DEFAULT 0x00000000
+#define mmCP_MES_DSCRATCH_HIGH_DEFAULT 0x00000000
+#define mmCP_MES_PERFCOUNT_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gusdec
+#define mmGUS_IO_RD_COMBINE_FLUSH_DEFAULT 0x00000000
+#define mmGUS_IO_WR_COMBINE_FLUSH_DEFAULT 0x00000000
+#define mmGUS_IO_RD_PRI_AGE_RATE_DEFAULT 0x00000000
+#define mmGUS_IO_WR_PRI_AGE_RATE_DEFAULT 0x00000000
+#define mmGUS_IO_RD_PRI_AGE_COEFF_DEFAULT 0x0003ffff
+#define mmGUS_IO_WR_PRI_AGE_COEFF_DEFAULT 0x0003ffff
+#define mmGUS_IO_RD_PRI_QUEUING_DEFAULT 0x0003ffff
+#define mmGUS_IO_WR_PRI_QUEUING_DEFAULT 0x0003ffff
+#define mmGUS_IO_RD_PRI_FIXED_DEFAULT 0x00000000
+#define mmGUS_IO_WR_PRI_FIXED_DEFAULT 0x00000000
+#define mmGUS_IO_RD_PRI_URGENCY_COEFF_DEFAULT 0x00000000
+#define mmGUS_IO_WR_PRI_URGENCY_COEFF_DEFAULT 0x00000000
+#define mmGUS_IO_RD_PRI_URGENCY_MODE_DEFAULT 0x00000000
+#define mmGUS_IO_WR_PRI_URGENCY_MODE_DEFAULT 0x00000000
+#define mmGUS_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x1f1f1f1f
+#define mmGUS_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x3f3f3f3f
+#define mmGUS_IO_RD_PRI_QUANT_PRI3_DEFAULT 0x7f7f7f7f
+#define mmGUS_IO_RD_PRI_QUANT_PRI4_DEFAULT 0xffffffff
+#define mmGUS_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x1f1f1f1f
+#define mmGUS_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x3f3f3f3f
+#define mmGUS_IO_WR_PRI_QUANT_PRI3_DEFAULT 0x7f7f7f7f
+#define mmGUS_IO_WR_PRI_QUANT_PRI4_DEFAULT 0xffffffff
+#define mmGUS_IO_RD_PRI_QUANT1_PRI1_DEFAULT 0x00001f1f
+#define mmGUS_IO_RD_PRI_QUANT1_PRI2_DEFAULT 0x00003f3f
+#define mmGUS_IO_RD_PRI_QUANT1_PRI3_DEFAULT 0x00007f7f
+#define mmGUS_IO_RD_PRI_QUANT1_PRI4_DEFAULT 0x0000ffff
+#define mmGUS_IO_WR_PRI_QUANT1_PRI1_DEFAULT 0x00001f1f
+#define mmGUS_IO_WR_PRI_QUANT1_PRI2_DEFAULT 0x00003f3f
+#define mmGUS_IO_WR_PRI_QUANT1_PRI3_DEFAULT 0x00007f7f
+#define mmGUS_IO_WR_PRI_QUANT1_PRI4_DEFAULT 0x0000ffff
+#define mmGUS_DRAM_COMBINE_FLUSH_DEFAULT 0x00000000
+#define mmGUS_DRAM_COMBINE_RD_WR_EN_DEFAULT 0x00000fff
+#define mmGUS_DRAM_PRI_AGE_RATE_DEFAULT 0x00001249
+#define mmGUS_DRAM_PRI_AGE_COEFF_DEFAULT 0x0003ffff
+#define mmGUS_DRAM_PRI_QUEUING_DEFAULT 0x0003edb6
+#define mmGUS_DRAM_PRI_FIXED_DEFAULT 0x00000000
+#define mmGUS_DRAM_PRI_URGENCY_COEFF_DEFAULT 0x00000000
+#define mmGUS_DRAM_PRI_URGENCY_MODE_DEFAULT 0x00000000
+#define mmGUS_DRAM_PRI_QUANT_PRI1_DEFAULT 0x0f0f0f0f
+#define mmGUS_DRAM_PRI_QUANT_PRI2_DEFAULT 0x1f1f1f1f
+#define mmGUS_DRAM_PRI_QUANT_PRI3_DEFAULT 0x3f3f3f3f
+#define mmGUS_DRAM_PRI_QUANT_PRI4_DEFAULT 0x7f7f7f7f
+#define mmGUS_DRAM_PRI_QUANT_PRI5_DEFAULT 0xffffffff
+#define mmGUS_DRAM_PRI_QUANT1_PRI1_DEFAULT 0x00000f0f
+#define mmGUS_DRAM_PRI_QUANT1_PRI2_DEFAULT 0x00001f1f
+#define mmGUS_DRAM_PRI_QUANT1_PRI3_DEFAULT 0x00003f3f
+#define mmGUS_DRAM_PRI_QUANT1_PRI4_DEFAULT 0x00007f7f
+#define mmGUS_DRAM_PRI_QUANT1_PRI5_DEFAULT 0x0000ffff
+#define mmGUS_IO_GROUP_BURST_DEFAULT 0x05040504
+#define mmGUS_DRAM_GROUP_BURST_DEFAULT 0x00000504
+#define mmGUS_SDP_ARB_FINAL_DEFAULT 0x00007fff
+#define mmGUS_SDP_QOS_VC_PRIORITY_DEFAULT 0x0000a000
+#define mmGUS_SDP_CREDITS_DEFAULT 0x000100ff
+#define mmGUS_SDP_TAG_RESERVE0_DEFAULT 0x07070000
+#define mmGUS_SDP_TAG_RESERVE1_DEFAULT 0x00000707
+#define mmGUS_SDP_VCC_RESERVE0_DEFAULT 0x02041000
+#define mmGUS_SDP_VCC_RESERVE1_DEFAULT 0x00000002
+#define mmGUS_SDP_VCD_RESERVE0_DEFAULT 0x02040000
+#define mmGUS_SDP_VCD_RESERVE1_DEFAULT 0x00000002
+#define mmGUS_SDP_REQ_CNTL_DEFAULT 0x0000001f
+#define mmGUS_MISC_DEFAULT 0x00003c07
+#define mmGUS_LATENCY_SAMPLING_DEFAULT 0x00000000
+#define mmGUS_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGUS_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmGUS_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmGUS_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmGUS_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmGUS_ERR_STATUS_DEFAULT 0x00000300
+#define mmGUS_MISC2_DEFAULT 0x000017fe
+#define mmGUS_SDP_BACKDOOR_CMDCREDITS0_DEFAULT 0x00000000
+#define mmGUS_SDP_BACKDOOR_CMDCREDITS1_DEFAULT 0x00000000
+#define mmGUS_SDP_BACKDOOR_DATACREDITS0_DEFAULT 0x00000000
+#define mmGUS_SDP_BACKDOOR_DATACREDITS1_DEFAULT 0x00000000
+#define mmGUS_SDP_BACKDOOR_MISCCREDITS_DEFAULT 0x00000000
+#define mmGUS_SDP_ENABLE_DEFAULT 0x00000000
+#define mmGUS_L1_CH0_CMD_IN_DEFAULT 0x00000000
+#define mmGUS_L1_CH0_CMD_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_CH0_DATA_IN_DEFAULT 0x00000000
+#define mmGUS_L1_CH0_DATA_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_CH1_CMD_IN_DEFAULT 0x00000000
+#define mmGUS_L1_CH1_CMD_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_CH1_DATA_IN_DEFAULT 0x00000000
+#define mmGUS_L1_CH1_DATA_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA0_CMD_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA0_CMD_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA0_DATA_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA0_DATA_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA0_DATA_U_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA0_DATA_U_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA1_CMD_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA1_CMD_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA1_DATA_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA1_DATA_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA1_DATA_U_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA1_DATA_U_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA2_CMD_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA2_CMD_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA2_DATA_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA2_DATA_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA2_DATA_U_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA2_DATA_U_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA3_CMD_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA3_CMD_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA3_DATA_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA3_DATA_OUT_DEFAULT 0x00000000
+#define mmGUS_L1_SA3_DATA_U_IN_DEFAULT 0x00000000
+#define mmGUS_L1_SA3_DATA_U_OUT_DEFAULT 0x00000000
+#define mmGUS_MISC3_DEFAULT 0x00000000
+#define mmGUS_WRRSP_FIFO_CNTL_DEFAULT 0x0000000a
+
+
+// addressBlock: gc_gl1dec
+#define mmGL1_ARB_CTRL_DEFAULT 0x00000000
+#define mmGL1_DRAM_BURST_MASK_DEFAULT 0x000000cf
+#define mmGL1_ARB_STATUS_DEFAULT 0x00000000
+#define mmGL1_DRAM_BURST_CTRL_DEFAULT 0x00000007
+#define mmGL1_PIPE_STEER_DEFAULT 0xe4e4e4e4
+#define mmGL1C_CTRL_DEFAULT 0x000000f0
+#define mmGL1C_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: gc_chdec
+#define mmCH_ARB_CTRL_DEFAULT 0x00000000
+#define mmCH_DRAM_BURST_MASK_DEFAULT 0x000000cf
+#define mmCH_ARB_STATUS_DEFAULT 0x00000000
+#define mmCH_DRAM_BURST_CTRL_DEFAULT 0x00000007
+#define mmCH_PIPE_STEER_DEFAULT 0xe4e4e4e4
+#define mmCH_VC5_ENABLE_DEFAULT 0x00000000
+#define mmCHC_CTRL_DEFAULT 0x0000000f
+#define mmCHC_STATUS_DEFAULT 0x00000000
+#define mmCHCG_CTRL_DEFAULT 0x000000ff
+#define mmCHCG_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gl2dec
+#define mmGL2C_CTRL_DEFAULT 0xf35fff7f
+#define mmGL2C_CTRL2_DEFAULT 0x1402002f
+#define mmGL2C_STATUS_DEFAULT 0x00000000
+#define mmGL2C_ADDR_MATCH_MASK_DEFAULT 0xffffffff
+#define mmGL2C_ADDR_MATCH_SIZE_DEFAULT 0x00000007
+#define mmGL2C_WBINVL2_DEFAULT 0x00000010
+#define mmGL2C_SOFT_RESET_DEFAULT 0x00000000
+#define mmGL2C_CM_CTRL0_DEFAULT 0x42108421
+#define mmGL2C_CM_CTRL1_DEFAULT 0x180f1008
+#define mmGL2C_CM_STALL_DEFAULT 0x00000000
+#define mmGL2C_MDC_PF_FLAG_CTRL_DEFAULT 0x00010000
+#define mmGL2C_CM_CTRL2_DEFAULT 0x00000000
+#define mmGL2C_CTRL3_DEFAULT 0x000001a8
+#define mmGL2C_LB_CTR_CTRL_DEFAULT 0x00000000
+#define mmGL2C_LB_DATA0_DEFAULT 0x00000000
+#define mmGL2C_LB_DATA1_DEFAULT 0x00000000
+#define mmGL2C_LB_DATA2_DEFAULT 0x00000000
+#define mmGL2C_LB_DATA3_DEFAULT 0x00000000
+#define mmGL2C_LB_CTR_SEL0_DEFAULT 0x00000000
+#define mmGL2C_LB_CTR_SEL1_DEFAULT 0x00000000
+#define mmGL2A_ADDR_MATCH_CTRL_DEFAULT 0x00000000
+#define mmGL2A_ADDR_MATCH_MASK_DEFAULT 0xffffffff
+#define mmGL2A_ADDR_MATCH_SIZE_DEFAULT 0x00000007
+#define mmGL2A_PRIORITY_CTRL_DEFAULT 0x00000000
+#define mmGL2A_CTRL_DEFAULT 0x00000002
+#define mmGL2_PIPE_STEER_0_DEFAULT 0x32103210
+#define mmGL2_PIPE_STEER_1_DEFAULT 0x32103210
+
+
+// addressBlock: gc_perfddec
+#define mmCPG_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCPG_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCPG_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCPG_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCPF_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCPF_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCPF_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCPF_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCPF_LATENCY_STATS_DATA_DEFAULT 0x00000000
+#define mmCPG_LATENCY_STATS_DATA_DEFAULT 0x00000000
+#define mmCPC_LATENCY_STATS_DATA_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGRBM_SE0_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGRBM_SE0_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmGRBM_SE1_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGRBM_SE1_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmGRBM_SE2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGRBM_SE2_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmGRBM_SE3_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGRBM_SE3_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER4_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER4_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER5_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER5_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER6_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER6_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER7_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER7_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER8_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER8_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER9_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER9_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER10_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER10_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER11_LO_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER11_HI_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER4_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER4_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER5_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER5_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER6_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER6_HI_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER7_LO_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER7_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER4_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER4_LO_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER5_HI_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER5_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER4_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER4_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER5_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER5_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER6_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER6_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER7_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER7_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER8_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER8_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER9_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER9_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER10_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER10_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER11_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER11_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER12_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER12_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER13_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER13_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER14_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER14_HI_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER15_LO_DEFAULT 0x00000000
+#define mmSQ_PERFCOUNTER15_HI_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmGCEA_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGCEA_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmGL2C_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGL2C_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGL2C_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGL2C_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGL2C_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGL2C_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmGL2C_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmGL2C_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmGL2A_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGL2A_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGL2A_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGL2A_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGL2A_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGL2A_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmGL2A_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmGL2A_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmGL1C_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGL1C_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGL1C_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGL1C_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGL1C_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGL1C_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmGL1C_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmGL1C_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmCHC_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCHC_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCHC_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCHC_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCHC_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmCHC_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmCHC_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmCHC_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmCHCG_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCHCG_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCHCG_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCHCG_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCHCG_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmCHCG_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmCHCG_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmCHCG_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmUTCL1_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmUTCL1_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmUTCL1_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmUTCL1_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGCR_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGCR_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGCR_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGCR_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER4_LO_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER4_HI_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER5_LO_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER5_HI_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER6_LO_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER6_HI_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER7_LO_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER7_HI_DEFAULT 0x00000000
+#define mmGL1A_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmGL1A_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmGL1A_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmGL1A_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmGL1A_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGL1A_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmGL1A_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmGL1A_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmCHA_PERFCOUNTER0_LO_DEFAULT 0x00000000
+#define mmCHA_PERFCOUNTER0_HI_DEFAULT 0x00000000
+#define mmCHA_PERFCOUNTER1_LO_DEFAULT 0x00000000
+#define mmCHA_PERFCOUNTER1_HI_DEFAULT 0x00000000
+#define mmCHA_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmCHA_PERFCOUNTER2_HI_DEFAULT 0x00000000
+#define mmCHA_PERFCOUNTER3_LO_DEFAULT 0x00000000
+#define mmCHA_PERFCOUNTER3_HI_DEFAULT 0x00000000
+#define mmGUS_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGUS_PERFCOUNTER2_HI_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcatcl2pfcntrdec
+#define mmGC_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGC_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcvml2prdec
+#define mmGCMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmGCMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcvml2perfddec
+#define mmGCVML2_PERFCOUNTER2_0_LO_DEFAULT 0x00000000
+#define mmGCVML2_PERFCOUNTER2_1_LO_DEFAULT 0x00000000
+#define mmGCVML2_PERFCOUNTER2_0_HI_DEFAULT 0x00000000
+#define mmGCVML2_PERFCOUNTER2_1_HI_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcatcl2perfddec
+#define mmGC_ATC_L2_PERFCOUNTER2_LO_DEFAULT 0x00000000
+#define mmGC_ATC_L2_PERFCOUNTER2_HI_DEFAULT 0x00000000
+
+
+// addressBlock: gc_perfsdec
+#define mmCPG_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmCPG_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmCPG_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmCPC_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmCPC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmCPF_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmCPF_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmCPF_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmCP_PERFMON_CNTL_DEFAULT 0x00000000
+#define mmCPC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000
+#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000
+#define mmCPF_LATENCY_STATS_SELECT_DEFAULT 0x00000000
+#define mmCPG_LATENCY_STATS_SELECT_DEFAULT 0x00000000
+#define mmCPC_LATENCY_STATS_SELECT_DEFAULT 0x00000000
+#define mmCP_DRAW_OBJECT_DEFAULT 0x00000000
+#define mmCP_DRAW_OBJECT_COUNTER_DEFAULT 0x00000000
+#define mmCP_DRAW_WINDOW_MASK_HI_DEFAULT 0x00000000
+#define mmCP_DRAW_WINDOW_HI_DEFAULT 0x00000000
+#define mmCP_DRAW_WINDOW_LO_DEFAULT 0x00000000
+#define mmCP_DRAW_WINDOW_CNTL_DEFAULT 0x00000007
+#define mmGRBM_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT 0x00000000
+#define mmGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT 0x00000000
+#define mmGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT 0x00000000
+#define mmGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER0_SELECT_HI_DEFAULT 0x00000000
+#define mmGRBM_PERFCOUNTER1_SELECT_HI_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER3_SELECT1_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER4_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER5_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER6_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER7_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER8_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER9_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER10_SELECT_DEFAULT 0x00000000
+#define mmGE_PERFCOUNTER11_SELECT_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmPA_SU_PERFCOUNTER3_SELECT1_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER4_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER5_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER6_SELECT_DEFAULT 0x00000000
+#define mmPA_SC_PERFCOUNTER7_SELECT_DEFAULT 0x00000000
+#define mmSPI_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff
+#define mmSPI_PERFCOUNTER4_SELECT_DEFAULT 0x000003ff
+#define mmSPI_PERFCOUNTER5_SELECT_DEFAULT 0x000003ff
+#define mmSPI_PERFCOUNTER_BINS_DEFAULT 0xfcb87430
+#define mmSQ_PERFCOUNTER0_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER1_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER2_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER3_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER4_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER5_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER6_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER7_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER8_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER9_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER10_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER11_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER12_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER13_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER14_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER15_SELECT_DEFAULT 0x0000f000
+#define mmSQ_PERFCOUNTER_CTRL_DEFAULT 0x00000200
+#define mmSQ_PERFCOUNTER_CTRL2_DEFAULT 0x00000000
+#define mmGCEA_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff
+#define mmGCEA_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff
+#define mmGCEA_PERFCOUNTER2_MODE_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmSX_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmGDS_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmTA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmTD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmTCP_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmTCP_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmTCP_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmTCP_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmTCP_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmTCP_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmGL2C_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmGL2C_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmGL2C_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmGL2C_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmGL2C_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmGL2C_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmGL2A_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmGL2A_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmGL2A_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff
+#define mmGL2A_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff
+#define mmGL2A_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmGL2A_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmGL1C_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmGL1C_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmGL1C_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff
+#define mmGL1C_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmGL1C_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmCHC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmCHC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmCHC_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff
+#define mmCHC_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmCHC_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmCHCG_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmCHCG_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmCHCG_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff
+#define mmCHCG_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmCHCG_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmCB_PERFCOUNTER_FILTER_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmCB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmDB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_CNTL_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_RING_SIZE_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT 0x00000000
+#define mmRLC_SPM_RING_RDPTR_DEFAULT 0x00000000
+#define mmRLC_SPM_SEGMENT_THRESHOLD_DEFAULT 0x00000000
+#define mmRLC_SPM_SE_MUXSEL_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPM_SE_MUXSEL_DATA_DEFAULT 0x00000000
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT 0x00000000
+#define mmRLC_SPM_DESER_START_SKEW_DEFAULT 0x00000000
+#define mmRLC_SPM_GLOBALS_SAMPLE_SKEW_DEFAULT 0x00000000
+#define mmRLC_SPM_GLOBALS_MUXSEL_SKEW_DEFAULT 0x00000000
+#define mmRLC_SPM_SE_SAMPLE_SKEW_DEFAULT 0x00000000
+#define mmRLC_SPM_SE_MUXSEL_SKEW_DEFAULT 0x00000000
+#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_DEFAULT 0x00000000
+#define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_DEFAULT 0x00000000
+#define mmRLC_SPM_RING_WRPTR_DEFAULT 0x00000000
+#define mmRLC_SPM_ACCUM_DATARAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPM_ACCUM_DATARAM_DATA_DEFAULT 0x00000000
+#define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPM_ACCUM_CTRLRAM_DATA_DEFAULT 0x00000000
+#define mmRLC_SPM_ACCUM_STATUS_DEFAULT 0x00000000
+#define mmRLC_SPM_ACCUM_CTRL_DEFAULT 0x00000000
+#define mmRLC_SPM_ACCUM_MODE_DEFAULT 0x00000000
+#define mmRLC_SPM_ACCUM_THRESHOLD_DEFAULT 0x00000001
+#define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_DEFAULT 0x00000001
+#define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_DEFAULT 0x00000000
+#define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_DEFAULT 0x00000000
+#define mmRLC_SPM_VIRT_CTRL_DEFAULT 0x00000000
+#define mmRLC_SPM_VIRT_STATUS_DEFAULT 0x00000000
+#define mmRLC_PERFMON_CNTL_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmRLC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT 0x00000000
+#define mmRLC_PERFMON_CLK_CNTL_DEFAULT 0x00000001
+#define mmRLC_PERFMON_CLK_CNTL_UCODE_DEFAULT 0x00000001
+#define mmRMI_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000
+#define mmRMI_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmRMI_PERF_COUNTER_CNTL_DEFAULT 0x00080240
+#define mmGCR_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmGCR_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmGCR_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmUTCL1_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmUTCL1_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER0_SELECT_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER1_SELECT_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER2_SELECT_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER3_SELECT_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER4_SELECT_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER5_SELECT_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER6_SELECT_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER7_SELECT_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000
+#define mmPA_PH_PERFCOUNTER3_SELECT1_DEFAULT 0x00000000
+#define mmGL1A_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmGL1A_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmGL1A_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff
+#define mmGL1A_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmGL1A_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmCHA_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff
+#define mmCHA_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff
+#define mmCHA_PERFCOUNTER1_SELECT_DEFAULT 0x000003ff
+#define mmCHA_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff
+#define mmCHA_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff
+#define mmGUS_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff
+#define mmGUS_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff
+#define mmGUS_PERFCOUNTER2_MODE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcatcl2pfcntldec
+#define mmGC_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmGC_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmGC_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+
+// addressBlock: gc_gcvml2pldec
+#define mmGCMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmGCMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmGCMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmGCMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmGCMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000
+#define mmGCMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000
+#define mmGCMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000
+#define mmGCMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000
+#define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+
+// addressBlock: gc_gcvml2perfsdec
+#define mmGCVML2_PERFCOUNTER2_0_SELECT_DEFAULT 0x000fffff
+#define mmGCVML2_PERFCOUNTER2_1_SELECT_DEFAULT 0x000fffff
+#define mmGCVML2_PERFCOUNTER2_0_SELECT1_DEFAULT 0x000fffff
+#define mmGCVML2_PERFCOUNTER2_1_SELECT1_DEFAULT 0x000fffff
+#define mmGCVML2_PERFCOUNTER2_0_MODE_DEFAULT 0x00000000
+#define mmGCVML2_PERFCOUNTER2_1_MODE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcatcl2perfsdec
+#define mmGC_ATC_L2_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff
+#define mmGC_ATC_L2_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff
+#define mmGC_ATC_L2_PERFCOUNTER2_MODE_DEFAULT 0x00000000
+
+
+// addressBlock: gc_rlcdec
+#define mmRLC_CNTL_DEFAULT 0x00000001
+#define mmRLC_F32_UCODE_VERSION_DEFAULT 0x00000000
+#define mmRLC_STAT_DEFAULT 0x00000000
+#define mmRLC_SAFE_MODE_DEFAULT 0x00000000
+#define mmRLC_MEM_SLP_CNTL_DEFAULT 0x00020200
+#define mmSMU_RLC_RESPONSE_DEFAULT 0x00000000
+#define mmRLC_RLCV_SAFE_MODE_DEFAULT 0x00000000
+#define mmRLC_SMU_SAFE_MODE_DEFAULT 0x00000000
+#define mmRLC_RLCV_COMMAND_DEFAULT 0x00000000
+#define mmRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT 0x00000000
+#define mmRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT 0x00000000
+#define mmRLC_GPM_TIMER_INT_0_DEFAULT 0x00000063
+#define mmRLC_GPM_TIMER_INT_1_DEFAULT 0x00000063
+#define mmRLC_GPM_TIMER_INT_2_DEFAULT 0x00000063
+#define mmRLC_GPM_TIMER_CTRL_DEFAULT 0x00000000
+#define mmRLC_LB_CNTR_MAX_1_DEFAULT 0xffffffff
+#define mmRLC_GPM_TIMER_STAT_DEFAULT 0x00000000
+#define mmRLC_GPM_TIMER_INT_3_DEFAULT 0x00000063
+#define mmRLC_INT_STAT_DEFAULT 0x00000000
+#define mmRLC_LB_CNTL_DEFAULT 0x00000000
+#define mmRLC_MGCG_CTRL_DEFAULT 0x00018800
+#define mmRLC_LB_CNTR_INIT_1_DEFAULT 0x00000000
+#define mmRLC_LB_CNTR_1_DEFAULT 0x00000000
+#define mmRLC_JUMP_TABLE_RESTORE_DEFAULT 0x00000000
+#define mmRLC_PG_DELAY_2_DEFAULT 0x00000004
+#define mmRLC_GPU_CLOCK_COUNT_LSB_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_COUNT_MSB_DEFAULT 0x00000000
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT 0x00000000
+#define mmRLC_UCODE_CNTL_DEFAULT 0x00000000
+#define mmRLC_GPM_THREAD_RESET_DEFAULT 0x00000004
+#define mmRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT 0x00000000
+#define mmRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT 0x00000000
+#define mmRLC_LB_CNTR_INIT_2_DEFAULT 0x00000000
+#define mmRLC_LB_CNTR_MAX_2_DEFAULT 0xffffffff
+#define mmRLC_LB_CONFIG_5_DEFAULT 0x00000000
+#define mmRLC_CLK_COUNT_GFXCLK_LSB_DEFAULT 0x00000000
+#define mmRLC_CLK_COUNT_GFXCLK_MSB_DEFAULT 0x00000000
+#define mmRLC_CLK_COUNT_REFCLK_LSB_DEFAULT 0x00000000
+#define mmRLC_CLK_COUNT_REFCLK_MSB_DEFAULT 0x00000000
+#define mmRLC_CLK_COUNT_CTRL_DEFAULT 0x00000000
+#define mmRLC_CLK_COUNT_STAT_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_32_RES_SEL_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_32_DEFAULT 0x00000000
+#define mmRLC_PG_CNTL_DEFAULT 0x00000000
+#define mmRLC_GPM_THREAD_PRIORITY_DEFAULT 0x08080808
+#define mmRLC_GPM_THREAD_ENABLE_DEFAULT 0x00000001
+#define mmRLC_CGTT_MGCG_OVERRIDE_DEFAULT 0x10000ffff
+#define mmRLC_CGCG_CGLS_CTRL_DEFAULT 0x0001003c
+#define mmRLC_CGCG_RAMP_CTRL_DEFAULT 0x00021711
+#define mmRLC_DYN_PG_STATUS_DEFAULT 0xffffffff
+#define mmRLC_DYN_PG_REQUEST_DEFAULT 0xffffffff
+#define mmRLC_PG_DELAY_DEFAULT 0x00101010
+#define mmRLC_WGP_STATUS_DEFAULT 0x00000000
+#define mmRLC_LB_INIT_WGP_MASK_DEFAULT 0xffffffff
+#define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_DEFAULT 0x00000001
+#define mmRLC_LB_PARAMS_DEFAULT 0x00601008
+#define mmRLC_LB_DELAY_DEFAULT 0x00400401
+#define mmRLC_PG_ALWAYS_ON_WGP_MASK_DEFAULT 0x00000003
+#define mmRLC_MAX_PG_WGP_DEFAULT 0x0000000a
+#define mmRLC_AUTO_PG_CTRL_DEFAULT 0x00000000
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_DEFAULT 0x00000000
+#define mmRLC_SERDES_RD_INDEX_DEFAULT 0x00000000
+#define mmRLC_SERDES_RD_DATA_0_DEFAULT 0x00000000
+#define mmRLC_SERDES_RD_DATA_1_DEFAULT 0x00000000
+#define mmRLC_SERDES_RD_DATA_2_DEFAULT 0x00000000
+#define mmRLC_SERDES_RD_DATA_3_DEFAULT 0x00000000
+#define mmRLC_SERDES_MASK_DEFAULT 0x00000000
+#define mmRLC_SERDES_CTRL_DEFAULT 0x00000000
+#define mmRLC_SERDES_DATA_DEFAULT 0x00000000
+#define mmRLC_SERDES_BUSY_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_0_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_1_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_2_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_3_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_4_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_5_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_6_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_7_DEFAULT 0x00000000
+#define mmRLC_STATIC_PG_STATUS_DEFAULT 0xffffffff
+#define mmRLC_SPM_INT_INFO_1_DEFAULT 0x00000000
+#define mmRLC_SPM_INT_INFO_2_DEFAULT 0x00ca0000
+#define mmRLC_SPM_MC_CNTL_DEFAULT 0x00000000
+#define mmRLC_SPM_INT_CNTL_DEFAULT 0x00000000
+#define mmRLC_SPM_INT_STATUS_DEFAULT 0x00000000
+#define mmRLC_SMU_MESSAGE_DEFAULT 0x00000000
+#define mmRLC_GPM_LOG_SIZE_DEFAULT 0x00000000
+#define mmRLC_PG_DELAY_3_DEFAULT 0x00000000
+#define mmRLC_GPR_REG1_DEFAULT 0x00000000
+#define mmRLC_GPR_REG2_DEFAULT 0x00000000
+#define mmRLC_GPM_LOG_CONT_DEFAULT 0x00000000
+#define mmRLC_GPM_INT_DISABLE_TH0_DEFAULT 0xffffffff
+#define mmRLC_GPM_INT_FORCE_TH0_DEFAULT 0x00000000
+#define mmRLC_SRM_CNTL_DEFAULT 0x00000002
+#define mmRLC_SRM_GPM_COMMAND_DEFAULT 0x00000000
+#define mmRLC_SRM_GPM_COMMAND_STATUS_DEFAULT 0x00000000
+#define mmRLC_SRM_RLCV_COMMAND_DEFAULT 0x00000000
+#define mmRLC_SRM_RLCV_COMMAND_STATUS_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT 0x00000000
+#define mmRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT 0x00000000
+#define mmRLC_SRM_STAT_DEFAULT 0x00000000
+#define mmRLC_SRM_GPM_ABORT_DEFAULT 0x00000000
+#define mmRLC_CSIB_ADDR_LO_DEFAULT 0x00000000
+#define mmRLC_CSIB_ADDR_HI_DEFAULT 0x00000000
+#define mmRLC_CSIB_LENGTH_DEFAULT 0x00000000
+#define mmRLC_PACE_INT_STAT_DEFAULT 0x00000000
+#define mmRLC_SMU_COMMAND_DEFAULT 0x00000000
+#define mmRLC_CP_SCHEDULERS_DEFAULT 0x58504840
+#define mmRLC_SMU_ARGUMENT_1_DEFAULT 0x00000000
+#define mmRLC_SMU_ARGUMENT_2_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_8_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_9_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_10_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_11_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_12_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_CNTL_0_DEFAULT 0x00000080
+#define mmRLC_GPM_UTCL1_CNTL_1_DEFAULT 0x00000080
+#define mmRLC_GPM_UTCL1_CNTL_2_DEFAULT 0x00000080
+#define mmRLC_SPM_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmRLC_UTCL1_STATUS_2_DEFAULT 0x00000000
+#define mmRLC_LB_CONFIG_2_DEFAULT 0x00000000
+#define mmRLC_LB_CONFIG_3_DEFAULT 0x00000000
+#define mmRLC_LB_CONFIG_4_DEFAULT 0x00000000
+#define mmRLC_SPM_UTCL1_ERROR_1_DEFAULT 0x00000000
+#define mmRLC_SPM_UTCL1_ERROR_2_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT 0x00000000
+#define mmRLC_LB_CONFIG_1_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT 0x00000000
+#define mmRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT 0x00000000
+#define mmRLC_CGCG_CGLS_CTRL_3D_DEFAULT 0x0001003c
+#define mmRLC_CGCG_RAMP_CTRL_3D_DEFAULT 0x00021711
+#define mmRLC_SEMAPHORE_0_DEFAULT 0x00000000
+#define mmRLC_SEMAPHORE_1_DEFAULT 0x00000000
+#define mmRLC_CP_EOF_INT_DEFAULT 0x00000000
+#define mmRLC_CP_EOF_INT_CNT_DEFAULT 0x00000000
+#define mmRLC_SPARE_INT_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_CNTL_DEFAULT 0x00000080
+#define mmRLC_PREWALKER_UTCL1_TRIG_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_DEFAULT 0x00000000
+#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_DEFAULT 0x00000000
+#define mmRLC_UTCL1_STATUS_DEFAULT 0x00000000
+#define mmRLC_R2I_CNTL_0_DEFAULT 0x00000000
+#define mmRLC_R2I_CNTL_1_DEFAULT 0x00000000
+#define mmRLC_R2I_CNTL_2_DEFAULT 0x00000000
+#define mmRLC_R2I_CNTL_3_DEFAULT 0x00000000
+#define mmRLC_LB_WGP_STAT_DEFAULT 0x00000000
+#define mmRLC_GPM_INT_STAT_TH0_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_13_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_14_DEFAULT 0x00000000
+#define mmRLC_GPM_GENERAL_15_DEFAULT 0x00000000
+#define mmRLC_SPARE_INT_1_DEFAULT 0x00000000
+#define mmRLC_RLCV_SPARE_INT_1_DEFAULT 0x00000000
+#define mmRLC_PACE_SPARE_INT_1_DEFAULT 0x00000000
+#define mmRLC_SEMAPHORE_2_DEFAULT 0x00000000
+#define mmRLC_SEMAPHORE_3_DEFAULT 0x00000000
+#define mmRLC_SMU_ARGUMENT_3_DEFAULT 0x00000000
+#define mmRLC_SMU_ARGUMENT_4_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_COUNT_LSB_1_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_COUNT_MSB_1_DEFAULT 0x00000000
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_COUNT_LSB_2_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_COUNT_MSB_2_DEFAULT 0x00000000
+#define mmRLC_PACE_INT_DISABLE_DEFAULT 0xffffffff
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_DEFAULT 0x00000000
+#define mmRLC_RLCV_SPARE_INT_DEFAULT 0x00000000
+#define mmRLC_PACE_TIMER_INT_0_DEFAULT 0x00000063
+#define mmRLC_PACE_TIMER_CTRL_DEFAULT 0x00000000
+#define mmRLC_PACE_TIMER_INT_1_DEFAULT 0x00000063
+#define mmRLC_PACE_SPARE_INT_DEFAULT 0x00000000
+#define mmRLC_SMU_CLK_REQ_DEFAULT 0x00000000
+#define mmRLC_CP_STAT_INVAL_STAT_DEFAULT 0x00000000
+#define mmRLC_CP_STAT_INVAL_CTRL_DEFAULT 0x00000007
+#define mmRLC_SPP_CTRL_DEFAULT 0x00000000
+#define mmRLC_SPP_SHADER_PROFILE_EN_DEFAULT 0x00000000
+#define mmRLC_SPP_SSF_CAPTURE_EN_DEFAULT 0x00000000
+#define mmRLC_SPP_SSF_THRESHOLD_0_DEFAULT 0x009f009f
+#define mmRLC_SPP_SSF_THRESHOLD_1_DEFAULT 0x009f009f
+#define mmRLC_SPP_SSF_THRESHOLD_2_DEFAULT 0x009f009f
+#define mmRLC_SPP_INFLIGHT_RD_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPP_INFLIGHT_RD_DATA_DEFAULT 0x00000000
+#define mmRLC_SPP_PROF_INFO_1_DEFAULT 0x00000000
+#define mmRLC_SPP_PROF_INFO_2_DEFAULT 0x00000000
+#define mmRLC_SPP_GLOBAL_SH_ID_DEFAULT 0x00000000
+#define mmRLC_SPP_GLOBAL_SH_ID_VALID_DEFAULT 0x00000000
+#define mmRLC_SPP_STATUS_DEFAULT 0x00000000
+#define mmRLC_SPP_PVT_STAT_0_DEFAULT 0x00000000
+#define mmRLC_SPP_PVT_STAT_1_DEFAULT 0x00000000
+#define mmRLC_SPP_PVT_STAT_2_DEFAULT 0x00000000
+#define mmRLC_SPP_PVT_STAT_3_DEFAULT 0x00000000
+#define mmRLC_SPP_PVT_LEVEL_MAX_DEFAULT 0x00000000
+#define mmRLC_SPP_STALL_STATE_UPDATE_DEFAULT 0x00000000
+#define mmRLC_SPP_PBB_INFO_DEFAULT 0x00000000
+#define mmRLC_SPP_RESET_DEFAULT 0x00000000
+#define mmRLC_SPM_SAMPLE_CNT_DEFAULT 0x00000000
+#define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_DEFAULT 0x00000001
+#define mmRLC_GPU_CLOCK_COUNT_SPM_LSB_DEFAULT 0x00000000
+#define mmRLC_GPU_CLOCK_COUNT_SPM_MSB_DEFAULT 0x00000000
+#define mmRLC_SPM_THREAD_TRACE_CTRL_DEFAULT 0x00000000
+#define mmRLC_LB_CNTR_2_DEFAULT 0x00000000
+#define mmRLC_CPAXI_DOORBELL_MON_CTRL_DEFAULT 0x00000000
+#define mmRLC_CPAXI_DOORBELL_MON_STAT_DEFAULT 0x00000000
+#define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_DEFAULT 0x00000000
+#define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_DEFAULT 0x00000000
+
+
+// addressBlock: gc_rlcrdec
+#define mmRLC_SPP_CAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPP_CAM_DATA_DEFAULT 0x00000000
+#define mmRLC_SPP_CAM_EXT_ADDR_DEFAULT 0x00000000
+#define mmRLC_SPP_CAM_EXT_DATA_DEFAULT 0x00000000
+#define mmRLC_PACE_SCRATCH_ADDR_DEFAULT 0x00000000
+#define mmRLC_PACE_SCRATCH_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: gc_rlcsdec
+#define mmRLC_RLCS_DEC_START_DEFAULT 0x00000000
+#define mmRLC_RLCS_DEC_DUMP_ADDR_DEFAULT 0x00000000
+#define mmRLC_RLCS_EXCEPTION_REG_1_DEFAULT 0x0003b984
+#define mmRLC_RLCS_EXCEPTION_REG_2_DEFAULT 0x0003b984
+#define mmRLC_RLCS_EXCEPTION_REG_3_DEFAULT 0x0003b984
+#define mmRLC_RLCS_EXCEPTION_REG_4_DEFAULT 0x0003b984
+#define mmRLC_RLCS_GENERAL_6_DEFAULT 0x00000000
+#define mmRLC_RLCS_GENERAL_7_DEFAULT 0x00000000
+#define mmRLC_RLCS_CGCG_REQUEST_DEFAULT 0x00000003
+#define mmRLC_RLCS_CGCG_STATUS_DEFAULT 0x00000000
+#define mmRLC_RLCS_SMU_GFXCLK_STATUS_DEFAULT 0x00000000
+#define mmRLC_RLCS_SMU_GFXCLK_CONTROL_DEFAULT 0x00000000
+#define mmRLC_RLCS_SOC_DS_CNTL_DEFAULT 0x000000fe
+#define mmRLC_RLCS_GFX_DS_CNTL_DEFAULT 0x000000fe
+#define mmRLC_GPM_STAT_DEFAULT 0x00a40012
+#define mmRLC_RLCS_GPM_STAT_DEFAULT 0x00a40012
+#define mmRLC_RLCS_ABORTED_PD_SEQUENCE_DEFAULT 0x00000000
+#define mmRLC_RLCS_DIDT_FORCE_STALL_DEFAULT 0x00000000
+#define mmRLC_RLCS_IOV_CMD_STATUS_DEFAULT 0x00000000
+#define mmRLC_RLCS_IOV_CNTX_LOC_SIZE_DEFAULT 0x00000000
+#define mmRLC_RLCS_IOV_SCH_BLOCK_DEFAULT 0x00000000
+#define mmRLC_RLCS_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000
+#define mmRLC_RLCS_GPM_STAT_2_DEFAULT 0x00000000
+#define mmRLC_RLCS_GRBM_SOFT_RESET_DEFAULT 0x00000001
+#define mmRLC_RLCS_PG_CHANGE_STATUS_DEFAULT 0x00000000
+#define mmRLC_RLCS_PG_CHANGE_READ_DEFAULT 0x00000000
+#define mmRLC_RLCS_LB_STATUS_DEFAULT 0x00000000
+#define mmRLC_RLCS_LB_READ_DEFAULT 0x00000000
+#define mmRLC_RLCS_LB_CONTROL_DEFAULT 0x00000000
+#define mmRLC_RLCS_IH_SEMAPHORE_DEFAULT 0x00000000
+#define mmRLC_RLCS_IH_COOKIE_SEMAPHORE_DEFAULT 0x00000000
+#define mmRLC_RLCS_IH_CTRL_1_DEFAULT 0x00000000
+#define mmRLC_RLCS_IH_CTRL_2_DEFAULT 0x00000000
+#define mmRLC_RLCS_IH_CTRL_3_DEFAULT 0x00000000
+#define mmRLC_RLCS_IH_STATUS_DEFAULT 0x00000040
+#define mmRLC_RLCS_WGP_STATUS_DEFAULT 0x00000000
+#define mmRLC_RLCS_WGP_READ_DEFAULT 0x00000000
+#define mmRLC_RLCS_CP_INT_CTRL_1_DEFAULT 0x00000000
+#define mmRLC_RLCS_CP_INT_CTRL_2_DEFAULT 0x00000000
+#define mmRLC_RLCS_CP_INT_INFO_1_DEFAULT 0x00000000
+#define mmRLC_RLCS_CP_INT_INFO_2_DEFAULT 0x00000000
+#define mmRLC_RLCS_SPM_INT_CTRL_DEFAULT 0x00000000
+#define mmRLC_RLCS_SPM_INT_INFO_1_DEFAULT 0x00000000
+#define mmRLC_RLCS_SPM_INT_INFO_2_DEFAULT 0x00000000
+#define mmRLC_RLCS_DSM_TRIG_DEFAULT 0x00000000
+#define mmRLC_RLCS_GE_FAST_CLOCK_DEFAULT 0x00000000
+#define mmRLC_RLCS_BOOTLOAD_STATUS_DEFAULT 0x00000000
+#define mmRLC_RLCS_POWER_BRAKE_CNTL_DEFAULT 0x00000004
+#define mmRLC_RLCS_GENERAL_0_DEFAULT 0x00000000
+#define mmRLC_RLCS_GENERAL_1_DEFAULT 0x00000000
+#define mmRLC_RLCS_GENERAL_2_DEFAULT 0x00000000
+#define mmRLC_RLCS_GENERAL_3_DEFAULT 0x00000000
+#define mmRLC_RLCS_GENERAL_4_DEFAULT 0x00000000
+#define mmRLC_RLCS_GENERAL_5_DEFAULT 0x00000000
+#define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_DEFAULT 0x00000000
+#define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_DEFAULT 0x00000000
+#define mmRLC_RLCS_CMP_IDLE_CNTL_DEFAULT 0x00000100
+#define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_DEFAULT 0x00000004
+#define mmRLC_RLCS_AUXILIARY_REG_1_DEFAULT 0x0003b984
+#define mmRLC_RLCS_AUXILIARY_REG_2_DEFAULT 0x0003b984
+#define mmRLC_RLCS_AUXILIARY_REG_3_DEFAULT 0x0003b984
+#define mmRLC_RLCS_AUXILIARY_REG_4_DEFAULT 0x0003b984
+#define mmRLC_RLCS_SPM_SQTT_MODE_DEFAULT 0x00000000
+#define mmRLC_RLCS_CP_DMA_SRCID_OVER_DEFAULT 0x00000000
+#define mmRLC_RLCS_UTCL2_CNTL_DEFAULT 0x00000018
+#define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_DEFAULT 0x00000000
+#define mmRLC_RLCS_BOOTLOAD_ID_STATUS1_DEFAULT 0x00000000
+#define mmRLC_RLCS_BOOTLOAD_ID_STATUS2_DEFAULT 0x00000000
+#define mmRLC_RLCS_EDC_INT_CNTL_DEFAULT 0x00000000
+#define mmRLC_RLCS_DEC_END_DEFAULT 0x00000000
+
+
+// addressBlock: gc_pwrdec
+#define mmCGTS_SA0_QUAD0_SM_CTRL_REG_DEFAULT 0x44e00200
+#define mmCGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG_DEFAULT 0x00004421
+#define mmCGTS_SA0_QUAD1_SM_CTRL_REG_DEFAULT 0x40e00200
+#define mmCGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG_DEFAULT 0x00004020
+#define mmCGTS_SA1_QUAD0_SM_CTRL_REG_DEFAULT 0x44e00200
+#define mmCGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG_DEFAULT 0x00004421
+#define mmCGTS_SA1_QUAD1_SM_CTRL_REG_DEFAULT 0x40e00200
+#define mmCGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG_DEFAULT 0x00004020
+#define mmCGTS_RD_CTRL_REG_DEFAULT 0x00000000
+#define mmCGTS_RD_REG_DEFAULT 0x00000000
+#define mmCGTS_TCC_DISABLE_DEFAULT 0x00000000
+#define mmCGTS_USER_TCC_DISABLE_DEFAULT 0x00000000
+#define mmCGTS_STATUS_REG_DEFAULT 0x00000000
+#define mmCGTT_SPI_CGTSSM_CLK_CTRL_DEFAULT 0x00000000
+#define mmCGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA0_WGP00_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA0_WGP00_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA0_WGP01_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA0_WGP01_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA0_WGP02_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA0_WGP02_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA0_WGP10_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA0_WGP10_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA0_WGP11_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA0_WGP11_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA1_WGP00_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA1_WGP00_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA1_WGP01_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA1_WGP01_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA1_WGP02_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA1_WGP02_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA1_WGP10_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA1_WGP10_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA1_WGP11_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA1_WGP11_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA0_WGP12_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA0_WGP12_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG_DEFAULT 0x00200400
+#define mmCGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG_DEFAULT 0x00500c04
+#define mmCGTS_SA1_WGP12_CU0_TATD_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG_DEFAULT 0x00002408
+#define mmCGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG_DEFAULT 0x00000400
+#define mmCGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG_DEFAULT 0x00000803
+#define mmCGTS_SA1_WGP12_CU1_TATD_CTRL_REG_DEFAULT 0x00001404
+#define mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG_DEFAULT 0x00001c06
+#define mmCGTT_SPI_PS_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_SPIS_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_SPI_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_PC_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_BCI_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_VGT_CLK_CTRL_DEFAULT 0x00018100
+#define mmCGTT_IA_CLK_CTRL_DEFAULT 0x06000100
+#define mmCGTT_WD_CLK_CTRL_DEFAULT 0x00018100
+#define mmCGTT_PA_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_SC_CLK_CTRL0_DEFAULT 0x00000100
+#define mmCGTT_SC_CLK_CTRL1_DEFAULT 0x00000100
+#define mmCGTT_SC_CLK_CTRL2_DEFAULT 0x00000100
+#define mmCGTT_SQ_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_SQG_CLK_CTRL_DEFAULT 0x00000100
+#define mmSQ_ALU_CLK_CTRL_DEFAULT 0x00000000
+#define mmSQ_TEX_CLK_CTRL_DEFAULT 0x00000000
+#define mmSQ_LDS_CLK_CTRL_DEFAULT 0x00000000
+#define mmCGTT_SX_CLK_CTRL0_DEFAULT 0x00000100
+#define mmCGTT_SX_CLK_CTRL1_DEFAULT 0x00000100
+#define mmCGTT_SX_CLK_CTRL2_DEFAULT 0x00000100
+#define mmCGTT_SX_CLK_CTRL3_DEFAULT 0x00000100
+#define mmCGTT_SX_CLK_CTRL4_DEFAULT 0x00000100
+#define mmTD_CGTT_CTRL_DEFAULT 0x00000100
+#define mmTA_CGTT_CTRL_DEFAULT 0x00000100
+#define mmCGTT_TCPI_CLK_CTRL_DEFAULT 0x00000000
+#define mmCGTT_TCI_CLK_CTRL_DEFAULT 0x00000000
+#define mmCGTT_GDS_CLK_CTRL_DEFAULT 0x00000100
+#define mmDB_CGTT_CLK_CTRL_0_DEFAULT 0x00000100
+#define mmCB_CGTT_SCLK_CTRL_DEFAULT 0x00000100
+#define mmGL2C_CGTT_SCLK_CTRL_DEFAULT 0x00000100
+#define mmGL2A_CGTT_SCLK_CTRL_DEFAULT 0x00000100
+#define mmGL2A_CGTT_SCLK_CTRL_1_DEFAULT 0x00000100
+#define mmCGTT_CP_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_CPF_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_CPC_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_RLC_CLK_CTRL_DEFAULT 0x00000100
+#define mmRLC_GFX_RM_CNTL_DEFAULT 0x00000000
+#define mmRMI_CGTT_SCLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_TCPF_CLK_CTRL_DEFAULT 0x00000000
+#define mmGCR_CGTT_SCLK_CTRL_DEFAULT 0x00000100
+#define mmUTCL1_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmGCEA_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmSE_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmGC_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
+#define mmCGTT_GL1C_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_CHC_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_CHCG_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_GL1A_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_CHA_CLK_CTRL_DEFAULT 0x00000100
+#define mmGUS_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmCGTT_PH_CLK_CTRL0_DEFAULT 0x00000100
+#define mmCGTT_PH_CLK_CTRL1_DEFAULT 0x00000100
+#define mmCGTT_PH_CLK_CTRL2_DEFAULT 0x00000100
+#define mmCGTT_PH_CLK_CTRL3_DEFAULT 0x00000100
+
+
+// addressBlock: gc_hypdec
+#define mmCP_PFP_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_PFP_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_ME_RAM_RADDR_DEFAULT 0x00000000
+#define mmCP_ME_RAM_WADDR_DEFAULT 0x00000000
+#define mmCP_ME_RAM_DATA_DEFAULT 0x00000000
+#define mmCP_CE_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_CE_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_MEC_ME1_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_MEC_ME1_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_MEC_ME2_UCODE_ADDR_DEFAULT 0x00000000
+#define mmCP_MEC_ME2_UCODE_DATA_DEFAULT 0x00000000
+#define mmCP_PFP_IC_BASE_LO_DEFAULT 0x00000000
+#define mmCP_PFP_IC_BASE_HI_DEFAULT 0x00000000
+#define mmCP_PFP_IC_BASE_CNTL_DEFAULT 0x00000010
+#define mmCP_PFP_IC_OP_CNTL_DEFAULT 0x00000000
+#define mmCP_ME_IC_BASE_LO_DEFAULT 0x00000000
+#define mmCP_ME_IC_BASE_HI_DEFAULT 0x00000000
+#define mmCP_ME_IC_BASE_CNTL_DEFAULT 0x00000010
+#define mmCP_ME_IC_OP_CNTL_DEFAULT 0x00000000
+#define mmCP_CE_IC_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CE_IC_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CE_IC_BASE_CNTL_DEFAULT 0x00000010
+#define mmCP_CE_IC_OP_CNTL_DEFAULT 0x00000000
+#define mmCP_CPC_IC_BASE_LO_DEFAULT 0x00000000
+#define mmCP_CPC_IC_BASE_HI_DEFAULT 0x00000000
+#define mmCP_CPC_IC_BASE_CNTL_DEFAULT 0x00000010
+#define mmCP_CPC_IC_OP_CNTL_DEFAULT 0x00000000
+#define mmCP_MES_IC_BASE_LO_DEFAULT 0x00000000
+#define mmCP_MES_MIBASE_LO_DEFAULT 0x00000000
+#define mmCP_MES_IC_BASE_HI_DEFAULT 0x00000000
+#define mmCP_MES_MIBASE_HI_DEFAULT 0x00000000
+#define mmCP_MES_IC_BASE_CNTL_DEFAULT 0x00000000
+#define mmCP_MES_IC_OP_CNTL_DEFAULT 0x00000000
+#define mmCP_MES_DC_BASE_LO_DEFAULT 0x00000000
+#define mmCP_MES_MDBASE_LO_DEFAULT 0x00000000
+#define mmCP_MES_DC_BASE_HI_DEFAULT 0x00000000
+#define mmCP_MES_MDBASE_HI_DEFAULT 0x00000000
+#define mmCP_MES_LOCAL_BASE0_LO_DEFAULT 0x00000000
+#define mmCP_MES_LOCAL_BASE0_HI_DEFAULT 0x00000000
+#define mmCP_MES_LOCAL_MASK0_LO_DEFAULT 0xffff0000
+#define mmCP_MES_LOCAL_MASK0_HI_DEFAULT 0x0000ffff
+#define mmCP_MES_LOCAL_APERTURE_DEFAULT 0x00000000
+#define mmCP_MES_MIBOUND_LO_DEFAULT 0x0000ffff
+#define mmCP_MES_MIBOUND_HI_DEFAULT 0x00000000
+#define mmCP_MES_MDBOUND_LO_DEFAULT 0x0000ffff
+#define mmCP_MES_MDBOUND_HI_DEFAULT 0x0000ffff
+#define mmGFX_PIPE_PRIORITY_DEFAULT 0x00000001
+#define mmGRBM_GFX_INDEX_SR_SELECT_DEFAULT 0x00000000
+#define mmGRBM_GFX_INDEX_SR_DATA_DEFAULT 0xe0000000
+#define mmGRBM_GFX_CNTL_SR_SELECT_DEFAULT 0x00000000
+#define mmGRBM_GFX_CNTL_SR_DATA_DEFAULT 0x00000000
+#define mmGRBM_CAM_INDEX_DEFAULT 0x00000000
+#define mmGRBM_HYP_CAM_INDEX_DEFAULT 0x00000000
+#define mmGRBM_CAM_DATA_DEFAULT 0x00000000
+#define mmGRBM_HYP_CAM_DATA_DEFAULT 0x00000000
+#define mmGRBM_CAM_DATA_UPPER_DEFAULT 0x00000000
+#define mmGRBM_HYP_CAM_DATA_UPPER_DEFAULT 0x00000000
+#define mmGC_IH_COOKIE_0_PTR_DEFAULT 0x00004300
+#define mmRLC_GPU_IOV_VF_ENABLE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_CFG_REG6_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_CFG_REG8_DEFAULT 0x00000000
+#define mmRLC_RLCV_TIMER_INT_0_DEFAULT 0x00000063
+#define mmRLC_RLCV_TIMER_CTRL_DEFAULT 0x00000000
+#define mmRLC_RLCV_TIMER_STAT_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT 0x7fffffff
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VF_MASK_DEFAULT 0x7fffffff
+#define mmRLC_HYP_SEMAPHORE_0_DEFAULT 0x00000000
+#define mmRLC_HYP_SEMAPHORE_1_DEFAULT 0x00000000
+#define mmRLC_BUSY_CLK_CNTL_DEFAULT 0x00000010
+#define mmRLC_CLK_CNTL_DEFAULT 0x00030c0f
+#define mmRLC_PACE_TIMER_STAT_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCH_BLOCK_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_CFG_REG1_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_CFG_REG2_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCH_0_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCH_3_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCH_1_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCH_2_DEFAULT 0x00000000
+#define mmRLC_PACE_INT_FORCE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_INT_STAT_DEFAULT 0x00000000
+#define mmRLC_RLCV_TIMER_INT_1_DEFAULT 0x00000063
+#define mmRLC_IH_COOKIE_DEFAULT 0x00000000
+#define mmRLC_IH_COOKIE_CNTL_DEFAULT 0x00000000
+#define mmRLC_HYP_RLCG_UCODE_CHKSUM_DEFAULT 0x00000000
+#define mmRLC_HYP_RLCP_UCODE_CHKSUM_DEFAULT 0x00000000
+#define mmRLC_HYP_RLCV_UCODE_CHKSUM_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_F32_CNTL_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_F32_RESET_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SDMA0_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SDMA1_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SMU_RESPONSE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_RLC_RESPONSE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_INT_DISABLE_DEFAULT 0xffffffff
+#define mmRLC_GPU_IOV_INT_FORCE_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT 0x00000000
+#define mmRLC_HYP_SEMAPHORE_2_DEFAULT 0x00000000
+#define mmRLC_HYP_SEMAPHORE_3_DEFAULT 0x00000000
+#define mmRLC_HYP_RESET_VECTOR_DEFAULT 0x00000000
+#define mmRLC_HYP_BOOTLOAD_SIZE_DEFAULT 0x00000000
+#define mmRLC_HYP_BOOTLOAD_ADDR_LO_DEFAULT 0x00000000
+#define mmRLC_HYP_BOOTLOAD_ADDR_HI_DEFAULT 0x00000000
+#define mmRLC_GPM_IRAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPM_IRAM_DATA_DEFAULT 0x00000000
+#define mmRLC_GPM_UCODE_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPM_UCODE_DATA_DEFAULT 0x00000000
+#define mmRLC_PACE_UCODE_ADDR_DEFAULT 0x00000000
+#define mmRLC_PACE_UCODE_DATA_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_UCODE_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_UCODE_DATA_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPU_IOV_SCRATCH_DATA_DEFAULT 0x00000000
+#define mmRLC_RLCV_IRAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_RLCV_IRAM_DATA_DEFAULT 0x00000000
+#define mmRLC_RLCP_IRAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_RLCP_IRAM_DATA_DEFAULT 0x00000000
+#define mmRLC_SRM_DRAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_SRM_DRAM_DATA_DEFAULT 0x00000000
+#define mmRLC_SRM_ARAM_ADDR_DEFAULT 0x00000000
+#define mmRLC_SRM_ARAM_DATA_DEFAULT 0x00000000
+#define mmRLC_GPM_SCRATCH_ADDR_DEFAULT 0x00000000
+#define mmRLC_GPM_SCRATCH_DATA_DEFAULT 0x00000000
+#define mmRLC_GTS_OFFSET_LSB_DEFAULT 0x00000000
+#define mmRLC_GTS_OFFSET_MSB_DEFAULT 0x00000000
+
+
+// addressBlock: gc_sdma0_sdma0hypdec
+#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
+#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
+#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
+#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
+#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000001
+#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
+#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
+#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
+#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
+#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_sdma1_sdma1hypdec
+#define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
+#define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
+#define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
+#define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
+#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
+#define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000001
+#define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
+#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
+#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
+#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
+#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
+#define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: gc_gcvmsharedhvdec
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF16_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF17_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF18_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF19_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF20_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF21_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF22_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF23_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF24_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF25_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF26_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF27_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF28_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF29_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF30_DEFAULT 0x00000000
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF31_DEFAULT 0x00000000
+#define mmGCVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100
+#define mmGCMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000
+#define mmGCMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000
+#define mmGCVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000
+#define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_16_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_17_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_18_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_19_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_20_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_21_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_22_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_23_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_24_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_25_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_26_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_27_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_28_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_29_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_30_DEFAULT 0x00000000
+#define mmGCVM_PCIE_ATS_CNTL_VF_31_DEFAULT 0x00000000
+#define mmGCUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+#define mmGCMC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000
+
+
+// addressBlock: gccacind
+#define ixPCC_STALL_PATTERN_CTRL_DEFAULT 0x07fa0401
+#define ixPWRBRK_STALL_PATTERN_CTRL_DEFAULT 0x00fa0401
+#define ixPCC_STALL_PATTERN_1_2_DEFAULT 0x00000000
+#define ixPCC_STALL_PATTERN_3_4_DEFAULT 0x00000000
+#define ixPCC_STALL_PATTERN_5_6_DEFAULT 0x00000000
+#define ixPCC_STALL_PATTERN_7_DEFAULT 0x00000000
+#define ixPWRBRK_STALL_PATTERN_1_2_DEFAULT 0x00000000
+#define ixPWRBRK_STALL_PATTERN_3_4_DEFAULT 0x00000000
+#define ixPWRBRK_STALL_PATTERN_5_6_DEFAULT 0x00000000
+#define ixPWRBRK_STALL_PATTERN_7_DEFAULT 0x00000000
+#define ixGC_CAC_ID_DEFAULT 0x00000000
+#define ixGC_CAC_CNTL_DEFAULT 0x000001fe
+#define ixGC_CAC_OVR_SEL_DEFAULT 0x00000000
+#define ixGC_CAC_OVR_VAL_DEFAULT 0x00000000
+#define ixGC_CAC_WEIGHT_BCI_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CB_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CB_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CBR_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CBR_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CP_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CP_1_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_DB_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_DB_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_DBR_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_DBR_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_GDS_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_GDS_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_LDS_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_LDS_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_PA_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_PC_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_SC_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_SPI_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SPI_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SPI_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SQ_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SQ_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SQ_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_SX_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_SXRB_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TA_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_TCP_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TCP_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TCP_2_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_TD_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TD_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TD_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TD_3_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_TD_4_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_RMI_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_EA_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_EA_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_EA_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_CU_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_UTCL1_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_GE_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_PMM_0_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_GL2C_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_GL2C_1_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_GL2C_2_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_GUS_0_DEFAULT 0x00010001
+#define ixGC_CAC_WEIGHT_GUS_1_DEFAULT 0x00000001
+#define ixGC_CAC_WEIGHT_PH_0_DEFAULT 0x00000001
+#define ixGC_CAC_ACC_BCI0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_BCI1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CB0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CB1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CB2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CB3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CBR0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CBR1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CBR2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CBR3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CP0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CP1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CP2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DB0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DB1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DB2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DB3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DBR0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DBR1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DBR2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_DBR3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GDS0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GDS1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GDS2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GDS3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_LDS0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_LDS1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_LDS2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_LDS3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_PA0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_PA1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_PC0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SC0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SPI5_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ0_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ0_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ1_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ1_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ2_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ2_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ3_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ3_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ4_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ4_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ5_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ5_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ6_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ6_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ7_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ7_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ8_LOWER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SQ8_UPPER_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SX0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_SXRB0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TA0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TCP4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD5_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD6_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD7_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD8_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_TD9_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_RMI0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_EA5_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ATCL20_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ATCL21_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ATCL22_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ATCL23_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ATCL24_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER5_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER6_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER7_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER8_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_ROUTER9_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML20_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML21_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML22_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML23_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_VML24_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_WALKER0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_WALKER1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_WALKER2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_WALKER3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL2_WALKER4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CU0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_UTCL10_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_CH0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GE0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_PMM0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GL2C0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GL2C1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GL2C2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GL2C3_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GL2C4_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GUS0_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GUS1_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_GUS2_DEFAULT 0x00000000
+#define ixGC_CAC_ACC_PH0_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_BCI_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_CB_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_CBR_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_CP_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_DB_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_DBR_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_GDS_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_LDS_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_PA_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_PC_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SC_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SPI_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_CU_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SQ_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SX_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_SXRB_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_TA_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_TCP_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_TD_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_RMI_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_EA_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_UTCL2_ATCL2_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_UTCL2_ROUTER_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_UTCL2_VML2_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_UTCL2_WALKER_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_UTCL1_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_GE_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_PMM_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_GL2C_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_GUS_DEFAULT 0x00000000
+#define ixGC_CAC_OVRD_PH_DEFAULT 0x00000000
+#define ixRELEASE_TO_STALL_LUT_1_8_DEFAULT 0x00000000
+#define ixRELEASE_TO_STALL_LUT_9_16_DEFAULT 0x00000000
+#define ixRELEASE_TO_STALL_LUT_17_20_DEFAULT 0x00000000
+#define ixSTALL_TO_RELEASE_LUT_1_4_DEFAULT 0x00000000
+#define ixSTALL_TO_RELEASE_LUT_5_7_DEFAULT 0x00000000
+#define ixSTALL_TO_PWRBRK_LUT_1_4_DEFAULT 0x00000000
+#define ixSTALL_TO_PWRBRK_LUT_5_7_DEFAULT 0x00000000
+#define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4_DEFAULT 0x00000000
+#define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7_DEFAULT 0x00000000
+#define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8_DEFAULT 0x00000000
+#define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16_DEFAULT 0x00000000
+#define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_1_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_2_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_3_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_4_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_5_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_6_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_7_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_8_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_9_DEFAULT 0x00000000
+#define ixFIXED_PATTERN_PERF_COUNTER_10_DEFAULT 0x00000000
+#define ixHW_LUT_UPDATE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: secacind
+#define ixSE_CAC_ID_DEFAULT 0x00000000
+#define ixSE_CAC_CNTL_DEFAULT 0x000001fe
+#define ixSE_CAC_OVR_SEL_DEFAULT 0x00000000
+#define ixSE_CAC_OVR_VAL_DEFAULT 0x00000000
+
+
+// addressBlock: spmglbind
+#define ixGLB_CPG_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_CPC_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_CPF_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GDS_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GCR_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_PH_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GE_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GUS_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_CHA_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_CHCG_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_ATCL2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_VML2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_SDMA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_SDMA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2A0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2A1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2A2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2A3_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C3_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C4_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C5_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C6_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C7_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C8_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C9_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C10_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C11_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C12_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C13_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C14_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_GL2C15_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA3_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA4_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA5_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA6_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA7_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA8_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA9_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA10_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA11_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA12_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA13_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA14_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_EA15_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_CHC0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_CHC1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_CHC2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixGLB_CHC3_SAMPLEDELAY_DEFAULT 0x00000000
+
+
+// addressBlock: spmind
+#define ixSE_SPI_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SQG_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_CBR_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_DBR_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0SX_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0PA_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0GL1A_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0GL1CG_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0CB0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0CB1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0CB2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0CB3_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0DB0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0DB1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0DB2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0DB3_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0SC0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0SC1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0RMI0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0RMI1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0GL1C0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0GL1C1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0GL1C2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0GL1C3_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP00TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP00TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP00TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP00TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP00TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP00TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP01TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP01TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP01TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP01TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP01TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP01TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP02TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP02TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP02TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP02TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP02TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP02TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP10TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP10TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP10TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP10TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP10TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP10TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP11TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP11TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP11TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP11TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP11TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA0WGP11TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1SX_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1PA_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1GL1A_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1GL1CG_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1CB0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1CB1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1CB2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1CB3_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1DB0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1DB1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1DB2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1DB3_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1SC0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1SC1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1RMI0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1RMI1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1GL1C0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1GL1C1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1GL1C2_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1GL1C3_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP00TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP00TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP00TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP00TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP00TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP00TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP01TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP01TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP01TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP01TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP01TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP01TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP02TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP02TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP02TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP02TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP02TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP02TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP10TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP10TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP10TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP10TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP10TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP10TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP11TA0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP11TA1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP11TD0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP11TD1_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP11TCP0_SAMPLEDELAY_DEFAULT 0x00000000
+#define ixSE_SA1WGP11TCP1_SAMPLEDELAY_DEFAULT 0x00000000
+
+
+// addressBlock: sqind
+#define ixSQ_WAVE_MODE_DEFAULT 0x00000000
+#define ixSQ_WAVE_STATUS_DEFAULT 0x00000000
+#define ixSQ_WAVE_TRAPSTS_DEFAULT 0x00000000
+#define ixSQ_WAVE_HW_ID_LEGACY_DEFAULT 0x00000000
+#define ixSQ_WAVE_GPR_ALLOC_DEFAULT 0x00000000
+#define ixSQ_WAVE_LDS_ALLOC_DEFAULT 0x00000000
+#define ixSQ_WAVE_IB_STS_DEFAULT 0x00000000
+#define ixSQ_WAVE_PC_LO_DEFAULT 0x00000000
+#define ixSQ_WAVE_PC_HI_DEFAULT 0x00000000
+#define ixSQ_WAVE_INST_DW0_DEFAULT 0x00000000
+#define ixSQ_WAVE_IB_DBG1_DEFAULT 0x00000000
+#define ixSQ_WAVE_FLUSH_IB_DEFAULT 0x00000000
+#define ixSQ_WAVE_HW_ID1_DEFAULT 0x00000000
+#define ixSQ_WAVE_HW_ID2_DEFAULT 0x00000000
+#define ixSQ_WAVE_POPS_PACKER_DEFAULT 0x00000000
+#define ixSQ_WAVE_SCHED_MODE_DEFAULT 0x00000000
+#define ixSQ_WAVE_VGPR_OFFSET_DEFAULT 0x00000000
+#define ixSQ_WAVE_IB_STS2_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP0_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP1_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP2_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP3_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP4_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP5_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP6_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP7_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP8_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP9_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP10_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP11_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP12_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP13_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP14_DEFAULT 0x00000000
+#define ixSQ_WAVE_TTMP15_DEFAULT 0x00000000
+#define ixSQ_WAVE_M0_DEFAULT 0x00000000
+#define ixSQ_WAVE_EXEC_LO_DEFAULT 0x00000000
+#define ixSQ_WAVE_EXEC_HI_DEFAULT 0x00000000
+#define ixSQ_WAVE_FLAT_SCRATCH_LO_DEFAULT 0x00000000
+#define ixSQ_WAVE_FLAT_SCRATCH_HI_DEFAULT 0x00000000
+#define ixSQ_WAVE_FLAT_XNACK_MASK_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_AUTO_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_ERROR_DEFAULT 0x00000000
+#define ixSQ_INTERRUPT_WORD_WAVE_DEFAULT 0x00000000
+
+
+// addressBlock: didtind
+#define ixDIDT_SQ_CTRL0_DEFAULT 0x0000ff00
+#define ixDIDT_SQ_CTRL1_DEFAULT 0x00ff00ff
+#define ixDIDT_SQ_CTRL2_DEFAULT 0x18800004
+#define ixDIDT_SQ_CTRL_OCP_DEFAULT 0x000000ff
+#define ixDIDT_SQ_STALL_CTRL_DEFAULT 0x00fff000
+#define ixDIDT_SQ_TUNING_CTRL_DEFAULT 0x00010004
+#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
+#define ixDIDT_SQ_CTRL3_DEFAULT 0x00038000
+#define ixDIDT_SQ_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_SQ_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_SQ_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_SQ_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_SQ_MPD_SCALE_FACTOR_DEFAULT 0x00000000
+#define ixDIDT_SQ_STALL_RELEASE_CNTL0_DEFAULT 0x00000000
+#define ixDIDT_SQ_STALL_RELEASE_CNTL1_DEFAULT 0x00000000
+#define ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS_DEFAULT 0x00000000
+#define ixDIDT_SQ_WEIGHT0_3_DEFAULT 0x00000000
+#define ixDIDT_SQ_WEIGHT4_7_DEFAULT 0x00000000
+#define ixDIDT_SQ_WEIGHT8_11_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_CTRL_DEFAULT 0x00001c00
+#define ixDIDT_SQ_EDC_THRESHOLD_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_SQ_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_SQ_EDC_TIMER_PERIOD_DEFAULT 0x00003fff
+#define ixDIDT_SQ_THROTTLE_CTRL_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STALL_DELAY_1_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STALL_DELAY_2_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STALL_DELAY_3_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_STATUS_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_OVERFLOW_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define ixDIDT_SQ_EDC_PCC_PERF_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_DB_CTRL0_DEFAULT 0x0000ff00
+#define ixDIDT_DB_CTRL1_DEFAULT 0x00ff00ff
+#define ixDIDT_DB_CTRL2_DEFAULT 0x18800004
+#define ixDIDT_DB_CTRL_OCP_DEFAULT 0x000000ff
+#define ixDIDT_DB_STALL_CTRL_DEFAULT 0x00fff000
+#define ixDIDT_DB_TUNING_CTRL_DEFAULT 0x00010004
+#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
+#define ixDIDT_DB_CTRL3_DEFAULT 0x00038000
+#define ixDIDT_DB_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_DB_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_DB_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_DB_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_DB_MPD_SCALE_FACTOR_DEFAULT 0x00000000
+#define ixDIDT_DB_STALL_RELEASE_CNTL0_DEFAULT 0x00000000
+#define ixDIDT_DB_STALL_RELEASE_CNTL1_DEFAULT 0x00000000
+#define ixDIDT_DB_STALL_RELEASE_CNTL_STATUS_DEFAULT 0x00000000
+#define ixDIDT_DB_WEIGHT0_3_DEFAULT 0x00000000
+#define ixDIDT_DB_WEIGHT4_7_DEFAULT 0x00000000
+#define ixDIDT_DB_WEIGHT8_11_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_CTRL_DEFAULT 0x00001c00
+#define ixDIDT_DB_EDC_THRESHOLD_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_DB_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_DB_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_DB_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_DB_EDC_TIMER_PERIOD_DEFAULT 0x00003fff
+#define ixDIDT_DB_THROTTLE_CTRL_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_STALL_DELAY_1_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_STATUS_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_OVERFLOW_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define ixDIDT_DB_EDC_PCC_PERF_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_TD_CTRL0_DEFAULT 0x0000ff00
+#define ixDIDT_TD_CTRL1_DEFAULT 0x00ff00ff
+#define ixDIDT_TD_CTRL2_DEFAULT 0x18800004
+#define ixDIDT_TD_CTRL_OCP_DEFAULT 0x000000ff
+#define ixDIDT_TD_STALL_CTRL_DEFAULT 0x00fff000
+#define ixDIDT_TD_TUNING_CTRL_DEFAULT 0x00010004
+#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
+#define ixDIDT_TD_CTRL3_DEFAULT 0x00038000
+#define ixDIDT_TD_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_TD_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_TD_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_TD_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_TD_MPD_SCALE_FACTOR_DEFAULT 0x00000000
+#define ixDIDT_TD_STALL_RELEASE_CNTL0_DEFAULT 0x00000000
+#define ixDIDT_TD_STALL_RELEASE_CNTL1_DEFAULT 0x00000000
+#define ixDIDT_TD_STALL_RELEASE_CNTL_STATUS_DEFAULT 0x00000000
+#define ixDIDT_TD_WEIGHT0_3_DEFAULT 0x00000000
+#define ixDIDT_TD_WEIGHT4_7_DEFAULT 0x00000000
+#define ixDIDT_TD_WEIGHT8_11_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_CTRL_DEFAULT 0x00001c00
+#define ixDIDT_TD_EDC_THRESHOLD_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_TD_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_TD_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_TD_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_TD_EDC_TIMER_PERIOD_DEFAULT 0x00003fff
+#define ixDIDT_TD_THROTTLE_CTRL_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STALL_DELAY_1_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STALL_DELAY_2_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STALL_DELAY_3_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_STATUS_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_OVERFLOW_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define ixDIDT_TD_EDC_PCC_PERF_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_TCP_CTRL0_DEFAULT 0x0000ff00
+#define ixDIDT_TCP_CTRL1_DEFAULT 0x00ff00ff
+#define ixDIDT_TCP_CTRL2_DEFAULT 0x18800004
+#define ixDIDT_TCP_CTRL_OCP_DEFAULT 0x0000ffff
+#define ixDIDT_TCP_STALL_CTRL_DEFAULT 0x00fff000
+#define ixDIDT_TCP_TUNING_CTRL_DEFAULT 0x00010004
+#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff
+#define ixDIDT_TCP_CTRL3_DEFAULT 0x00038000
+#define ixDIDT_TCP_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_TCP_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_TCP_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_TCP_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_TCP_MPD_SCALE_FACTOR_DEFAULT 0x00000000
+#define ixDIDT_TCP_STALL_RELEASE_CNTL0_DEFAULT 0x00000000
+#define ixDIDT_TCP_STALL_RELEASE_CNTL1_DEFAULT 0x00000000
+#define ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS_DEFAULT 0x00000000
+#define ixDIDT_TCP_WEIGHT0_3_DEFAULT 0x00000000
+#define ixDIDT_TCP_WEIGHT4_7_DEFAULT 0x00000000
+#define ixDIDT_TCP_WEIGHT8_11_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_CTRL_DEFAULT 0x00001c00
+#define ixDIDT_TCP_EDC_THRESHOLD_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001
+#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421
+#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249
+#define ixDIDT_TCP_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa
+#define ixDIDT_TCP_EDC_TIMER_PERIOD_DEFAULT 0x00003fff
+#define ixDIDT_TCP_THROTTLE_CTRL_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STALL_DELAY_1_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STALL_DELAY_2_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STALL_DELAY_3_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_STATUS_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_OVERFLOW_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000
+#define ixDIDT_TCP_EDC_PCC_PERF_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_SQ_STALL_EVENT_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_DB_STALL_EVENT_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_TD_STALL_EVENT_COUNTER_DEFAULT 0x00000000
+#define ixDIDT_TCP_STALL_EVENT_COUNTER_DEFAULT 0x00000000
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
new file mode 100644
index 000000000000..1dbc7cefbc05
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -0,0 +1,11339 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _gc_10_1_0_OFFSET_HEADER
+#define _gc_10_1_0_OFFSET_HEADER
+
+
+
+// addressBlock: gc_sdma0_sdma0dec
+// base address: 0x4980
+#define mmSDMA0_DEC_START 0x0000
+#define mmSDMA0_DEC_START_BASE_IDX 0
+#define mmSDMA0_PG_CNTL 0x0016
+#define mmSDMA0_PG_CNTL_BASE_IDX 0
+#define mmSDMA0_PG_CTX_LO 0x0017
+#define mmSDMA0_PG_CTX_LO_BASE_IDX 0
+#define mmSDMA0_PG_CTX_HI 0x0018
+#define mmSDMA0_PG_CTX_HI_BASE_IDX 0
+#define mmSDMA0_PG_CTX_CNTL 0x0019
+#define mmSDMA0_PG_CTX_CNTL_BASE_IDX 0
+#define mmSDMA0_POWER_CNTL 0x001a
+#define mmSDMA0_POWER_CNTL_BASE_IDX 0
+#define mmSDMA0_CLK_CTRL 0x001b
+#define mmSDMA0_CLK_CTRL_BASE_IDX 0
+#define mmSDMA0_CNTL 0x001c
+#define mmSDMA0_CNTL_BASE_IDX 0
+#define mmSDMA0_CHICKEN_BITS 0x001d
+#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0
+#define mmSDMA0_GB_ADDR_CONFIG 0x001e
+#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0
+#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f
+#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020
+#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define mmSDMA0_RB_RPTR_FETCH 0x0022
+#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0
+#define mmSDMA0_IB_OFFSET_FETCH 0x0023
+#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0
+#define mmSDMA0_PROGRAM 0x0024
+#define mmSDMA0_PROGRAM_BASE_IDX 0
+#define mmSDMA0_STATUS_REG 0x0025
+#define mmSDMA0_STATUS_REG_BASE_IDX 0
+#define mmSDMA0_STATUS1_REG 0x0026
+#define mmSDMA0_STATUS1_REG_BASE_IDX 0
+#define mmSDMA0_RD_BURST_CNTL 0x0027
+#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0
+#define mmSDMA0_HBM_PAGE_CONFIG 0x0028
+#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0
+#define mmSDMA0_UCODE_CHECKSUM 0x0029
+#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0
+#define mmSDMA0_F32_CNTL 0x002a
+#define mmSDMA0_F32_CNTL_BASE_IDX 0
+#define mmSDMA0_FREEZE 0x002b
+#define mmSDMA0_FREEZE_BASE_IDX 0
+#define mmSDMA0_PHASE0_QUANTUM 0x002c
+#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0
+#define mmSDMA0_PHASE1_QUANTUM 0x002d
+#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0
+#define mmSDMA_POWER_GATING 0x002e
+#define mmSDMA_POWER_GATING_BASE_IDX 0
+#define mmSDMA_PGFSM_CONFIG 0x002f
+#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0
+#define mmSDMA_PGFSM_WRITE 0x0030
+#define mmSDMA_PGFSM_WRITE_BASE_IDX 0
+#define mmSDMA_PGFSM_READ 0x0031
+#define mmSDMA_PGFSM_READ_BASE_IDX 0
+#define mmSDMA0_EDC_CONFIG 0x0032
+#define mmSDMA0_EDC_CONFIG_BASE_IDX 0
+#define mmSDMA0_BA_THRESHOLD 0x0033
+#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0
+#define mmSDMA0_ID 0x0034
+#define mmSDMA0_ID_BASE_IDX 0
+#define mmSDMA0_VERSION 0x0035
+#define mmSDMA0_VERSION_BASE_IDX 0
+#define mmSDMA0_EDC_COUNTER 0x0036
+#define mmSDMA0_EDC_COUNTER_BASE_IDX 0
+#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037
+#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0
+#define mmSDMA0_STATUS2_REG 0x0038
+#define mmSDMA0_STATUS2_REG_BASE_IDX 0
+#define mmSDMA0_ATOMIC_CNTL 0x0039
+#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0
+#define mmSDMA0_ATOMIC_PREOP_LO 0x003a
+#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0
+#define mmSDMA0_ATOMIC_PREOP_HI 0x003b
+#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0
+#define mmSDMA0_UTCL1_CNTL 0x003c
+#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0
+#define mmSDMA0_UTCL1_WATERMK 0x003d
+#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0
+#define mmSDMA0_UTCL1_RD_STATUS 0x003e
+#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0
+#define mmSDMA0_UTCL1_WR_STATUS 0x003f
+#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0
+#define mmSDMA0_UTCL1_INV0 0x0040
+#define mmSDMA0_UTCL1_INV0_BASE_IDX 0
+#define mmSDMA0_UTCL1_INV1 0x0041
+#define mmSDMA0_UTCL1_INV1_BASE_IDX 0
+#define mmSDMA0_UTCL1_INV2 0x0042
+#define mmSDMA0_UTCL1_INV2_BASE_IDX 0
+#define mmSDMA0_UTCL1_RD_XNACK0 0x0043
+#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0
+#define mmSDMA0_UTCL1_RD_XNACK1 0x0044
+#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0
+#define mmSDMA0_UTCL1_WR_XNACK0 0x0045
+#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0
+#define mmSDMA0_UTCL1_WR_XNACK1 0x0046
+#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0
+#define mmSDMA0_UTCL1_TIMEOUT 0x0047
+#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0
+#define mmSDMA0_UTCL1_PAGE 0x0048
+#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0
+#define mmSDMA0_POWER_CNTL_IDLE 0x0049
+#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0
+#define mmSDMA0_RELAX_ORDERING_LUT 0x004a
+#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0
+#define mmSDMA0_CHICKEN_BITS_2 0x004b
+#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0
+#define mmSDMA0_STATUS3_REG 0x004c
+#define mmSDMA0_STATUS3_REG_BASE_IDX 0
+#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d
+#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e
+#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PHASE2_QUANTUM 0x004f
+#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0
+#define mmSDMA0_ERROR_LOG 0x0050
+#define mmSDMA0_ERROR_LOG_BASE_IDX 0
+#define mmSDMA0_PUB_DUMMY_REG0 0x0051
+#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0
+#define mmSDMA0_F32_COUNTER 0x0055
+#define mmSDMA0_F32_COUNTER_BASE_IDX 0
+#define mmSDMA0_PERFMON_CNTL 0x0057
+#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058
+#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059
+#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a
+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0
+#define mmSDMA0_CRD_CNTL 0x005b
+#define mmSDMA0_CRD_CNTL_BASE_IDX 0
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d
+#define mmSDMA0_AQL_STATUS 0x005f
+#define mmSDMA0_AQL_STATUS_BASE_IDX 0
+#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060
+#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061
+#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define mmSDMA0_TLBI_GCR_CNTL 0x0062
+#define mmSDMA0_TLBI_GCR_CNTL_BASE_IDX 0
+#define mmSDMA0_TILING_CONFIG 0x0063
+#define mmSDMA0_TILING_CONFIG_BASE_IDX 0
+#define mmSDMA0_HASH 0x0064
+#define mmSDMA0_HASH_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER0_SELECT 0x0068
+#define mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER0_SELECT1 0x0069
+#define mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER0_LO 0x006a
+#define mmSDMA0_PERFCOUNTER0_LO_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER0_HI 0x006b
+#define mmSDMA0_PERFCOUNTER0_HI_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER1_SELECT 0x006c
+#define mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER1_SELECT1 0x006d
+#define mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER1_LO 0x006e
+#define mmSDMA0_PERFCOUNTER1_LO_BASE_IDX 0
+#define mmSDMA0_PERFCOUNTER1_HI 0x006f
+#define mmSDMA0_PERFCOUNTER1_HI_BASE_IDX 0
+#define mmSDMA0_INT_STATUS 0x0070
+#define mmSDMA0_INT_STATUS_BASE_IDX 0
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG2 0x0071
+#define mmSDMA0_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0
+#define mmSDMA0_HOLE_ADDR_LO 0x0072
+#define mmSDMA0_HOLE_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_HOLE_ADDR_HI 0x0073
+#define mmSDMA0_HOLE_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_CNTL 0x0080
+#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_RB_BASE 0x0081
+#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0
+#define mmSDMA0_GFX_RB_BASE_HI 0x0082
+#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR 0x0083
+#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR_HI 0x0084
+#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR 0x0085
+#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_HI 0x0086
+#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_GFX_IB_CNTL 0x008a
+#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_IB_RPTR 0x008b
+#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_GFX_IB_OFFSET 0x008c
+#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_GFX_IB_BASE_LO 0x008d
+#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_GFX_IB_BASE_HI 0x008e
+#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_GFX_IB_SIZE 0x008f
+#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_GFX_SKIP_CNTL 0x0090
+#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091
+#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_GFX_DOORBELL 0x0092
+#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0
+#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093
+#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_STATUS 0x00a8
+#define mmSDMA0_GFX_STATUS_BASE_IDX 0
+#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9
+#define mmSDMA0_GFX_WATERMARK 0x00aa
+#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0
+#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab
+#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac
+#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad
+#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af
+#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_GFX_PREEMPT 0x00b0
+#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0
+#define mmSDMA0_GFX_DUMMY_REG 0x00b1
+#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4
+#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5
+#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0
+#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1
+#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2
+#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3
+#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4
+#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5
+#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6
+#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7
+#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8
+#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9
+#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_CNTL 0x00e0
+#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_BASE 0x00e1
+#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_BASE_HI 0x00e2
+#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR 0x00e3
+#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4
+#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR 0x00e5
+#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6
+#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7
+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9
+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_CNTL 0x00ea
+#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_RPTR 0x00eb
+#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_OFFSET 0x00ec
+#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_BASE_LO 0x00ed
+#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_BASE_HI 0x00ee
+#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_SIZE 0x00ef
+#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_PAGE_SKIP_CNTL 0x00f0
+#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1
+#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_PAGE_DOORBELL 0x00f2
+#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0
+#define mmSDMA0_PAGE_STATUS 0x0108
+#define mmSDMA0_PAGE_STATUS_BASE_IDX 0
+#define mmSDMA0_PAGE_DOORBELL_LOG 0x0109
+#define mmSDMA0_PAGE_WATERMARK 0x010a
+#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0
+#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b
+#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c
+#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d
+#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f
+#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_PAGE_PREEMPT 0x0110
+#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0
+#define mmSDMA0_PAGE_DUMMY_REG 0x0111
+#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113
+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114
+#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115
+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120
+#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121
+#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122
+#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123
+#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124
+#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125
+#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126
+#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127
+#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128
+#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129
+#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_CNTL 0x0140
+#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_BASE 0x0141
+#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_BASE_HI 0x0142
+#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR 0x0143
+#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144
+#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR 0x0145
+#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146
+#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_CNTL 0x014a
+#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_RPTR 0x014b
+#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_OFFSET 0x014c
+#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_BASE_LO 0x014d
+#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_BASE_HI 0x014e
+#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_SIZE 0x014f
+#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC0_SKIP_CNTL 0x0150
+#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151
+#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC0_DOORBELL 0x0152
+#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC0_STATUS 0x0168
+#define mmSDMA0_RLC0_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169
+#define mmSDMA0_RLC0_WATERMARK 0x016a
+#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b
+#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c
+#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d
+#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f
+#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC0_PREEMPT 0x0170
+#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC0_DUMMY_REG 0x0171
+#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174
+#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175
+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180
+#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181
+#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182
+#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183
+#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184
+#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185
+#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186
+#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187
+#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188
+#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189
+#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_CNTL 0x01a0
+#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_BASE 0x01a1
+#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2
+#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR 0x01a3
+#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4
+#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR 0x01a5
+#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6
+#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_CNTL 0x01aa
+#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_RPTR 0x01ab
+#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_OFFSET 0x01ac
+#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad
+#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae
+#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_SIZE 0x01af
+#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0
+#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1
+#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC1_DOORBELL 0x01b2
+#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC1_STATUS 0x01c8
+#define mmSDMA0_RLC1_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9
+#define mmSDMA0_RLC1_WATERMARK 0x01ca
+#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb
+#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc
+#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd
+#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf
+#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC1_PREEMPT 0x01d0
+#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC1_DUMMY_REG 0x01d1
+#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4
+#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5
+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0
+#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1
+#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2
+#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3
+#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4
+#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5
+#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6
+#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7
+#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8
+#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9
+#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_CNTL 0x0200
+#define mmSDMA0_RLC2_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_BASE 0x0201
+#define mmSDMA0_RLC2_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_BASE_HI 0x0202
+#define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_RPTR 0x0203
+#define mmSDMA0_RLC2_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_RPTR_HI 0x0204
+#define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_WPTR 0x0205
+#define mmSDMA0_RLC2_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_WPTR_HI 0x0206
+#define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x0207
+#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0x0208
+#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0x0209
+#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC2_IB_CNTL 0x020a
+#define mmSDMA0_RLC2_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC2_IB_RPTR 0x020b
+#define mmSDMA0_RLC2_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC2_IB_OFFSET 0x020c
+#define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC2_IB_BASE_LO 0x020d
+#define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC2_IB_BASE_HI 0x020e
+#define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC2_IB_SIZE 0x020f
+#define mmSDMA0_RLC2_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC2_SKIP_CNTL 0x0210
+#define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC2_CONTEXT_STATUS 0x0211
+#define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC2_DOORBELL 0x0212
+#define mmSDMA0_RLC2_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC2_STATUS 0x0228
+#define mmSDMA0_RLC2_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC2_DOORBELL_LOG 0x0229
+#define mmSDMA0_RLC2_WATERMARK 0x022a
+#define mmSDMA0_RLC2_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC2_DOORBELL_OFFSET 0x022b
+#define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC2_CSA_ADDR_LO 0x022c
+#define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC2_CSA_ADDR_HI 0x022d
+#define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC2_IB_SUB_REMAIN 0x022f
+#define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC2_PREEMPT 0x0230
+#define mmSDMA0_RLC2_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC2_DUMMY_REG 0x0231
+#define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0232
+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0233
+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC2_RB_AQL_CNTL 0x0234
+#define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC2_MINOR_PTR_UPDATE 0x0235
+#define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_DATA0 0x0240
+#define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_DATA1 0x0241
+#define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_DATA2 0x0242
+#define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_DATA3 0x0243
+#define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_DATA4 0x0244
+#define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_DATA5 0x0245
+#define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_DATA6 0x0246
+#define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_DATA7 0x0247
+#define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_DATA8 0x0248
+#define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC2_MIDCMD_CNTL 0x0249
+#define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_CNTL 0x0260
+#define mmSDMA0_RLC3_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_BASE 0x0261
+#define mmSDMA0_RLC3_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_BASE_HI 0x0262
+#define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_RPTR 0x0263
+#define mmSDMA0_RLC3_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_RPTR_HI 0x0264
+#define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_WPTR 0x0265
+#define mmSDMA0_RLC3_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_WPTR_HI 0x0266
+#define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x0267
+#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0268
+#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0269
+#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC3_IB_CNTL 0x026a
+#define mmSDMA0_RLC3_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC3_IB_RPTR 0x026b
+#define mmSDMA0_RLC3_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC3_IB_OFFSET 0x026c
+#define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC3_IB_BASE_LO 0x026d
+#define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC3_IB_BASE_HI 0x026e
+#define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC3_IB_SIZE 0x026f
+#define mmSDMA0_RLC3_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC3_SKIP_CNTL 0x0270
+#define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC3_CONTEXT_STATUS 0x0271
+#define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC3_DOORBELL 0x0272
+#define mmSDMA0_RLC3_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC3_STATUS 0x0288
+#define mmSDMA0_RLC3_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC3_DOORBELL_LOG 0x0289
+#define mmSDMA0_RLC3_WATERMARK 0x028a
+#define mmSDMA0_RLC3_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC3_DOORBELL_OFFSET 0x028b
+#define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC3_CSA_ADDR_LO 0x028c
+#define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC3_CSA_ADDR_HI 0x028d
+#define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC3_IB_SUB_REMAIN 0x028f
+#define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC3_PREEMPT 0x0290
+#define mmSDMA0_RLC3_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC3_DUMMY_REG 0x0291
+#define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x0292
+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x0293
+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC3_RB_AQL_CNTL 0x0294
+#define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC3_MINOR_PTR_UPDATE 0x0295
+#define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_DATA0 0x02a0
+#define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_DATA1 0x02a1
+#define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_DATA2 0x02a2
+#define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_DATA3 0x02a3
+#define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_DATA4 0x02a4
+#define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_DATA5 0x02a5
+#define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_DATA6 0x02a6
+#define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_DATA7 0x02a7
+#define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_DATA8 0x02a8
+#define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC3_MIDCMD_CNTL 0x02a9
+#define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_CNTL 0x02c0
+#define mmSDMA0_RLC4_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_BASE 0x02c1
+#define mmSDMA0_RLC4_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_BASE_HI 0x02c2
+#define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_RPTR 0x02c3
+#define mmSDMA0_RLC4_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_RPTR_HI 0x02c4
+#define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_WPTR 0x02c5
+#define mmSDMA0_RLC4_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_WPTR_HI 0x02c6
+#define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x02c7
+#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0x02c8
+#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0x02c9
+#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC4_IB_CNTL 0x02ca
+#define mmSDMA0_RLC4_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC4_IB_RPTR 0x02cb
+#define mmSDMA0_RLC4_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC4_IB_OFFSET 0x02cc
+#define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC4_IB_BASE_LO 0x02cd
+#define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC4_IB_BASE_HI 0x02ce
+#define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC4_IB_SIZE 0x02cf
+#define mmSDMA0_RLC4_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC4_SKIP_CNTL 0x02d0
+#define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC4_CONTEXT_STATUS 0x02d1
+#define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC4_DOORBELL 0x02d2
+#define mmSDMA0_RLC4_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC4_STATUS 0x02e8
+#define mmSDMA0_RLC4_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC4_DOORBELL_LOG 0x02e9
+#define mmSDMA0_RLC4_WATERMARK 0x02ea
+#define mmSDMA0_RLC4_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC4_DOORBELL_OFFSET 0x02eb
+#define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC4_CSA_ADDR_LO 0x02ec
+#define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC4_CSA_ADDR_HI 0x02ed
+#define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC4_IB_SUB_REMAIN 0x02ef
+#define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC4_PREEMPT 0x02f0
+#define mmSDMA0_RLC4_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC4_DUMMY_REG 0x02f1
+#define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02f2
+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02f3
+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC4_RB_AQL_CNTL 0x02f4
+#define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC4_MINOR_PTR_UPDATE 0x02f5
+#define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_DATA0 0x0300
+#define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_DATA1 0x0301
+#define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_DATA2 0x0302
+#define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_DATA3 0x0303
+#define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_DATA4 0x0304
+#define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_DATA5 0x0305
+#define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_DATA6 0x0306
+#define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_DATA7 0x0307
+#define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_DATA8 0x0308
+#define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC4_MIDCMD_CNTL 0x0309
+#define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_CNTL 0x0320
+#define mmSDMA0_RLC5_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_BASE 0x0321
+#define mmSDMA0_RLC5_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_BASE_HI 0x0322
+#define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_RPTR 0x0323
+#define mmSDMA0_RLC5_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_RPTR_HI 0x0324
+#define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_WPTR 0x0325
+#define mmSDMA0_RLC5_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_WPTR_HI 0x0326
+#define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x0327
+#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0x0328
+#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0x0329
+#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC5_IB_CNTL 0x032a
+#define mmSDMA0_RLC5_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC5_IB_RPTR 0x032b
+#define mmSDMA0_RLC5_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC5_IB_OFFSET 0x032c
+#define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC5_IB_BASE_LO 0x032d
+#define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC5_IB_BASE_HI 0x032e
+#define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC5_IB_SIZE 0x032f
+#define mmSDMA0_RLC5_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC5_SKIP_CNTL 0x0330
+#define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC5_CONTEXT_STATUS 0x0331
+#define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC5_DOORBELL 0x0332
+#define mmSDMA0_RLC5_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC5_STATUS 0x0348
+#define mmSDMA0_RLC5_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC5_DOORBELL_LOG 0x0349
+#define mmSDMA0_RLC5_WATERMARK 0x034a
+#define mmSDMA0_RLC5_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC5_DOORBELL_OFFSET 0x034b
+#define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC5_CSA_ADDR_LO 0x034c
+#define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC5_CSA_ADDR_HI 0x034d
+#define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC5_IB_SUB_REMAIN 0x034f
+#define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC5_PREEMPT 0x0350
+#define mmSDMA0_RLC5_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC5_DUMMY_REG 0x0351
+#define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x0352
+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x0353
+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC5_RB_AQL_CNTL 0x0354
+#define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC5_MINOR_PTR_UPDATE 0x0355
+#define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_DATA0 0x0360
+#define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_DATA1 0x0361
+#define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_DATA2 0x0362
+#define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_DATA3 0x0363
+#define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_DATA4 0x0364
+#define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_DATA5 0x0365
+#define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_DATA6 0x0366
+#define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_DATA7 0x0367
+#define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_DATA8 0x0368
+#define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC5_MIDCMD_CNTL 0x0369
+#define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_CNTL 0x0380
+#define mmSDMA0_RLC6_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_BASE 0x0381
+#define mmSDMA0_RLC6_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_BASE_HI 0x0382
+#define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_RPTR 0x0383
+#define mmSDMA0_RLC6_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_RPTR_HI 0x0384
+#define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_WPTR 0x0385
+#define mmSDMA0_RLC6_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_WPTR_HI 0x0386
+#define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0387
+#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0388
+#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0389
+#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC6_IB_CNTL 0x038a
+#define mmSDMA0_RLC6_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC6_IB_RPTR 0x038b
+#define mmSDMA0_RLC6_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC6_IB_OFFSET 0x038c
+#define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC6_IB_BASE_LO 0x038d
+#define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC6_IB_BASE_HI 0x038e
+#define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC6_IB_SIZE 0x038f
+#define mmSDMA0_RLC6_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC6_SKIP_CNTL 0x0390
+#define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC6_CONTEXT_STATUS 0x0391
+#define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC6_DOORBELL 0x0392
+#define mmSDMA0_RLC6_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC6_STATUS 0x03a8
+#define mmSDMA0_RLC6_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC6_DOORBELL_LOG 0x03a9
+#define mmSDMA0_RLC6_WATERMARK 0x03aa
+#define mmSDMA0_RLC6_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC6_DOORBELL_OFFSET 0x03ab
+#define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC6_CSA_ADDR_LO 0x03ac
+#define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC6_CSA_ADDR_HI 0x03ad
+#define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC6_IB_SUB_REMAIN 0x03af
+#define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC6_PREEMPT 0x03b0
+#define mmSDMA0_RLC6_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC6_DUMMY_REG 0x03b1
+#define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x03b2
+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x03b3
+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC6_RB_AQL_CNTL 0x03b4
+#define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC6_MINOR_PTR_UPDATE 0x03b5
+#define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_DATA0 0x03c0
+#define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_DATA1 0x03c1
+#define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_DATA2 0x03c2
+#define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_DATA3 0x03c3
+#define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_DATA4 0x03c4
+#define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_DATA5 0x03c5
+#define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_DATA6 0x03c6
+#define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_DATA7 0x03c7
+#define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_DATA8 0x03c8
+#define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC6_MIDCMD_CNTL 0x03c9
+#define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_CNTL 0x03e0
+#define mmSDMA0_RLC7_RB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_BASE 0x03e1
+#define mmSDMA0_RLC7_RB_BASE_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_BASE_HI 0x03e2
+#define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_RPTR 0x03e3
+#define mmSDMA0_RLC7_RB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_RPTR_HI 0x03e4
+#define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_WPTR 0x03e5
+#define mmSDMA0_RLC7_RB_WPTR_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_WPTR_HI 0x03e6
+#define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x03e7
+#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03e8
+#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03e9
+#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC7_IB_CNTL 0x03ea
+#define mmSDMA0_RLC7_IB_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC7_IB_RPTR 0x03eb
+#define mmSDMA0_RLC7_IB_RPTR_BASE_IDX 0
+#define mmSDMA0_RLC7_IB_OFFSET 0x03ec
+#define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC7_IB_BASE_LO 0x03ed
+#define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA0_RLC7_IB_BASE_HI 0x03ee
+#define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA0_RLC7_IB_SIZE 0x03ef
+#define mmSDMA0_RLC7_IB_SIZE_BASE_IDX 0
+#define mmSDMA0_RLC7_SKIP_CNTL 0x03f0
+#define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC7_CONTEXT_STATUS 0x03f1
+#define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC7_DOORBELL 0x03f2
+#define mmSDMA0_RLC7_DOORBELL_BASE_IDX 0
+#define mmSDMA0_RLC7_STATUS 0x0408
+#define mmSDMA0_RLC7_STATUS_BASE_IDX 0
+#define mmSDMA0_RLC7_DOORBELL_LOG 0x0409
+#define mmSDMA0_RLC7_WATERMARK 0x040a
+#define mmSDMA0_RLC7_WATERMARK_BASE_IDX 0
+#define mmSDMA0_RLC7_DOORBELL_OFFSET 0x040b
+#define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA0_RLC7_CSA_ADDR_LO 0x040c
+#define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC7_CSA_ADDR_HI 0x040d
+#define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC7_IB_SUB_REMAIN 0x040f
+#define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA0_RLC7_PREEMPT 0x0410
+#define mmSDMA0_RLC7_PREEMPT_BASE_IDX 0
+#define mmSDMA0_RLC7_DUMMY_REG 0x0411
+#define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x0412
+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x0413
+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA0_RLC7_RB_AQL_CNTL 0x0414
+#define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA0_RLC7_MINOR_PTR_UPDATE 0x0415
+#define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_DATA0 0x0420
+#define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_DATA1 0x0421
+#define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_DATA2 0x0422
+#define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_DATA3 0x0423
+#define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_DATA4 0x0424
+#define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_DATA5 0x0425
+#define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_DATA6 0x0426
+#define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_DATA7 0x0427
+#define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_DATA8 0x0428
+#define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA0_RLC7_MIDCMD_CNTL 0x0429
+#define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0
+
+
+// addressBlock: gc_sdma1_sdma1dec
+// base address: 0x6180
+#define mmSDMA1_DEC_START 0x0600
+#define mmSDMA1_DEC_START_BASE_IDX 0
+#define mmSDMA1_PG_CNTL 0x0616
+#define mmSDMA1_PG_CNTL_BASE_IDX 0
+#define mmSDMA1_PG_CTX_LO 0x0617
+#define mmSDMA1_PG_CTX_LO_BASE_IDX 0
+#define mmSDMA1_PG_CTX_HI 0x0618
+#define mmSDMA1_PG_CTX_HI_BASE_IDX 0
+#define mmSDMA1_PG_CTX_CNTL 0x0619
+#define mmSDMA1_PG_CTX_CNTL_BASE_IDX 0
+#define mmSDMA1_POWER_CNTL 0x061a
+#define mmSDMA1_POWER_CNTL_BASE_IDX 0
+#define mmSDMA1_CLK_CTRL 0x061b
+#define mmSDMA1_CLK_CTRL_BASE_IDX 0
+#define mmSDMA1_CNTL 0x061c
+#define mmSDMA1_CNTL_BASE_IDX 0
+#define mmSDMA1_CHICKEN_BITS 0x061d
+#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0
+#define mmSDMA1_GB_ADDR_CONFIG 0x061e
+#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0
+#define mmSDMA1_GB_ADDR_CONFIG_READ 0x061f
+#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0
+#define mmSDMA1_RB_RPTR_FETCH_HI 0x0620
+#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0621
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
+#define mmSDMA1_RB_RPTR_FETCH 0x0622
+#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0
+#define mmSDMA1_IB_OFFSET_FETCH 0x0623
+#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0
+#define mmSDMA1_PROGRAM 0x0624
+#define mmSDMA1_PROGRAM_BASE_IDX 0
+#define mmSDMA1_STATUS_REG 0x0625
+#define mmSDMA1_STATUS_REG_BASE_IDX 0
+#define mmSDMA1_STATUS1_REG 0x0626
+#define mmSDMA1_STATUS1_REG_BASE_IDX 0
+#define mmSDMA1_RD_BURST_CNTL 0x0627
+#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0
+#define mmSDMA1_HBM_PAGE_CONFIG 0x0628
+#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0
+#define mmSDMA1_UCODE_CHECKSUM 0x0629
+#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0
+#define mmSDMA1_F32_CNTL 0x062a
+#define mmSDMA1_F32_CNTL_BASE_IDX 0
+#define mmSDMA1_FREEZE 0x062b
+#define mmSDMA1_FREEZE_BASE_IDX 0
+#define mmSDMA1_PHASE0_QUANTUM 0x062c
+#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0
+#define mmSDMA1_PHASE1_QUANTUM 0x062d
+#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0
+#define mmSDMA1_EDC_CONFIG 0x0632
+#define mmSDMA1_EDC_CONFIG_BASE_IDX 0
+#define mmSDMA1_BA_THRESHOLD 0x0633
+#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0
+#define mmSDMA1_ID 0x0634
+#define mmSDMA1_ID_BASE_IDX 0
+#define mmSDMA1_VERSION 0x0635
+#define mmSDMA1_VERSION_BASE_IDX 0
+#define mmSDMA1_EDC_COUNTER 0x0636
+#define mmSDMA1_EDC_COUNTER_BASE_IDX 0
+#define mmSDMA1_EDC_COUNTER_CLEAR 0x0637
+#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0
+#define mmSDMA1_STATUS2_REG 0x0638
+#define mmSDMA1_STATUS2_REG_BASE_IDX 0
+#define mmSDMA1_ATOMIC_CNTL 0x0639
+#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0
+#define mmSDMA1_ATOMIC_PREOP_LO 0x063a
+#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0
+#define mmSDMA1_ATOMIC_PREOP_HI 0x063b
+#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0
+#define mmSDMA1_UTCL1_CNTL 0x063c
+#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0
+#define mmSDMA1_UTCL1_WATERMK 0x063d
+#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0
+#define mmSDMA1_UTCL1_RD_STATUS 0x063e
+#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0
+#define mmSDMA1_UTCL1_WR_STATUS 0x063f
+#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0
+#define mmSDMA1_UTCL1_INV0 0x0640
+#define mmSDMA1_UTCL1_INV0_BASE_IDX 0
+#define mmSDMA1_UTCL1_INV1 0x0641
+#define mmSDMA1_UTCL1_INV1_BASE_IDX 0
+#define mmSDMA1_UTCL1_INV2 0x0642
+#define mmSDMA1_UTCL1_INV2_BASE_IDX 0
+#define mmSDMA1_UTCL1_RD_XNACK0 0x0643
+#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0
+#define mmSDMA1_UTCL1_RD_XNACK1 0x0644
+#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0
+#define mmSDMA1_UTCL1_WR_XNACK0 0x0645
+#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0
+#define mmSDMA1_UTCL1_WR_XNACK1 0x0646
+#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0
+#define mmSDMA1_UTCL1_TIMEOUT 0x0647
+#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0
+#define mmSDMA1_UTCL1_PAGE 0x0648
+#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0
+#define mmSDMA1_POWER_CNTL_IDLE 0x0649
+#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0
+#define mmSDMA1_RELAX_ORDERING_LUT 0x064a
+#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0
+#define mmSDMA1_CHICKEN_BITS_2 0x064b
+#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0
+#define mmSDMA1_STATUS3_REG 0x064c
+#define mmSDMA1_STATUS3_REG_BASE_IDX 0
+#define mmSDMA1_PHYSICAL_ADDR_LO 0x064d
+#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PHYSICAL_ADDR_HI 0x064e
+#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PHASE2_QUANTUM 0x064f
+#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0
+#define mmSDMA1_ERROR_LOG 0x0650
+#define mmSDMA1_ERROR_LOG_BASE_IDX 0
+#define mmSDMA1_PUB_DUMMY_REG0 0x0651
+#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0
+#define mmSDMA1_F32_COUNTER 0x0655
+#define mmSDMA1_F32_COUNTER_BASE_IDX 0
+#define mmSDMA1_PERFMON_CNTL 0x0657
+#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER0_RESULT 0x0658
+#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER1_RESULT 0x0659
+#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x065a
+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0
+#define mmSDMA1_CRD_CNTL 0x065b
+#define mmSDMA1_CRD_CNTL_BASE_IDX 0
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x065d
+#define mmSDMA1_AQL_STATUS 0x065f
+#define mmSDMA1_AQL_STATUS_BASE_IDX 0
+#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0660
+#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0
+#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0661
+#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0
+#define mmSDMA1_TLBI_GCR_CNTL 0x0662
+#define mmSDMA1_TLBI_GCR_CNTL_BASE_IDX 0
+#define mmSDMA1_TILING_CONFIG 0x0663
+#define mmSDMA1_TILING_CONFIG_BASE_IDX 0
+#define mmSDMA1_HASH 0x0664
+#define mmSDMA1_HASH_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER0_SELECT 0x0668
+#define mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER0_SELECT1 0x0669
+#define mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER0_LO 0x066a
+#define mmSDMA1_PERFCOUNTER0_LO_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER0_HI 0x066b
+#define mmSDMA1_PERFCOUNTER0_HI_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER1_SELECT 0x066c
+#define mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER1_SELECT1 0x066d
+#define mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER1_LO 0x066e
+#define mmSDMA1_PERFCOUNTER1_LO_BASE_IDX 0
+#define mmSDMA1_PERFCOUNTER1_HI 0x066f
+#define mmSDMA1_PERFCOUNTER1_HI_BASE_IDX 0
+#define mmSDMA1_INT_STATUS 0x0670
+#define mmSDMA1_INT_STATUS_BASE_IDX 0
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG2 0x0671
+#define mmSDMA1_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0
+#define mmSDMA1_HOLE_ADDR_LO 0x0672
+#define mmSDMA1_HOLE_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_HOLE_ADDR_HI 0x0673
+#define mmSDMA1_HOLE_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_CNTL 0x0680
+#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_RB_BASE 0x0681
+#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0
+#define mmSDMA1_GFX_RB_BASE_HI 0x0682
+#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR 0x0683
+#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR_HI 0x0684
+#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR 0x0685
+#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_HI 0x0686
+#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0687
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0688
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0689
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_GFX_IB_CNTL 0x068a
+#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_IB_RPTR 0x068b
+#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_GFX_IB_OFFSET 0x068c
+#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_GFX_IB_BASE_LO 0x068d
+#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_GFX_IB_BASE_HI 0x068e
+#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_GFX_IB_SIZE 0x068f
+#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_GFX_SKIP_CNTL 0x0690
+#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_CONTEXT_STATUS 0x0691
+#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_GFX_DOORBELL 0x0692
+#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0
+#define mmSDMA1_GFX_CONTEXT_CNTL 0x0693
+#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_STATUS 0x06a8
+#define mmSDMA1_GFX_STATUS_BASE_IDX 0
+#define mmSDMA1_GFX_DOORBELL_LOG 0x06a9
+#define mmSDMA1_GFX_WATERMARK 0x06aa
+#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0
+#define mmSDMA1_GFX_DOORBELL_OFFSET 0x06ab
+#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_GFX_CSA_ADDR_LO 0x06ac
+#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_GFX_CSA_ADDR_HI 0x06ad
+#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_IB_SUB_REMAIN 0x06af
+#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_GFX_PREEMPT 0x06b0
+#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0
+#define mmSDMA1_GFX_DUMMY_REG 0x06b1
+#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x06b2
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x06b3
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_GFX_RB_AQL_CNTL 0x06b4
+#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x06b5
+#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA0 0x06c0
+#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA1 0x06c1
+#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA2 0x06c2
+#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA3 0x06c3
+#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA4 0x06c4
+#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA5 0x06c5
+#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA6 0x06c6
+#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA7 0x06c7
+#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_DATA8 0x06c8
+#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_GFX_MIDCMD_CNTL 0x06c9
+#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_CNTL 0x06e0
+#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_BASE 0x06e1
+#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_BASE_HI 0x06e2
+#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR 0x06e3
+#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR_HI 0x06e4
+#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR 0x06e5
+#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_HI 0x06e6
+#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x06e7
+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x06e8
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x06e9
+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_CNTL 0x06ea
+#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_RPTR 0x06eb
+#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_OFFSET 0x06ec
+#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_BASE_LO 0x06ed
+#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_BASE_HI 0x06ee
+#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_SIZE 0x06ef
+#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_PAGE_SKIP_CNTL 0x06f0
+#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_CONTEXT_STATUS 0x06f1
+#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_PAGE_DOORBELL 0x06f2
+#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0
+#define mmSDMA1_PAGE_STATUS 0x0708
+#define mmSDMA1_PAGE_STATUS_BASE_IDX 0
+#define mmSDMA1_PAGE_DOORBELL_LOG 0x0709
+#define mmSDMA1_PAGE_WATERMARK 0x070a
+#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0
+#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x070b
+#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_PAGE_CSA_ADDR_LO 0x070c
+#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_CSA_ADDR_HI 0x070d
+#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x070f
+#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_PAGE_PREEMPT 0x0710
+#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0
+#define mmSDMA1_PAGE_DUMMY_REG 0x0711
+#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0712
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0713
+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0714
+#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0715
+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0720
+#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0721
+#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0722
+#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0723
+#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0724
+#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0725
+#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0726
+#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0727
+#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0728
+#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0729
+#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_CNTL 0x0740
+#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_BASE 0x0741
+#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_BASE_HI 0x0742
+#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR 0x0743
+#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR_HI 0x0744
+#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR 0x0745
+#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_HI 0x0746
+#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0747
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0748
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0749
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_CNTL 0x074a
+#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_RPTR 0x074b
+#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_OFFSET 0x074c
+#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_BASE_LO 0x074d
+#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_BASE_HI 0x074e
+#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_SIZE 0x074f
+#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC0_SKIP_CNTL 0x0750
+#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0751
+#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC0_DOORBELL 0x0752
+#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC0_STATUS 0x0768
+#define mmSDMA1_RLC0_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC0_DOORBELL_LOG 0x0769
+#define mmSDMA1_RLC0_WATERMARK 0x076a
+#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x076b
+#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC0_CSA_ADDR_LO 0x076c
+#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_CSA_ADDR_HI 0x076d
+#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x076f
+#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC0_PREEMPT 0x0770
+#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC0_DUMMY_REG 0x0771
+#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0772
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0773
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0774
+#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0775
+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0780
+#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0781
+#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0782
+#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0783
+#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0784
+#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0785
+#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0786
+#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0787
+#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0788
+#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0789
+#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_CNTL 0x07a0
+#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_BASE 0x07a1
+#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_BASE_HI 0x07a2
+#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR 0x07a3
+#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR_HI 0x07a4
+#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR 0x07a5
+#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_HI 0x07a6
+#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x07a7
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x07a8
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x07a9
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_CNTL 0x07aa
+#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_RPTR 0x07ab
+#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_OFFSET 0x07ac
+#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_BASE_LO 0x07ad
+#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_BASE_HI 0x07ae
+#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_SIZE 0x07af
+#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC1_SKIP_CNTL 0x07b0
+#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_CONTEXT_STATUS 0x07b1
+#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC1_DOORBELL 0x07b2
+#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC1_STATUS 0x07c8
+#define mmSDMA1_RLC1_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC1_DOORBELL_LOG 0x07c9
+#define mmSDMA1_RLC1_WATERMARK 0x07ca
+#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x07cb
+#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC1_CSA_ADDR_LO 0x07cc
+#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_CSA_ADDR_HI 0x07cd
+#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x07cf
+#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC1_PREEMPT 0x07d0
+#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC1_DUMMY_REG 0x07d1
+#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x07d2
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x07d3
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC1_RB_AQL_CNTL 0x07d4
+#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x07d5
+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA0 0x07e0
+#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA1 0x07e1
+#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA2 0x07e2
+#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA3 0x07e3
+#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA4 0x07e4
+#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA5 0x07e5
+#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA6 0x07e6
+#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA7 0x07e7
+#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_DATA8 0x07e8
+#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC1_MIDCMD_CNTL 0x07e9
+#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_CNTL 0x0800
+#define mmSDMA1_RLC2_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_BASE 0x0801
+#define mmSDMA1_RLC2_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_BASE_HI 0x0802
+#define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_RPTR 0x0803
+#define mmSDMA1_RLC2_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_RPTR_HI 0x0804
+#define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_WPTR 0x0805
+#define mmSDMA1_RLC2_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_WPTR_HI 0x0806
+#define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x0807
+#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI 0x0808
+#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO 0x0809
+#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC2_IB_CNTL 0x080a
+#define mmSDMA1_RLC2_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC2_IB_RPTR 0x080b
+#define mmSDMA1_RLC2_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC2_IB_OFFSET 0x080c
+#define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC2_IB_BASE_LO 0x080d
+#define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC2_IB_BASE_HI 0x080e
+#define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC2_IB_SIZE 0x080f
+#define mmSDMA1_RLC2_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC2_SKIP_CNTL 0x0810
+#define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC2_CONTEXT_STATUS 0x0811
+#define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC2_DOORBELL 0x0812
+#define mmSDMA1_RLC2_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC2_STATUS 0x0828
+#define mmSDMA1_RLC2_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC2_DOORBELL_LOG 0x0829
+#define mmSDMA1_RLC2_WATERMARK 0x082a
+#define mmSDMA1_RLC2_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC2_DOORBELL_OFFSET 0x082b
+#define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC2_CSA_ADDR_LO 0x082c
+#define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC2_CSA_ADDR_HI 0x082d
+#define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC2_IB_SUB_REMAIN 0x082f
+#define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC2_PREEMPT 0x0830
+#define mmSDMA1_RLC2_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC2_DUMMY_REG 0x0831
+#define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0x0832
+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0x0833
+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC2_RB_AQL_CNTL 0x0834
+#define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC2_MINOR_PTR_UPDATE 0x0835
+#define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_DATA0 0x0840
+#define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_DATA1 0x0841
+#define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_DATA2 0x0842
+#define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_DATA3 0x0843
+#define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_DATA4 0x0844
+#define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_DATA5 0x0845
+#define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_DATA6 0x0846
+#define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_DATA7 0x0847
+#define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_DATA8 0x0848
+#define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC2_MIDCMD_CNTL 0x0849
+#define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_CNTL 0x0860
+#define mmSDMA1_RLC3_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_BASE 0x0861
+#define mmSDMA1_RLC3_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_BASE_HI 0x0862
+#define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_RPTR 0x0863
+#define mmSDMA1_RLC3_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_RPTR_HI 0x0864
+#define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_WPTR 0x0865
+#define mmSDMA1_RLC3_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_WPTR_HI 0x0866
+#define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL 0x0867
+#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI 0x0868
+#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO 0x0869
+#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC3_IB_CNTL 0x086a
+#define mmSDMA1_RLC3_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC3_IB_RPTR 0x086b
+#define mmSDMA1_RLC3_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC3_IB_OFFSET 0x086c
+#define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC3_IB_BASE_LO 0x086d
+#define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC3_IB_BASE_HI 0x086e
+#define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC3_IB_SIZE 0x086f
+#define mmSDMA1_RLC3_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC3_SKIP_CNTL 0x0870
+#define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC3_CONTEXT_STATUS 0x0871
+#define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC3_DOORBELL 0x0872
+#define mmSDMA1_RLC3_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC3_STATUS 0x0888
+#define mmSDMA1_RLC3_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC3_DOORBELL_LOG 0x0889
+#define mmSDMA1_RLC3_WATERMARK 0x088a
+#define mmSDMA1_RLC3_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC3_DOORBELL_OFFSET 0x088b
+#define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC3_CSA_ADDR_LO 0x088c
+#define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC3_CSA_ADDR_HI 0x088d
+#define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC3_IB_SUB_REMAIN 0x088f
+#define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC3_PREEMPT 0x0890
+#define mmSDMA1_RLC3_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC3_DUMMY_REG 0x0891
+#define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0x0892
+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0x0893
+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC3_RB_AQL_CNTL 0x0894
+#define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC3_MINOR_PTR_UPDATE 0x0895
+#define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_DATA0 0x08a0
+#define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_DATA1 0x08a1
+#define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_DATA2 0x08a2
+#define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_DATA3 0x08a3
+#define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_DATA4 0x08a4
+#define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_DATA5 0x08a5
+#define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_DATA6 0x08a6
+#define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_DATA7 0x08a7
+#define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_DATA8 0x08a8
+#define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC3_MIDCMD_CNTL 0x08a9
+#define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_CNTL 0x08c0
+#define mmSDMA1_RLC4_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_BASE 0x08c1
+#define mmSDMA1_RLC4_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_BASE_HI 0x08c2
+#define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_RPTR 0x08c3
+#define mmSDMA1_RLC4_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_RPTR_HI 0x08c4
+#define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_WPTR 0x08c5
+#define mmSDMA1_RLC4_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_WPTR_HI 0x08c6
+#define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL 0x08c7
+#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI 0x08c8
+#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO 0x08c9
+#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC4_IB_CNTL 0x08ca
+#define mmSDMA1_RLC4_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC4_IB_RPTR 0x08cb
+#define mmSDMA1_RLC4_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC4_IB_OFFSET 0x08cc
+#define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC4_IB_BASE_LO 0x08cd
+#define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC4_IB_BASE_HI 0x08ce
+#define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC4_IB_SIZE 0x08cf
+#define mmSDMA1_RLC4_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC4_SKIP_CNTL 0x08d0
+#define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC4_CONTEXT_STATUS 0x08d1
+#define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC4_DOORBELL 0x08d2
+#define mmSDMA1_RLC4_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC4_STATUS 0x08e8
+#define mmSDMA1_RLC4_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC4_DOORBELL_LOG 0x08e9
+#define mmSDMA1_RLC4_WATERMARK 0x08ea
+#define mmSDMA1_RLC4_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC4_DOORBELL_OFFSET 0x08eb
+#define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC4_CSA_ADDR_LO 0x08ec
+#define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC4_CSA_ADDR_HI 0x08ed
+#define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC4_IB_SUB_REMAIN 0x08ef
+#define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC4_PREEMPT 0x08f0
+#define mmSDMA1_RLC4_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC4_DUMMY_REG 0x08f1
+#define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0x08f2
+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0x08f3
+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC4_RB_AQL_CNTL 0x08f4
+#define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC4_MINOR_PTR_UPDATE 0x08f5
+#define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_DATA0 0x0900
+#define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_DATA1 0x0901
+#define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_DATA2 0x0902
+#define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_DATA3 0x0903
+#define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_DATA4 0x0904
+#define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_DATA5 0x0905
+#define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_DATA6 0x0906
+#define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_DATA7 0x0907
+#define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_DATA8 0x0908
+#define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC4_MIDCMD_CNTL 0x0909
+#define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_CNTL 0x0920
+#define mmSDMA1_RLC5_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_BASE 0x0921
+#define mmSDMA1_RLC5_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_BASE_HI 0x0922
+#define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_RPTR 0x0923
+#define mmSDMA1_RLC5_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_RPTR_HI 0x0924
+#define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_WPTR 0x0925
+#define mmSDMA1_RLC5_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_WPTR_HI 0x0926
+#define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL 0x0927
+#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI 0x0928
+#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO 0x0929
+#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC5_IB_CNTL 0x092a
+#define mmSDMA1_RLC5_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC5_IB_RPTR 0x092b
+#define mmSDMA1_RLC5_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC5_IB_OFFSET 0x092c
+#define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC5_IB_BASE_LO 0x092d
+#define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC5_IB_BASE_HI 0x092e
+#define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC5_IB_SIZE 0x092f
+#define mmSDMA1_RLC5_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC5_SKIP_CNTL 0x0930
+#define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC5_CONTEXT_STATUS 0x0931
+#define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC5_DOORBELL 0x0932
+#define mmSDMA1_RLC5_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC5_STATUS 0x0948
+#define mmSDMA1_RLC5_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC5_DOORBELL_LOG 0x0949
+#define mmSDMA1_RLC5_WATERMARK 0x094a
+#define mmSDMA1_RLC5_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC5_DOORBELL_OFFSET 0x094b
+#define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC5_CSA_ADDR_LO 0x094c
+#define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC5_CSA_ADDR_HI 0x094d
+#define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC5_IB_SUB_REMAIN 0x094f
+#define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC5_PREEMPT 0x0950
+#define mmSDMA1_RLC5_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC5_DUMMY_REG 0x0951
+#define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0x0952
+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0x0953
+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC5_RB_AQL_CNTL 0x0954
+#define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC5_MINOR_PTR_UPDATE 0x0955
+#define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_DATA0 0x0960
+#define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_DATA1 0x0961
+#define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_DATA2 0x0962
+#define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_DATA3 0x0963
+#define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_DATA4 0x0964
+#define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_DATA5 0x0965
+#define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_DATA6 0x0966
+#define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_DATA7 0x0967
+#define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_DATA8 0x0968
+#define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC5_MIDCMD_CNTL 0x0969
+#define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_CNTL 0x0980
+#define mmSDMA1_RLC6_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_BASE 0x0981
+#define mmSDMA1_RLC6_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_BASE_HI 0x0982
+#define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_RPTR 0x0983
+#define mmSDMA1_RLC6_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_RPTR_HI 0x0984
+#define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_WPTR 0x0985
+#define mmSDMA1_RLC6_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_WPTR_HI 0x0986
+#define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL 0x0987
+#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI 0x0988
+#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO 0x0989
+#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC6_IB_CNTL 0x098a
+#define mmSDMA1_RLC6_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC6_IB_RPTR 0x098b
+#define mmSDMA1_RLC6_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC6_IB_OFFSET 0x098c
+#define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC6_IB_BASE_LO 0x098d
+#define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC6_IB_BASE_HI 0x098e
+#define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC6_IB_SIZE 0x098f
+#define mmSDMA1_RLC6_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC6_SKIP_CNTL 0x0990
+#define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC6_CONTEXT_STATUS 0x0991
+#define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC6_DOORBELL 0x0992
+#define mmSDMA1_RLC6_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC6_STATUS 0x09a8
+#define mmSDMA1_RLC6_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC6_DOORBELL_LOG 0x09a9
+#define mmSDMA1_RLC6_WATERMARK 0x09aa
+#define mmSDMA1_RLC6_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC6_DOORBELL_OFFSET 0x09ab
+#define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC6_CSA_ADDR_LO 0x09ac
+#define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC6_CSA_ADDR_HI 0x09ad
+#define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC6_IB_SUB_REMAIN 0x09af
+#define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC6_PREEMPT 0x09b0
+#define mmSDMA1_RLC6_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC6_DUMMY_REG 0x09b1
+#define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0x09b2
+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0x09b3
+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC6_RB_AQL_CNTL 0x09b4
+#define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC6_MINOR_PTR_UPDATE 0x09b5
+#define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_DATA0 0x09c0
+#define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_DATA1 0x09c1
+#define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_DATA2 0x09c2
+#define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_DATA3 0x09c3
+#define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_DATA4 0x09c4
+#define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_DATA5 0x09c5
+#define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_DATA6 0x09c6
+#define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_DATA7 0x09c7
+#define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_DATA8 0x09c8
+#define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC6_MIDCMD_CNTL 0x09c9
+#define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_CNTL 0x09e0
+#define mmSDMA1_RLC7_RB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_BASE 0x09e1
+#define mmSDMA1_RLC7_RB_BASE_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_BASE_HI 0x09e2
+#define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_RPTR 0x09e3
+#define mmSDMA1_RLC7_RB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_RPTR_HI 0x09e4
+#define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_WPTR 0x09e5
+#define mmSDMA1_RLC7_RB_WPTR_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_WPTR_HI 0x09e6
+#define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL 0x09e7
+#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI 0x09e8
+#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO 0x09e9
+#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC7_IB_CNTL 0x09ea
+#define mmSDMA1_RLC7_IB_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC7_IB_RPTR 0x09eb
+#define mmSDMA1_RLC7_IB_RPTR_BASE_IDX 0
+#define mmSDMA1_RLC7_IB_OFFSET 0x09ec
+#define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC7_IB_BASE_LO 0x09ed
+#define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX 0
+#define mmSDMA1_RLC7_IB_BASE_HI 0x09ee
+#define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX 0
+#define mmSDMA1_RLC7_IB_SIZE 0x09ef
+#define mmSDMA1_RLC7_IB_SIZE_BASE_IDX 0
+#define mmSDMA1_RLC7_SKIP_CNTL 0x09f0
+#define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC7_CONTEXT_STATUS 0x09f1
+#define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC7_DOORBELL 0x09f2
+#define mmSDMA1_RLC7_DOORBELL_BASE_IDX 0
+#define mmSDMA1_RLC7_STATUS 0x0a08
+#define mmSDMA1_RLC7_STATUS_BASE_IDX 0
+#define mmSDMA1_RLC7_DOORBELL_LOG 0x0a09
+#define mmSDMA1_RLC7_WATERMARK 0x0a0a
+#define mmSDMA1_RLC7_WATERMARK_BASE_IDX 0
+#define mmSDMA1_RLC7_DOORBELL_OFFSET 0x0a0b
+#define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX 0
+#define mmSDMA1_RLC7_CSA_ADDR_LO 0x0a0c
+#define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC7_CSA_ADDR_HI 0x0a0d
+#define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC7_IB_SUB_REMAIN 0x0a0f
+#define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX 0
+#define mmSDMA1_RLC7_PREEMPT 0x0a10
+#define mmSDMA1_RLC7_PREEMPT_BASE_IDX 0
+#define mmSDMA1_RLC7_DUMMY_REG 0x0a11
+#define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0x0a12
+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0x0a13
+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmSDMA1_RLC7_RB_AQL_CNTL 0x0a14
+#define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX 0
+#define mmSDMA1_RLC7_MINOR_PTR_UPDATE 0x0a15
+#define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_DATA0 0x0a20
+#define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_DATA1 0x0a21
+#define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_DATA2 0x0a22
+#define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_DATA3 0x0a23
+#define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_DATA4 0x0a24
+#define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_DATA5 0x0a25
+#define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_DATA6 0x0a26
+#define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_DATA7 0x0a27
+#define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_DATA8 0x0a28
+#define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX 0
+#define mmSDMA1_RLC7_MIDCMD_CNTL 0x0a29
+#define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX 0
+
+
+// addressBlock: gc_grbmdec
+// base address: 0x8000
+#define mmGRBM_CNTL 0x0da0
+#define mmGRBM_CNTL_BASE_IDX 0
+#define mmGRBM_SKEW_CNTL 0x0da1
+#define mmGRBM_SKEW_CNTL_BASE_IDX 0
+#define mmGRBM_STATUS2 0x0da2
+#define mmGRBM_STATUS2_BASE_IDX 0
+#define mmGRBM_PWR_CNTL 0x0da3
+#define mmGRBM_PWR_CNTL_BASE_IDX 0
+#define mmGRBM_STATUS 0x0da4
+#define mmGRBM_STATUS_BASE_IDX 0
+#define mmGRBM_STATUS_SE0 0x0da5
+#define mmGRBM_STATUS_SE0_BASE_IDX 0
+#define mmGRBM_STATUS_SE1 0x0da6
+#define mmGRBM_STATUS_SE1_BASE_IDX 0
+#define mmGRBM_STATUS3 0x0da7
+#define mmGRBM_STATUS3_BASE_IDX 0
+#define mmGRBM_SOFT_RESET 0x0da8
+#define mmGRBM_SOFT_RESET_BASE_IDX 0
+#define mmGRBM_GFX_CLKEN_CNTL 0x0dac
+#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0
+#define mmGRBM_WAIT_IDLE_CLOCKS 0x0dad
+#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0
+#define mmGRBM_STATUS_SE2 0x0dae
+#define mmGRBM_STATUS_SE2_BASE_IDX 0
+#define mmGRBM_STATUS_SE3 0x0daf
+#define mmGRBM_STATUS_SE3_BASE_IDX 0
+#define mmGRBM_PM_CNTL 0x0db0
+#define mmGRBM_PM_CNTL_BASE_IDX 0
+#define mmGRBM_READ_ERROR 0x0db6
+#define mmGRBM_READ_ERROR_BASE_IDX 0
+#define mmGRBM_READ_ERROR2 0x0db7
+#define mmGRBM_READ_ERROR2_BASE_IDX 0
+#define mmGRBM_INT_CNTL 0x0db8
+#define mmGRBM_INT_CNTL_BASE_IDX 0
+#define mmGRBM_TRAP_OP 0x0db9
+#define mmGRBM_TRAP_OP_BASE_IDX 0
+#define mmGRBM_TRAP_ADDR 0x0dba
+#define mmGRBM_TRAP_ADDR_BASE_IDX 0
+#define mmGRBM_TRAP_ADDR_MSK 0x0dbb
+#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0
+#define mmGRBM_TRAP_WD 0x0dbc
+#define mmGRBM_TRAP_WD_BASE_IDX 0
+#define mmGRBM_TRAP_WD_MSK 0x0dbd
+#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0
+#define mmGRBM_DSM_BYPASS 0x0dbe
+#define mmGRBM_DSM_BYPASS_BASE_IDX 0
+#define mmGRBM_WRITE_ERROR 0x0dbf
+#define mmGRBM_WRITE_ERROR_BASE_IDX 0
+#define mmGRBM_IOV_ERROR 0x0dc0
+#define mmGRBM_IOV_ERROR_BASE_IDX 0
+#define mmGRBM_CHIP_REVISION 0x0dc1
+#define mmGRBM_CHIP_REVISION_BASE_IDX 0
+#define mmGRBM_GFX_CNTL 0x0dc2
+#define mmGRBM_GFX_CNTL_BASE_IDX 0
+#define mmGRBM_IH_CREDIT 0x0dc4
+#define mmGRBM_IH_CREDIT_BASE_IDX 0
+#define mmGRBM_PWR_CNTL2 0x0dc5
+#define mmGRBM_PWR_CNTL2_BASE_IDX 0
+#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0dc6
+#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0
+#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0dc7
+#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0
+#define mmGRBM_IOV_READ_ERROR 0x0dc9
+#define mmGRBM_IOV_READ_ERROR_BASE_IDX 0
+#define mmGRBM_FENCE_RANGE0 0x0dca
+#define mmGRBM_FENCE_RANGE0_BASE_IDX 0
+#define mmGRBM_FENCE_RANGE1 0x0dcb
+#define mmGRBM_FENCE_RANGE1_BASE_IDX 0
+#define mmGRBM_NOWHERE 0x0ddf
+#define mmGRBM_NOWHERE_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG0 0x0de0
+#define mmGRBM_SCRATCH_REG0_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG1 0x0de1
+#define mmGRBM_SCRATCH_REG1_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG2 0x0de2
+#define mmGRBM_SCRATCH_REG2_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG3 0x0de3
+#define mmGRBM_SCRATCH_REG3_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG4 0x0de4
+#define mmGRBM_SCRATCH_REG4_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG5 0x0de5
+#define mmGRBM_SCRATCH_REG5_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG6 0x0de6
+#define mmGRBM_SCRATCH_REG6_BASE_IDX 0
+#define mmGRBM_SCRATCH_REG7 0x0de7
+#define mmGRBM_SCRATCH_REG7_BASE_IDX 0
+
+
+// addressBlock: gc_cpdec
+// base address: 0x8200
+#define mmCP_CPC_STATUS 0x0e24
+#define mmCP_CPC_STATUS_BASE_IDX 0
+#define mmCP_CPC_BUSY_STAT 0x0e25
+#define mmCP_CPC_BUSY_STAT_BASE_IDX 0
+#define mmCP_CPC_STALLED_STAT1 0x0e26
+#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0
+#define mmCP_CPF_STATUS 0x0e27
+#define mmCP_CPF_STATUS_BASE_IDX 0
+#define mmCP_CPF_BUSY_STAT 0x0e28
+#define mmCP_CPF_BUSY_STAT_BASE_IDX 0
+#define mmCP_CPF_STALLED_STAT1 0x0e29
+#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0
+#define mmCP_CPC_BUSY_STAT2 0x0e2a
+#define mmCP_CPC_BUSY_STAT2_BASE_IDX 0
+#define mmCP_CPC_GRBM_FREE_COUNT 0x0e2b
+#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0
+#define mmCP_MEC_CNTL 0x0e2d
+#define mmCP_MEC_CNTL_BASE_IDX 0
+#define mmCP_MEC_ME1_HEADER_DUMP 0x0e2e
+#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0
+#define mmCP_MEC_ME2_HEADER_DUMP 0x0e2f
+#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0
+#define mmCP_CPC_SCRATCH_INDEX 0x0e30
+#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0
+#define mmCP_CPC_SCRATCH_DATA 0x0e31
+#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0
+#define mmCP_CPF_GRBM_FREE_COUNT 0x0e32
+#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0
+#define mmCP_CPF_BUSY_STAT2 0x0e33
+#define mmCP_CPF_BUSY_STAT2_BASE_IDX 0
+#define mmCP_CPC_HALT_HYST_COUNT 0x0e47
+#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0
+#define mmCP_CE_COMPARE_COUNT 0x0e60
+#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0
+#define mmCP_CE_DE_COUNT 0x0e61
+#define mmCP_CE_DE_COUNT_BASE_IDX 0
+#define mmCP_DE_CE_COUNT 0x0e62
+#define mmCP_DE_CE_COUNT_BASE_IDX 0
+#define mmCP_DE_LAST_INVAL_COUNT 0x0e63
+#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0
+#define mmCP_DE_DE_COUNT 0x0e64
+#define mmCP_DE_DE_COUNT_BASE_IDX 0
+#define mmCP_STALLED_STAT3 0x0f3c
+#define mmCP_STALLED_STAT3_BASE_IDX 0
+#define mmCP_STALLED_STAT1 0x0f3d
+#define mmCP_STALLED_STAT1_BASE_IDX 0
+#define mmCP_STALLED_STAT2 0x0f3e
+#define mmCP_STALLED_STAT2_BASE_IDX 0
+#define mmCP_BUSY_STAT 0x0f3f
+#define mmCP_BUSY_STAT_BASE_IDX 0
+#define mmCP_STAT 0x0f40
+#define mmCP_STAT_BASE_IDX 0
+#define mmCP_ME_HEADER_DUMP 0x0f41
+#define mmCP_ME_HEADER_DUMP_BASE_IDX 0
+#define mmCP_PFP_HEADER_DUMP 0x0f42
+#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0
+#define mmCP_GRBM_FREE_COUNT 0x0f43
+#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0
+#define mmCP_CE_HEADER_DUMP 0x0f44
+#define mmCP_CE_HEADER_DUMP_BASE_IDX 0
+#define mmCP_PFP_INSTR_PNTR 0x0f45
+#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0
+#define mmCP_ME_INSTR_PNTR 0x0f46
+#define mmCP_ME_INSTR_PNTR_BASE_IDX 0
+#define mmCP_CE_INSTR_PNTR 0x0f47
+#define mmCP_CE_INSTR_PNTR_BASE_IDX 0
+#define mmCP_MEC1_INSTR_PNTR 0x0f48
+#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0
+#define mmCP_MEC2_INSTR_PNTR 0x0f49
+#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0
+#define mmCP_CSF_STAT 0x0f54
+#define mmCP_CSF_STAT_BASE_IDX 0
+#define mmCP_ME_CNTL 0x0f56
+#define mmCP_ME_CNTL_BASE_IDX 0
+#define mmCP_CNTX_STAT 0x0f58
+#define mmCP_CNTX_STAT_BASE_IDX 0
+#define mmCP_ME_PREEMPTION 0x0f59
+#define mmCP_ME_PREEMPTION_BASE_IDX 0
+#define mmCP_ROQ_THRESHOLDS 0x0f5c
+#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0
+#define mmCP_MEQ_STQ_THRESHOLD 0x0f5d
+#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0
+#define mmCP_RB2_RPTR 0x0f5e
+#define mmCP_RB2_RPTR_BASE_IDX 0
+#define mmCP_RB1_RPTR 0x0f5f
+#define mmCP_RB1_RPTR_BASE_IDX 0
+#define mmCP_RB0_RPTR 0x0f60
+#define mmCP_RB0_RPTR_BASE_IDX 0
+#define mmCP_RB_RPTR 0x0f60
+#define mmCP_RB_RPTR_BASE_IDX 0
+#define mmCP_RB_WPTR_DELAY 0x0f61
+#define mmCP_RB_WPTR_DELAY_BASE_IDX 0
+#define mmCP_RB_WPTR_POLL_CNTL 0x0f62
+#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmCP_ROQ1_THRESHOLDS 0x0f75
+#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0
+#define mmCP_ROQ2_THRESHOLDS 0x0f76
+#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0
+#define mmCP_STQ_THRESHOLDS 0x0f77
+#define mmCP_STQ_THRESHOLDS_BASE_IDX 0
+#define mmCP_QUEUE_THRESHOLDS 0x0f78
+#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0
+#define mmCP_MEQ_THRESHOLDS 0x0f79
+#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0
+#define mmCP_ROQ_AVAIL 0x0f7a
+#define mmCP_ROQ_AVAIL_BASE_IDX 0
+#define mmCP_STQ_AVAIL 0x0f7b
+#define mmCP_STQ_AVAIL_BASE_IDX 0
+#define mmCP_ROQ2_AVAIL 0x0f7c
+#define mmCP_ROQ2_AVAIL_BASE_IDX 0
+#define mmCP_MEQ_AVAIL 0x0f7d
+#define mmCP_MEQ_AVAIL_BASE_IDX 0
+#define mmCP_CMD_INDEX 0x0f7e
+#define mmCP_CMD_INDEX_BASE_IDX 0
+#define mmCP_CMD_DATA 0x0f7f
+#define mmCP_CMD_DATA_BASE_IDX 0
+#define mmCP_ROQ_RB_STAT 0x0f80
+#define mmCP_ROQ_RB_STAT_BASE_IDX 0
+#define mmCP_ROQ_IB1_STAT 0x0f81
+#define mmCP_ROQ_IB1_STAT_BASE_IDX 0
+#define mmCP_ROQ_IB2_STAT 0x0f82
+#define mmCP_ROQ_IB2_STAT_BASE_IDX 0
+#define mmCP_STQ_STAT 0x0f83
+#define mmCP_STQ_STAT_BASE_IDX 0
+#define mmCP_STQ_WR_STAT 0x0f84
+#define mmCP_STQ_WR_STAT_BASE_IDX 0
+#define mmCP_MEQ_STAT 0x0f85
+#define mmCP_MEQ_STAT_BASE_IDX 0
+#define mmCP_CEQ1_AVAIL 0x0f86
+#define mmCP_CEQ1_AVAIL_BASE_IDX 0
+#define mmCP_CEQ2_AVAIL 0x0f87
+#define mmCP_CEQ2_AVAIL_BASE_IDX 0
+#define mmCP_CE_ROQ_RB_STAT 0x0f88
+#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0
+#define mmCP_CE_ROQ_IB1_STAT 0x0f89
+#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0
+#define mmCP_CE_ROQ_IB2_STAT 0x0f8a
+#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0
+#define mmCP_CE_ROQ_DB_STAT 0x0f8b
+#define mmCP_CE_ROQ_DB_STAT_BASE_IDX 0
+#define mmCP_ROQ3_THRESHOLDS 0x0f8c
+#define mmCP_ROQ3_THRESHOLDS_BASE_IDX 0
+#define mmCP_ROQ_DB_STAT 0x0f8d
+#define mmCP_ROQ_DB_STAT_BASE_IDX 0
+
+
+// addressBlock: gc_padec
+// base address: 0x8800
+#define mmVGT_VTX_VECT_EJECT_REG 0x0fcc
+#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0
+#define mmVGT_DMA_DATA_FIFO_DEPTH 0x0fcd
+#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0
+#define mmVGT_DMA_REQ_FIFO_DEPTH 0x0fce
+#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0
+#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x0fcf
+#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0
+#define mmVGT_LAST_COPY_STATE 0x0fd0
+#define mmVGT_LAST_COPY_STATE_BASE_IDX 0
+#define mmVGT_CACHE_INVALIDATION 0x0fd1
+#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0
+#define mmVGT_ESGS_RING_SIZE 0x0fd2
+#define mmVGT_ESGS_RING_SIZE_BASE_IDX 0
+#define mmVGT_GSVS_RING_SIZE 0x0fd3
+#define mmVGT_GSVS_RING_SIZE_BASE_IDX 0
+#define mmVGT_FIFO_DEPTHS 0x0fd4
+#define mmVGT_FIFO_DEPTHS_BASE_IDX 0
+#define mmVGT_GS_VERTEX_REUSE 0x0fd5
+#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0
+#define mmVGT_MC_LAT_CNTL 0x0fd6
+#define mmVGT_MC_LAT_CNTL_BASE_IDX 0
+#define mmIA_UTCL1_STATUS_2 0x0fd7
+#define mmIA_UTCL1_STATUS_2_BASE_IDX 0
+#define mmVGT_CNTL_STATUS 0x0fdc
+#define mmVGT_CNTL_STATUS_BASE_IDX 0
+#define mmWD_CNTL_STATUS 0x0fdf
+#define mmWD_CNTL_STATUS_BASE_IDX 0
+#define mmCC_GC_PRIM_CONFIG 0x0fe0
+#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0
+#define mmGC_USER_PRIM_CONFIG 0x0fe1
+#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0
+#define mmWD_QOS 0x0fe2
+#define mmWD_QOS_BASE_IDX 0
+#define mmWD_UTCL1_CNTL 0x0fe3
+#define mmWD_UTCL1_CNTL_BASE_IDX 0
+#define mmWD_UTCL1_STATUS 0x0fe4
+#define mmWD_UTCL1_STATUS_BASE_IDX 0
+#define mmGE_PC_CNTL 0x0fe5
+#define mmGE_PC_CNTL_BASE_IDX 0
+#define mmIA_UTCL1_CNTL 0x0fe6
+#define mmIA_UTCL1_CNTL_BASE_IDX 0
+#define mmIA_UTCL1_STATUS 0x0fe7
+#define mmIA_UTCL1_STATUS_BASE_IDX 0
+#define mmGE_FAST_CLKS 0x0fe8
+#define mmGE_FAST_CLKS_BASE_IDX 0
+#define mmVGT_TF_RING_SIZE 0x1002
+#define mmVGT_TF_RING_SIZE_BASE_IDX 0
+#define mmVGT_SYS_CONFIG 0x1003
+#define mmVGT_SYS_CONFIG_BASE_IDX 0
+#define mmGE_PRIV_CONTROL 0x1004
+#define mmGE_PRIV_CONTROL_BASE_IDX 0
+#define mmGE_STATUS 0x1005
+#define mmGE_STATUS_BASE_IDX 0
+#define mmVGT_VS_MAX_WAVE_ID 0x1008
+#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0
+#define mmVGT_GS_MAX_WAVE_ID 0x1009
+#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0
+#define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0 0x100b
+#define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX 0
+#define mmVGT_HS_OFFCHIP_PARAM 0x100c
+#define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX 0
+#define mmGFX_PIPE_CONTROL 0x100d
+#define mmGFX_PIPE_CONTROL_BASE_IDX 0
+#define mmVGT_TF_MEMORY_BASE 0x100e
+#define mmVGT_TF_MEMORY_BASE_BASE_IDX 0
+#define mmCC_GC_SHADER_ARRAY_CONFIG 0x100f
+#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0
+#define mmGC_USER_SHADER_ARRAY_CONFIG 0x1010
+#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0
+#define mmVGT_DMA_PRIMITIVE_TYPE 0x1011
+#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0
+#define mmVGT_DMA_CONTROL 0x1012
+#define mmVGT_DMA_CONTROL_BASE_IDX 0
+#define mmVGT_DMA_LS_HS_CONFIG 0x1013
+#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0
+#define mmVGT_STRMOUT_DELAY 0x1015
+#define mmVGT_STRMOUT_DELAY_BASE_IDX 0
+#define mmWD_BUF_RESOURCE_1 0x1016
+#define mmWD_BUF_RESOURCE_1_BASE_IDX 0
+#define mmWD_BUF_RESOURCE_2 0x1017
+#define mmWD_BUF_RESOURCE_2_BASE_IDX 0
+#define mmVGT_TF_MEMORY_BASE_HI 0x1018
+#define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX 0
+#define mmPA_CL_CNTL_STATUS 0x1024
+#define mmPA_CL_CNTL_STATUS_BASE_IDX 0
+#define mmPA_CL_ENHANCE 0x1025
+#define mmPA_CL_ENHANCE_BASE_IDX 0
+#define mmPA_SU_CNTL_STATUS 0x1034
+#define mmPA_SU_CNTL_STATUS_BASE_IDX 0
+#define mmPA_SC_FIFO_DEPTH_CNTL 0x1035
+#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x1060
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x1061
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x1062
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
+#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x1069
+#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0
+#define mmPA_SC_BINNER_EVENT_CNTL_0 0x106c
+#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0
+#define mmPA_SC_BINNER_EVENT_CNTL_1 0x106d
+#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0
+#define mmPA_SC_BINNER_EVENT_CNTL_2 0x106e
+#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0
+#define mmPA_SC_BINNER_EVENT_CNTL_3 0x106f
+#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0
+#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x1070
+#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0
+#define mmPA_SC_BINNER_PERF_CNTL_0 0x1071
+#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0
+#define mmPA_SC_BINNER_PERF_CNTL_1 0x1072
+#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0
+#define mmPA_SC_BINNER_PERF_CNTL_2 0x1073
+#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0
+#define mmPA_SC_BINNER_PERF_CNTL_3 0x1074
+#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0
+#define mmPA_SC_ENHANCE_2 0x107c
+#define mmPA_SC_ENHANCE_2_BASE_IDX 0
+#define mmPA_SC_ENHANCE_INTERNAL 0x107d
+#define mmPA_SC_ENHANCE_INTERNAL_BASE_IDX 0
+#define mmPA_SC_BINNER_CNTL_OVERRIDE 0x107e
+#define mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX 0
+#define mmPA_SC_PBB_OVERRIDE_FLAG 0x107f
+#define mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX 0
+#define mmPA_PH_INTERFACE_FIFO_SIZE 0x1080
+#define mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX 0
+#define mmPA_PH_ENHANCE 0x1081
+#define mmPA_PH_ENHANCE_BASE_IDX 0
+#define mmPA_SC_BC_WAVE_BREAK 0x1084
+#define mmPA_SC_BC_WAVE_BREAK_BASE_IDX 0
+#define mmPA_SC_FIFO_SIZE 0x1093
+#define mmPA_SC_FIFO_SIZE_BASE_IDX 0
+#define mmPA_SC_IF_FIFO_SIZE 0x1095
+#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0
+#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x1098
+#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0
+#define mmPA_SIDEBAND_REQUEST_DELAYS 0x109b
+#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0
+#define mmPA_SC_ENHANCE 0x109c
+#define mmPA_SC_ENHANCE_BASE_IDX 0
+#define mmPA_SC_ENHANCE_1 0x109d
+#define mmPA_SC_ENHANCE_1_BASE_IDX 0
+#define mmPA_SC_DSM_CNTL 0x109e
+#define mmPA_SC_DSM_CNTL_BASE_IDX 0
+#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x109f
+#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0
+
+
+// addressBlock: gc_sqdec
+// base address: 0x8c00
+#define mmSQ_CONFIG 0x10a0
+#define mmSQ_CONFIG_BASE_IDX 0
+#define mmSQC_CONFIG 0x10a1
+#define mmSQC_CONFIG_BASE_IDX 0
+#define mmLDS_CONFIG 0x10a2
+#define mmLDS_CONFIG_BASE_IDX 0
+#define mmSQ_RANDOM_WAVE_PRI 0x10a3
+#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0
+#define mmSQG_STATUS 0x10a4
+#define mmSQG_STATUS_BASE_IDX 0
+#define mmSQ_FIFO_SIZES 0x10a5
+#define mmSQ_FIFO_SIZES_BASE_IDX 0
+#define mmSQ_DSM_CNTL 0x10a6
+#define mmSQ_DSM_CNTL_BASE_IDX 0
+#define mmSQ_DSM_CNTL2 0x10a7
+#define mmSQ_DSM_CNTL2_BASE_IDX 0
+#define mmSQ_RUNTIME_CONFIG 0x10a8
+#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0
+#define mmSH_MEM_BASES 0x10aa
+#define mmSH_MEM_BASES_BASE_IDX 0
+#define mmSP_CONFIG 0x10ab
+#define mmSP_CONFIG_BASE_IDX 0
+#define mmSQ_ARB_CONFIG 0x10ac
+#define mmSQ_ARB_CONFIG_BASE_IDX 0
+#define mmSH_MEM_CONFIG 0x10ad
+#define mmSH_MEM_CONFIG_BASE_IDX 0
+#define mmCC_GC_SHADER_RATE_CONFIG 0x10b2
+#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0
+#define mmGC_USER_SHADER_RATE_CONFIG 0x10b3
+#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0
+#define mmSQ_INTERRUPT_AUTO_MASK 0x10b4
+#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0
+#define mmSQ_INTERRUPT_MSG_CTRL 0x10b5
+#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0
+#define mmSQG_UTCL0_CNTL1 0x10b7
+#define mmSQG_UTCL0_CNTL1_BASE_IDX 0
+#define mmSQG_UTCL0_CNTL2 0x10b8
+#define mmSQG_UTCL0_CNTL2_BASE_IDX 0
+#define mmSQG_UTCL0_STATUS 0x10b9
+#define mmSQG_UTCL0_STATUS_BASE_IDX 0
+#define mmSQG_CONFIG 0x10ba
+#define mmSQG_CONFIG_BASE_IDX 0
+#define mmSQ_SHADER_TBA_LO 0x10bc
+#define mmSQ_SHADER_TBA_LO_BASE_IDX 0
+#define mmSQ_SHADER_TBA_HI 0x10bd
+#define mmSQ_SHADER_TBA_HI_BASE_IDX 0
+#define mmSQ_SHADER_TMA_LO 0x10be
+#define mmSQ_SHADER_TMA_LO_BASE_IDX 0
+#define mmSQ_SHADER_TMA_HI 0x10bf
+#define mmSQ_SHADER_TMA_HI_BASE_IDX 0
+#define mmSQ_WATCH0_ADDR_H 0x10d0
+#define mmSQ_WATCH0_ADDR_H_BASE_IDX 0
+#define mmSQ_WATCH0_ADDR_L 0x10d1
+#define mmSQ_WATCH0_ADDR_L_BASE_IDX 0
+#define mmSQ_WATCH0_CNTL 0x10d2
+#define mmSQ_WATCH0_CNTL_BASE_IDX 0
+#define mmSQ_WATCH1_ADDR_H 0x10d3
+#define mmSQ_WATCH1_ADDR_H_BASE_IDX 0
+#define mmSQ_WATCH1_ADDR_L 0x10d4
+#define mmSQ_WATCH1_ADDR_L_BASE_IDX 0
+#define mmSQ_WATCH1_CNTL 0x10d5
+#define mmSQ_WATCH1_CNTL_BASE_IDX 0
+#define mmSQ_WATCH2_ADDR_H 0x10d6
+#define mmSQ_WATCH2_ADDR_H_BASE_IDX 0
+#define mmSQ_WATCH2_ADDR_L 0x10d7
+#define mmSQ_WATCH2_ADDR_L_BASE_IDX 0
+#define mmSQ_WATCH2_CNTL 0x10d8
+#define mmSQ_WATCH2_CNTL_BASE_IDX 0
+#define mmSQ_WATCH3_ADDR_H 0x10d9
+#define mmSQ_WATCH3_ADDR_H_BASE_IDX 0
+#define mmSQ_WATCH3_ADDR_L 0x10da
+#define mmSQ_WATCH3_ADDR_L_BASE_IDX 0
+#define mmSQ_WATCH3_CNTL 0x10db
+#define mmSQ_WATCH3_CNTL_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_BUF0_BASE 0x10e0
+#define mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_BUF0_SIZE 0x10e1
+#define mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_BUF1_BASE 0x10e2
+#define mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_BUF1_SIZE 0x10e3
+#define mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_WPTR 0x10e4
+#define mmSQ_THREAD_TRACE_WPTR_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_MASK 0x10e5
+#define mmSQ_THREAD_TRACE_MASK_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x10e6
+#define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_CTRL 0x10e7
+#define mmSQ_THREAD_TRACE_CTRL_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_STATUS 0x10e8
+#define mmSQ_THREAD_TRACE_STATUS_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_DROPPED_CNTR 0x10e9
+#define mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR 0x10eb
+#define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR 0x10ec
+#define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR 0x10ed
+#define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX 0
+#define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR 0x10ee
+#define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX 0
+#define mmSQ_IND_INDEX 0x1118
+#define mmSQ_IND_INDEX_BASE_IDX 0
+#define mmSQ_IND_DATA 0x1119
+#define mmSQ_IND_DATA_BASE_IDX 0
+#define mmSQ_CMD 0x111b
+#define mmSQ_CMD_BASE_IDX 0
+#define mmSQ_TIME_HI 0x111c
+#define mmSQ_TIME_HI_BASE_IDX 0
+#define mmSQ_TIME_LO 0x111d
+#define mmSQ_TIME_LO_BASE_IDX 0
+#define mmSQ_LB_CTR_CTRL 0x1138
+#define mmSQ_LB_CTR_CTRL_BASE_IDX 0
+#define mmSQ_LB_DATA0 0x1139
+#define mmSQ_LB_DATA0_BASE_IDX 0
+#define mmSQ_LB_DATA1 0x113a
+#define mmSQ_LB_DATA1_BASE_IDX 0
+#define mmSQ_LB_DATA2 0x113b
+#define mmSQ_LB_DATA2_BASE_IDX 0
+#define mmSQ_LB_DATA3 0x113c
+#define mmSQ_LB_DATA3_BASE_IDX 0
+#define mmSQ_LB_CTR_SEL0 0x113d
+#define mmSQ_LB_CTR_SEL0_BASE_IDX 0
+#define mmSQ_LB_CTR_SEL1 0x113e
+#define mmSQ_LB_CTR_SEL1_BASE_IDX 0
+#define mmSQ_EDC_CNT 0x1146
+#define mmSQ_EDC_CNT_BASE_IDX 0
+#define mmSQ_EDC_FUE_CNTL 0x1147
+#define mmSQ_EDC_FUE_CNTL_BASE_IDX 0
+#define mmSQ_WREXEC_EXEC_HI 0x1151
+#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0
+#define mmSQ_WREXEC_EXEC_LO 0x1151
+#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0
+#define mmSQC_ICACHE_UTCL0_CNTL1 0x1173
+#define mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX 0
+#define mmSQC_ICACHE_UTCL0_CNTL2 0x1174
+#define mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX 0
+#define mmSQC_DCACHE_UTCL0_CNTL1 0x1175
+#define mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX 0
+#define mmSQC_DCACHE_UTCL0_CNTL2 0x1176
+#define mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX 0
+#define mmSQC_ICACHE_UTCL0_STATUS 0x1177
+#define mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX 0
+#define mmSQC_DCACHE_UTCL0_STATUS 0x1178
+#define mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX 0
+#define mmSQC_MISC_CONFIG 0x1179
+#define mmSQC_MISC_CONFIG_BASE_IDX 0
+
+
+// addressBlock: gc_shsdec
+// base address: 0x9000
+#define mmSX_DEBUG_1 0x11b8
+#define mmSX_DEBUG_1_BASE_IDX 0
+#define mmSPI_PS_MAX_WAVE_ID 0x11da
+#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0
+#define mmSPI_START_PHASE 0x11db
+#define mmSPI_START_PHASE_BASE_IDX 0
+#define mmSPI_GFX_CNTL 0x11dc
+#define mmSPI_GFX_CNTL_BASE_IDX 0
+#define mmSPI_USER_ACCUM_VMID_CNTL 0x11df
+#define mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX 0
+#define mmSPI_CONFIG_CNTL 0x11e0
+#define mmSPI_CONFIG_CNTL_BASE_IDX 0
+#define mmSPI_DSM_CNTL 0x11e3
+#define mmSPI_DSM_CNTL_BASE_IDX 0
+#define mmSPI_DSM_CNTL2 0x11e4
+#define mmSPI_DSM_CNTL2_BASE_IDX 0
+#define mmSPI_EDC_CNT 0x11e5
+#define mmSPI_EDC_CNT_BASE_IDX 0
+#define mmSPI_WAVE_LIMIT_CNTL 0x11ed
+#define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX 0
+#define mmSPI_CONFIG_CNTL_2 0x11ee
+#define mmSPI_CONFIG_CNTL_2_BASE_IDX 0
+#define mmSPI_CONFIG_CNTL_1 0x11ef
+#define mmSPI_CONFIG_CNTL_1_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_CNTL 0x124a
+#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_0 0x124b
+#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_1 0x124c
+#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_2 0x124d
+#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_3 0x124e
+#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_4 0x124f
+#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_5 0x1250
+#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_6 0x1251
+#define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_7 0x1252
+#define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_8 0x1253
+#define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_LIMIT_9 0x1254
+#define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_0 0x1255
+#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_1 0x1256
+#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_2 0x1257
+#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_3 0x1258
+#define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_4 0x1259
+#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_5 0x125a
+#define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_6 0x125b
+#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_7 0x125c
+#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_8 0x125d
+#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_9 0x125e
+#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_10 0x125f
+#define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_11 0x1260
+#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_12 0x1261
+#define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_13 0x1262
+#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_14 0x1263
+#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_15 0x1264
+#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_16 0x1265
+#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_17 0x1266
+#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_18 0x1267
+#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_19 0x1268
+#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0
+#define mmSPI_WF_LIFETIME_STATUS_20 0x1269
+#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0
+#define mmSPI_LB_CTR_CTRL 0x1274
+#define mmSPI_LB_CTR_CTRL_BASE_IDX 0
+#define mmSPI_LB_WGP_MASK 0x1275
+#define mmSPI_LB_WGP_MASK_BASE_IDX 0
+#define mmSPI_LB_DATA_REG 0x1276
+#define mmSPI_LB_DATA_REG_BASE_IDX 0
+#define mmSPI_PG_ENABLE_STATIC_WGP_MASK 0x1277
+#define mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX 0
+#define mmSPI_GDS_CREDITS 0x1278
+#define mmSPI_GDS_CREDITS_BASE_IDX 0
+#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x1279
+#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x127a
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x127b
+#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x127c
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x127d
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x127e
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x127f
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x1280
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x1281
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x1282
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x1283
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0
+#define mmSPI_LB_DATA_WAVES 0x1284
+#define mmSPI_LB_DATA_WAVES_BASE_IDX 0
+#define mmSPI_LB_DATA_PERWGP_WAVE_HSGS 0x1285
+#define mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX 0
+#define mmSPI_LB_DATA_PERWGP_WAVE_VSPS 0x1286
+#define mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX 0
+#define mmSPI_LB_DATA_PERWGP_WAVE_CS 0x1287
+#define mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x128c
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x128d
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x128e
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x128f
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x1290
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x1291
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x1292
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x1293
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x1294
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x1295
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
+
+
+// addressBlock: gc_tpdec
+// base address: 0x9400
+#define mmTD_CNTL 0x12c5
+#define mmTD_CNTL_BASE_IDX 0
+#define mmTD_STATUS 0x12c6
+#define mmTD_STATUS_BASE_IDX 0
+#define mmTD_POWER_CNTL 0x12ca
+#define mmTD_POWER_CNTL_BASE_IDX 0
+#define mmTD_DSM_CNTL 0x12cf
+#define mmTD_DSM_CNTL_BASE_IDX 0
+#define mmTD_DSM_CNTL2 0x12d0
+#define mmTD_DSM_CNTL2_BASE_IDX 0
+#define mmTD_SCRATCH 0x12d3
+#define mmTD_SCRATCH_BASE_IDX 0
+#define mmTA_POWER_CNTL 0x12e0
+#define mmTA_POWER_CNTL_BASE_IDX 0
+#define mmTA_CNTL 0x12e1
+#define mmTA_CNTL_BASE_IDX 0
+#define mmTA_CNTL_AUX 0x12e2
+#define mmTA_CNTL_AUX_BASE_IDX 0
+#define mmTA_RESERVED_010C 0x12e3
+#define mmTA_RESERVED_010C_BASE_IDX 0
+#define mmTA_STATUS 0x12e8
+#define mmTA_STATUS_BASE_IDX 0
+#define mmTA_SCRATCH 0x1304
+#define mmTA_SCRATCH_BASE_IDX 0
+
+
+// addressBlock: gc_gdsdec
+// base address: 0x9700
+#define mmGDS_CONFIG 0x1360
+#define mmGDS_CONFIG_BASE_IDX 0
+#define mmGDS_CNTL_STATUS 0x1361
+#define mmGDS_CNTL_STATUS_BASE_IDX 0
+#define mmGDS_ENHANCE 0x1362
+#define mmGDS_ENHANCE_BASE_IDX 0
+#define mmGDS_PROTECTION_FAULT 0x1363
+#define mmGDS_PROTECTION_FAULT_BASE_IDX 0
+#define mmGDS_VM_PROTECTION_FAULT 0x1364
+#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0
+#define mmGDS_EDC_CNT 0x1365
+#define mmGDS_EDC_CNT_BASE_IDX 0
+#define mmGDS_EDC_GRBM_CNT 0x1366
+#define mmGDS_EDC_GRBM_CNT_BASE_IDX 0
+#define mmGDS_EDC_OA_DED 0x1367
+#define mmGDS_EDC_OA_DED_BASE_IDX 0
+#define mmGDS_DSM_CNTL 0x136a
+#define mmGDS_DSM_CNTL_BASE_IDX 0
+#define mmGDS_EDC_OA_PHY_CNT 0x136b
+#define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0
+#define mmGDS_EDC_OA_PIPE_CNT 0x136c
+#define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0
+#define mmGDS_DSM_CNTL2 0x136d
+#define mmGDS_DSM_CNTL2_BASE_IDX 0
+#define mmGDS_WD_GDS_CSB 0x136e
+#define mmGDS_WD_GDS_CSB_BASE_IDX 0
+
+
+// addressBlock: gc_rbdec
+// base address: 0x9800
+#define mmDB_DEBUG 0x13ac
+#define mmDB_DEBUG_BASE_IDX 0
+#define mmDB_DEBUG2 0x13ad
+#define mmDB_DEBUG2_BASE_IDX 0
+#define mmDB_DEBUG3 0x13ae
+#define mmDB_DEBUG3_BASE_IDX 0
+#define mmDB_DEBUG4 0x13af
+#define mmDB_DEBUG4_BASE_IDX 0
+#define mmDB_ETILE_STUTTER_CONTROL 0x13b0
+#define mmDB_ETILE_STUTTER_CONTROL_BASE_IDX 0
+#define mmDB_LTILE_STUTTER_CONTROL 0x13b1
+#define mmDB_LTILE_STUTTER_CONTROL_BASE_IDX 0
+#define mmDB_EQUAD_STUTTER_CONTROL 0x13b2
+#define mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX 0
+#define mmDB_LQUAD_STUTTER_CONTROL 0x13b3
+#define mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX 0
+#define mmDB_CREDIT_LIMIT 0x13b4
+#define mmDB_CREDIT_LIMIT_BASE_IDX 0
+#define mmDB_WATERMARKS 0x13b5
+#define mmDB_WATERMARKS_BASE_IDX 0
+#define mmDB_SUBTILE_CONTROL 0x13b6
+#define mmDB_SUBTILE_CONTROL_BASE_IDX 0
+#define mmDB_FREE_CACHELINES 0x13b7
+#define mmDB_FREE_CACHELINES_BASE_IDX 0
+#define mmDB_FIFO_DEPTH1 0x13b8
+#define mmDB_FIFO_DEPTH1_BASE_IDX 0
+#define mmDB_FIFO_DEPTH2 0x13b9
+#define mmDB_FIFO_DEPTH2_BASE_IDX 0
+#define mmDB_LAST_OF_BURST_CONFIG 0x13ba
+#define mmDB_LAST_OF_BURST_CONFIG_BASE_IDX 0
+#define mmDB_RING_CONTROL 0x13bb
+#define mmDB_RING_CONTROL_BASE_IDX 0
+#define mmDB_MEM_ARB_WATERMARKS 0x13bc
+#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0
+#define mmDB_FIFO_DEPTH3 0x13bd
+#define mmDB_FIFO_DEPTH3_BASE_IDX 0
+#define mmDB_RMI_BC_GL2_CACHE_CONTROL 0x13be
+#define mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX 0
+#define mmDB_EXCEPTION_CONTROL 0x13bf
+#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0
+#define mmDB_DFSM_CONFIG 0x13d0
+#define mmDB_DFSM_CONFIG_BASE_IDX 0
+#define mmDB_DFSM_TILES_IN_FLIGHT 0x13d2
+#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0
+#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x13d3
+#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0
+#define mmDB_DFSM_WATCHDOG 0x13d4
+#define mmDB_DFSM_WATCHDOG_BASE_IDX 0
+#define mmDB_DFSM_FLUSH_ENABLE 0x13d5
+#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0
+#define mmDB_DFSM_FLUSH_AUX_EVENT 0x13d6
+#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0
+#define mmDB_FGCG_SRAMS_CLK_CTRL 0x13d7
+#define mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX 0
+#define mmDB_FGCG_INTERFACES_CLK_CTRL 0x13d8
+#define mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX 0
+#define mmCC_RB_REDUNDANCY 0x13dc
+#define mmCC_RB_REDUNDANCY_BASE_IDX 0
+#define mmCC_RB_BACKEND_DISABLE 0x13dd
+#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0
+#define mmGB_ADDR_CONFIG 0x13de
+#define mmGB_ADDR_CONFIG_BASE_IDX 0
+#define mmGB_BACKEND_MAP 0x13df
+#define mmGB_BACKEND_MAP_BASE_IDX 0
+#define mmGB_GPU_ID 0x13e0
+#define mmGB_GPU_ID_BASE_IDX 0
+#define mmCC_RB_DAISY_CHAIN 0x13e1
+#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0
+#define mmGB_ADDR_CONFIG_READ 0x13e2
+#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0
+#define mmGB_TILE_MODE0 0x13e4
+#define mmGB_TILE_MODE0_BASE_IDX 0
+#define mmGB_TILE_MODE1 0x13e5
+#define mmGB_TILE_MODE1_BASE_IDX 0
+#define mmGB_TILE_MODE2 0x13e6
+#define mmGB_TILE_MODE2_BASE_IDX 0
+#define mmGB_TILE_MODE3 0x13e7
+#define mmGB_TILE_MODE3_BASE_IDX 0
+#define mmGB_TILE_MODE4 0x13e8
+#define mmGB_TILE_MODE4_BASE_IDX 0
+#define mmGB_TILE_MODE5 0x13e9
+#define mmGB_TILE_MODE5_BASE_IDX 0
+#define mmGB_TILE_MODE6 0x13ea
+#define mmGB_TILE_MODE6_BASE_IDX 0
+#define mmGB_TILE_MODE7 0x13eb
+#define mmGB_TILE_MODE7_BASE_IDX 0
+#define mmGB_TILE_MODE8 0x13ec
+#define mmGB_TILE_MODE8_BASE_IDX 0
+#define mmGB_TILE_MODE9 0x13ed
+#define mmGB_TILE_MODE9_BASE_IDX 0
+#define mmGB_TILE_MODE10 0x13ee
+#define mmGB_TILE_MODE10_BASE_IDX 0
+#define mmGB_TILE_MODE11 0x13ef
+#define mmGB_TILE_MODE11_BASE_IDX 0
+#define mmGB_TILE_MODE12 0x13f0
+#define mmGB_TILE_MODE12_BASE_IDX 0
+#define mmGB_TILE_MODE13 0x13f1
+#define mmGB_TILE_MODE13_BASE_IDX 0
+#define mmGB_TILE_MODE14 0x13f2
+#define mmGB_TILE_MODE14_BASE_IDX 0
+#define mmGB_TILE_MODE15 0x13f3
+#define mmGB_TILE_MODE15_BASE_IDX 0
+#define mmGB_TILE_MODE16 0x13f4
+#define mmGB_TILE_MODE16_BASE_IDX 0
+#define mmGB_TILE_MODE17 0x13f5
+#define mmGB_TILE_MODE17_BASE_IDX 0
+#define mmGB_TILE_MODE18 0x13f6
+#define mmGB_TILE_MODE18_BASE_IDX 0
+#define mmGB_TILE_MODE19 0x13f7
+#define mmGB_TILE_MODE19_BASE_IDX 0
+#define mmGB_TILE_MODE20 0x13f8
+#define mmGB_TILE_MODE20_BASE_IDX 0
+#define mmGB_TILE_MODE21 0x13f9
+#define mmGB_TILE_MODE21_BASE_IDX 0
+#define mmGB_TILE_MODE22 0x13fa
+#define mmGB_TILE_MODE22_BASE_IDX 0
+#define mmGB_TILE_MODE23 0x13fb
+#define mmGB_TILE_MODE23_BASE_IDX 0
+#define mmGB_TILE_MODE24 0x13fc
+#define mmGB_TILE_MODE24_BASE_IDX 0
+#define mmGB_TILE_MODE25 0x13fd
+#define mmGB_TILE_MODE25_BASE_IDX 0
+#define mmGB_TILE_MODE26 0x13fe
+#define mmGB_TILE_MODE26_BASE_IDX 0
+#define mmGB_TILE_MODE27 0x13ff
+#define mmGB_TILE_MODE27_BASE_IDX 0
+#define mmGB_TILE_MODE28 0x1400
+#define mmGB_TILE_MODE28_BASE_IDX 0
+#define mmGB_TILE_MODE29 0x1401
+#define mmGB_TILE_MODE29_BASE_IDX 0
+#define mmGB_TILE_MODE30 0x1402
+#define mmGB_TILE_MODE30_BASE_IDX 0
+#define mmGB_TILE_MODE31 0x1403
+#define mmGB_TILE_MODE31_BASE_IDX 0
+#define mmGB_MACROTILE_MODE0 0x1404
+#define mmGB_MACROTILE_MODE0_BASE_IDX 0
+#define mmGB_MACROTILE_MODE1 0x1405
+#define mmGB_MACROTILE_MODE1_BASE_IDX 0
+#define mmGB_MACROTILE_MODE2 0x1406
+#define mmGB_MACROTILE_MODE2_BASE_IDX 0
+#define mmGB_MACROTILE_MODE3 0x1407
+#define mmGB_MACROTILE_MODE3_BASE_IDX 0
+#define mmGB_MACROTILE_MODE4 0x1408
+#define mmGB_MACROTILE_MODE4_BASE_IDX 0
+#define mmGB_MACROTILE_MODE5 0x1409
+#define mmGB_MACROTILE_MODE5_BASE_IDX 0
+#define mmGB_MACROTILE_MODE6 0x140a
+#define mmGB_MACROTILE_MODE6_BASE_IDX 0
+#define mmGB_MACROTILE_MODE7 0x140b
+#define mmGB_MACROTILE_MODE7_BASE_IDX 0
+#define mmGB_MACROTILE_MODE8 0x140c
+#define mmGB_MACROTILE_MODE8_BASE_IDX 0
+#define mmGB_MACROTILE_MODE9 0x140d
+#define mmGB_MACROTILE_MODE9_BASE_IDX 0
+#define mmGB_MACROTILE_MODE10 0x140e
+#define mmGB_MACROTILE_MODE10_BASE_IDX 0
+#define mmGB_MACROTILE_MODE11 0x140f
+#define mmGB_MACROTILE_MODE11_BASE_IDX 0
+#define mmGB_MACROTILE_MODE12 0x1410
+#define mmGB_MACROTILE_MODE12_BASE_IDX 0
+#define mmGB_MACROTILE_MODE13 0x1411
+#define mmGB_MACROTILE_MODE13_BASE_IDX 0
+#define mmGB_MACROTILE_MODE14 0x1412
+#define mmGB_MACROTILE_MODE14_BASE_IDX 0
+#define mmGB_MACROTILE_MODE15 0x1413
+#define mmGB_MACROTILE_MODE15_BASE_IDX 0
+#define mmCB_HW_CONTROL_4 0x1422
+#define mmCB_HW_CONTROL_4_BASE_IDX 0
+#define mmCB_HW_CONTROL_3 0x1423
+#define mmCB_HW_CONTROL_3_BASE_IDX 0
+#define mmCB_HW_CONTROL 0x1424
+#define mmCB_HW_CONTROL_BASE_IDX 0
+#define mmCB_HW_CONTROL_1 0x1425
+#define mmCB_HW_CONTROL_1_BASE_IDX 0
+#define mmCB_HW_CONTROL_2 0x1426
+#define mmCB_HW_CONTROL_2_BASE_IDX 0
+#define mmCB_DCC_CONFIG 0x1427
+#define mmCB_DCC_CONFIG_BASE_IDX 0
+#define mmCB_HW_MEM_ARBITER_RD 0x1428
+#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0
+#define mmCB_HW_MEM_ARBITER_WR 0x1429
+#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0
+#define mmCB_RMI_BC_GL2_CACHE_CONTROL 0x142a
+#define mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX 0
+#define mmCB_STUTTER_CONTROL_CMASK_RDLAT 0x142b
+#define mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX 0
+#define mmCB_STUTTER_CONTROL_FMASK_RDLAT 0x142c
+#define mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX 0
+#define mmCB_STUTTER_CONTROL_COLOR_RDLAT 0x142d
+#define mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX 0
+#define mmCB_CACHE_EVICT_POINTS 0x142e
+#define mmCB_CACHE_EVICT_POINTS_BASE_IDX 0
+#define mmGC_USER_RB_REDUNDANCY 0x147e
+#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0
+#define mmGC_USER_RB_BACKEND_DISABLE 0x147f
+#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0
+
+
+// addressBlock: gc_gceadec2
+// base address: 0x9c00
+#define mmGCEA_SDP_VCD_RESERVE1 0x14a0
+#define mmGCEA_SDP_VCD_RESERVE1_BASE_IDX 0
+#define mmGCEA_SDP_REQ_CNTL 0x14a1
+#define mmGCEA_SDP_REQ_CNTL_BASE_IDX 0
+#define mmGCEA_MISC 0x14a2
+#define mmGCEA_MISC_BASE_IDX 0
+#define mmGCEA_LATENCY_SAMPLING 0x14a3
+#define mmGCEA_LATENCY_SAMPLING_BASE_IDX 0
+#define mmGCEA_PERFCOUNTER_LO 0x14a4
+#define mmGCEA_PERFCOUNTER_LO_BASE_IDX 0
+#define mmGCEA_PERFCOUNTER_HI 0x14a5
+#define mmGCEA_PERFCOUNTER_HI_BASE_IDX 0
+#define mmGCEA_PERFCOUNTER0_CFG 0x14a6
+#define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmGCEA_PERFCOUNTER1_CFG 0x14a7
+#define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmGCEA_PERFCOUNTER_RSLT_CNTL 0x14a8
+#define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmGCEA_EDC_CNT 0x14b2
+#define mmGCEA_EDC_CNT_BASE_IDX 0
+#define mmGCEA_EDC_CNT2 0x14b3
+#define mmGCEA_EDC_CNT2_BASE_IDX 0
+#define mmGCEA_DSM_CNTL 0x14b4
+#define mmGCEA_DSM_CNTL_BASE_IDX 0
+#define mmGCEA_DSM_CNTLA 0x14b5
+#define mmGCEA_DSM_CNTLA_BASE_IDX 0
+#define mmGCEA_DSM_CNTLB 0x14b6
+#define mmGCEA_DSM_CNTLB_BASE_IDX 0
+#define mmGCEA_DSM_CNTL2 0x14b7
+#define mmGCEA_DSM_CNTL2_BASE_IDX 0
+#define mmGCEA_DSM_CNTL2A 0x14b8
+#define mmGCEA_DSM_CNTL2A_BASE_IDX 0
+#define mmGCEA_DSM_CNTL2B 0x14b9
+#define mmGCEA_DSM_CNTL2B_BASE_IDX 0
+#define mmGCEA_GL2C_XBR_CREDITS 0x14ba
+#define mmGCEA_GL2C_XBR_CREDITS_BASE_IDX 0
+#define mmGCEA_GL2C_XBR_MAXBURST 0x14bb
+#define mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX 0
+#define mmGCEA_PROBE_CNTL 0x14bc
+#define mmGCEA_PROBE_CNTL_BASE_IDX 0
+#define mmGCEA_PROBE_MAP 0x14bd
+#define mmGCEA_PROBE_MAP_BASE_IDX 0
+#define mmGCEA_ERR_STATUS 0x14be
+#define mmGCEA_ERR_STATUS_BASE_IDX 0
+#define mmGCEA_MISC2 0x14bf
+#define mmGCEA_MISC2_BASE_IDX 0
+
+
+// addressBlock: gc_spipdec2
+// base address: 0x9c80
+#define mmSPI_PQEV_CTRL 0x14c0
+#define mmSPI_PQEV_CTRL_BASE_IDX 0
+#define mmSPI_SYS_COMPUTE 0x14c1
+#define mmSPI_SYS_COMPUTE_BASE_IDX 0
+#define mmSPI_SYS_WIF_CNTL 0x14c2
+#define mmSPI_SYS_WIF_CNTL_BASE_IDX 0
+
+
+// addressBlock: gc_gceadec3
+// base address: 0x9dc0
+#define mmGCEA_DRAM_BANK_ARB 0x1510
+#define mmGCEA_DRAM_BANK_ARB_BASE_IDX 0
+#define mmGCEA_DRAM_BANK_ARB_RFSH 0x1511
+#define mmGCEA_DRAM_BANK_ARB_RFSH_BASE_IDX 0
+#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0 0x1512
+#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0
+#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1 0x1513
+#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0
+#define mmGCEA_SDP_BACKDOOR_DATACREDITS0 0x1514
+#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0
+#define mmGCEA_SDP_BACKDOOR_DATACREDITS1 0x1515
+#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0
+#define mmGCEA_SDP_BACKDOOR_MISCCREDITS 0x1516
+#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PACH 0x1517
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PACH_BASE_IDX 0
+#define mmGCEA_RRET_MEM_RESERVE 0x1518
+#define mmGCEA_RRET_MEM_RESERVE_BASE_IDX 0
+#define mmGCEA_ADDRDEC_SELECT 0x1519
+#define mmGCEA_ADDRDEC_SELECT_BASE_IDX 0
+#define mmGCEA_SDP_ENABLE 0x151a
+#define mmGCEA_SDP_ENABLE_BASE_IDX 0
+
+
+// addressBlock: gc_rmi_rmidec
+// base address: 0x9e00
+#define mmRMI_GENERAL_CNTL 0x1520
+#define mmRMI_GENERAL_CNTL_BASE_IDX 0
+#define mmRMI_GENERAL_CNTL1 0x1521
+#define mmRMI_GENERAL_CNTL1_BASE_IDX 0
+#define mmRMI_GENERAL_STATUS 0x1522
+#define mmRMI_GENERAL_STATUS_BASE_IDX 0
+#define mmRMI_SUBBLOCK_STATUS0 0x1523
+#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0
+#define mmRMI_SUBBLOCK_STATUS1 0x1524
+#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0
+#define mmRMI_SUBBLOCK_STATUS2 0x1525
+#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0
+#define mmRMI_SUBBLOCK_STATUS3 0x1526
+#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0
+#define mmRMI_XBAR_CONFIG 0x1527
+#define mmRMI_XBAR_CONFIG_BASE_IDX 0
+#define mmRMI_PROBE_POP_LOGIC_CNTL 0x1528
+#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0
+#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x1529
+#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0
+#define mmRMI_DEMUX_CNTL 0x152a
+#define mmRMI_DEMUX_CNTL_BASE_IDX 0
+#define mmRMI_UTCL1_CNTL1 0x152b
+#define mmRMI_UTCL1_CNTL1_BASE_IDX 0
+#define mmRMI_UTCL1_CNTL2 0x152c
+#define mmRMI_UTCL1_CNTL2_BASE_IDX 0
+#define mmRMI_UTC_UNIT_CONFIG 0x152d
+#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0
+#define mmRMI_TCIW_FORMATTER0_CNTL 0x152e
+#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0
+#define mmRMI_TCIW_FORMATTER1_CNTL 0x152f
+#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0
+#define mmRMI_SCOREBOARD_CNTL 0x1530
+#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0
+#define mmRMI_SCOREBOARD_STATUS0 0x1531
+#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0
+#define mmRMI_SCOREBOARD_STATUS1 0x1532
+#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0
+#define mmRMI_SCOREBOARD_STATUS2 0x1533
+#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0
+#define mmRMI_XBAR_ARBITER_CONFIG 0x1534
+#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0
+#define mmRMI_XBAR_ARBITER_CONFIG_1 0x1535
+#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0
+#define mmRMI_CLOCK_CNTRL 0x1536
+#define mmRMI_CLOCK_CNTRL_BASE_IDX 0
+#define mmRMI_UTCL1_STATUS 0x1537
+#define mmRMI_UTCL1_STATUS_BASE_IDX 0
+#define mmRMI_RB_GLX_CID_MAP 0x1538
+#define mmRMI_RB_GLX_CID_MAP_BASE_IDX 0
+#define mmRMI_SPARE 0x153f
+#define mmRMI_SPARE_BASE_IDX 0
+#define mmRMI_SPARE_1 0x1540
+#define mmRMI_SPARE_1_BASE_IDX 0
+#define mmRMI_SPARE_2 0x1541
+#define mmRMI_SPARE_2_BASE_IDX 0
+#define mmCC_RMI_REDUNDANCY 0x1542
+#define mmCC_RMI_REDUNDANCY_BASE_IDX 0
+#define mmGC_USER_RMI_REDUNDANCY 0x1543
+#define mmGC_USER_RMI_REDUNDANCY_BASE_IDX 0
+
+
+// addressBlock: gc_pmmdec
+// base address: 0x9f80
+#define mmPMM_GENERAL_CNTL 0x1580
+#define mmPMM_GENERAL_CNTL_BASE_IDX 0
+#define mmGCR_PIO_CNTL 0x1581
+#define mmGCR_PIO_CNTL_BASE_IDX 0
+#define mmGCR_PIO_DATA 0x1582
+#define mmGCR_PIO_DATA_BASE_IDX 0
+#define mmGCR_GENERAL_CNTL 0x1583
+#define mmGCR_GENERAL_CNTL_BASE_IDX 0
+#define mmGCR_TARGET_DISABLE 0x1584
+#define mmGCR_TARGET_DISABLE_BASE_IDX 0
+#define mmGCR_CMD_STATUS 0x1585
+#define mmGCR_CMD_STATUS_BASE_IDX 0
+#define mmGCR_SPARE 0x1586
+#define mmGCR_SPARE_BASE_IDX 0
+
+
+// addressBlock: gc_utcl1dec
+// base address: 0x9fa0
+#define mmUTCL1_CTRL 0x1588
+#define mmUTCL1_CTRL_BASE_IDX 0
+#define mmUTCL1_ALOG 0x1589
+#define mmUTCL1_ALOG_BASE_IDX 0
+#define mmUTCL1_UTCL0_INVREQ_DISABLE 0x158a
+#define mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX 0
+#define mmGCRD_SA_TARGETS_DISABLE 0x158b
+#define mmGCRD_SA_TARGETS_DISABLE_BASE_IDX 0
+
+
+// addressBlock: gc_gcatcl2dec
+// base address: 0xa000
+#define mmGC_ATC_L2_CNTL 0x15a0
+#define mmGC_ATC_L2_CNTL_BASE_IDX 0
+#define mmGC_ATC_L2_CNTL2 0x15a1
+#define mmGC_ATC_L2_CNTL2_BASE_IDX 0
+#define mmGC_ATC_L2_CACHE_DATA0 0x15a4
+#define mmGC_ATC_L2_CACHE_DATA0_BASE_IDX 0
+#define mmGC_ATC_L2_CACHE_DATA1 0x15a5
+#define mmGC_ATC_L2_CACHE_DATA1_BASE_IDX 0
+#define mmGC_ATC_L2_CACHE_DATA2 0x15a6
+#define mmGC_ATC_L2_CACHE_DATA2_BASE_IDX 0
+#define mmGC_ATC_L2_CNTL3 0x15a7
+#define mmGC_ATC_L2_CNTL3_BASE_IDX 0
+#define mmGC_ATC_L2_STATUS 0x15a8
+#define mmGC_ATC_L2_STATUS_BASE_IDX 0
+#define mmGC_ATC_L2_STATUS2 0x15a9
+#define mmGC_ATC_L2_STATUS2_BASE_IDX 0
+#define mmGC_ATC_L2_MISC_CG 0x15aa
+#define mmGC_ATC_L2_MISC_CG_BASE_IDX 0
+#define mmGC_ATC_L2_MEM_POWER_LS 0x15ab
+#define mmGC_ATC_L2_MEM_POWER_LS_BASE_IDX 0
+#define mmGC_ATC_L2_CGTT_CLK_CTRL 0x15ac
+#define mmGC_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmGC_ATC_L2_SDPPORT_CTRL 0x15ad
+#define mmGC_ATC_L2_SDPPORT_CTRL_BASE_IDX 0
+
+
+// addressBlock: gc_gcvml2pfdec
+// base address: 0xa100
+#define mmGCVM_L2_CNTL 0x15e0
+#define mmGCVM_L2_CNTL_BASE_IDX 0
+#define mmGCVM_L2_CNTL2 0x15e1
+#define mmGCVM_L2_CNTL2_BASE_IDX 0
+#define mmGCVM_L2_CNTL3 0x15e2
+#define mmGCVM_L2_CNTL3_BASE_IDX 0
+#define mmGCVM_L2_STATUS 0x15e3
+#define mmGCVM_L2_STATUS_BASE_IDX 0
+#define mmGCVM_DUMMY_PAGE_FAULT_CNTL 0x15e4
+#define mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
+#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x15e5
+#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x15e6
+#define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_CNTL 0x15e7
+#define mmGCVM_INVALIDATE_CNTL_BASE_IDX 0
+#define mmGCVM_L2_PROTECTION_FAULT_CNTL 0x15e8
+#define mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
+#define mmGCVM_L2_PROTECTION_FAULT_CNTL2 0x15e9
+#define mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
+#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3 0x15ea
+#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
+#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4 0x15eb
+#define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
+#define mmGCVM_L2_PROTECTION_FAULT_STATUS 0x15ec
+#define mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
+#define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32 0x15ed
+#define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32 0x15ee
+#define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x15ef
+#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15f0
+#define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15f2
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15f3
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x15f4
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x15f5
+#define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x15f6
+#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
+#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x15f7
+#define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
+#define mmGCVM_L2_CNTL4 0x15f8
+#define mmGCVM_L2_CNTL4_BASE_IDX 0
+#define mmGCVM_L2_MM_GROUP_RT_CLASSES 0x15f9
+#define mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
+#define mmGCVM_L2_BANK_SELECT_RESERVED_CID 0x15fa
+#define mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
+#define mmGCVM_L2_BANK_SELECT_RESERVED_CID2 0x15fb
+#define mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
+#define mmGCVM_L2_CACHE_PARITY_CNTL 0x15fc
+#define mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
+#define mmGCVM_L2_CGTT_CLK_CTRL 0x15ff
+#define mmGCVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmGCVM_L2_CNTL5 0x1601
+#define mmGCVM_L2_CNTL5_BASE_IDX 0
+#define mmGCVM_L2_GCR_CNTL 0x1602
+#define mmGCVM_L2_GCR_CNTL_BASE_IDX 0
+#define mmGCVML2_WALKER_MACRO_THROTTLE_TIME 0x1603
+#define mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0
+#define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x1604
+#define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0
+#define mmGCVML2_WALKER_MICRO_THROTTLE_TIME 0x1605
+#define mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0
+#define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x1606
+#define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0
+
+
+// addressBlock: gc_gcvml2vcdec
+// base address: 0xa200
+#define mmGCVM_CONTEXT0_CNTL 0x1620
+#define mmGCVM_CONTEXT0_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT1_CNTL 0x1621
+#define mmGCVM_CONTEXT1_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT2_CNTL 0x1622
+#define mmGCVM_CONTEXT2_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT3_CNTL 0x1623
+#define mmGCVM_CONTEXT3_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT4_CNTL 0x1624
+#define mmGCVM_CONTEXT4_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT5_CNTL 0x1625
+#define mmGCVM_CONTEXT5_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT6_CNTL 0x1626
+#define mmGCVM_CONTEXT6_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT7_CNTL 0x1627
+#define mmGCVM_CONTEXT7_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT8_CNTL 0x1628
+#define mmGCVM_CONTEXT8_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT9_CNTL 0x1629
+#define mmGCVM_CONTEXT9_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT10_CNTL 0x162a
+#define mmGCVM_CONTEXT10_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT11_CNTL 0x162b
+#define mmGCVM_CONTEXT11_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT12_CNTL 0x162c
+#define mmGCVM_CONTEXT12_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT13_CNTL 0x162d
+#define mmGCVM_CONTEXT13_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT14_CNTL 0x162e
+#define mmGCVM_CONTEXT14_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXT15_CNTL 0x162f
+#define mmGCVM_CONTEXT15_CNTL_BASE_IDX 0
+#define mmGCVM_CONTEXTS_DISABLE 0x1630
+#define mmGCVM_CONTEXTS_DISABLE_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG0_SEM 0x1631
+#define mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG1_SEM 0x1632
+#define mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG2_SEM 0x1633
+#define mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG3_SEM 0x1634
+#define mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG4_SEM 0x1635
+#define mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG5_SEM 0x1636
+#define mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG6_SEM 0x1637
+#define mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG7_SEM 0x1638
+#define mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG8_SEM 0x1639
+#define mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG9_SEM 0x163a
+#define mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG10_SEM 0x163b
+#define mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG11_SEM 0x163c
+#define mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG12_SEM 0x163d
+#define mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG13_SEM 0x163e
+#define mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG14_SEM 0x163f
+#define mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG15_SEM 0x1640
+#define mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG16_SEM 0x1641
+#define mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG17_SEM 0x1642
+#define mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG0_REQ 0x1643
+#define mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG1_REQ 0x1644
+#define mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG2_REQ 0x1645
+#define mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG3_REQ 0x1646
+#define mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG4_REQ 0x1647
+#define mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG5_REQ 0x1648
+#define mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG6_REQ 0x1649
+#define mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG7_REQ 0x164a
+#define mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG8_REQ 0x164b
+#define mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG9_REQ 0x164c
+#define mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG10_REQ 0x164d
+#define mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG11_REQ 0x164e
+#define mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG12_REQ 0x164f
+#define mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG13_REQ 0x1650
+#define mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG14_REQ 0x1651
+#define mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG15_REQ 0x1652
+#define mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG16_REQ 0x1653
+#define mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG17_REQ 0x1654
+#define mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG0_ACK 0x1655
+#define mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG1_ACK 0x1656
+#define mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG2_ACK 0x1657
+#define mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG3_ACK 0x1658
+#define mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG4_ACK 0x1659
+#define mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG5_ACK 0x165a
+#define mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG6_ACK 0x165b
+#define mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG7_ACK 0x165c
+#define mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG8_ACK 0x165d
+#define mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG9_ACK 0x165e
+#define mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG10_ACK 0x165f
+#define mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG11_ACK 0x1660
+#define mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG12_ACK 0x1661
+#define mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG13_ACK 0x1662
+#define mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG14_ACK 0x1663
+#define mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG15_ACK 0x1664
+#define mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG16_ACK 0x1665
+#define mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG17_ACK 0x1666
+#define mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x1667
+#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x1668
+#define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x1669
+#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x166a
+#define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x166b
+#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x166c
+#define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x166d
+#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x166e
+#define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x166f
+#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x1670
+#define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x1671
+#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x1672
+#define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x1673
+#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x1674
+#define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x1675
+#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x1676
+#define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x1677
+#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x1678
+#define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x1679
+#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x167a
+#define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x167b
+#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x167c
+#define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x167d
+#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x167e
+#define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x167f
+#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x1680
+#define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x1681
+#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x1682
+#define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x1683
+#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x1684
+#define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x1685
+#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x1686
+#define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x1687
+#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x1688
+#define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x1689
+#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x168a
+#define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x168b
+#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x168c
+#define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x168d
+#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x168e
+#define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x168f
+#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x1690
+#define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x1691
+#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x1692
+#define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x1693
+#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x1694
+#define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x1695
+#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x1696
+#define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x1697
+#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x1698
+#define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x1699
+#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x169a
+#define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x169b
+#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x169c
+#define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x169d
+#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x169e
+#define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x169f
+#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x16a0
+#define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x16a1
+#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x16a2
+#define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x16a3
+#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x16a4
+#define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x16a5
+#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x16a6
+#define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x16a7
+#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x16a8
+#define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x16a9
+#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x16aa
+#define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x16ab
+#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x16ac
+#define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x16ad
+#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x16ae
+#define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x16af
+#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x16b0
+#define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x16b1
+#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x16b2
+#define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x16b3
+#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x16b4
+#define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x16b5
+#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x16b6
+#define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x16b7
+#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x16b8
+#define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x16b9
+#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x16ba
+#define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x16bb
+#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x16bc
+#define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x16bd
+#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x16be
+#define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x16bf
+#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x16c0
+#define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x16c1
+#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x16c2
+#define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x16c3
+#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x16c4
+#define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x16c5
+#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x16c6
+#define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x16c7
+#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x16c8
+#define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x16c9
+#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x16ca
+#define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x16cb
+#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x16cc
+#define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x16cd
+#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x16ce
+#define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x16cf
+#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x16d0
+#define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x16d1
+#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x16d2
+#define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x16d3
+#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x16d4
+#define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x16d5
+#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x16d6
+#define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x16d7
+#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x16d8
+#define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x16d9
+#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x16da
+#define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x16db
+#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x16dc
+#define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x16dd
+#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x16de
+#define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x16df
+#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x16e0
+#define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x16e1
+#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x16e2
+#define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x16e3
+#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x16e4
+#define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x16e5
+#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x16e6
+#define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x16e7
+#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x16e8
+#define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x16e9
+#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x16ea
+#define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+
+
+// addressBlock: gc_gcvmsharedpfdec
+// base address: 0xa590
+#define mmGCMC_VM_NB_MMIOBASE 0x1704
+#define mmGCMC_VM_NB_MMIOBASE_BASE_IDX 0
+#define mmGCMC_VM_NB_MMIOLIMIT 0x1705
+#define mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX 0
+#define mmGCMC_VM_NB_PCI_CTRL 0x1706
+#define mmGCMC_VM_NB_PCI_CTRL_BASE_IDX 0
+#define mmGCMC_VM_NB_PCI_ARB 0x1707
+#define mmGCMC_VM_NB_PCI_ARB_BASE_IDX 0
+#define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1 0x1708
+#define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0
+#define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2 0x1709
+#define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0
+#define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2 0x170a
+#define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0
+#define mmGCMC_VM_FB_OFFSET 0x170b
+#define mmGCMC_VM_FB_OFFSET_BASE_IDX 0
+#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x170c
+#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
+#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x170d
+#define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
+#define mmGCMC_VM_STEERING 0x170e
+#define mmGCMC_VM_STEERING_BASE_IDX 0
+#define mmGCMC_SHARED_VIRT_RESET_REQ 0x170f
+#define mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
+#define mmGCMC_MEM_POWER_LS 0x1710
+#define mmGCMC_MEM_POWER_LS_BASE_IDX 0
+#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x1711
+#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
+#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x1712
+#define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
+#define mmGCMC_VM_APT_CNTL 0x1713
+#define mmGCMC_VM_APT_CNTL_BASE_IDX 0
+#define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x1714
+#define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
+#define mmGCMC_VM_LOCAL_HBM_ADDRESS_START 0x1715
+#define mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
+#define mmGCMC_VM_LOCAL_HBM_ADDRESS_END 0x1716
+#define mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
+#define mmGCMC_SHARED_VIRT_RESET_REQ2 0x1717
+#define mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX 0
+
+
+// addressBlock: gc_gcvmsharedvcdec
+// base address: 0xa600
+#define mmGCMC_VM_FB_LOCATION_BASE 0x1720
+#define mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX 0
+#define mmGCMC_VM_FB_LOCATION_TOP 0x1721
+#define mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX 0
+#define mmGCMC_VM_AGP_TOP 0x1722
+#define mmGCMC_VM_AGP_TOP_BASE_IDX 0
+#define mmGCMC_VM_AGP_BOT 0x1723
+#define mmGCMC_VM_AGP_BOT_BASE_IDX 0
+#define mmGCMC_VM_AGP_BASE 0x1724
+#define mmGCMC_VM_AGP_BASE_BASE_IDX 0
+#define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x1725
+#define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
+#define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x1726
+#define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
+#define mmGCMC_VM_MX_L1_TLB_CNTL 0x1727
+#define mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
+
+
+// addressBlock: gc_gceadec
+// base address: 0xa800
+#define mmGCEA_DRAM_RD_CLI2GRP_MAP0 0x17a0
+#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define mmGCEA_DRAM_RD_CLI2GRP_MAP1 0x17a1
+#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define mmGCEA_DRAM_WR_CLI2GRP_MAP0 0x17a2
+#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define mmGCEA_DRAM_WR_CLI2GRP_MAP1 0x17a3
+#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define mmGCEA_DRAM_RD_GRP2VC_MAP 0x17a4
+#define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define mmGCEA_DRAM_WR_GRP2VC_MAP 0x17a5
+#define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define mmGCEA_DRAM_RD_LAZY 0x17a6
+#define mmGCEA_DRAM_RD_LAZY_BASE_IDX 0
+#define mmGCEA_DRAM_WR_LAZY 0x17a7
+#define mmGCEA_DRAM_WR_LAZY_BASE_IDX 0
+#define mmGCEA_DRAM_RD_CAM_CNTL 0x17a8
+#define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define mmGCEA_DRAM_WR_CAM_CNTL 0x17a9
+#define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define mmGCEA_DRAM_PAGE_BURST 0x17aa
+#define mmGCEA_DRAM_PAGE_BURST_BASE_IDX 0
+#define mmGCEA_DRAM_RD_PRI_AGE 0x17ab
+#define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define mmGCEA_DRAM_WR_PRI_AGE 0x17ac
+#define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define mmGCEA_DRAM_RD_PRI_QUEUING 0x17ad
+#define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define mmGCEA_DRAM_WR_PRI_QUEUING 0x17ae
+#define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define mmGCEA_DRAM_RD_PRI_FIXED 0x17af
+#define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define mmGCEA_DRAM_WR_PRI_FIXED 0x17b0
+#define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define mmGCEA_DRAM_RD_PRI_URGENCY 0x17b1
+#define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define mmGCEA_DRAM_WR_PRI_URGENCY 0x17b2
+#define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1 0x17b3
+#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2 0x17b4
+#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3 0x17b5
+#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1 0x17b6
+#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2 0x17b7
+#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3 0x17b8
+#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmGCEA_ADDRNORM_BASE_ADDR0 0x17d4
+#define mmGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define mmGCEA_ADDRNORM_LIMIT_ADDR0 0x17d5
+#define mmGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define mmGCEA_ADDRNORM_BASE_ADDR1 0x17d6
+#define mmGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define mmGCEA_ADDRNORM_LIMIT_ADDR1 0x17d7
+#define mmGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define mmGCEA_ADDRNORM_OFFSET_ADDR1 0x17d8
+#define mmGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define mmGCEA_ADDRNORMDRAM_HOLE_CNTL 0x17e3
+#define mmGCEA_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
+#define mmGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x17e5
+#define mmGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
+#define mmGCEA_ADDRDEC_BANK_CFG 0x17e7
+#define mmGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define mmGCEA_ADDRDEC_MISC_CFG 0x17e8
+#define mmGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0 0x17e9
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1 0x17ea
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2 0x17eb
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3 0x17ec
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4 0x17ed
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC 0x17ee
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2 0x17ef
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0 0x17f0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1 0x17f1
+#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x17f2
+#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START0 0x17f3
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END0 0x17f4
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START1 0x17f5
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX 0
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END1 0x17f6
+#define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0 0x1805
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1 0x1806
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2 0x1807
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3 0x1808
+#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x1809
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x180a
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x180b
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x180c
+#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01 0x180d
+#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23 0x180e
+#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x180f
+#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x1810
+#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01 0x1811
+#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23 0x1812
+#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01 0x1813
+#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23 0x1814
+#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x1815
+#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x1816
+#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x1817
+#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x1818
+#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_RM_SEL_CS01 0x1819
+#define mmGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_RM_SEL_CS23 0x181a
+#define mmGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01 0x181b
+#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23 0x181c
+#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0 0x181d
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1 0x181e
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2 0x181f
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3 0x1820
+#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x1821
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x1822
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x1823
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x1824
+#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01 0x1825
+#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23 0x1826
+#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x1827
+#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x1828
+#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01 0x1829
+#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23 0x182a
+#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01 0x182b
+#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23 0x182c
+#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x182d
+#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x182e
+#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x182f
+#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x1830
+#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_RM_SEL_CS01 0x1831
+#define mmGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_RM_SEL_CS23 0x1832
+#define mmGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01 0x1833
+#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23 0x1834
+#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define mmGCEA_IO_RD_CLI2GRP_MAP0 0x187d
+#define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define mmGCEA_IO_RD_CLI2GRP_MAP1 0x187e
+#define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define mmGCEA_IO_WR_CLI2GRP_MAP0 0x187f
+#define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define mmGCEA_IO_WR_CLI2GRP_MAP1 0x1880
+#define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define mmGCEA_IO_RD_COMBINE_FLUSH 0x1881
+#define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define mmGCEA_IO_WR_COMBINE_FLUSH 0x1882
+#define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define mmGCEA_IO_GROUP_BURST 0x1883
+#define mmGCEA_IO_GROUP_BURST_BASE_IDX 0
+#define mmGCEA_IO_RD_PRI_AGE 0x1884
+#define mmGCEA_IO_RD_PRI_AGE_BASE_IDX 0
+#define mmGCEA_IO_WR_PRI_AGE 0x1885
+#define mmGCEA_IO_WR_PRI_AGE_BASE_IDX 0
+#define mmGCEA_IO_RD_PRI_QUEUING 0x1886
+#define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define mmGCEA_IO_WR_PRI_QUEUING 0x1887
+#define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define mmGCEA_IO_RD_PRI_FIXED 0x1888
+#define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX 0
+#define mmGCEA_IO_WR_PRI_FIXED 0x1889
+#define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX 0
+#define mmGCEA_IO_RD_PRI_URGENCY 0x188a
+#define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define mmGCEA_IO_WR_PRI_URGENCY 0x188b
+#define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define mmGCEA_IO_RD_PRI_URGENCY_MASKING 0x188c
+#define mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define mmGCEA_IO_WR_PRI_URGENCY_MASKING 0x188d
+#define mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define mmGCEA_IO_RD_PRI_QUANT_PRI1 0x188e
+#define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmGCEA_IO_RD_PRI_QUANT_PRI2 0x188f
+#define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmGCEA_IO_RD_PRI_QUANT_PRI3 0x1890
+#define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmGCEA_IO_WR_PRI_QUANT_PRI1 0x1891
+#define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmGCEA_IO_WR_PRI_QUANT_PRI2 0x1892
+#define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmGCEA_IO_WR_PRI_QUANT_PRI3 0x1893
+#define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmGCEA_SDP_ARB_DRAM 0x1894
+#define mmGCEA_SDP_ARB_DRAM_BASE_IDX 0
+#define mmGCEA_SDP_ARB_FINAL 0x1896
+#define mmGCEA_SDP_ARB_FINAL_BASE_IDX 0
+#define mmGCEA_SDP_DRAM_PRIORITY 0x1897
+#define mmGCEA_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define mmGCEA_SDP_IO_PRIORITY 0x1899
+#define mmGCEA_SDP_IO_PRIORITY_BASE_IDX 0
+#define mmGCEA_SDP_CREDITS 0x189a
+#define mmGCEA_SDP_CREDITS_BASE_IDX 0
+#define mmGCEA_SDP_TAG_RESERVE0 0x189b
+#define mmGCEA_SDP_TAG_RESERVE0_BASE_IDX 0
+#define mmGCEA_SDP_TAG_RESERVE1 0x189c
+#define mmGCEA_SDP_TAG_RESERVE1_BASE_IDX 0
+#define mmGCEA_SDP_VCC_RESERVE0 0x189d
+#define mmGCEA_SDP_VCC_RESERVE0_BASE_IDX 0
+#define mmGCEA_SDP_VCC_RESERVE1 0x189e
+#define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX 0
+#define mmGCEA_SDP_VCD_RESERVE0 0x189f
+#define mmGCEA_SDP_VCD_RESERVE0_BASE_IDX 0
+
+
+// addressBlock: gc_tcdec
+// base address: 0xac00
+#define mmTCP_INVALIDATE 0x18a0
+#define mmTCP_INVALIDATE_BASE_IDX 0
+#define mmTCP_STATUS 0x18a1
+#define mmTCP_STATUS_BASE_IDX 0
+#define mmTCP_CNTL 0x18a2
+#define mmTCP_CNTL_BASE_IDX 0
+#define mmTCP_CREDIT 0x18a6
+#define mmTCP_CREDIT_BASE_IDX 0
+#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x18b6
+#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0
+#define mmTCP_EDC_CNT 0x18b7
+#define mmTCP_EDC_CNT_BASE_IDX 0
+#define mmTCI_STATUS 0x1901
+#define mmTCI_STATUS_BASE_IDX 0
+#define mmTCI_CNTL_1 0x1902
+#define mmTCI_CNTL_1_BASE_IDX 0
+#define mmTCI_CNTL_2 0x1903
+#define mmTCI_CNTL_2_BASE_IDX 0
+
+
+// addressBlock: gc_shdec
+// base address: 0xb000
+#define mmSPI_SHADER_PGM_RSRC4_PS 0x19a1
+#define mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_CHKSUM_PS 0x19a6
+#define mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC3_PS 0x19a7
+#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_PS 0x19a8
+#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_PS 0x19a9
+#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_PS 0x19aa
+#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_PS 0x19ab
+#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_0 0x19ac
+#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_1 0x19ad
+#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_2 0x19ae
+#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_3 0x19af
+#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_4 0x19b0
+#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_5 0x19b1
+#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_6 0x19b2
+#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_7 0x19b3
+#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_8 0x19b4
+#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_9 0x19b5
+#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_10 0x19b6
+#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_11 0x19b7
+#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_12 0x19b8
+#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_13 0x19b9
+#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_14 0x19ba
+#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_15 0x19bb
+#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_16 0x19bc
+#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_17 0x19bd
+#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_18 0x19be
+#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_19 0x19bf
+#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_20 0x19c0
+#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_21 0x19c1
+#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_22 0x19c2
+#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_23 0x19c3
+#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_24 0x19c4
+#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_25 0x19c5
+#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_26 0x19c6
+#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_27 0x19c7
+#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_28 0x19c8
+#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_29 0x19c9
+#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_30 0x19ca
+#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_PS_31 0x19cb
+#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0
+#define mmSPI_SHADER_REQ_CTRL_PS 0x19d0
+#define mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_PS 0x19d1
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_PS_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_0 0x19d2
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_PS_0 0x19d2
+#define mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_1 0x19d3
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_PS_1 0x19d3
+#define mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_2 0x19d4
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_PS_2 0x19d4
+#define mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_3 0x19d5
+#define mmSPI_SHADER_PREF_PRI_ACCUM_PS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_PS_3 0x19d5
+#define mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC4_VS 0x19e1
+#define mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_CHKSUM_VS 0x19e5
+#define mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC3_VS 0x19e6
+#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0
+#define mmSPI_SHADER_LATE_ALLOC_VS 0x19e7
+#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_VS 0x19e8
+#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_VS 0x19e9
+#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_VS 0x19ea
+#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_VS 0x19eb
+#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_0 0x19ec
+#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_1 0x19ed
+#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_2 0x19ee
+#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_3 0x19ef
+#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_4 0x19f0
+#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_5 0x19f1
+#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_6 0x19f2
+#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_7 0x19f3
+#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_8 0x19f4
+#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_9 0x19f5
+#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_10 0x19f6
+#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_11 0x19f7
+#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_12 0x19f8
+#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_13 0x19f9
+#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_14 0x19fa
+#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_15 0x19fb
+#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_16 0x19fc
+#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_17 0x19fd
+#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_18 0x19fe
+#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_19 0x19ff
+#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_20 0x1a00
+#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_21 0x1a01
+#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_22 0x1a02
+#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_23 0x1a03
+#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_24 0x1a04
+#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_25 0x1a05
+#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_26 0x1a06
+#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_27 0x1a07
+#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_28 0x1a08
+#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_29 0x1a09
+#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_30 0x1a0a
+#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_VS_31 0x1a0b
+#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0
+#define mmSPI_SHADER_REQ_CTRL_VS 0x1a10
+#define mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_VS 0x1a11
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_VS_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_0 0x1a12
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_VS_0 0x1a12
+#define mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_1 0x1a13
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_VS_1 0x1a13
+#define mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_2 0x1a14
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_VS_2 0x1a14
+#define mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_3 0x1a15
+#define mmSPI_SHADER_PREF_PRI_ACCUM_VS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_VS_3 0x1a15
+#define mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x1a1b
+#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x1a1c
+#define mmSPI_SHADER_PGM_RSRC2_ES_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x1a1d
+#define mmSPI_SHADER_PGM_RSRC2_LS_VS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_CHKSUM_GS 0x1a20
+#define mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC4_GS 0x1a21
+#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x1a22
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x1a23
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_ES_GS 0x1a24
+#define mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_ES_GS 0x1a25
+#define mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC3_GS 0x1a27
+#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_GS 0x1a28
+#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_GS 0x1a29
+#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_GS 0x1a2a
+#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_GS 0x1a2b
+#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_0 0x1a2c
+#define mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_1 0x1a2d
+#define mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_2 0x1a2e
+#define mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_3 0x1a2f
+#define mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_4 0x1a30
+#define mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_5 0x1a31
+#define mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_6 0x1a32
+#define mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_7 0x1a33
+#define mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_8 0x1a34
+#define mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_9 0x1a35
+#define mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_10 0x1a36
+#define mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_11 0x1a37
+#define mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_12 0x1a38
+#define mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_13 0x1a39
+#define mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_14 0x1a3a
+#define mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_15 0x1a3b
+#define mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_16 0x1a3c
+#define mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_17 0x1a3d
+#define mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_18 0x1a3e
+#define mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_19 0x1a3f
+#define mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_20 0x1a40
+#define mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_21 0x1a41
+#define mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_22 0x1a42
+#define mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_23 0x1a43
+#define mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_24 0x1a44
+#define mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_25 0x1a45
+#define mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_26 0x1a46
+#define mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_27 0x1a47
+#define mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_28 0x1a48
+#define mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_29 0x1a49
+#define mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_30 0x1a4a
+#define mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_GS_31 0x1a4b
+#define mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX 0
+#define mmSPI_SHADER_REQ_CTRL_ESGS 0x1a50
+#define mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS 0x1a51
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_0 0x1a52
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_ESGS_0 0x1a52
+#define mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_1 0x1a53
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_ESGS_1 0x1a53
+#define mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_2 0x1a54
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_ESGS_2 0x1a54
+#define mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_3 0x1a55
+#define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_ESGS_3 0x1a55
+#define mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x1a5c
+#define mmSPI_SHADER_PGM_RSRC2_ES_GS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC3_ES 0x1a67
+#define mmSPI_SHADER_PGM_RSRC3_ES_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_ES 0x1a68
+#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_ES 0x1a69
+#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_ES 0x1a6a
+#define mmSPI_SHADER_PGM_RSRC1_ES_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_ES 0x1a6b
+#define mmSPI_SHADER_PGM_RSRC2_ES_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_0 0x1a6c
+#define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_1 0x1a6d
+#define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_2 0x1a6e
+#define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_3 0x1a6f
+#define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_4 0x1a70
+#define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_5 0x1a71
+#define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_6 0x1a72
+#define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_7 0x1a73
+#define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_8 0x1a74
+#define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_9 0x1a75
+#define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_10 0x1a76
+#define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_11 0x1a77
+#define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_12 0x1a78
+#define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_13 0x1a79
+#define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_14 0x1a7a
+#define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ES_15 0x1a7b
+#define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x1a9d
+#define mmSPI_SHADER_PGM_RSRC2_LS_ES_BASE_IDX 0
+#define mmSPI_SHADER_PGM_CHKSUM_HS 0x1aa0
+#define mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC4_HS 0x1aa1
+#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x1aa2
+#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x1aa3
+#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_LS_HS 0x1aa4
+#define mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_LS_HS 0x1aa5
+#define mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC3_HS 0x1aa7
+#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_HS 0x1aa8
+#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_HS 0x1aa9
+#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_HS 0x1aaa
+#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_HS 0x1aab
+#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_0 0x1aac
+#define mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_1 0x1aad
+#define mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_2 0x1aae
+#define mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_3 0x1aaf
+#define mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_4 0x1ab0
+#define mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_5 0x1ab1
+#define mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_6 0x1ab2
+#define mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_7 0x1ab3
+#define mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_8 0x1ab4
+#define mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_9 0x1ab5
+#define mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_10 0x1ab6
+#define mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_11 0x1ab7
+#define mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_12 0x1ab8
+#define mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_13 0x1ab9
+#define mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_14 0x1aba
+#define mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_15 0x1abb
+#define mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_16 0x1abc
+#define mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_17 0x1abd
+#define mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_18 0x1abe
+#define mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_19 0x1abf
+#define mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_20 0x1ac0
+#define mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_21 0x1ac1
+#define mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_22 0x1ac2
+#define mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_23 0x1ac3
+#define mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_24 0x1ac4
+#define mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_25 0x1ac5
+#define mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_26 0x1ac6
+#define mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_27 0x1ac7
+#define mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_28 0x1ac8
+#define mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_29 0x1ac9
+#define mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_30 0x1aca
+#define mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_HS_31 0x1acb
+#define mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX 0
+#define mmSPI_SHADER_REQ_CTRL_LSHS 0x1ad0
+#define mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS 0x1ad1
+#define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_0 0x1ad2
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_LSHS_0 0x1ad2
+#define mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_1 0x1ad3
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_LSHS_1 0x1ad3
+#define mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_2 0x1ad4
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_LSHS_2 0x1ad4
+#define mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX 0
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_3 0x1ad5
+#define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_ACCUM_LSHS_3 0x1ad5
+#define mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x1add
+#define mmSPI_SHADER_PGM_RSRC2_LS_HS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC3_LS 0x1ae7
+#define mmSPI_SHADER_PGM_RSRC3_LS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_LO_LS 0x1ae8
+#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_HI_LS 0x1ae9
+#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC1_LS 0x1aea
+#define mmSPI_SHADER_PGM_RSRC1_LS_BASE_IDX 0
+#define mmSPI_SHADER_PGM_RSRC2_LS 0x1aeb
+#define mmSPI_SHADER_PGM_RSRC2_LS_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_0 0x1aec
+#define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_1 0x1aed
+#define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_2 0x1aee
+#define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_3 0x1aef
+#define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_4 0x1af0
+#define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_5 0x1af1
+#define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_6 0x1af2
+#define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_7 0x1af3
+#define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_8 0x1af4
+#define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_9 0x1af5
+#define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_10 0x1af6
+#define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_11 0x1af7
+#define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_12 0x1af8
+#define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_13 0x1af9
+#define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_14 0x1afa
+#define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0
+#define mmSPI_SHADER_USER_DATA_LS_15 0x1afb
+#define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_INITIATOR 0x1ba0
+#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0
+#define mmCOMPUTE_DIM_X 0x1ba1
+#define mmCOMPUTE_DIM_X_BASE_IDX 0
+#define mmCOMPUTE_DIM_Y 0x1ba2
+#define mmCOMPUTE_DIM_Y_BASE_IDX 0
+#define mmCOMPUTE_DIM_Z 0x1ba3
+#define mmCOMPUTE_DIM_Z_BASE_IDX 0
+#define mmCOMPUTE_START_X 0x1ba4
+#define mmCOMPUTE_START_X_BASE_IDX 0
+#define mmCOMPUTE_START_Y 0x1ba5
+#define mmCOMPUTE_START_Y_BASE_IDX 0
+#define mmCOMPUTE_START_Z 0x1ba6
+#define mmCOMPUTE_START_Z_BASE_IDX 0
+#define mmCOMPUTE_NUM_THREAD_X 0x1ba7
+#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0
+#define mmCOMPUTE_NUM_THREAD_Y 0x1ba8
+#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0
+#define mmCOMPUTE_NUM_THREAD_Z 0x1ba9
+#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0
+#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x1baa
+#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0
+#define mmCOMPUTE_PERFCOUNT_ENABLE 0x1bab
+#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0
+#define mmCOMPUTE_PGM_LO 0x1bac
+#define mmCOMPUTE_PGM_LO_BASE_IDX 0
+#define mmCOMPUTE_PGM_HI 0x1bad
+#define mmCOMPUTE_PGM_HI_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x1bae
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x1baf
+#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x1bb0
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x1bb1
+#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0
+#define mmCOMPUTE_PGM_RSRC1 0x1bb2
+#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0
+#define mmCOMPUTE_PGM_RSRC2 0x1bb3
+#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0
+#define mmCOMPUTE_VMID 0x1bb4
+#define mmCOMPUTE_VMID_BASE_IDX 0
+#define mmCOMPUTE_RESOURCE_LIMITS 0x1bb5
+#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0
+#define mmCOMPUTE_DESTINATION_EN_SE0 0x1bb6
+#define mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX 0
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x1bb6
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0
+#define mmCOMPUTE_DESTINATION_EN_SE1 0x1bb7
+#define mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX 0
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x1bb7
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0
+#define mmCOMPUTE_TMPRING_SIZE 0x1bb8
+#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0
+#define mmCOMPUTE_DESTINATION_EN_SE2 0x1bb9
+#define mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX 0
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x1bb9
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0
+#define mmCOMPUTE_DESTINATION_EN_SE3 0x1bba
+#define mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX 0
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x1bba
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0
+#define mmCOMPUTE_RESTART_X 0x1bbb
+#define mmCOMPUTE_RESTART_X_BASE_IDX 0
+#define mmCOMPUTE_RESTART_Y 0x1bbc
+#define mmCOMPUTE_RESTART_Y_BASE_IDX 0
+#define mmCOMPUTE_RESTART_Z 0x1bbd
+#define mmCOMPUTE_RESTART_Z_BASE_IDX 0
+#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x1bbe
+#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0
+#define mmCOMPUTE_MISC_RESERVED 0x1bbf
+#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_ID 0x1bc0
+#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0
+#define mmCOMPUTE_THREADGROUP_ID 0x1bc1
+#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0
+#define mmCOMPUTE_REQ_CTRL 0x1bc2
+#define mmCOMPUTE_REQ_CTRL_BASE_IDX 0
+#define mmCOMPUTE_PREF_PRI_ACCUM_0 0x1bc4
+#define mmCOMPUTE_PREF_PRI_ACCUM_0_BASE_IDX 0
+#define mmCOMPUTE_USER_ACCUM_0 0x1bc4
+#define mmCOMPUTE_USER_ACCUM_0_BASE_IDX 0
+#define mmCOMPUTE_PREF_PRI_ACCUM_1 0x1bc5
+#define mmCOMPUTE_PREF_PRI_ACCUM_1_BASE_IDX 0
+#define mmCOMPUTE_USER_ACCUM_1 0x1bc5
+#define mmCOMPUTE_USER_ACCUM_1_BASE_IDX 0
+#define mmCOMPUTE_PREF_PRI_ACCUM_2 0x1bc6
+#define mmCOMPUTE_PREF_PRI_ACCUM_2_BASE_IDX 0
+#define mmCOMPUTE_USER_ACCUM_2 0x1bc6
+#define mmCOMPUTE_USER_ACCUM_2_BASE_IDX 0
+#define mmCOMPUTE_PREF_PRI_ACCUM_3 0x1bc7
+#define mmCOMPUTE_PREF_PRI_ACCUM_3_BASE_IDX 0
+#define mmCOMPUTE_USER_ACCUM_3 0x1bc7
+#define mmCOMPUTE_USER_ACCUM_3_BASE_IDX 0
+#define mmCOMPUTE_PGM_RSRC3 0x1bc8
+#define mmCOMPUTE_PGM_RSRC3_BASE_IDX 0
+#define mmCOMPUTE_DDID_INDEX 0x1bc9
+#define mmCOMPUTE_DDID_INDEX_BASE_IDX 0
+#define mmCOMPUTE_SHADER_CHKSUM 0x1bca
+#define mmCOMPUTE_SHADER_CHKSUM_BASE_IDX 0
+#define mmCOMPUTE_RELAUNCH 0x1bcb
+#define mmCOMPUTE_RELAUNCH_BASE_IDX 0
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x1bcc
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x1bcd
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0
+#define mmCOMPUTE_RELAUNCH2 0x1bce
+#define mmCOMPUTE_RELAUNCH2_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_0 0x1be0
+#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_1 0x1be1
+#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_2 0x1be2
+#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_3 0x1be3
+#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_4 0x1be4
+#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_5 0x1be5
+#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_6 0x1be6
+#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_7 0x1be7
+#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_8 0x1be8
+#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_9 0x1be9
+#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_10 0x1bea
+#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_11 0x1beb
+#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_12 0x1bec
+#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_13 0x1bed
+#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_14 0x1bee
+#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0
+#define mmCOMPUTE_USER_DATA_15 0x1bef
+#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_TUNNEL 0x1c1d
+#define mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX 0
+#define mmCOMPUTE_DISPATCH_END 0x1c1e
+#define mmCOMPUTE_DISPATCH_END_BASE_IDX 0
+#define mmCOMPUTE_NOWHERE 0x1c1f
+#define mmCOMPUTE_NOWHERE_BASE_IDX 0
+
+
+// addressBlock: gc_cppdec
+// base address: 0xc080
+#define mmCP_EOPQ_WAIT_TIME 0x1dd5
+#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0
+#define mmCP_CPC_MGCG_SYNC_CNTL 0x1dd6
+#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0
+#define mmCPC_INT_INFO 0x1dd7
+#define mmCPC_INT_INFO_BASE_IDX 0
+#define mmCP_VIRT_STATUS 0x1dd8
+#define mmCP_VIRT_STATUS_BASE_IDX 0
+#define mmCPC_INT_ADDR 0x1dd9
+#define mmCPC_INT_ADDR_BASE_IDX 0
+#define mmCPC_INT_PASID 0x1dda
+#define mmCPC_INT_PASID_BASE_IDX 0
+#define mmCP_GFX_ERROR 0x1ddb
+#define mmCP_GFX_ERROR_BASE_IDX 0
+#define mmCPG_UTCL1_CNTL 0x1ddc
+#define mmCPG_UTCL1_CNTL_BASE_IDX 0
+#define mmCPC_UTCL1_CNTL 0x1ddd
+#define mmCPC_UTCL1_CNTL_BASE_IDX 0
+#define mmCPF_UTCL1_CNTL 0x1dde
+#define mmCPF_UTCL1_CNTL_BASE_IDX 0
+#define mmCP_AQL_SMM_STATUS 0x1ddf
+#define mmCP_AQL_SMM_STATUS_BASE_IDX 0
+#define mmCP_RB0_BASE 0x1de0
+#define mmCP_RB0_BASE_BASE_IDX 0
+#define mmCP_RB_BASE 0x1de0
+#define mmCP_RB_BASE_BASE_IDX 0
+#define mmCP_RB0_CNTL 0x1de1
+#define mmCP_RB0_CNTL_BASE_IDX 0
+#define mmCP_RB_CNTL 0x1de1
+#define mmCP_RB_CNTL_BASE_IDX 0
+#define mmCP_RB_RPTR_WR 0x1de2
+#define mmCP_RB_RPTR_WR_BASE_IDX 0
+#define mmCP_RB0_RPTR_ADDR 0x1de3
+#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0
+#define mmCP_RB_RPTR_ADDR 0x1de3
+#define mmCP_RB_RPTR_ADDR_BASE_IDX 0
+#define mmCP_RB0_RPTR_ADDR_HI 0x1de4
+#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_RB_RPTR_ADDR_HI 0x1de4
+#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_RB0_BUFSZ_MASK 0x1de5
+#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0
+#define mmCP_RB_BUFSZ_MASK 0x1de5
+#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0
+#define mmGC_PRIV_MODE 0x1de8
+#define mmGC_PRIV_MODE_BASE_IDX 0
+#define mmCP_INT_CNTL 0x1de9
+#define mmCP_INT_CNTL_BASE_IDX 0
+#define mmCP_INT_STATUS 0x1dea
+#define mmCP_INT_STATUS_BASE_IDX 0
+#define mmCP_DEVICE_ID 0x1deb
+#define mmCP_DEVICE_ID_BASE_IDX 0
+#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x1dec
+#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0
+#define mmCP_RING_PRIORITY_CNTS 0x1dec
+#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0
+#define mmCP_ME0_PIPE0_PRIORITY 0x1ded
+#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0
+#define mmCP_RING0_PRIORITY 0x1ded
+#define mmCP_RING0_PRIORITY_BASE_IDX 0
+#define mmCP_ME0_PIPE1_PRIORITY 0x1dee
+#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0
+#define mmCP_RING1_PRIORITY 0x1dee
+#define mmCP_RING1_PRIORITY_BASE_IDX 0
+#define mmCP_ME0_PIPE2_PRIORITY 0x1def
+#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0
+#define mmCP_RING2_PRIORITY 0x1def
+#define mmCP_RING2_PRIORITY_BASE_IDX 0
+#define mmCP_FATAL_ERROR 0x1df0
+#define mmCP_FATAL_ERROR_BASE_IDX 0
+#define mmCP_RB_VMID 0x1df1
+#define mmCP_RB_VMID_BASE_IDX 0
+#define mmCP_ME0_PIPE0_VMID 0x1df2
+#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0
+#define mmCP_ME0_PIPE1_VMID 0x1df3
+#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0
+#define mmCP_RB0_WPTR 0x1df4
+#define mmCP_RB0_WPTR_BASE_IDX 0
+#define mmCP_RB_WPTR 0x1df4
+#define mmCP_RB_WPTR_BASE_IDX 0
+#define mmCP_RB0_WPTR_HI 0x1df5
+#define mmCP_RB0_WPTR_HI_BASE_IDX 0
+#define mmCP_RB_WPTR_HI 0x1df5
+#define mmCP_RB_WPTR_HI_BASE_IDX 0
+#define mmCP_RB1_WPTR 0x1df6
+#define mmCP_RB1_WPTR_BASE_IDX 0
+#define mmCP_RB1_WPTR_HI 0x1df7
+#define mmCP_RB1_WPTR_HI_BASE_IDX 0
+#define mmCP_RB2_WPTR 0x1df8
+#define mmCP_RB2_WPTR_BASE_IDX 0
+#define mmCP_PROCESS_QUANTUM 0x1df9
+#define mmCP_PROCESS_QUANTUM_BASE_IDX 0
+#define mmCP_RB_DOORBELL_RANGE_LOWER 0x1dfa
+#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0
+#define mmCP_RB_DOORBELL_RANGE_UPPER 0x1dfb
+#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0
+#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x1dfc
+#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0
+#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x1dfd
+#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0
+#define mmCPG_UTCL1_ERROR 0x1dfe
+#define mmCPG_UTCL1_ERROR_BASE_IDX 0
+#define mmCPC_UTCL1_ERROR 0x1dff
+#define mmCPC_UTCL1_ERROR_BASE_IDX 0
+#define mmCP_RB1_BASE 0x1e00
+#define mmCP_RB1_BASE_BASE_IDX 0
+#define mmCP_RB1_CNTL 0x1e01
+#define mmCP_RB1_CNTL_BASE_IDX 0
+#define mmCP_RB1_RPTR_ADDR 0x1e02
+#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0
+#define mmCP_RB1_RPTR_ADDR_HI 0x1e03
+#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_RB1_BUFSZ_MASK 0x1e04
+#define mmCP_RB1_BUFSZ_MASK_BASE_IDX 0
+#define mmCP_RB2_BASE 0x1e05
+#define mmCP_RB2_BASE_BASE_IDX 0
+#define mmCP_RB2_CNTL 0x1e06
+#define mmCP_RB2_CNTL_BASE_IDX 0
+#define mmCP_RB2_RPTR_ADDR 0x1e07
+#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0
+#define mmCP_RB2_RPTR_ADDR_HI 0x1e08
+#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_INT_CNTL_RING0 0x1e0a
+#define mmCP_INT_CNTL_RING0_BASE_IDX 0
+#define mmCP_INT_CNTL_RING1 0x1e0b
+#define mmCP_INT_CNTL_RING1_BASE_IDX 0
+#define mmCP_INT_CNTL_RING2 0x1e0c
+#define mmCP_INT_CNTL_RING2_BASE_IDX 0
+#define mmCP_INT_STATUS_RING0 0x1e0d
+#define mmCP_INT_STATUS_RING0_BASE_IDX 0
+#define mmCP_INT_STATUS_RING1 0x1e0e
+#define mmCP_INT_STATUS_RING1_BASE_IDX 0
+#define mmCP_INT_STATUS_RING2 0x1e0f
+#define mmCP_INT_STATUS_RING2_BASE_IDX 0
+#define mmCP_PWR_CNTL 0x1e18
+#define mmCP_PWR_CNTL_BASE_IDX 0
+#define mmCP_MEM_SLP_CNTL 0x1e19
+#define mmCP_MEM_SLP_CNTL_BASE_IDX 0
+#define mmCP_ECC_FIRSTOCCURRENCE 0x1e1a
+#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x1e1b
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x1e1c
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x1e1d
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
+#define mmGB_EDC_MODE 0x1e1e
+#define mmGB_EDC_MODE_BASE_IDX 0
+#define mmCP_FETCHER_SOURCE 0x1e22
+#define mmCP_FETCHER_SOURCE_BASE_IDX 0
+#define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
+#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0
+#define mmCP_PQ_WPTR_POLL_CNTL1 0x1e24
+#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0
+#define mmCP_ME1_PIPE0_INT_CNTL 0x1e25
+#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0
+#define mmCP_ME1_PIPE1_INT_CNTL 0x1e26
+#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0
+#define mmCP_ME1_PIPE2_INT_CNTL 0x1e27
+#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0
+#define mmCP_ME1_PIPE3_INT_CNTL 0x1e28
+#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0
+#define mmCP_ME2_PIPE0_INT_CNTL 0x1e29
+#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0
+#define mmCP_ME2_PIPE1_INT_CNTL 0x1e2a
+#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0
+#define mmCP_ME2_PIPE2_INT_CNTL 0x1e2b
+#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0
+#define mmCP_ME2_PIPE3_INT_CNTL 0x1e2c
+#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0
+#define mmCP_ME1_PIPE0_INT_STATUS 0x1e2d
+#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0
+#define mmCP_ME1_PIPE1_INT_STATUS 0x1e2e
+#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0
+#define mmCP_ME1_PIPE2_INT_STATUS 0x1e2f
+#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0
+#define mmCP_ME1_PIPE3_INT_STATUS 0x1e30
+#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0
+#define mmCP_ME2_PIPE0_INT_STATUS 0x1e31
+#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0
+#define mmCP_ME2_PIPE1_INT_STATUS 0x1e32
+#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0
+#define mmCP_ME2_PIPE2_INT_STATUS 0x1e33
+#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0
+#define mmCP_ME2_PIPE3_INT_STATUS 0x1e34
+#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0
+#define mmCP_GFX_QUEUE_INDEX 0x1e37
+#define mmCP_GFX_QUEUE_INDEX_BASE_IDX 0
+#define mmCC_GC_EDC_CONFIG 0x1e38
+#define mmCC_GC_EDC_CONFIG_BASE_IDX 0
+#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1e39
+#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0
+#define mmCP_ME1_PIPE0_PRIORITY 0x1e3a
+#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0
+#define mmCP_ME1_PIPE1_PRIORITY 0x1e3b
+#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0
+#define mmCP_ME1_PIPE2_PRIORITY 0x1e3c
+#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0
+#define mmCP_ME1_PIPE3_PRIORITY 0x1e3d
+#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0
+#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x1e3e
+#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0
+#define mmCP_ME2_PIPE0_PRIORITY 0x1e3f
+#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0
+#define mmCP_ME2_PIPE1_PRIORITY 0x1e40
+#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0
+#define mmCP_ME2_PIPE2_PRIORITY 0x1e41
+#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0
+#define mmCP_ME2_PIPE3_PRIORITY 0x1e42
+#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0
+#define mmCP_CE_PRGRM_CNTR_START 0x1e43
+#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_PFP_PRGRM_CNTR_START 0x1e44
+#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_ME_PRGRM_CNTR_START 0x1e45
+#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_MEC1_PRGRM_CNTR_START 0x1e46
+#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_MEC2_PRGRM_CNTR_START 0x1e47
+#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0
+#define mmCP_CE_INTR_ROUTINE_START 0x1e48
+#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_PFP_INTR_ROUTINE_START 0x1e49
+#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_ME_INTR_ROUTINE_START 0x1e4a
+#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_MEC1_INTR_ROUTINE_START 0x1e4b
+#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_MEC2_INTR_ROUTINE_START 0x1e4c
+#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0
+#define mmCP_CONTEXT_CNTL 0x1e4d
+#define mmCP_CONTEXT_CNTL_BASE_IDX 0
+#define mmCP_MAX_CONTEXT 0x1e4e
+#define mmCP_MAX_CONTEXT_BASE_IDX 0
+#define mmCP_IQ_WAIT_TIME1 0x1e4f
+#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0
+#define mmCP_IQ_WAIT_TIME2 0x1e50
+#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0
+#define mmCP_RB0_BASE_HI 0x1e51
+#define mmCP_RB0_BASE_HI_BASE_IDX 0
+#define mmCP_RB1_BASE_HI 0x1e52
+#define mmCP_RB1_BASE_HI_BASE_IDX 0
+#define mmCP_VMID_RESET 0x1e53
+#define mmCP_VMID_RESET_BASE_IDX 0
+#define mmCPC_INT_CNTL 0x1e54
+#define mmCPC_INT_CNTL_BASE_IDX 0
+#define mmCPC_INT_STATUS 0x1e55
+#define mmCPC_INT_STATUS_BASE_IDX 0
+#define mmCP_VMID_PREEMPT 0x1e56
+#define mmCP_VMID_PREEMPT_BASE_IDX 0
+#define mmCPC_INT_CNTX_ID 0x1e57
+#define mmCPC_INT_CNTX_ID_BASE_IDX 0
+#define mmCP_PQ_STATUS 0x1e58
+#define mmCP_PQ_STATUS_BASE_IDX 0
+#define mmCP_CE_CS_PARTITION_INDEX 0x1e59
+#define mmCP_CE_CS_PARTITION_INDEX_BASE_IDX 0
+#define mmCP_MEC1_F32_INT_DIS 0x1e5d
+#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0
+#define mmCP_MEC2_F32_INT_DIS 0x1e5e
+#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0
+#define mmCP_VMID_STATUS 0x1e5f
+#define mmCP_VMID_STATUS_BASE_IDX 0
+#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x1e60
+#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0
+#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x1e61
+#define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0
+#define mmCPC_SUSPEND_CTX_SAVE_CONTROL 0x1e62
+#define mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 0
+#define mmCPC_SUSPEND_CNTL_STACK_OFFSET 0x1e63
+#define mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0
+#define mmCPC_SUSPEND_CNTL_STACK_SIZE 0x1e64
+#define mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 0
+#define mmCPC_SUSPEND_WG_STATE_OFFSET 0x1e65
+#define mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0
+#define mmCPC_SUSPEND_CTX_SAVE_SIZE 0x1e66
+#define mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 0
+#define mmCPC_OS_PIPES 0x1e67
+#define mmCPC_OS_PIPES_BASE_IDX 0
+#define mmCP_SUSPEND_RESUME_REQ 0x1e68
+#define mmCP_SUSPEND_RESUME_REQ_BASE_IDX 0
+#define mmCP_SUSPEND_CNTL 0x1e69
+#define mmCP_SUSPEND_CNTL_BASE_IDX 0
+#define mmCP_IQ_WAIT_TIME3 0x1e6a
+#define mmCP_IQ_WAIT_TIME3_BASE_IDX 0
+#define mmCPC_DDID_BASE_ADDR_LO 0x1e6b
+#define mmCPC_DDID_BASE_ADDR_LO_BASE_IDX 0
+#define mmCP_DDID_BASE_ADDR_LO 0x1e6b
+#define mmCP_DDID_BASE_ADDR_LO_BASE_IDX 0
+#define mmCPC_DDID_BASE_ADDR_HI 0x1e6c
+#define mmCPC_DDID_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_DDID_BASE_ADDR_HI 0x1e6c
+#define mmCP_DDID_BASE_ADDR_HI_BASE_IDX 0
+#define mmCPC_DDID_CNTL 0x1e6d
+#define mmCPC_DDID_CNTL_BASE_IDX 0
+#define mmCP_DDID_CNTL 0x1e6d
+#define mmCP_DDID_CNTL_BASE_IDX 0
+#define mmCP_GFX_DDID_INFLIGHT_COUNT 0x1e6e
+#define mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX 0
+#define mmCP_GFX_DDID_WPTR 0x1e6f
+#define mmCP_GFX_DDID_WPTR_BASE_IDX 0
+#define mmCP_GFX_DDID_RPTR 0x1e70
+#define mmCP_GFX_DDID_RPTR_BASE_IDX 0
+#define mmCP_GFX_DDID_DELTA_RPT_COUNT 0x1e71
+#define mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX 0
+#define mmCP_GFX_HPD_STATUS0 0x1e72
+#define mmCP_GFX_HPD_STATUS0_BASE_IDX 0
+#define mmCP_GFX_HPD_CONTROL0 0x1e73
+#define mmCP_GFX_HPD_CONTROL0_BASE_IDX 0
+#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO 0x1e74
+#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX 0
+#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI 0x1e75
+#define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX 0
+#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO 0x1e76
+#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX 0
+#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI 0x1e77
+#define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX 0
+#define mmCP_GFX_INDEX_MUTEX 0x1e78
+#define mmCP_GFX_INDEX_MUTEX_BASE_IDX 0
+#define mmCP_GFX_MQD_BASE_ADDR 0x1e7e
+#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0
+#define mmCP_GFX_MQD_BASE_ADDR_HI 0x1e7f
+#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_GFX_HQD_ACTIVE 0x1e80
+#define mmCP_GFX_HQD_ACTIVE_BASE_IDX 0
+#define mmCP_GFX_HQD_VMID 0x1e81
+#define mmCP_GFX_HQD_VMID_BASE_IDX 0
+#define mmCP_GFX_HQD_QUEUE_PRIORITY 0x1e84
+#define mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX 0
+#define mmCP_GFX_HQD_QUANTUM 0x1e85
+#define mmCP_GFX_HQD_QUANTUM_BASE_IDX 0
+#define mmCP_GFX_HQD_BASE 0x1e86
+#define mmCP_GFX_HQD_BASE_BASE_IDX 0
+#define mmCP_GFX_HQD_BASE_HI 0x1e87
+#define mmCP_GFX_HQD_BASE_HI_BASE_IDX 0
+#define mmCP_GFX_HQD_RPTR 0x1e88
+#define mmCP_GFX_HQD_RPTR_BASE_IDX 0
+#define mmCP_GFX_HQD_RPTR_ADDR 0x1e89
+#define mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX 0
+#define mmCP_GFX_HQD_RPTR_ADDR_HI 0x1e8a
+#define mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1e8b
+#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1e8c
+#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CONTROL 0x1e8d
+#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0
+#define mmCP_GFX_HQD_OFFSET 0x1e8e
+#define mmCP_GFX_HQD_OFFSET_BASE_IDX 0
+#define mmCP_GFX_HQD_CNTL 0x1e8f
+#define mmCP_GFX_HQD_CNTL_BASE_IDX 0
+#define mmCP_GFX_HQD_CSMD_RPTR 0x1e90
+#define mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX 0
+#define mmCP_GFX_HQD_WPTR 0x1e91
+#define mmCP_GFX_HQD_WPTR_BASE_IDX 0
+#define mmCP_GFX_HQD_WPTR_HI 0x1e92
+#define mmCP_GFX_HQD_WPTR_HI_BASE_IDX 0
+#define mmCP_GFX_HQD_DEQUEUE_REQUEST 0x1e93
+#define mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX 0
+#define mmCP_GFX_HQD_MAPPED 0x1e94
+#define mmCP_GFX_HQD_MAPPED_BASE_IDX 0
+#define mmCP_GFX_HQD_QUE_MGR_CONTROL 0x1e95
+#define mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX 0
+#define mmCP_GFX_HQD_HQ_STATUS0 0x1e98
+#define mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX 0
+#define mmCP_GFX_HQD_HQ_CONTROL0 0x1e99
+#define mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX 0
+#define mmCP_GFX_MQD_CONTROL 0x1e9a
+#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0
+#define mmCP_HQD_GFX_CONTROL 0x1e9f
+#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0
+#define mmCP_HQD_GFX_STATUS 0x1ea0
+#define mmCP_HQD_GFX_STATUS_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_RPTR_WR 0x1ea1
+#define mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_BASE 0x1ea2
+#define mmCP_GFX_HQD_CE_BASE_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_BASE_HI 0x1ea3
+#define mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_RPTR 0x1ea4
+#define mmCP_GFX_HQD_CE_RPTR_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_RPTR_ADDR 0x1ea5
+#define mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_RPTR_ADDR_HI 0x1ea6
+#define mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO 0x1ea7
+#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI 0x1ea8
+#define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_OFFSET 0x1ea9
+#define mmCP_GFX_HQD_CE_OFFSET_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_CNTL 0x1eaa
+#define mmCP_GFX_HQD_CE_CNTL_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_CSMD_RPTR 0x1eab
+#define mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_WPTR 0x1eac
+#define mmCP_GFX_HQD_CE_WPTR_BASE_IDX 0
+#define mmCP_GFX_HQD_CE_WPTR_HI 0x1ead
+#define mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX 0
+#define mmCP_CE_DOORBELL_CONTROL 0x1eae
+#define mmCP_CE_DOORBELL_CONTROL_BASE_IDX 0
+#define mmCP_DMA_WATCH0_ADDR_LO 0x1ec0
+#define mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX 0
+#define mmCP_DMA_WATCH0_ADDR_HI 0x1ec1
+#define mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX 0
+#define mmCP_DMA_WATCH0_MASK 0x1ec2
+#define mmCP_DMA_WATCH0_MASK_BASE_IDX 0
+#define mmCP_DMA_WATCH0_CNTL 0x1ec3
+#define mmCP_DMA_WATCH0_CNTL_BASE_IDX 0
+#define mmCP_DMA_WATCH1_ADDR_LO 0x1ec4
+#define mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX 0
+#define mmCP_DMA_WATCH1_ADDR_HI 0x1ec5
+#define mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX 0
+#define mmCP_DMA_WATCH1_MASK 0x1ec6
+#define mmCP_DMA_WATCH1_MASK_BASE_IDX 0
+#define mmCP_DMA_WATCH1_CNTL 0x1ec7
+#define mmCP_DMA_WATCH1_CNTL_BASE_IDX 0
+#define mmCP_DMA_WATCH2_ADDR_LO 0x1ec8
+#define mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX 0
+#define mmCP_DMA_WATCH2_ADDR_HI 0x1ec9
+#define mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX 0
+#define mmCP_DMA_WATCH2_MASK 0x1eca
+#define mmCP_DMA_WATCH2_MASK_BASE_IDX 0
+#define mmCP_DMA_WATCH2_CNTL 0x1ecb
+#define mmCP_DMA_WATCH2_CNTL_BASE_IDX 0
+#define mmCP_DMA_WATCH3_ADDR_LO 0x1ecc
+#define mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX 0
+#define mmCP_DMA_WATCH3_ADDR_HI 0x1ecd
+#define mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX 0
+#define mmCP_DMA_WATCH3_MASK 0x1ece
+#define mmCP_DMA_WATCH3_MASK_BASE_IDX 0
+#define mmCP_DMA_WATCH3_CNTL 0x1ecf
+#define mmCP_DMA_WATCH3_CNTL_BASE_IDX 0
+#define mmCP_DMA_WATCH_STAT_ADDR_LO 0x1ed0
+#define mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX 0
+#define mmCP_DMA_WATCH_STAT_ADDR_HI 0x1ed1
+#define mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX 0
+#define mmCP_DMA_WATCH_STAT 0x1ed2
+#define mmCP_DMA_WATCH_STAT_BASE_IDX 0
+#define mmCP_PFP_JT_STAT 0x1ed3
+#define mmCP_PFP_JT_STAT_BASE_IDX 0
+#define mmCP_CE_JT_STAT 0x1ed4
+#define mmCP_CE_JT_STAT_BASE_IDX 0
+#define mmCP_MEC_JT_STAT 0x1ed5
+#define mmCP_MEC_JT_STAT_BASE_IDX 0
+#define mmCP_RB_DOORBELL_CLEAR 0x1f28
+#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0
+#define mmCP_RB0_ACTIVE 0x1f40
+#define mmCP_RB0_ACTIVE_BASE_IDX 0
+#define mmCP_RB_ACTIVE 0x1f40
+#define mmCP_RB_ACTIVE_BASE_IDX 0
+#define mmCP_RB1_ACTIVE 0x1f41
+#define mmCP_RB1_ACTIVE_BASE_IDX 0
+#define mmCP_RB_STATUS 0x1f43
+#define mmCP_RB_STATUS_BASE_IDX 0
+#define mmCPG_RCIU_CAM_INDEX 0x1f44
+#define mmCPG_RCIU_CAM_INDEX_BASE_IDX 0
+#define mmCPG_RCIU_CAM_DATA 0x1f45
+#define mmCPG_RCIU_CAM_DATA_BASE_IDX 0
+#define mmCPG_RCIU_CAM_DATA_PHASE0 0x1f45
+#define mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX 0
+#define mmCPG_RCIU_CAM_DATA_PHASE1 0x1f45
+#define mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX 0
+#define mmCPG_RCIU_CAM_DATA_PHASE2 0x1f45
+#define mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX 0
+#define mmCPF_GCR_CNTL 0x1f53
+#define mmCPF_GCR_CNTL_BASE_IDX 0
+#define mmCPG_UTCL1_STATUS 0x1f54
+#define mmCPG_UTCL1_STATUS_BASE_IDX 0
+#define mmCPC_UTCL1_STATUS 0x1f55
+#define mmCPC_UTCL1_STATUS_BASE_IDX 0
+#define mmCPF_UTCL1_STATUS 0x1f56
+#define mmCPF_UTCL1_STATUS_BASE_IDX 0
+#define mmCP_SD_CNTL 0x1f57
+#define mmCP_SD_CNTL_BASE_IDX 0
+#define mmCP_SOFT_RESET_CNTL 0x1f59
+#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0
+#define mmCP_CPC_GFX_CNTL 0x1f5a
+#define mmCP_CPC_GFX_CNTL_BASE_IDX 0
+
+
+// addressBlock: gc_spipdec
+// base address: 0xc700
+#define mmSPI_ARB_PRIORITY 0x1f60
+#define mmSPI_ARB_PRIORITY_BASE_IDX 0
+#define mmSPI_ARB_CYCLES_0 0x1f61
+#define mmSPI_ARB_CYCLES_0_BASE_IDX 0
+#define mmSPI_ARB_CYCLES_1 0x1f62
+#define mmSPI_ARB_CYCLES_1_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_GFX 0x1f67
+#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x1f68
+#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS0 0x1f69
+#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS1 0x1f6a
+#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS2 0x1f6b
+#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS3 0x1f6c
+#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS4 0x1f6d
+#define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS5 0x1f6e
+#define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS6 0x1f6f
+#define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0
+#define mmSPI_WCL_PIPE_PERCENT_CS7 0x1f70
+#define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0
+#define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b
+#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_0 0x1f7c
+#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_1 0x1f7d
+#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_2 0x1f7e
+#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_3 0x1f7f
+#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_4 0x1f80
+#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_5 0x1f81
+#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_6 0x1f82
+#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_7 0x1f83
+#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_8 0x1f84
+#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_9 0x1f85
+#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x1f86
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x1f87
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x1f88
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x1f89
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x1f8a
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x1f8b
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x1f8c
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x1f8d
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x1f8e
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x1f8f
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_10 0x1f90
+#define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_11 0x1f91
+#define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x1f92
+#define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x1f93
+#define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_12 0x1f94
+#define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_13 0x1f95
+#define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_14 0x1f96
+#define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_CU_15 0x1f97
+#define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x1f98
+#define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x1f99
+#define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x1f9a
+#define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0
+#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x1f9b
+#define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0
+#define mmSPI_COMPUTE_WF_CTX_SAVE 0x1f9c
+#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0
+#define mmSPI_ARB_CNTL_0 0x1f9d
+#define mmSPI_ARB_CNTL_0_BASE_IDX 0
+#define mmSPI_FEATURE_CTRL 0x1f9e
+#define mmSPI_FEATURE_CTRL_BASE_IDX 0
+#define mmSPI_SHADER_RSRC_LIMIT_CTRL 0x1f9f
+#define mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX 0
+
+
+// addressBlock: gc_cpphqddec
+// base address: 0xc800
+#define mmCP_HPD_MES_ROQ_OFFSETS 0x1fa4
+#define mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX 0
+#define mmCP_HPD_ROQ_OFFSETS 0x1fa4
+#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0
+#define mmCP_HPD_STATUS0 0x1fa5
+#define mmCP_HPD_STATUS0_BASE_IDX 0
+#define mmCP_HPD_UTCL1_CNTL 0x1fa6
+#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0
+#define mmCP_HPD_UTCL1_ERROR 0x1fa7
+#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0
+#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1fa8
+#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0
+#define mmCP_MQD_BASE_ADDR 0x1fa9
+#define mmCP_MQD_BASE_ADDR_BASE_IDX 0
+#define mmCP_MQD_BASE_ADDR_HI 0x1faa
+#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_ACTIVE 0x1fab
+#define mmCP_HQD_ACTIVE_BASE_IDX 0
+#define mmCP_HQD_VMID 0x1fac
+#define mmCP_HQD_VMID_BASE_IDX 0
+#define mmCP_HQD_PERSISTENT_STATE 0x1fad
+#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0
+#define mmCP_HQD_PIPE_PRIORITY 0x1fae
+#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0
+#define mmCP_HQD_QUEUE_PRIORITY 0x1faf
+#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0
+#define mmCP_HQD_QUANTUM 0x1fb0
+#define mmCP_HQD_QUANTUM_BASE_IDX 0
+#define mmCP_HQD_PQ_BASE 0x1fb1
+#define mmCP_HQD_PQ_BASE_BASE_IDX 0
+#define mmCP_HQD_PQ_BASE_HI 0x1fb2
+#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0
+#define mmCP_HQD_PQ_RPTR 0x1fb3
+#define mmCP_HQD_PQ_RPTR_BASE_IDX 0
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1fb7
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8
+#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0
+#define mmCP_HQD_PQ_CONTROL 0x1fba
+#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0
+#define mmCP_HQD_IB_BASE_ADDR 0x1fbb
+#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0
+#define mmCP_HQD_IB_BASE_ADDR_HI 0x1fbc
+#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_IB_RPTR 0x1fbd
+#define mmCP_HQD_IB_RPTR_BASE_IDX 0
+#define mmCP_HQD_IB_CONTROL 0x1fbe
+#define mmCP_HQD_IB_CONTROL_BASE_IDX 0
+#define mmCP_HQD_IQ_TIMER 0x1fbf
+#define mmCP_HQD_IQ_TIMER_BASE_IDX 0
+#define mmCP_HQD_IQ_RPTR 0x1fc0
+#define mmCP_HQD_IQ_RPTR_BASE_IDX 0
+#define mmCP_HQD_DEQUEUE_REQUEST 0x1fc1
+#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0
+#define mmCP_HQD_DMA_OFFLOAD 0x1fc2
+#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0
+#define mmCP_HQD_OFFLOAD 0x1fc2
+#define mmCP_HQD_OFFLOAD_BASE_IDX 0
+#define mmCP_HQD_SEMA_CMD 0x1fc3
+#define mmCP_HQD_SEMA_CMD_BASE_IDX 0
+#define mmCP_HQD_MSG_TYPE 0x1fc4
+#define mmCP_HQD_MSG_TYPE_BASE_IDX 0
+#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1fc5
+#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0
+#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1fc6
+#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0
+#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1fc7
+#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0
+#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1fc8
+#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0
+#define mmCP_HQD_HQ_SCHEDULER0 0x1fc9
+#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0
+#define mmCP_HQD_HQ_STATUS0 0x1fc9
+#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0
+#define mmCP_HQD_HQ_CONTROL0 0x1fca
+#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0
+#define mmCP_HQD_HQ_SCHEDULER1 0x1fca
+#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0
+#define mmCP_MQD_CONTROL 0x1fcb
+#define mmCP_MQD_CONTROL_BASE_IDX 0
+#define mmCP_HQD_HQ_STATUS1 0x1fcc
+#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0
+#define mmCP_HQD_HQ_CONTROL1 0x1fcd
+#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0
+#define mmCP_HQD_EOP_BASE_ADDR 0x1fce
+#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0
+#define mmCP_HQD_EOP_BASE_ADDR_HI 0x1fcf
+#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_EOP_CONTROL 0x1fd0
+#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0
+#define mmCP_HQD_EOP_RPTR 0x1fd1
+#define mmCP_HQD_EOP_RPTR_BASE_IDX 0
+#define mmCP_HQD_EOP_WPTR 0x1fd2
+#define mmCP_HQD_EOP_WPTR_BASE_IDX 0
+#define mmCP_HQD_EOP_EVENTS 0x1fd3
+#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1fd4
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1fd5
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0
+#define mmCP_HQD_CTX_SAVE_CONTROL 0x1fd6
+#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0
+#define mmCP_HQD_CNTL_STACK_OFFSET 0x1fd7
+#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0
+#define mmCP_HQD_CNTL_STACK_SIZE 0x1fd8
+#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0
+#define mmCP_HQD_WG_STATE_OFFSET 0x1fd9
+#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0
+#define mmCP_HQD_CTX_SAVE_SIZE 0x1fda
+#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0
+#define mmCP_HQD_GDS_RESOURCE_STATE 0x1fdb
+#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0
+#define mmCP_HQD_ERROR 0x1fdc
+#define mmCP_HQD_ERROR_BASE_IDX 0
+#define mmCP_HQD_EOP_WPTR_MEM 0x1fdd
+#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0
+#define mmCP_HQD_AQL_CONTROL 0x1fde
+#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0
+#define mmCP_HQD_PQ_WPTR_LO 0x1fdf
+#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0
+#define mmCP_HQD_PQ_WPTR_HI 0x1fe0
+#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0
+#define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET 0x1fe1
+#define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0
+#define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT 0x1fe2
+#define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX 0
+#define mmCP_HQD_SUSPEND_WG_STATE_OFFSET 0x1fe3
+#define mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0
+#define mmCP_HQD_DDID_RPTR 0x1fe4
+#define mmCP_HQD_DDID_RPTR_BASE_IDX 0
+#define mmCP_HQD_DDID_WPTR 0x1fe5
+#define mmCP_HQD_DDID_WPTR_BASE_IDX 0
+#define mmCP_HQD_DDID_INFLIGHT_COUNT 0x1fe6
+#define mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX 0
+#define mmCP_HQD_DDID_DELTA_RPT_COUNT 0x1fe7
+#define mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX 0
+#define mmCP_HQD_DEQUEUE_STATUS 0x1fe8
+#define mmCP_HQD_DEQUEUE_STATUS_BASE_IDX 0
+
+
+// addressBlock: gc_didtdec
+// base address: 0xca00
+#define mmDIDT_IND_INDEX 0x2020
+#define mmDIDT_IND_INDEX_BASE_IDX 0
+#define mmDIDT_IND_DATA 0x2021
+#define mmDIDT_IND_DATA_BASE_IDX 0
+#define mmDIDT_INDEX_AUTO_INCR_EN 0x2022
+#define mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 0
+
+
+// addressBlock: gc_gccacdec
+// base address: 0xca10
+#define mmGC_CAC_CTRL_1 0x2024
+#define mmGC_CAC_CTRL_1_BASE_IDX 0
+#define mmGC_CAC_CTRL_2 0x2025
+#define mmGC_CAC_CTRL_2_BASE_IDX 0
+#define mmGC_CAC_AGGR_LOWER 0x2026
+#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0
+#define mmGC_CAC_AGGR_UPPER 0x2027
+#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0
+#define mmGC_CAC_SOFT_CTRL 0x2028
+#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0
+#define mmGC_DIDT_CTRL0 0x2029
+#define mmGC_DIDT_CTRL0_BASE_IDX 0
+#define mmGC_DIDT_CTRL1 0x202a
+#define mmGC_DIDT_CTRL1_BASE_IDX 0
+#define mmGC_DIDT_CTRL2 0x202b
+#define mmGC_DIDT_CTRL2_BASE_IDX 0
+#define mmGC_DIDT_WEIGHT 0x202c
+#define mmGC_DIDT_WEIGHT_BASE_IDX 0
+#define mmGC_THROTTLE_CTRL 0x202d
+#define mmGC_THROTTLE_CTRL_BASE_IDX 0
+#define mmGC_EDC_CTRL 0x202e
+#define mmGC_EDC_CTRL_BASE_IDX 0
+#define mmGC_EDC_THRESHOLD 0x202f
+#define mmGC_EDC_THRESHOLD_BASE_IDX 0
+#define mmGC_EDC_STATUS 0x2030
+#define mmGC_EDC_STATUS_BASE_IDX 0
+#define mmGC_EDC_OVERFLOW 0x2031
+#define mmGC_EDC_OVERFLOW_BASE_IDX 0
+#define mmGC_EDC_ROLLING_POWER_DELTA 0x2032
+#define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0
+#define mmGC_THROTTLE_CTRL1 0x2033
+#define mmGC_THROTTLE_CTRL1_BASE_IDX 0
+#define mmGC_THROTTLE_STATUS 0x2036
+#define mmGC_THROTTLE_STATUS_BASE_IDX 0
+#define mmEDC_PERF_COUNTER 0x2037
+#define mmEDC_PERF_COUNTER_BASE_IDX 0
+#define mmPCC_PERF_COUNTER 0x2038
+#define mmPCC_PERF_COUNTER_BASE_IDX 0
+#define mmPWRBRK_PERF_COUNTER 0x2039
+#define mmPWRBRK_PERF_COUNTER_BASE_IDX 0
+#define mmGC_CAC_IND_INDEX 0x203c
+#define mmGC_CAC_IND_INDEX_BASE_IDX 0
+#define mmGC_CAC_IND_DATA 0x203d
+#define mmGC_CAC_IND_DATA_BASE_IDX 0
+#define mmSE_CAC_IND_INDEX 0x203e
+#define mmSE_CAC_IND_INDEX_BASE_IDX 0
+#define mmSE_CAC_IND_DATA 0x203f
+#define mmSE_CAC_IND_DATA_BASE_IDX 0
+
+
+// addressBlock: gc_tcpdec
+// base address: 0xca80
+#define mmTCP_WATCH0_ADDR_H 0x2040
+#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0
+#define mmTCP_WATCH0_ADDR_L 0x2041
+#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0
+#define mmTCP_WATCH0_CNTL 0x2042
+#define mmTCP_WATCH0_CNTL_BASE_IDX 0
+#define mmTCP_WATCH1_ADDR_H 0x2043
+#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0
+#define mmTCP_WATCH1_ADDR_L 0x2044
+#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0
+#define mmTCP_WATCH1_CNTL 0x2045
+#define mmTCP_WATCH1_CNTL_BASE_IDX 0
+#define mmTCP_WATCH2_ADDR_H 0x2046
+#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0
+#define mmTCP_WATCH2_ADDR_L 0x2047
+#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0
+#define mmTCP_WATCH2_CNTL 0x2048
+#define mmTCP_WATCH2_CNTL_BASE_IDX 0
+#define mmTCP_WATCH3_ADDR_H 0x2049
+#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0
+#define mmTCP_WATCH3_ADDR_L 0x204a
+#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0
+#define mmTCP_WATCH3_CNTL 0x204b
+#define mmTCP_WATCH3_CNTL_BASE_IDX 0
+#define mmTCP_CNTL2 0x2054
+#define mmTCP_CNTL2_BASE_IDX 0
+#define mmTCP_UTCL0_CNTL1 0x2055
+#define mmTCP_UTCL0_CNTL1_BASE_IDX 0
+#define mmTCP_UTCL0_CNTL2 0x2056
+#define mmTCP_UTCL0_CNTL2_BASE_IDX 0
+#define mmTCP_UTCL0_STATUS 0x2057
+#define mmTCP_UTCL0_STATUS_BASE_IDX 0
+#define mmTCP_PERFCOUNTER_FILTER 0x2059
+#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0
+#define mmTCP_PERFCOUNTER_FILTER_EN 0x205a
+#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0
+#define mmTCP_PERFCOUNTER_FILTER2 0x205b
+#define mmTCP_PERFCOUNTER_FILTER2_BASE_IDX 0
+
+
+// addressBlock: gc_gdspdec
+// base address: 0xcc00
+#define mmGDS_VMID0_BASE 0x20a0
+#define mmGDS_VMID0_BASE_BASE_IDX 0
+#define mmGDS_VMID0_SIZE 0x20a1
+#define mmGDS_VMID0_SIZE_BASE_IDX 0
+#define mmGDS_VMID1_BASE 0x20a2
+#define mmGDS_VMID1_BASE_BASE_IDX 0
+#define mmGDS_VMID1_SIZE 0x20a3
+#define mmGDS_VMID1_SIZE_BASE_IDX 0
+#define mmGDS_VMID2_BASE 0x20a4
+#define mmGDS_VMID2_BASE_BASE_IDX 0
+#define mmGDS_VMID2_SIZE 0x20a5
+#define mmGDS_VMID2_SIZE_BASE_IDX 0
+#define mmGDS_VMID3_BASE 0x20a6
+#define mmGDS_VMID3_BASE_BASE_IDX 0
+#define mmGDS_VMID3_SIZE 0x20a7
+#define mmGDS_VMID3_SIZE_BASE_IDX 0
+#define mmGDS_VMID4_BASE 0x20a8
+#define mmGDS_VMID4_BASE_BASE_IDX 0
+#define mmGDS_VMID4_SIZE 0x20a9
+#define mmGDS_VMID4_SIZE_BASE_IDX 0
+#define mmGDS_VMID5_BASE 0x20aa
+#define mmGDS_VMID5_BASE_BASE_IDX 0
+#define mmGDS_VMID5_SIZE 0x20ab
+#define mmGDS_VMID5_SIZE_BASE_IDX 0
+#define mmGDS_VMID6_BASE 0x20ac
+#define mmGDS_VMID6_BASE_BASE_IDX 0
+#define mmGDS_VMID6_SIZE 0x20ad
+#define mmGDS_VMID6_SIZE_BASE_IDX 0
+#define mmGDS_VMID7_BASE 0x20ae
+#define mmGDS_VMID7_BASE_BASE_IDX 0
+#define mmGDS_VMID7_SIZE 0x20af
+#define mmGDS_VMID7_SIZE_BASE_IDX 0
+#define mmGDS_VMID8_BASE 0x20b0
+#define mmGDS_VMID8_BASE_BASE_IDX 0
+#define mmGDS_VMID8_SIZE 0x20b1
+#define mmGDS_VMID8_SIZE_BASE_IDX 0
+#define mmGDS_VMID9_BASE 0x20b2
+#define mmGDS_VMID9_BASE_BASE_IDX 0
+#define mmGDS_VMID9_SIZE 0x20b3
+#define mmGDS_VMID9_SIZE_BASE_IDX 0
+#define mmGDS_VMID10_BASE 0x20b4
+#define mmGDS_VMID10_BASE_BASE_IDX 0
+#define mmGDS_VMID10_SIZE 0x20b5
+#define mmGDS_VMID10_SIZE_BASE_IDX 0
+#define mmGDS_VMID11_BASE 0x20b6
+#define mmGDS_VMID11_BASE_BASE_IDX 0
+#define mmGDS_VMID11_SIZE 0x20b7
+#define mmGDS_VMID11_SIZE_BASE_IDX 0
+#define mmGDS_VMID12_BASE 0x20b8
+#define mmGDS_VMID12_BASE_BASE_IDX 0
+#define mmGDS_VMID12_SIZE 0x20b9
+#define mmGDS_VMID12_SIZE_BASE_IDX 0
+#define mmGDS_VMID13_BASE 0x20ba
+#define mmGDS_VMID13_BASE_BASE_IDX 0
+#define mmGDS_VMID13_SIZE 0x20bb
+#define mmGDS_VMID13_SIZE_BASE_IDX 0
+#define mmGDS_VMID14_BASE 0x20bc
+#define mmGDS_VMID14_BASE_BASE_IDX 0
+#define mmGDS_VMID14_SIZE 0x20bd
+#define mmGDS_VMID14_SIZE_BASE_IDX 0
+#define mmGDS_VMID15_BASE 0x20be
+#define mmGDS_VMID15_BASE_BASE_IDX 0
+#define mmGDS_VMID15_SIZE 0x20bf
+#define mmGDS_VMID15_SIZE_BASE_IDX 0
+#define mmGDS_GWS_VMID0 0x20c0
+#define mmGDS_GWS_VMID0_BASE_IDX 0
+#define mmGDS_GWS_VMID1 0x20c1
+#define mmGDS_GWS_VMID1_BASE_IDX 0
+#define mmGDS_GWS_VMID2 0x20c2
+#define mmGDS_GWS_VMID2_BASE_IDX 0
+#define mmGDS_GWS_VMID3 0x20c3
+#define mmGDS_GWS_VMID3_BASE_IDX 0
+#define mmGDS_GWS_VMID4 0x20c4
+#define mmGDS_GWS_VMID4_BASE_IDX 0
+#define mmGDS_GWS_VMID5 0x20c5
+#define mmGDS_GWS_VMID5_BASE_IDX 0
+#define mmGDS_GWS_VMID6 0x20c6
+#define mmGDS_GWS_VMID6_BASE_IDX 0
+#define mmGDS_GWS_VMID7 0x20c7
+#define mmGDS_GWS_VMID7_BASE_IDX 0
+#define mmGDS_GWS_VMID8 0x20c8
+#define mmGDS_GWS_VMID8_BASE_IDX 0
+#define mmGDS_GWS_VMID9 0x20c9
+#define mmGDS_GWS_VMID9_BASE_IDX 0
+#define mmGDS_GWS_VMID10 0x20ca
+#define mmGDS_GWS_VMID10_BASE_IDX 0
+#define mmGDS_GWS_VMID11 0x20cb
+#define mmGDS_GWS_VMID11_BASE_IDX 0
+#define mmGDS_GWS_VMID12 0x20cc
+#define mmGDS_GWS_VMID12_BASE_IDX 0
+#define mmGDS_GWS_VMID13 0x20cd
+#define mmGDS_GWS_VMID13_BASE_IDX 0
+#define mmGDS_GWS_VMID14 0x20ce
+#define mmGDS_GWS_VMID14_BASE_IDX 0
+#define mmGDS_GWS_VMID15 0x20cf
+#define mmGDS_GWS_VMID15_BASE_IDX 0
+#define mmGDS_OA_VMID0 0x20d0
+#define mmGDS_OA_VMID0_BASE_IDX 0
+#define mmGDS_OA_VMID1 0x20d1
+#define mmGDS_OA_VMID1_BASE_IDX 0
+#define mmGDS_OA_VMID2 0x20d2
+#define mmGDS_OA_VMID2_BASE_IDX 0
+#define mmGDS_OA_VMID3 0x20d3
+#define mmGDS_OA_VMID3_BASE_IDX 0
+#define mmGDS_OA_VMID4 0x20d4
+#define mmGDS_OA_VMID4_BASE_IDX 0
+#define mmGDS_OA_VMID5 0x20d5
+#define mmGDS_OA_VMID5_BASE_IDX 0
+#define mmGDS_OA_VMID6 0x20d6
+#define mmGDS_OA_VMID6_BASE_IDX 0
+#define mmGDS_OA_VMID7 0x20d7
+#define mmGDS_OA_VMID7_BASE_IDX 0
+#define mmGDS_OA_VMID8 0x20d8
+#define mmGDS_OA_VMID8_BASE_IDX 0
+#define mmGDS_OA_VMID9 0x20d9
+#define mmGDS_OA_VMID9_BASE_IDX 0
+#define mmGDS_OA_VMID10 0x20da
+#define mmGDS_OA_VMID10_BASE_IDX 0
+#define mmGDS_OA_VMID11 0x20db
+#define mmGDS_OA_VMID11_BASE_IDX 0
+#define mmGDS_OA_VMID12 0x20dc
+#define mmGDS_OA_VMID12_BASE_IDX 0
+#define mmGDS_OA_VMID13 0x20dd
+#define mmGDS_OA_VMID13_BASE_IDX 0
+#define mmGDS_OA_VMID14 0x20de
+#define mmGDS_OA_VMID14_BASE_IDX 0
+#define mmGDS_OA_VMID15 0x20df
+#define mmGDS_OA_VMID15_BASE_IDX 0
+#define mmGDS_GWS_RESET0 0x20e4
+#define mmGDS_GWS_RESET0_BASE_IDX 0
+#define mmGDS_GWS_RESET1 0x20e5
+#define mmGDS_GWS_RESET1_BASE_IDX 0
+#define mmGDS_GWS_RESOURCE_RESET 0x20e6
+#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0
+#define mmGDS_COMPUTE_MAX_WAVE_ID 0x20e8
+#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0
+#define mmGDS_OA_RESET_MASK 0x20e9
+#define mmGDS_OA_RESET_MASK_BASE_IDX 0
+#define mmGDS_OA_RESET 0x20ea
+#define mmGDS_OA_RESET_BASE_IDX 0
+#define mmGDS_ENHANCE2 0x20eb
+#define mmGDS_ENHANCE2_BASE_IDX 0
+#define mmGDS_OA_CGPG_RESTORE 0x20ec
+#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0
+#define mmGDS_CS_CTXSW_STATUS 0x20ed
+#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0
+#define mmGDS_CS_CTXSW_CNT0 0x20ee
+#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_CS_CTXSW_CNT1 0x20ef
+#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_CS_CTXSW_CNT2 0x20f0
+#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_CS_CTXSW_CNT3 0x20f1
+#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_GFX_CTXSW_STATUS 0x20f2
+#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0
+#define mmGDS_VS_CTXSW_CNT0 0x20f3
+#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_VS_CTXSW_CNT1 0x20f4
+#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_VS_CTXSW_CNT2 0x20f5
+#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_VS_CTXSW_CNT3 0x20f6
+#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS_CTXSW_CNT0 0x20f7
+#define mmGDS_PS_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_PS_CTXSW_CNT1 0x20f8
+#define mmGDS_PS_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_PS_CTXSW_CNT2 0x20f9
+#define mmGDS_PS_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_PS_CTXSW_CNT3 0x20fa
+#define mmGDS_PS_CTXSW_CNT3_BASE_IDX 0
+#define mmGDS_PS_CTXSW_IDX 0x20fb
+#define mmGDS_PS_CTXSW_IDX_BASE_IDX 0
+#define mmGDS_GS_CTXSW_CNT0 0x2117
+#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0
+#define mmGDS_GS_CTXSW_CNT1 0x2118
+#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0
+#define mmGDS_GS_CTXSW_CNT2 0x2119
+#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0
+#define mmGDS_GS_CTXSW_CNT3 0x211a
+#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0
+
+
+// addressBlock: gc_gfxdec0
+// base address: 0x28000
+#define mmDB_RENDER_CONTROL 0x0000
+#define mmDB_RENDER_CONTROL_BASE_IDX 1
+#define mmDB_COUNT_CONTROL 0x0001
+#define mmDB_COUNT_CONTROL_BASE_IDX 1
+#define mmDB_DEPTH_VIEW 0x0002
+#define mmDB_DEPTH_VIEW_BASE_IDX 1
+#define mmDB_RENDER_OVERRIDE 0x0003
+#define mmDB_RENDER_OVERRIDE_BASE_IDX 1
+#define mmDB_RENDER_OVERRIDE2 0x0004
+#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1
+#define mmDB_HTILE_DATA_BASE 0x0005
+#define mmDB_HTILE_DATA_BASE_BASE_IDX 1
+#define mmDB_DEPTH_SIZE_XY 0x0007
+#define mmDB_DEPTH_SIZE_XY_BASE_IDX 1
+#define mmDB_DEPTH_BOUNDS_MIN 0x0008
+#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1
+#define mmDB_DEPTH_BOUNDS_MAX 0x0009
+#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1
+#define mmDB_STENCIL_CLEAR 0x000a
+#define mmDB_STENCIL_CLEAR_BASE_IDX 1
+#define mmDB_DEPTH_CLEAR 0x000b
+#define mmDB_DEPTH_CLEAR_BASE_IDX 1
+#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c
+#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1
+#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d
+#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1
+#define mmDB_DFSM_CONTROL 0x000e
+#define mmDB_DFSM_CONTROL_BASE_IDX 1
+#define mmDB_RESERVED_REG_2 0x000f
+#define mmDB_RESERVED_REG_2_BASE_IDX 1
+#define mmDB_Z_INFO 0x0010
+#define mmDB_Z_INFO_BASE_IDX 1
+#define mmDB_STENCIL_INFO 0x0011
+#define mmDB_STENCIL_INFO_BASE_IDX 1
+#define mmDB_Z_READ_BASE 0x0012
+#define mmDB_Z_READ_BASE_BASE_IDX 1
+#define mmDB_STENCIL_READ_BASE 0x0013
+#define mmDB_STENCIL_READ_BASE_BASE_IDX 1
+#define mmDB_Z_WRITE_BASE 0x0014
+#define mmDB_Z_WRITE_BASE_BASE_IDX 1
+#define mmDB_STENCIL_WRITE_BASE 0x0015
+#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1
+#define mmDB_RESERVED_REG_1 0x0016
+#define mmDB_RESERVED_REG_1_BASE_IDX 1
+#define mmDB_RESERVED_REG_3 0x0017
+#define mmDB_RESERVED_REG_3_BASE_IDX 1
+#define mmDB_Z_READ_BASE_HI 0x001a
+#define mmDB_Z_READ_BASE_HI_BASE_IDX 1
+#define mmDB_STENCIL_READ_BASE_HI 0x001b
+#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1
+#define mmDB_Z_WRITE_BASE_HI 0x001c
+#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1
+#define mmDB_STENCIL_WRITE_BASE_HI 0x001d
+#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1
+#define mmDB_HTILE_DATA_BASE_HI 0x001e
+#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1
+#define mmDB_RMI_L2_CACHE_CONTROL 0x001f
+#define mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX 1
+#define mmTA_BC_BASE_ADDR 0x0020
+#define mmTA_BC_BASE_ADDR_BASE_IDX 1
+#define mmTA_BC_BASE_ADDR_HI 0x0021
+#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1
+#define mmCOHER_DEST_BASE_HI_0 0x007a
+#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1
+#define mmCOHER_DEST_BASE_HI_1 0x007b
+#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1
+#define mmCOHER_DEST_BASE_HI_2 0x007c
+#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1
+#define mmCOHER_DEST_BASE_HI_3 0x007d
+#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1
+#define mmCOHER_DEST_BASE_2 0x007e
+#define mmCOHER_DEST_BASE_2_BASE_IDX 1
+#define mmCOHER_DEST_BASE_3 0x007f
+#define mmCOHER_DEST_BASE_3_BASE_IDX 1
+#define mmPA_SC_WINDOW_OFFSET 0x0080
+#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1
+#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081
+#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1
+#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082
+#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_RULE 0x0083
+#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_0_TL 0x0084
+#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_0_BR 0x0085
+#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_1_TL 0x0086
+#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_1_BR 0x0087
+#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_2_TL 0x0088
+#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_2_BR 0x0089
+#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_3_TL 0x008a
+#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1
+#define mmPA_SC_CLIPRECT_3_BR 0x008b
+#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1
+#define mmPA_SC_EDGERULE 0x008c
+#define mmPA_SC_EDGERULE_BASE_IDX 1
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1
+#define mmCB_TARGET_MASK 0x008e
+#define mmCB_TARGET_MASK_BASE_IDX 1
+#define mmCB_SHADER_MASK 0x008f
+#define mmCB_SHADER_MASK_BASE_IDX 1
+#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090
+#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1
+#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091
+#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1
+#define mmCOHER_DEST_BASE_0 0x0092
+#define mmCOHER_DEST_BASE_0_BASE_IDX 1
+#define mmCOHER_DEST_BASE_1 0x0093
+#define mmCOHER_DEST_BASE_1_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094
+#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095
+#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096
+#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097
+#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098
+#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099
+#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a
+#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b
+#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c
+#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d
+#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e
+#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f
+#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0
+#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1
+#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2
+#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3
+#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4
+#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5
+#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6
+#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7
+#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8
+#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9
+#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa
+#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab
+#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac
+#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad
+#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae
+#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af
+#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0
+#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1
+#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2
+#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1
+#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3
+#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_0 0x00b4
+#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_0 0x00b5
+#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_1 0x00b6
+#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_1 0x00b7
+#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_2 0x00b8
+#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_2 0x00b9
+#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_3 0x00ba
+#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_3 0x00bb
+#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_4 0x00bc
+#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_4 0x00bd
+#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_5 0x00be
+#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_5 0x00bf
+#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_6 0x00c0
+#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_6 0x00c1
+#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_7 0x00c2
+#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_7 0x00c3
+#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_8 0x00c4
+#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_8 0x00c5
+#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_9 0x00c6
+#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_9 0x00c7
+#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_10 0x00c8
+#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_10 0x00c9
+#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_11 0x00ca
+#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_11 0x00cb
+#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_12 0x00cc
+#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_12 0x00cd
+#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_13 0x00ce
+#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_13 0x00cf
+#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_14 0x00d0
+#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_14 0x00d1
+#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMIN_15 0x00d2
+#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1
+#define mmPA_SC_VPORT_ZMAX_15 0x00d3
+#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1
+#define mmPA_SC_RASTER_CONFIG 0x00d4
+#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1
+#define mmPA_SC_RASTER_CONFIG_1 0x00d5
+#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6
+#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1
+#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7
+#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1
+#define mmCP_PERFMON_CNTX_CNTL 0x00d8
+#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1
+#define mmCP_PIPEID 0x00d9
+#define mmCP_PIPEID_BASE_IDX 1
+#define mmCP_RINGID 0x00d9
+#define mmCP_RINGID_BASE_IDX 1
+#define mmCP_VMID 0x00da
+#define mmCP_VMID_BASE_IDX 1
+#define mmPA_SC_RIGHT_VERT_GRID 0x00e8
+#define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX 1
+#define mmPA_SC_LEFT_VERT_GRID 0x00e9
+#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1
+#define mmPA_SC_HORIZ_GRID 0x00ea
+#define mmPA_SC_HORIZ_GRID_BASE_IDX 1
+#define mmVGT_MAX_VTX_INDX 0x0100
+#define mmVGT_MAX_VTX_INDX_BASE_IDX 1
+#define mmVGT_MIN_VTX_INDX 0x0101
+#define mmVGT_MIN_VTX_INDX_BASE_IDX 1
+#define mmVGT_INDX_OFFSET 0x0102
+#define mmVGT_INDX_OFFSET_BASE_IDX 1
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1
+#define mmCB_RMI_GL2_CACHE_CONTROL 0x0104
+#define mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX 1
+#define mmCB_BLEND_RED 0x0105
+#define mmCB_BLEND_RED_BASE_IDX 1
+#define mmCB_BLEND_GREEN 0x0106
+#define mmCB_BLEND_GREEN_BASE_IDX 1
+#define mmCB_BLEND_BLUE 0x0107
+#define mmCB_BLEND_BLUE_BASE_IDX 1
+#define mmCB_BLEND_ALPHA 0x0108
+#define mmCB_BLEND_ALPHA_BASE_IDX 1
+#define mmCB_DCC_CONTROL 0x0109
+#define mmCB_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COVERAGE_OUT_CONTROL 0x010a
+#define mmCB_COVERAGE_OUT_CONTROL_BASE_IDX 1
+#define mmDB_STENCIL_CONTROL 0x010b
+#define mmDB_STENCIL_CONTROL_BASE_IDX 1
+#define mmDB_STENCILREFMASK 0x010c
+#define mmDB_STENCILREFMASK_BASE_IDX 1
+#define mmDB_STENCILREFMASK_BF 0x010d
+#define mmDB_STENCILREFMASK_BF_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE 0x010f
+#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET 0x0110
+#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE 0x0111
+#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET 0x0112
+#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE 0x0113
+#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET 0x0114
+#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_1 0x0115
+#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_1 0x0116
+#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_1 0x0117
+#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_1 0x0118
+#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_1 0x0119
+#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_1 0x011a
+#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_2 0x011b
+#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_2 0x011c
+#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_2 0x011d
+#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_2 0x011e
+#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_2 0x011f
+#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_2 0x0120
+#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_3 0x0121
+#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_3 0x0122
+#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_3 0x0123
+#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_3 0x0124
+#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_3 0x0125
+#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_3 0x0126
+#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_4 0x0127
+#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_4 0x0128
+#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_4 0x0129
+#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_4 0x012a
+#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_4 0x012b
+#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_4 0x012c
+#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_5 0x012d
+#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_5 0x012e
+#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_5 0x012f
+#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_5 0x0130
+#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_5 0x0131
+#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_5 0x0132
+#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_6 0x0133
+#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_6 0x0134
+#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_6 0x0135
+#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_6 0x0136
+#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_6 0x0137
+#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_6 0x0138
+#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_7 0x0139
+#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_7 0x013a
+#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_7 0x013b
+#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_7 0x013c
+#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_7 0x013d
+#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_7 0x013e
+#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_8 0x013f
+#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_8 0x0140
+#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_8 0x0141
+#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_8 0x0142
+#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_8 0x0143
+#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_8 0x0144
+#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_9 0x0145
+#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_9 0x0146
+#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_9 0x0147
+#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_9 0x0148
+#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_9 0x0149
+#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_9 0x014a
+#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_10 0x014b
+#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_10 0x014c
+#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_10 0x014d
+#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_10 0x014e
+#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_10 0x014f
+#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_10 0x0150
+#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_11 0x0151
+#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_11 0x0152
+#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_11 0x0153
+#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_11 0x0154
+#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_11 0x0155
+#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_11 0x0156
+#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_12 0x0157
+#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_12 0x0158
+#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_12 0x0159
+#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_12 0x015a
+#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_12 0x015b
+#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_12 0x015c
+#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_13 0x015d
+#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_13 0x015e
+#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_13 0x015f
+#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_13 0x0160
+#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_13 0x0161
+#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_13 0x0162
+#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_14 0x0163
+#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_14 0x0164
+#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_14 0x0165
+#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_14 0x0166
+#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_14 0x0167
+#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_14 0x0168
+#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1
+#define mmPA_CL_VPORT_XSCALE_15 0x0169
+#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1
+#define mmPA_CL_VPORT_XOFFSET_15 0x016a
+#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1
+#define mmPA_CL_VPORT_YSCALE_15 0x016b
+#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1
+#define mmPA_CL_VPORT_YOFFSET_15 0x016c
+#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1
+#define mmPA_CL_VPORT_ZSCALE_15 0x016d
+#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1
+#define mmPA_CL_VPORT_ZOFFSET_15 0x016e
+#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1
+#define mmPA_CL_UCP_0_X 0x016f
+#define mmPA_CL_UCP_0_X_BASE_IDX 1
+#define mmPA_CL_UCP_0_Y 0x0170
+#define mmPA_CL_UCP_0_Y_BASE_IDX 1
+#define mmPA_CL_UCP_0_Z 0x0171
+#define mmPA_CL_UCP_0_Z_BASE_IDX 1
+#define mmPA_CL_UCP_0_W 0x0172
+#define mmPA_CL_UCP_0_W_BASE_IDX 1
+#define mmPA_CL_UCP_1_X 0x0173
+#define mmPA_CL_UCP_1_X_BASE_IDX 1
+#define mmPA_CL_UCP_1_Y 0x0174
+#define mmPA_CL_UCP_1_Y_BASE_IDX 1
+#define mmPA_CL_UCP_1_Z 0x0175
+#define mmPA_CL_UCP_1_Z_BASE_IDX 1
+#define mmPA_CL_UCP_1_W 0x0176
+#define mmPA_CL_UCP_1_W_BASE_IDX 1
+#define mmPA_CL_UCP_2_X 0x0177
+#define mmPA_CL_UCP_2_X_BASE_IDX 1
+#define mmPA_CL_UCP_2_Y 0x0178
+#define mmPA_CL_UCP_2_Y_BASE_IDX 1
+#define mmPA_CL_UCP_2_Z 0x0179
+#define mmPA_CL_UCP_2_Z_BASE_IDX 1
+#define mmPA_CL_UCP_2_W 0x017a
+#define mmPA_CL_UCP_2_W_BASE_IDX 1
+#define mmPA_CL_UCP_3_X 0x017b
+#define mmPA_CL_UCP_3_X_BASE_IDX 1
+#define mmPA_CL_UCP_3_Y 0x017c
+#define mmPA_CL_UCP_3_Y_BASE_IDX 1
+#define mmPA_CL_UCP_3_Z 0x017d
+#define mmPA_CL_UCP_3_Z_BASE_IDX 1
+#define mmPA_CL_UCP_3_W 0x017e
+#define mmPA_CL_UCP_3_W_BASE_IDX 1
+#define mmPA_CL_UCP_4_X 0x017f
+#define mmPA_CL_UCP_4_X_BASE_IDX 1
+#define mmPA_CL_UCP_4_Y 0x0180
+#define mmPA_CL_UCP_4_Y_BASE_IDX 1
+#define mmPA_CL_UCP_4_Z 0x0181
+#define mmPA_CL_UCP_4_Z_BASE_IDX 1
+#define mmPA_CL_UCP_4_W 0x0182
+#define mmPA_CL_UCP_4_W_BASE_IDX 1
+#define mmPA_CL_UCP_5_X 0x0183
+#define mmPA_CL_UCP_5_X_BASE_IDX 1
+#define mmPA_CL_UCP_5_Y 0x0184
+#define mmPA_CL_UCP_5_Y_BASE_IDX 1
+#define mmPA_CL_UCP_5_Z 0x0185
+#define mmPA_CL_UCP_5_Z_BASE_IDX 1
+#define mmPA_CL_UCP_5_W 0x0186
+#define mmPA_CL_UCP_5_W_BASE_IDX 1
+#define mmPA_CL_PROG_NEAR_CLIP_Z 0x0187
+#define mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_0 0x0191
+#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_1 0x0192
+#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_2 0x0193
+#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_3 0x0194
+#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_4 0x0195
+#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_5 0x0196
+#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_6 0x0197
+#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_7 0x0198
+#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_8 0x0199
+#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_9 0x019a
+#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_10 0x019b
+#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_11 0x019c
+#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_12 0x019d
+#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_13 0x019e
+#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_14 0x019f
+#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_15 0x01a0
+#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_16 0x01a1
+#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_17 0x01a2
+#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_18 0x01a3
+#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_19 0x01a4
+#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_20 0x01a5
+#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_21 0x01a6
+#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_22 0x01a7
+#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_23 0x01a8
+#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_24 0x01a9
+#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_25 0x01aa
+#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_26 0x01ab
+#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_27 0x01ac
+#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_28 0x01ad
+#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_29 0x01ae
+#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_30 0x01af
+#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1
+#define mmSPI_PS_INPUT_CNTL_31 0x01b0
+#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1
+#define mmSPI_VS_OUT_CONFIG 0x01b1
+#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1
+#define mmSPI_PS_INPUT_ENA 0x01b3
+#define mmSPI_PS_INPUT_ENA_BASE_IDX 1
+#define mmSPI_PS_INPUT_ADDR 0x01b4
+#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1
+#define mmSPI_INTERP_CONTROL_0 0x01b5
+#define mmSPI_INTERP_CONTROL_0_BASE_IDX 1
+#define mmSPI_PS_IN_CONTROL 0x01b6
+#define mmSPI_PS_IN_CONTROL_BASE_IDX 1
+#define mmSPI_BARYC_CNTL 0x01b8
+#define mmSPI_BARYC_CNTL_BASE_IDX 1
+#define mmSPI_TMPRING_SIZE 0x01ba
+#define mmSPI_TMPRING_SIZE_BASE_IDX 1
+#define mmSPI_SHADER_IDX_FORMAT 0x01c2
+#define mmSPI_SHADER_IDX_FORMAT_BASE_IDX 1
+#define mmSPI_SHADER_POS_FORMAT 0x01c3
+#define mmSPI_SHADER_POS_FORMAT_BASE_IDX 1
+#define mmSPI_SHADER_Z_FORMAT 0x01c4
+#define mmSPI_SHADER_Z_FORMAT_BASE_IDX 1
+#define mmSPI_SHADER_COL_FORMAT 0x01c5
+#define mmSPI_SHADER_COL_FORMAT_BASE_IDX 1
+#define mmSX_PS_DOWNCONVERT 0x01d5
+#define mmSX_PS_DOWNCONVERT_BASE_IDX 1
+#define mmSX_BLEND_OPT_EPSILON 0x01d6
+#define mmSX_BLEND_OPT_EPSILON_BASE_IDX 1
+#define mmSX_BLEND_OPT_CONTROL 0x01d7
+#define mmSX_BLEND_OPT_CONTROL_BASE_IDX 1
+#define mmSX_MRT0_BLEND_OPT 0x01d8
+#define mmSX_MRT0_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT1_BLEND_OPT 0x01d9
+#define mmSX_MRT1_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT2_BLEND_OPT 0x01da
+#define mmSX_MRT2_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT3_BLEND_OPT 0x01db
+#define mmSX_MRT3_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT4_BLEND_OPT 0x01dc
+#define mmSX_MRT4_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT5_BLEND_OPT 0x01dd
+#define mmSX_MRT5_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT6_BLEND_OPT 0x01de
+#define mmSX_MRT6_BLEND_OPT_BASE_IDX 1
+#define mmSX_MRT7_BLEND_OPT 0x01df
+#define mmSX_MRT7_BLEND_OPT_BASE_IDX 1
+#define mmCB_BLEND0_CONTROL 0x01e0
+#define mmCB_BLEND0_CONTROL_BASE_IDX 1
+#define mmCB_BLEND1_CONTROL 0x01e1
+#define mmCB_BLEND1_CONTROL_BASE_IDX 1
+#define mmCB_BLEND2_CONTROL 0x01e2
+#define mmCB_BLEND2_CONTROL_BASE_IDX 1
+#define mmCB_BLEND3_CONTROL 0x01e3
+#define mmCB_BLEND3_CONTROL_BASE_IDX 1
+#define mmCB_BLEND4_CONTROL 0x01e4
+#define mmCB_BLEND4_CONTROL_BASE_IDX 1
+#define mmCB_BLEND5_CONTROL 0x01e5
+#define mmCB_BLEND5_CONTROL_BASE_IDX 1
+#define mmCB_BLEND6_CONTROL 0x01e6
+#define mmCB_BLEND6_CONTROL_BASE_IDX 1
+#define mmCB_BLEND7_CONTROL 0x01e7
+#define mmCB_BLEND7_CONTROL_BASE_IDX 1
+#define mmCS_COPY_STATE 0x01f3
+#define mmCS_COPY_STATE_BASE_IDX 1
+#define mmGFX_COPY_STATE 0x01f4
+#define mmGFX_COPY_STATE_BASE_IDX 1
+#define mmPA_CL_POINT_X_RAD 0x01f5
+#define mmPA_CL_POINT_X_RAD_BASE_IDX 1
+#define mmPA_CL_POINT_Y_RAD 0x01f6
+#define mmPA_CL_POINT_Y_RAD_BASE_IDX 1
+#define mmPA_CL_POINT_SIZE 0x01f7
+#define mmPA_CL_POINT_SIZE_BASE_IDX 1
+#define mmPA_CL_POINT_CULL_RAD 0x01f8
+#define mmPA_CL_POINT_CULL_RAD_BASE_IDX 1
+#define mmVGT_DMA_BASE_HI 0x01f9
+#define mmVGT_DMA_BASE_HI_BASE_IDX 1
+#define mmVGT_DMA_BASE 0x01fa
+#define mmVGT_DMA_BASE_BASE_IDX 1
+#define mmVGT_DRAW_INITIATOR 0x01fc
+#define mmVGT_DRAW_INITIATOR_BASE_IDX 1
+#define mmVGT_IMMED_DATA 0x01fd
+#define mmVGT_IMMED_DATA_BASE_IDX 1
+#define mmVGT_EVENT_ADDRESS_REG 0x01fe
+#define mmVGT_EVENT_ADDRESS_REG_BASE_IDX 1
+#define mmGE_MAX_OUTPUT_PER_SUBGROUP 0x01ff
+#define mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX 1
+#define mmDB_DEPTH_CONTROL 0x0200
+#define mmDB_DEPTH_CONTROL_BASE_IDX 1
+#define mmDB_EQAA 0x0201
+#define mmDB_EQAA_BASE_IDX 1
+#define mmCB_COLOR_CONTROL 0x0202
+#define mmCB_COLOR_CONTROL_BASE_IDX 1
+#define mmDB_SHADER_CONTROL 0x0203
+#define mmDB_SHADER_CONTROL_BASE_IDX 1
+#define mmPA_CL_CLIP_CNTL 0x0204
+#define mmPA_CL_CLIP_CNTL_BASE_IDX 1
+#define mmPA_SU_SC_MODE_CNTL 0x0205
+#define mmPA_SU_SC_MODE_CNTL_BASE_IDX 1
+#define mmPA_CL_VTE_CNTL 0x0206
+#define mmPA_CL_VTE_CNTL_BASE_IDX 1
+#define mmPA_CL_VS_OUT_CNTL 0x0207
+#define mmPA_CL_VS_OUT_CNTL_BASE_IDX 1
+#define mmPA_CL_NANINF_CNTL 0x0208
+#define mmPA_CL_NANINF_CNTL_BASE_IDX 1
+#define mmPA_SU_LINE_STIPPLE_CNTL 0x0209
+#define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1
+#define mmPA_SU_LINE_STIPPLE_SCALE 0x020a
+#define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1
+#define mmPA_SU_PRIM_FILTER_CNTL 0x020b
+#define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1
+#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c
+#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1
+#define mmPA_CL_OBJPRIM_ID_CNTL 0x020d
+#define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1
+#define mmPA_CL_NGG_CNTL 0x020e
+#define mmPA_CL_NGG_CNTL_BASE_IDX 1
+#define mmPA_SU_OVER_RASTERIZATION_CNTL 0x020f
+#define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1
+#define mmPA_STEREO_CNTL 0x0210
+#define mmPA_STEREO_CNTL_BASE_IDX 1
+#define mmPA_STATE_STEREO_X 0x0211
+#define mmPA_STATE_STEREO_X_BASE_IDX 1
+#define mmPA_SU_POINT_SIZE 0x0280
+#define mmPA_SU_POINT_SIZE_BASE_IDX 1
+#define mmPA_SU_POINT_MINMAX 0x0281
+#define mmPA_SU_POINT_MINMAX_BASE_IDX 1
+#define mmPA_SU_LINE_CNTL 0x0282
+#define mmPA_SU_LINE_CNTL_BASE_IDX 1
+#define mmPA_SC_LINE_STIPPLE 0x0283
+#define mmPA_SC_LINE_STIPPLE_BASE_IDX 1
+#define mmVGT_OUTPUT_PATH_CNTL 0x0284
+#define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX 1
+#define mmVGT_HOS_CNTL 0x0285
+#define mmVGT_HOS_CNTL_BASE_IDX 1
+#define mmVGT_HOS_MAX_TESS_LEVEL 0x0286
+#define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1
+#define mmVGT_HOS_MIN_TESS_LEVEL 0x0287
+#define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1
+#define mmVGT_HOS_REUSE_DEPTH 0x0288
+#define mmVGT_HOS_REUSE_DEPTH_BASE_IDX 1
+#define mmVGT_GROUP_PRIM_TYPE 0x0289
+#define mmVGT_GROUP_PRIM_TYPE_BASE_IDX 1
+#define mmVGT_GROUP_FIRST_DECR 0x028a
+#define mmVGT_GROUP_FIRST_DECR_BASE_IDX 1
+#define mmVGT_GROUP_DECR 0x028b
+#define mmVGT_GROUP_DECR_BASE_IDX 1
+#define mmVGT_GROUP_VECT_0_CNTL 0x028c
+#define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX 1
+#define mmVGT_GROUP_VECT_1_CNTL 0x028d
+#define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX 1
+#define mmVGT_GROUP_VECT_0_FMT_CNTL 0x028e
+#define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1
+#define mmVGT_GROUP_VECT_1_FMT_CNTL 0x028f
+#define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1
+#define mmVGT_GS_MODE 0x0290
+#define mmVGT_GS_MODE_BASE_IDX 1
+#define mmVGT_GS_ONCHIP_CNTL 0x0291
+#define mmVGT_GS_ONCHIP_CNTL_BASE_IDX 1
+#define mmPA_SC_MODE_CNTL_0 0x0292
+#define mmPA_SC_MODE_CNTL_0_BASE_IDX 1
+#define mmPA_SC_MODE_CNTL_1 0x0293
+#define mmPA_SC_MODE_CNTL_1_BASE_IDX 1
+#define mmVGT_ENHANCE 0x0294
+#define mmVGT_ENHANCE_BASE_IDX 1
+#define mmVGT_GS_PER_ES 0x0295
+#define mmVGT_GS_PER_ES_BASE_IDX 1
+#define mmVGT_ES_PER_GS 0x0296
+#define mmVGT_ES_PER_GS_BASE_IDX 1
+#define mmVGT_GS_PER_VS 0x0297
+#define mmVGT_GS_PER_VS_BASE_IDX 1
+#define mmVGT_GSVS_RING_OFFSET_1 0x0298
+#define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX 1
+#define mmVGT_GSVS_RING_OFFSET_2 0x0299
+#define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX 1
+#define mmVGT_GSVS_RING_OFFSET_3 0x029a
+#define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX 1
+#define mmVGT_GS_OUT_PRIM_TYPE 0x029b
+#define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1
+#define mmIA_ENHANCE 0x029c
+#define mmIA_ENHANCE_BASE_IDX 1
+#define mmVGT_DMA_SIZE 0x029d
+#define mmVGT_DMA_SIZE_BASE_IDX 1
+#define mmVGT_DMA_MAX_SIZE 0x029e
+#define mmVGT_DMA_MAX_SIZE_BASE_IDX 1
+#define mmVGT_DMA_INDEX_TYPE 0x029f
+#define mmVGT_DMA_INDEX_TYPE_BASE_IDX 1
+#define mmWD_ENHANCE 0x02a0
+#define mmWD_ENHANCE_BASE_IDX 1
+#define mmVGT_PRIMITIVEID_EN 0x02a1
+#define mmVGT_PRIMITIVEID_EN_BASE_IDX 1
+#define mmVGT_DMA_NUM_INSTANCES 0x02a2
+#define mmVGT_DMA_NUM_INSTANCES_BASE_IDX 1
+#define mmVGT_PRIMITIVEID_RESET 0x02a3
+#define mmVGT_PRIMITIVEID_RESET_BASE_IDX 1
+#define mmVGT_EVENT_INITIATOR 0x02a4
+#define mmVGT_EVENT_INITIATOR_BASE_IDX 1
+#define mmVGT_MULTI_PRIM_IB_RESET_EN 0x02a5
+#define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1
+#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6
+#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1
+#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8
+#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1
+#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9
+#define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1
+#define mmIA_MULTI_VGT_PARAM 0x02aa
+#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1
+#define mmVGT_ESGS_RING_ITEMSIZE 0x02ab
+#define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1
+#define mmVGT_GSVS_RING_ITEMSIZE 0x02ac
+#define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1
+#define mmVGT_REUSE_OFF 0x02ad
+#define mmVGT_REUSE_OFF_BASE_IDX 1
+#define mmVGT_VTX_CNT_EN 0x02ae
+#define mmVGT_VTX_CNT_EN_BASE_IDX 1
+#define mmDB_HTILE_SURFACE 0x02af
+#define mmDB_HTILE_SURFACE_BASE_IDX 1
+#define mmDB_SRESULTS_COMPARE_STATE0 0x02b0
+#define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1
+#define mmDB_SRESULTS_COMPARE_STATE1 0x02b1
+#define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1
+#define mmDB_PRELOAD_CONTROL 0x02b2
+#define mmDB_PRELOAD_CONTROL_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_SIZE_0 0x02b4
+#define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1
+#define mmVGT_STRMOUT_VTX_STRIDE_0 0x02b5
+#define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_SIZE_1 0x02b8
+#define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1
+#define mmVGT_STRMOUT_VTX_STRIDE_1 0x02b9
+#define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_SIZE_2 0x02bc
+#define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1
+#define mmVGT_STRMOUT_VTX_STRIDE_2 0x02bd
+#define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_SIZE_3 0x02c0
+#define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1
+#define mmVGT_STRMOUT_VTX_STRIDE_3 0x02c1
+#define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1
+#define mmVGT_GS_MAX_VERT_OUT 0x02ce
+#define mmVGT_GS_MAX_VERT_OUT_BASE_IDX 1
+#define mmGE_NGG_SUBGRP_CNTL 0x02d3
+#define mmGE_NGG_SUBGRP_CNTL_BASE_IDX 1
+#define mmVGT_TESS_DISTRIBUTION 0x02d4
+#define mmVGT_TESS_DISTRIBUTION_BASE_IDX 1
+#define mmVGT_SHADER_STAGES_EN 0x02d5
+#define mmVGT_SHADER_STAGES_EN_BASE_IDX 1
+#define mmVGT_LS_HS_CONFIG 0x02d6
+#define mmVGT_LS_HS_CONFIG_BASE_IDX 1
+#define mmVGT_GS_VERT_ITEMSIZE 0x02d7
+#define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX 1
+#define mmVGT_GS_VERT_ITEMSIZE_1 0x02d8
+#define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1
+#define mmVGT_GS_VERT_ITEMSIZE_2 0x02d9
+#define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1
+#define mmVGT_GS_VERT_ITEMSIZE_3 0x02da
+#define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1
+#define mmVGT_TF_PARAM 0x02db
+#define mmVGT_TF_PARAM_BASE_IDX 1
+#define mmDB_ALPHA_TO_MASK 0x02dc
+#define mmDB_ALPHA_TO_MASK_BASE_IDX 1
+#define mmVGT_DISPATCH_DRAW_INDEX 0x02dd
+#define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_CLAMP 0x02df
+#define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1
+#define mmVGT_GS_INSTANCE_CNT 0x02e4
+#define mmVGT_GS_INSTANCE_CNT_BASE_IDX 1
+#define mmVGT_STRMOUT_CONFIG 0x02e5
+#define mmVGT_STRMOUT_CONFIG_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_CONFIG 0x02e6
+#define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1
+#define mmVGT_DMA_EVENT_INITIATOR 0x02e7
+#define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX 1
+#define mmPA_SC_CENTROID_PRIORITY_0 0x02f5
+#define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1
+#define mmPA_SC_CENTROID_PRIORITY_1 0x02f6
+#define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1
+#define mmPA_SC_LINE_CNTL 0x02f7
+#define mmPA_SC_LINE_CNTL_BASE_IDX 1
+#define mmPA_SC_AA_CONFIG 0x02f8
+#define mmPA_SC_AA_CONFIG_BASE_IDX 1
+#define mmPA_SU_VTX_CNTL 0x02f9
+#define mmPA_SU_VTX_CNTL_BASE_IDX 1
+#define mmPA_CL_GB_VERT_CLIP_ADJ 0x02fa
+#define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1
+#define mmPA_CL_GB_VERT_DISC_ADJ 0x02fb
+#define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1
+#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x02fc
+#define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1
+#define mmPA_CL_GB_HORZ_DISC_ADJ 0x02fd
+#define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0x030e
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0x030f
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1
+#define mmPA_SC_SHADER_CONTROL 0x0310
+#define mmPA_SC_SHADER_CONTROL_BASE_IDX 1
+#define mmPA_SC_BINNER_CNTL_0 0x0311
+#define mmPA_SC_BINNER_CNTL_0_BASE_IDX 1
+#define mmPA_SC_BINNER_CNTL_1 0x0312
+#define mmPA_SC_BINNER_CNTL_1_BASE_IDX 1
+#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313
+#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1
+#define mmPA_SC_NGG_MODE_CNTL 0x0314
+#define mmPA_SC_NGG_MODE_CNTL_BASE_IDX 1
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1
+#define mmVGT_OUT_DEALLOC_CNTL 0x0317
+#define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX 1
+#define mmCB_COLOR0_BASE 0x0318
+#define mmCB_COLOR0_BASE_BASE_IDX 1
+#define mmCB_COLOR0_PITCH 0x0319
+#define mmCB_COLOR0_PITCH_BASE_IDX 1
+#define mmCB_COLOR0_SLICE 0x031a
+#define mmCB_COLOR0_SLICE_BASE_IDX 1
+#define mmCB_COLOR0_VIEW 0x031b
+#define mmCB_COLOR0_VIEW_BASE_IDX 1
+#define mmCB_COLOR0_INFO 0x031c
+#define mmCB_COLOR0_INFO_BASE_IDX 1
+#define mmCB_COLOR0_ATTRIB 0x031d
+#define mmCB_COLOR0_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR0_DCC_CONTROL 0x031e
+#define mmCB_COLOR0_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR0_CMASK 0x031f
+#define mmCB_COLOR0_CMASK_BASE_IDX 1
+#define mmCB_COLOR0_CMASK_SLICE 0x0320
+#define mmCB_COLOR0_CMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR0_FMASK 0x0321
+#define mmCB_COLOR0_FMASK_BASE_IDX 1
+#define mmCB_COLOR0_FMASK_SLICE 0x0322
+#define mmCB_COLOR0_FMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR0_CLEAR_WORD0 0x0323
+#define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR0_CLEAR_WORD1 0x0324
+#define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR0_DCC_BASE 0x0325
+#define mmCB_COLOR0_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR1_BASE 0x0327
+#define mmCB_COLOR1_BASE_BASE_IDX 1
+#define mmCB_COLOR1_PITCH 0x0328
+#define mmCB_COLOR1_PITCH_BASE_IDX 1
+#define mmCB_COLOR1_SLICE 0x0329
+#define mmCB_COLOR1_SLICE_BASE_IDX 1
+#define mmCB_COLOR1_VIEW 0x032a
+#define mmCB_COLOR1_VIEW_BASE_IDX 1
+#define mmCB_COLOR1_INFO 0x032b
+#define mmCB_COLOR1_INFO_BASE_IDX 1
+#define mmCB_COLOR1_ATTRIB 0x032c
+#define mmCB_COLOR1_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR1_DCC_CONTROL 0x032d
+#define mmCB_COLOR1_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR1_CMASK 0x032e
+#define mmCB_COLOR1_CMASK_BASE_IDX 1
+#define mmCB_COLOR1_CMASK_SLICE 0x032f
+#define mmCB_COLOR1_CMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR1_FMASK 0x0330
+#define mmCB_COLOR1_FMASK_BASE_IDX 1
+#define mmCB_COLOR1_FMASK_SLICE 0x0331
+#define mmCB_COLOR1_FMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR1_CLEAR_WORD0 0x0332
+#define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR1_CLEAR_WORD1 0x0333
+#define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR1_DCC_BASE 0x0334
+#define mmCB_COLOR1_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR2_BASE 0x0336
+#define mmCB_COLOR2_BASE_BASE_IDX 1
+#define mmCB_COLOR2_PITCH 0x0337
+#define mmCB_COLOR2_PITCH_BASE_IDX 1
+#define mmCB_COLOR2_SLICE 0x0338
+#define mmCB_COLOR2_SLICE_BASE_IDX 1
+#define mmCB_COLOR2_VIEW 0x0339
+#define mmCB_COLOR2_VIEW_BASE_IDX 1
+#define mmCB_COLOR2_INFO 0x033a
+#define mmCB_COLOR2_INFO_BASE_IDX 1
+#define mmCB_COLOR2_ATTRIB 0x033b
+#define mmCB_COLOR2_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR2_DCC_CONTROL 0x033c
+#define mmCB_COLOR2_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR2_CMASK 0x033d
+#define mmCB_COLOR2_CMASK_BASE_IDX 1
+#define mmCB_COLOR2_CMASK_SLICE 0x033e
+#define mmCB_COLOR2_CMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR2_FMASK 0x033f
+#define mmCB_COLOR2_FMASK_BASE_IDX 1
+#define mmCB_COLOR2_FMASK_SLICE 0x0340
+#define mmCB_COLOR2_FMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR2_CLEAR_WORD0 0x0341
+#define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR2_CLEAR_WORD1 0x0342
+#define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR2_DCC_BASE 0x0343
+#define mmCB_COLOR2_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR3_BASE 0x0345
+#define mmCB_COLOR3_BASE_BASE_IDX 1
+#define mmCB_COLOR3_PITCH 0x0346
+#define mmCB_COLOR3_PITCH_BASE_IDX 1
+#define mmCB_COLOR3_SLICE 0x0347
+#define mmCB_COLOR3_SLICE_BASE_IDX 1
+#define mmCB_COLOR3_VIEW 0x0348
+#define mmCB_COLOR3_VIEW_BASE_IDX 1
+#define mmCB_COLOR3_INFO 0x0349
+#define mmCB_COLOR3_INFO_BASE_IDX 1
+#define mmCB_COLOR3_ATTRIB 0x034a
+#define mmCB_COLOR3_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR3_DCC_CONTROL 0x034b
+#define mmCB_COLOR3_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR3_CMASK 0x034c
+#define mmCB_COLOR3_CMASK_BASE_IDX 1
+#define mmCB_COLOR3_CMASK_SLICE 0x034d
+#define mmCB_COLOR3_CMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR3_FMASK 0x034e
+#define mmCB_COLOR3_FMASK_BASE_IDX 1
+#define mmCB_COLOR3_FMASK_SLICE 0x034f
+#define mmCB_COLOR3_FMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR3_CLEAR_WORD0 0x0350
+#define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR3_CLEAR_WORD1 0x0351
+#define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR3_DCC_BASE 0x0352
+#define mmCB_COLOR3_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR4_BASE 0x0354
+#define mmCB_COLOR4_BASE_BASE_IDX 1
+#define mmCB_COLOR4_PITCH 0x0355
+#define mmCB_COLOR4_PITCH_BASE_IDX 1
+#define mmCB_COLOR4_SLICE 0x0356
+#define mmCB_COLOR4_SLICE_BASE_IDX 1
+#define mmCB_COLOR4_VIEW 0x0357
+#define mmCB_COLOR4_VIEW_BASE_IDX 1
+#define mmCB_COLOR4_INFO 0x0358
+#define mmCB_COLOR4_INFO_BASE_IDX 1
+#define mmCB_COLOR4_ATTRIB 0x0359
+#define mmCB_COLOR4_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR4_DCC_CONTROL 0x035a
+#define mmCB_COLOR4_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR4_CMASK 0x035b
+#define mmCB_COLOR4_CMASK_BASE_IDX 1
+#define mmCB_COLOR4_CMASK_SLICE 0x035c
+#define mmCB_COLOR4_CMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR4_FMASK 0x035d
+#define mmCB_COLOR4_FMASK_BASE_IDX 1
+#define mmCB_COLOR4_FMASK_SLICE 0x035e
+#define mmCB_COLOR4_FMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR4_CLEAR_WORD0 0x035f
+#define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR4_CLEAR_WORD1 0x0360
+#define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR4_DCC_BASE 0x0361
+#define mmCB_COLOR4_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR5_BASE 0x0363
+#define mmCB_COLOR5_BASE_BASE_IDX 1
+#define mmCB_COLOR5_PITCH 0x0364
+#define mmCB_COLOR5_PITCH_BASE_IDX 1
+#define mmCB_COLOR5_SLICE 0x0365
+#define mmCB_COLOR5_SLICE_BASE_IDX 1
+#define mmCB_COLOR5_VIEW 0x0366
+#define mmCB_COLOR5_VIEW_BASE_IDX 1
+#define mmCB_COLOR5_INFO 0x0367
+#define mmCB_COLOR5_INFO_BASE_IDX 1
+#define mmCB_COLOR5_ATTRIB 0x0368
+#define mmCB_COLOR5_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR5_DCC_CONTROL 0x0369
+#define mmCB_COLOR5_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR5_CMASK 0x036a
+#define mmCB_COLOR5_CMASK_BASE_IDX 1
+#define mmCB_COLOR5_CMASK_SLICE 0x036b
+#define mmCB_COLOR5_CMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR5_FMASK 0x036c
+#define mmCB_COLOR5_FMASK_BASE_IDX 1
+#define mmCB_COLOR5_FMASK_SLICE 0x036d
+#define mmCB_COLOR5_FMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR5_CLEAR_WORD0 0x036e
+#define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR5_CLEAR_WORD1 0x036f
+#define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR5_DCC_BASE 0x0370
+#define mmCB_COLOR5_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR6_BASE 0x0372
+#define mmCB_COLOR6_BASE_BASE_IDX 1
+#define mmCB_COLOR6_PITCH 0x0373
+#define mmCB_COLOR6_PITCH_BASE_IDX 1
+#define mmCB_COLOR6_SLICE 0x0374
+#define mmCB_COLOR6_SLICE_BASE_IDX 1
+#define mmCB_COLOR6_VIEW 0x0375
+#define mmCB_COLOR6_VIEW_BASE_IDX 1
+#define mmCB_COLOR6_INFO 0x0376
+#define mmCB_COLOR6_INFO_BASE_IDX 1
+#define mmCB_COLOR6_ATTRIB 0x0377
+#define mmCB_COLOR6_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR6_DCC_CONTROL 0x0378
+#define mmCB_COLOR6_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR6_CMASK 0x0379
+#define mmCB_COLOR6_CMASK_BASE_IDX 1
+#define mmCB_COLOR6_CMASK_SLICE 0x037a
+#define mmCB_COLOR6_CMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR6_FMASK 0x037b
+#define mmCB_COLOR6_FMASK_BASE_IDX 1
+#define mmCB_COLOR6_FMASK_SLICE 0x037c
+#define mmCB_COLOR6_FMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR6_CLEAR_WORD0 0x037d
+#define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR6_CLEAR_WORD1 0x037e
+#define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR6_DCC_BASE 0x037f
+#define mmCB_COLOR6_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR7_BASE 0x0381
+#define mmCB_COLOR7_BASE_BASE_IDX 1
+#define mmCB_COLOR7_PITCH 0x0382
+#define mmCB_COLOR7_PITCH_BASE_IDX 1
+#define mmCB_COLOR7_SLICE 0x0383
+#define mmCB_COLOR7_SLICE_BASE_IDX 1
+#define mmCB_COLOR7_VIEW 0x0384
+#define mmCB_COLOR7_VIEW_BASE_IDX 1
+#define mmCB_COLOR7_INFO 0x0385
+#define mmCB_COLOR7_INFO_BASE_IDX 1
+#define mmCB_COLOR7_ATTRIB 0x0386
+#define mmCB_COLOR7_ATTRIB_BASE_IDX 1
+#define mmCB_COLOR7_DCC_CONTROL 0x0387
+#define mmCB_COLOR7_DCC_CONTROL_BASE_IDX 1
+#define mmCB_COLOR7_CMASK 0x0388
+#define mmCB_COLOR7_CMASK_BASE_IDX 1
+#define mmCB_COLOR7_CMASK_SLICE 0x0389
+#define mmCB_COLOR7_CMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR7_FMASK 0x038a
+#define mmCB_COLOR7_FMASK_BASE_IDX 1
+#define mmCB_COLOR7_FMASK_SLICE 0x038b
+#define mmCB_COLOR7_FMASK_SLICE_BASE_IDX 1
+#define mmCB_COLOR7_CLEAR_WORD0 0x038c
+#define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX 1
+#define mmCB_COLOR7_CLEAR_WORD1 0x038d
+#define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX 1
+#define mmCB_COLOR7_DCC_BASE 0x038e
+#define mmCB_COLOR7_DCC_BASE_BASE_IDX 1
+#define mmCB_COLOR0_BASE_EXT 0x0390
+#define mmCB_COLOR0_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR1_BASE_EXT 0x0391
+#define mmCB_COLOR1_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR2_BASE_EXT 0x0392
+#define mmCB_COLOR2_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR3_BASE_EXT 0x0393
+#define mmCB_COLOR3_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR4_BASE_EXT 0x0394
+#define mmCB_COLOR4_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR5_BASE_EXT 0x0395
+#define mmCB_COLOR5_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR6_BASE_EXT 0x0396
+#define mmCB_COLOR6_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR7_BASE_EXT 0x0397
+#define mmCB_COLOR7_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR0_CMASK_BASE_EXT 0x0398
+#define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR1_CMASK_BASE_EXT 0x0399
+#define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR2_CMASK_BASE_EXT 0x039a
+#define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR3_CMASK_BASE_EXT 0x039b
+#define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR4_CMASK_BASE_EXT 0x039c
+#define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR5_CMASK_BASE_EXT 0x039d
+#define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR6_CMASK_BASE_EXT 0x039e
+#define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR7_CMASK_BASE_EXT 0x039f
+#define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR0_FMASK_BASE_EXT 0x03a0
+#define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR1_FMASK_BASE_EXT 0x03a1
+#define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR2_FMASK_BASE_EXT 0x03a2
+#define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR3_FMASK_BASE_EXT 0x03a3
+#define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR4_FMASK_BASE_EXT 0x03a4
+#define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR5_FMASK_BASE_EXT 0x03a5
+#define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR6_FMASK_BASE_EXT 0x03a6
+#define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR7_FMASK_BASE_EXT 0x03a7
+#define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR0_DCC_BASE_EXT 0x03a8
+#define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR1_DCC_BASE_EXT 0x03a9
+#define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR2_DCC_BASE_EXT 0x03aa
+#define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR3_DCC_BASE_EXT 0x03ab
+#define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR4_DCC_BASE_EXT 0x03ac
+#define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR5_DCC_BASE_EXT 0x03ad
+#define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR6_DCC_BASE_EXT 0x03ae
+#define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR7_DCC_BASE_EXT 0x03af
+#define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1
+#define mmCB_COLOR0_ATTRIB2 0x03b0
+#define mmCB_COLOR0_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR1_ATTRIB2 0x03b1
+#define mmCB_COLOR1_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR2_ATTRIB2 0x03b2
+#define mmCB_COLOR2_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR3_ATTRIB2 0x03b3
+#define mmCB_COLOR3_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR4_ATTRIB2 0x03b4
+#define mmCB_COLOR4_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR5_ATTRIB2 0x03b5
+#define mmCB_COLOR5_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR6_ATTRIB2 0x03b6
+#define mmCB_COLOR6_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR7_ATTRIB2 0x03b7
+#define mmCB_COLOR7_ATTRIB2_BASE_IDX 1
+#define mmCB_COLOR0_ATTRIB3 0x03b8
+#define mmCB_COLOR0_ATTRIB3_BASE_IDX 1
+#define mmCB_COLOR1_ATTRIB3 0x03b9
+#define mmCB_COLOR1_ATTRIB3_BASE_IDX 1
+#define mmCB_COLOR2_ATTRIB3 0x03ba
+#define mmCB_COLOR2_ATTRIB3_BASE_IDX 1
+#define mmCB_COLOR3_ATTRIB3 0x03bb
+#define mmCB_COLOR3_ATTRIB3_BASE_IDX 1
+#define mmCB_COLOR4_ATTRIB3 0x03bc
+#define mmCB_COLOR4_ATTRIB3_BASE_IDX 1
+#define mmCB_COLOR5_ATTRIB3 0x03bd
+#define mmCB_COLOR5_ATTRIB3_BASE_IDX 1
+#define mmCB_COLOR6_ATTRIB3 0x03be
+#define mmCB_COLOR6_ATTRIB3_BASE_IDX 1
+#define mmCB_COLOR7_ATTRIB3 0x03bf
+#define mmCB_COLOR7_ATTRIB3_BASE_IDX 1
+
+
+// addressBlock: gc_gfxudec
+// base address: 0x30000
+#define mmCP_EOP_DONE_ADDR_LO 0x2000
+#define mmCP_EOP_DONE_ADDR_LO_BASE_IDX 1
+#define mmCP_EOP_DONE_ADDR_HI 0x2001
+#define mmCP_EOP_DONE_ADDR_HI_BASE_IDX 1
+#define mmCP_EOP_DONE_DATA_LO 0x2002
+#define mmCP_EOP_DONE_DATA_LO_BASE_IDX 1
+#define mmCP_EOP_DONE_DATA_HI 0x2003
+#define mmCP_EOP_DONE_DATA_HI_BASE_IDX 1
+#define mmCP_EOP_LAST_FENCE_LO 0x2004
+#define mmCP_EOP_LAST_FENCE_LO_BASE_IDX 1
+#define mmCP_EOP_LAST_FENCE_HI 0x2005
+#define mmCP_EOP_LAST_FENCE_HI_BASE_IDX 1
+#define mmCP_STREAM_OUT_ADDR_LO 0x2006
+#define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX 1
+#define mmCP_STREAM_OUT_ADDR_HI 0x2007
+#define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1
+#define mmCP_PIPE_STATS_ADDR_LO 0x2018
+#define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX 1
+#define mmCP_PIPE_STATS_ADDR_HI 0x2019
+#define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX 1
+#define mmCP_VGT_IAVERT_COUNT_LO 0x201a
+#define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_IAVERT_COUNT_HI 0x201b
+#define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_IAPRIM_COUNT_LO 0x201c
+#define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_IAPRIM_COUNT_HI 0x201d
+#define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_GSPRIM_COUNT_LO 0x201e
+#define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_GSPRIM_COUNT_HI 0x201f
+#define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_VSINVOC_COUNT_LO 0x2020
+#define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_VSINVOC_COUNT_HI 0x2021
+#define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_GSINVOC_COUNT_LO 0x2022
+#define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_GSINVOC_COUNT_HI 0x2023
+#define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_HSINVOC_COUNT_LO 0x2024
+#define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_HSINVOC_COUNT_HI 0x2025
+#define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_VGT_DSINVOC_COUNT_LO 0x2026
+#define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_DSINVOC_COUNT_HI 0x2027
+#define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_PA_CINVOC_COUNT_LO 0x2028
+#define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_PA_CINVOC_COUNT_HI 0x2029
+#define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_PA_CPRIM_COUNT_LO 0x202a
+#define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX 1
+#define mmCP_PA_CPRIM_COUNT_HI 0x202b
+#define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX 1
+#define mmCP_SC_PSINVOC_COUNT0_LO 0x202c
+#define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1
+#define mmCP_SC_PSINVOC_COUNT0_HI 0x202d
+#define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1
+#define mmCP_SC_PSINVOC_COUNT1_LO 0x202e
+#define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1
+#define mmCP_SC_PSINVOC_COUNT1_HI 0x202f
+#define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1
+#define mmCP_VGT_CSINVOC_COUNT_LO 0x2030
+#define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1
+#define mmCP_VGT_CSINVOC_COUNT_HI 0x2031
+#define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1
+#define mmCP_EOP_DONE_DOORBELL 0x2032
+#define mmCP_EOP_DONE_DOORBELL_BASE_IDX 1
+#define mmCP_STREAM_OUT_DOORBELL 0x2033
+#define mmCP_STREAM_OUT_DOORBELL_BASE_IDX 1
+#define mmCP_SEM_DOORBELL 0x2034
+#define mmCP_SEM_DOORBELL_BASE_IDX 1
+#define mmCP_PIPE_STATS_CONTROL 0x203d
+#define mmCP_PIPE_STATS_CONTROL_BASE_IDX 1
+#define mmCP_STREAM_OUT_CONTROL 0x203e
+#define mmCP_STREAM_OUT_CONTROL_BASE_IDX 1
+#define mmCP_STRMOUT_CNTL 0x203f
+#define mmCP_STRMOUT_CNTL_BASE_IDX 1
+#define mmSCRATCH_REG0 0x2040
+#define mmSCRATCH_REG0_BASE_IDX 1
+#define mmSCRATCH_REG1 0x2041
+#define mmSCRATCH_REG1_BASE_IDX 1
+#define mmSCRATCH_REG2 0x2042
+#define mmSCRATCH_REG2_BASE_IDX 1
+#define mmSCRATCH_REG3 0x2043
+#define mmSCRATCH_REG3_BASE_IDX 1
+#define mmSCRATCH_REG4 0x2044
+#define mmSCRATCH_REG4_BASE_IDX 1
+#define mmSCRATCH_REG5 0x2045
+#define mmSCRATCH_REG5_BASE_IDX 1
+#define mmSCRATCH_REG6 0x2046
+#define mmSCRATCH_REG6_BASE_IDX 1
+#define mmSCRATCH_REG7 0x2047
+#define mmSCRATCH_REG7_BASE_IDX 1
+#define mmCP_PIPE_STATS_DOORBELL 0x2048
+#define mmCP_PIPE_STATS_DOORBELL_BASE_IDX 1
+#define mmCP_APPEND_DDID_CNT 0x204b
+#define mmCP_APPEND_DDID_CNT_BASE_IDX 1
+#define mmCP_APPEND_DATA_HI 0x204c
+#define mmCP_APPEND_DATA_HI_BASE_IDX 1
+#define mmCP_APPEND_LAST_CS_FENCE_HI 0x204d
+#define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1
+#define mmCP_APPEND_LAST_PS_FENCE_HI 0x204e
+#define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1
+#define mmSCRATCH_UMSK 0x2050
+#define mmSCRATCH_UMSK_BASE_IDX 1
+#define mmSCRATCH_ADDR 0x2051
+#define mmSCRATCH_ADDR_BASE_IDX 1
+#define mmCP_PFP_ATOMIC_PREOP_LO 0x2052
+#define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1
+#define mmCP_PFP_ATOMIC_PREOP_HI 0x2053
+#define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1
+#define mmCP_APPEND_ADDR_LO 0x2058
+#define mmCP_APPEND_ADDR_LO_BASE_IDX 1
+#define mmCP_APPEND_ADDR_HI 0x2059
+#define mmCP_APPEND_ADDR_HI_BASE_IDX 1
+#define mmCP_APPEND_DATA 0x205a
+#define mmCP_APPEND_DATA_BASE_IDX 1
+#define mmCP_APPEND_DATA_LO 0x205a
+#define mmCP_APPEND_DATA_LO_BASE_IDX 1
+#define mmCP_APPEND_LAST_CS_FENCE 0x205b
+#define mmCP_APPEND_LAST_CS_FENCE_BASE_IDX 1
+#define mmCP_APPEND_LAST_CS_FENCE_LO 0x205b
+#define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1
+#define mmCP_APPEND_LAST_PS_FENCE 0x205c
+#define mmCP_APPEND_LAST_PS_FENCE_BASE_IDX 1
+#define mmCP_APPEND_LAST_PS_FENCE_LO 0x205c
+#define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1
+#define mmCP_ATOMIC_PREOP_LO 0x205d
+#define mmCP_ATOMIC_PREOP_LO_BASE_IDX 1
+#define mmCP_ME_ATOMIC_PREOP_LO 0x205d
+#define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1
+#define mmCP_ATOMIC_PREOP_HI 0x205e
+#define mmCP_ATOMIC_PREOP_HI_BASE_IDX 1
+#define mmCP_ME_ATOMIC_PREOP_HI 0x205e
+#define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1
+#define mmCP_GDS_ATOMIC0_PREOP_LO 0x205f
+#define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1
+#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2060
+#define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1
+#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2061
+#define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1
+#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2062
+#define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1
+#define mmCP_ME_MC_WADDR_LO 0x2069
+#define mmCP_ME_MC_WADDR_LO_BASE_IDX 1
+#define mmCP_ME_MC_WADDR_HI 0x206a
+#define mmCP_ME_MC_WADDR_HI_BASE_IDX 1
+#define mmCP_ME_MC_WDATA_LO 0x206b
+#define mmCP_ME_MC_WDATA_LO_BASE_IDX 1
+#define mmCP_ME_MC_WDATA_HI 0x206c
+#define mmCP_ME_MC_WDATA_HI_BASE_IDX 1
+#define mmCP_ME_MC_RADDR_LO 0x206d
+#define mmCP_ME_MC_RADDR_LO_BASE_IDX 1
+#define mmCP_ME_MC_RADDR_HI 0x206e
+#define mmCP_ME_MC_RADDR_HI_BASE_IDX 1
+#define mmCP_SEM_WAIT_TIMER 0x206f
+#define mmCP_SEM_WAIT_TIMER_BASE_IDX 1
+#define mmCP_SIG_SEM_ADDR_LO 0x2070
+#define mmCP_SIG_SEM_ADDR_LO_BASE_IDX 1
+#define mmCP_SIG_SEM_ADDR_HI 0x2071
+#define mmCP_SIG_SEM_ADDR_HI_BASE_IDX 1
+#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2074
+#define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1
+#define mmCP_WAIT_SEM_ADDR_LO 0x2075
+#define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX 1
+#define mmCP_WAIT_SEM_ADDR_HI 0x2076
+#define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_PFP_CONTROL 0x2077
+#define mmCP_DMA_PFP_CONTROL_BASE_IDX 1
+#define mmCP_DMA_ME_CONTROL 0x2078
+#define mmCP_DMA_ME_CONTROL_BASE_IDX 1
+#define mmCP_COHER_BASE_HI 0x2079
+#define mmCP_COHER_BASE_HI_BASE_IDX 1
+#define mmCP_COHER_START_DELAY 0x207b
+#define mmCP_COHER_START_DELAY_BASE_IDX 1
+#define mmCP_COHER_CNTL 0x207c
+#define mmCP_COHER_CNTL_BASE_IDX 1
+#define mmCP_COHER_SIZE 0x207d
+#define mmCP_COHER_SIZE_BASE_IDX 1
+#define mmCP_COHER_BASE 0x207e
+#define mmCP_COHER_BASE_BASE_IDX 1
+#define mmCP_COHER_STATUS 0x207f
+#define mmCP_COHER_STATUS_BASE_IDX 1
+#define mmCP_DMA_ME_SRC_ADDR 0x2080
+#define mmCP_DMA_ME_SRC_ADDR_BASE_IDX 1
+#define mmCP_DMA_ME_SRC_ADDR_HI 0x2081
+#define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_ME_DST_ADDR 0x2082
+#define mmCP_DMA_ME_DST_ADDR_BASE_IDX 1
+#define mmCP_DMA_ME_DST_ADDR_HI 0x2083
+#define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_ME_COMMAND 0x2084
+#define mmCP_DMA_ME_COMMAND_BASE_IDX 1
+#define mmCP_DMA_PFP_SRC_ADDR 0x2085
+#define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX 1
+#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2086
+#define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_PFP_DST_ADDR 0x2087
+#define mmCP_DMA_PFP_DST_ADDR_BASE_IDX 1
+#define mmCP_DMA_PFP_DST_ADDR_HI 0x2088
+#define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_PFP_COMMAND 0x2089
+#define mmCP_DMA_PFP_COMMAND_BASE_IDX 1
+#define mmCP_DMA_CNTL 0x208a
+#define mmCP_DMA_CNTL_BASE_IDX 1
+#define mmCP_DMA_READ_TAGS 0x208b
+#define mmCP_DMA_READ_TAGS_BASE_IDX 1
+#define mmCP_COHER_SIZE_HI 0x208c
+#define mmCP_COHER_SIZE_HI_BASE_IDX 1
+#define mmCP_PFP_IB_CONTROL 0x208d
+#define mmCP_PFP_IB_CONTROL_BASE_IDX 1
+#define mmCP_PFP_LOAD_CONTROL 0x208e
+#define mmCP_PFP_LOAD_CONTROL_BASE_IDX 1
+#define mmCP_SCRATCH_INDEX 0x208f
+#define mmCP_SCRATCH_INDEX_BASE_IDX 1
+#define mmCP_SCRATCH_DATA 0x2090
+#define mmCP_SCRATCH_DATA_BASE_IDX 1
+#define mmCP_RB_OFFSET 0x2091
+#define mmCP_RB_OFFSET_BASE_IDX 1
+#define mmCP_IB1_OFFSET 0x2092
+#define mmCP_IB1_OFFSET_BASE_IDX 1
+#define mmCP_IB2_OFFSET 0x2093
+#define mmCP_IB2_OFFSET_BASE_IDX 1
+#define mmCP_IB1_PREAMBLE_BEGIN 0x2094
+#define mmCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1
+#define mmCP_IB1_PREAMBLE_END 0x2095
+#define mmCP_IB1_PREAMBLE_END_BASE_IDX 1
+#define mmCP_IB2_PREAMBLE_BEGIN 0x2096
+#define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1
+#define mmCP_IB2_PREAMBLE_END 0x2097
+#define mmCP_IB2_PREAMBLE_END_BASE_IDX 1
+#define mmCP_CE_IB1_OFFSET 0x2098
+#define mmCP_CE_IB1_OFFSET_BASE_IDX 1
+#define mmCP_CE_IB2_OFFSET 0x2099
+#define mmCP_CE_IB2_OFFSET_BASE_IDX 1
+#define mmCP_CE_COUNTER 0x209a
+#define mmCP_CE_COUNTER_BASE_IDX 1
+#define mmCP_DMA_ME_CMD_ADDR_LO 0x209c
+#define mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX 1
+#define mmCP_DMA_ME_CMD_ADDR_HI 0x209d
+#define mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX 1
+#define mmCP_DMA_PFP_CMD_ADDR_LO 0x209e
+#define mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX 1
+#define mmCP_DMA_PFP_CMD_ADDR_HI 0x209f
+#define mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX 1
+#define mmCP_APPEND_CMD_ADDR_LO 0x20a0
+#define mmCP_APPEND_CMD_ADDR_LO_BASE_IDX 1
+#define mmCP_APPEND_CMD_ADDR_HI 0x20a1
+#define mmCP_APPEND_CMD_ADDR_HI_BASE_IDX 1
+#define mmCP_CE_INIT_CMD_BUFSZ 0x20bd
+#define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_CE_IB1_CMD_BUFSZ 0x20be
+#define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_CE_IB2_CMD_BUFSZ 0x20bf
+#define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_IB1_CMD_BUFSZ 0x20c0
+#define mmCP_IB1_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_IB2_CMD_BUFSZ 0x20c1
+#define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_ST_CMD_BUFSZ 0x20c2
+#define mmCP_ST_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_CE_INIT_BASE_LO 0x20c3
+#define mmCP_CE_INIT_BASE_LO_BASE_IDX 1
+#define mmCP_CE_INIT_BASE_HI 0x20c4
+#define mmCP_CE_INIT_BASE_HI_BASE_IDX 1
+#define mmCP_CE_INIT_BUFSZ 0x20c5
+#define mmCP_CE_INIT_BUFSZ_BASE_IDX 1
+#define mmCP_CE_IB1_BASE_LO 0x20c6
+#define mmCP_CE_IB1_BASE_LO_BASE_IDX 1
+#define mmCP_CE_IB1_BASE_HI 0x20c7
+#define mmCP_CE_IB1_BASE_HI_BASE_IDX 1
+#define mmCP_CE_IB1_BUFSZ 0x20c8
+#define mmCP_CE_IB1_BUFSZ_BASE_IDX 1
+#define mmCP_CE_IB2_BASE_LO 0x20c9
+#define mmCP_CE_IB2_BASE_LO_BASE_IDX 1
+#define mmCP_CE_IB2_BASE_HI 0x20ca
+#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1
+#define mmCP_CE_IB2_BUFSZ 0x20cb
+#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1
+#define mmCP_IB1_BASE_LO 0x20cc
+#define mmCP_IB1_BASE_LO_BASE_IDX 1
+#define mmCP_IB1_BASE_HI 0x20cd
+#define mmCP_IB1_BASE_HI_BASE_IDX 1
+#define mmCP_IB1_BUFSZ 0x20ce
+#define mmCP_IB1_BUFSZ_BASE_IDX 1
+#define mmCP_IB2_BASE_LO 0x20cf
+#define mmCP_IB2_BASE_LO_BASE_IDX 1
+#define mmCP_IB2_BASE_HI 0x20d0
+#define mmCP_IB2_BASE_HI_BASE_IDX 1
+#define mmCP_IB2_BUFSZ 0x20d1
+#define mmCP_IB2_BUFSZ_BASE_IDX 1
+#define mmCP_ST_BASE_LO 0x20d2
+#define mmCP_ST_BASE_LO_BASE_IDX 1
+#define mmCP_ST_BASE_HI 0x20d3
+#define mmCP_ST_BASE_HI_BASE_IDX 1
+#define mmCP_ST_BUFSZ 0x20d4
+#define mmCP_ST_BUFSZ_BASE_IDX 1
+#define mmCP_EOP_DONE_EVENT_CNTL 0x20d5
+#define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1
+#define mmCP_EOP_DONE_DATA_CNTL 0x20d6
+#define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX 1
+#define mmCP_EOP_DONE_CNTX_ID 0x20d7
+#define mmCP_EOP_DONE_CNTX_ID_BASE_IDX 1
+#define mmCP_DB_BASE_LO 0x20d8
+#define mmCP_DB_BASE_LO_BASE_IDX 1
+#define mmCP_DB_BASE_HI 0x20d9
+#define mmCP_DB_BASE_HI_BASE_IDX 1
+#define mmCP_DB_BUFSZ 0x20da
+#define mmCP_DB_BUFSZ_BASE_IDX 1
+#define mmCP_DB_CMD_BUFSZ 0x20db
+#define mmCP_DB_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_CE_DB_BASE_LO 0x20dc
+#define mmCP_CE_DB_BASE_LO_BASE_IDX 1
+#define mmCP_CE_DB_BASE_HI 0x20dd
+#define mmCP_CE_DB_BASE_HI_BASE_IDX 1
+#define mmCP_CE_DB_BUFSZ 0x20de
+#define mmCP_CE_DB_BUFSZ_BASE_IDX 1
+#define mmCP_CE_DB_CMD_BUFSZ 0x20df
+#define mmCP_CE_DB_CMD_BUFSZ_BASE_IDX 1
+#define mmCP_PFP_COMPLETION_STATUS 0x20ec
+#define mmCP_PFP_COMPLETION_STATUS_BASE_IDX 1
+#define mmCP_CE_COMPLETION_STATUS 0x20ed
+#define mmCP_CE_COMPLETION_STATUS_BASE_IDX 1
+#define mmCP_PRED_NOT_VISIBLE 0x20ee
+#define mmCP_PRED_NOT_VISIBLE_BASE_IDX 1
+#define mmCP_PFP_METADATA_BASE_ADDR 0x20f0
+#define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1
+#define mmCP_PFP_METADATA_BASE_ADDR_HI 0x20f1
+#define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1
+#define mmCP_CE_METADATA_BASE_ADDR 0x20f2
+#define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX 1
+#define mmCP_CE_METADATA_BASE_ADDR_HI 0x20f3
+#define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1
+#define mmCP_DRAW_INDX_INDR_ADDR 0x20f4
+#define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1
+#define mmCP_DRAW_INDX_INDR_ADDR_HI 0x20f5
+#define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1
+#define mmCP_DISPATCH_INDR_ADDR 0x20f6
+#define mmCP_DISPATCH_INDR_ADDR_BASE_IDX 1
+#define mmCP_DISPATCH_INDR_ADDR_HI 0x20f7
+#define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1
+#define mmCP_INDEX_BASE_ADDR 0x20f8
+#define mmCP_INDEX_BASE_ADDR_BASE_IDX 1
+#define mmCP_INDEX_BASE_ADDR_HI 0x20f9
+#define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX 1
+#define mmCP_INDEX_TYPE 0x20fa
+#define mmCP_INDEX_TYPE_BASE_IDX 1
+#define mmCP_GDS_BKUP_ADDR 0x20fb
+#define mmCP_GDS_BKUP_ADDR_BASE_IDX 1
+#define mmCP_GDS_BKUP_ADDR_HI 0x20fc
+#define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX 1
+#define mmCP_SAMPLE_STATUS 0x20fd
+#define mmCP_SAMPLE_STATUS_BASE_IDX 1
+#define mmCP_ME_COHER_CNTL 0x20fe
+#define mmCP_ME_COHER_CNTL_BASE_IDX 1
+#define mmCP_ME_COHER_SIZE 0x20ff
+#define mmCP_ME_COHER_SIZE_BASE_IDX 1
+#define mmCP_ME_COHER_SIZE_HI 0x2100
+#define mmCP_ME_COHER_SIZE_HI_BASE_IDX 1
+#define mmCP_ME_COHER_BASE 0x2101
+#define mmCP_ME_COHER_BASE_BASE_IDX 1
+#define mmCP_ME_COHER_BASE_HI 0x2102
+#define mmCP_ME_COHER_BASE_HI_BASE_IDX 1
+#define mmCP_ME_COHER_STATUS 0x2103
+#define mmCP_ME_COHER_STATUS_BASE_IDX 1
+#define mmRLC_GPM_PERF_COUNT_0 0x2140
+#define mmRLC_GPM_PERF_COUNT_0_BASE_IDX 1
+#define mmRLC_GPM_PERF_COUNT_1 0x2141
+#define mmRLC_GPM_PERF_COUNT_1_BASE_IDX 1
+#define mmGRBM_GFX_INDEX 0x2200
+#define mmGRBM_GFX_INDEX_BASE_IDX 1
+#define mmVGT_ESGS_RING_SIZE_UMD 0x2240
+#define mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX 1
+#define mmVGT_GSVS_RING_SIZE_UMD 0x2241
+#define mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX 1
+#define mmVGT_PRIMITIVE_TYPE 0x2242
+#define mmVGT_PRIMITIVE_TYPE_BASE_IDX 1
+#define mmVGT_INDEX_TYPE 0x2243
+#define mmVGT_INDEX_TYPE_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1
+#define mmGE_MIN_VTX_INDX 0x2249
+#define mmGE_MIN_VTX_INDX_BASE_IDX 1
+#define mmGE_INDX_OFFSET 0x224a
+#define mmGE_INDX_OFFSET_BASE_IDX 1
+#define mmGE_MULTI_PRIM_IB_RESET_EN 0x224b
+#define mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1
+#define mmVGT_NUM_INDICES 0x224c
+#define mmVGT_NUM_INDICES_BASE_IDX 1
+#define mmVGT_NUM_INSTANCES 0x224d
+#define mmVGT_NUM_INSTANCES_BASE_IDX 1
+#define mmVGT_TF_RING_SIZE_UMD 0x224e
+#define mmVGT_TF_RING_SIZE_UMD_BASE_IDX 1
+#define mmVGT_HS_OFFCHIP_PARAM_UMD 0x224f
+#define mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX 1
+#define mmVGT_TF_MEMORY_BASE_UMD 0x2250
+#define mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX 1
+#define mmGE_DMA_FIRST_INDEX 0x2251
+#define mmGE_DMA_FIRST_INDEX_BASE_IDX 1
+#define mmWD_POS_BUF_BASE 0x2252
+#define mmWD_POS_BUF_BASE_BASE_IDX 1
+#define mmWD_POS_BUF_BASE_HI 0x2253
+#define mmWD_POS_BUF_BASE_HI_BASE_IDX 1
+#define mmWD_CNTL_SB_BUF_BASE 0x2254
+#define mmWD_CNTL_SB_BUF_BASE_BASE_IDX 1
+#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255
+#define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1
+#define mmWD_INDEX_BUF_BASE 0x2256
+#define mmWD_INDEX_BUF_BASE_BASE_IDX 1
+#define mmWD_INDEX_BUF_BASE_HI 0x2257
+#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1
+#define mmIA_MULTI_VGT_PARAM_PIPED 0x2258
+#define mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX 1
+#define mmGE_MAX_VTX_INDX 0x2259
+#define mmGE_MAX_VTX_INDX_BASE_IDX 1
+#define mmVGT_INSTANCE_BASE_ID 0x225a
+#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1
+#define mmGE_CNTL 0x225b
+#define mmGE_CNTL_BASE_IDX 1
+#define mmGE_USER_VGPR1 0x225c
+#define mmGE_USER_VGPR1_BASE_IDX 1
+#define mmGE_USER_VGPR2 0x225d
+#define mmGE_USER_VGPR2_BASE_IDX 1
+#define mmGE_USER_VGPR3 0x225e
+#define mmGE_USER_VGPR3_BASE_IDX 1
+#define mmGE_STEREO_CNTL 0x225f
+#define mmGE_STEREO_CNTL_BASE_IDX 1
+#define mmGE_PC_ALLOC 0x2260
+#define mmGE_PC_ALLOC_BASE_IDX 1
+#define mmVGT_TF_MEMORY_BASE_HI_UMD 0x2261
+#define mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX 1
+#define mmGE_USER_VGPR_EN 0x2262
+#define mmGE_USER_VGPR_EN_BASE_IDX 1
+#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280
+#define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1
+#define mmPA_SC_LINE_STIPPLE_STATE 0x2281
+#define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_MIN_0 0x2284
+#define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_MAX_0 0x2285
+#define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_MIN_1 0x2286
+#define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1
+#define mmPA_SC_SCREEN_EXTENT_MAX_1 0x228b
+#define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_H 0x22a1
+#define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_V 0x22a2
+#define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_H 0x22a9
+#define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_V 0x22aa
+#define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_HV_EN 0x22b0
+#define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_H 0x22b1
+#define mmPA_SC_TRAP_SCREEN_H_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_V 0x22b2
+#define mmPA_SC_TRAP_SCREEN_V_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1
+#define mmPA_SC_TRAP_SCREEN_COUNT 0x22b4
+#define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_0 0x2340
+#define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_1 0x2341
+#define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_2 0x2342
+#define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_3 0x2343
+#define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_4 0x2344
+#define mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_5 0x2345
+#define mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_6 0x2346
+#define mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX 1
+#define mmSQ_THREAD_TRACE_USERDATA_7 0x2347
+#define mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX 1
+#define mmSQC_CACHES 0x2348
+#define mmSQC_CACHES_BASE_IDX 1
+#define mmSQC_WRITEBACK 0x2349
+#define mmSQC_WRITEBACK_BASE_IDX 1
+#define mmTA_CS_BC_BASE_ADDR 0x2380
+#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1
+#define mmTA_CS_BC_BASE_ADDR_HI 0x2381
+#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0
+#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT0_HI 0x23c1
+#define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT1_LOW 0x23c2
+#define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT1_HI 0x23c3
+#define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT2_LOW 0x23c4
+#define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT2_HI 0x23c5
+#define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT3_LOW 0x23c6
+#define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1
+#define mmDB_OCCLUSION_COUNT3_HI 0x23c7
+#define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX 1
+#define mmDB_ZPASS_COUNT_LOW 0x23fe
+#define mmDB_ZPASS_COUNT_LOW_BASE_IDX 1
+#define mmDB_ZPASS_COUNT_HI 0x23ff
+#define mmDB_ZPASS_COUNT_HI_BASE_IDX 1
+#define mmGDS_RD_ADDR 0x2400
+#define mmGDS_RD_ADDR_BASE_IDX 1
+#define mmGDS_RD_DATA 0x2401
+#define mmGDS_RD_DATA_BASE_IDX 1
+#define mmGDS_RD_BURST_ADDR 0x2402
+#define mmGDS_RD_BURST_ADDR_BASE_IDX 1
+#define mmGDS_RD_BURST_COUNT 0x2403
+#define mmGDS_RD_BURST_COUNT_BASE_IDX 1
+#define mmGDS_RD_BURST_DATA 0x2404
+#define mmGDS_RD_BURST_DATA_BASE_IDX 1
+#define mmGDS_WR_ADDR 0x2405
+#define mmGDS_WR_ADDR_BASE_IDX 1
+#define mmGDS_WR_DATA 0x2406
+#define mmGDS_WR_DATA_BASE_IDX 1
+#define mmGDS_WR_BURST_ADDR 0x2407
+#define mmGDS_WR_BURST_ADDR_BASE_IDX 1
+#define mmGDS_WR_BURST_DATA 0x2408
+#define mmGDS_WR_BURST_DATA_BASE_IDX 1
+#define mmGDS_WRITE_COMPLETE 0x2409
+#define mmGDS_WRITE_COMPLETE_BASE_IDX 1
+#define mmGDS_ATOM_CNTL 0x240a
+#define mmGDS_ATOM_CNTL_BASE_IDX 1
+#define mmGDS_ATOM_COMPLETE 0x240b
+#define mmGDS_ATOM_COMPLETE_BASE_IDX 1
+#define mmGDS_ATOM_BASE 0x240c
+#define mmGDS_ATOM_BASE_BASE_IDX 1
+#define mmGDS_ATOM_SIZE 0x240d
+#define mmGDS_ATOM_SIZE_BASE_IDX 1
+#define mmGDS_ATOM_OFFSET0 0x240e
+#define mmGDS_ATOM_OFFSET0_BASE_IDX 1
+#define mmGDS_ATOM_OFFSET1 0x240f
+#define mmGDS_ATOM_OFFSET1_BASE_IDX 1
+#define mmGDS_ATOM_DST 0x2410
+#define mmGDS_ATOM_DST_BASE_IDX 1
+#define mmGDS_ATOM_OP 0x2411
+#define mmGDS_ATOM_OP_BASE_IDX 1
+#define mmGDS_ATOM_SRC0 0x2412
+#define mmGDS_ATOM_SRC0_BASE_IDX 1
+#define mmGDS_ATOM_SRC0_U 0x2413
+#define mmGDS_ATOM_SRC0_U_BASE_IDX 1
+#define mmGDS_ATOM_SRC1 0x2414
+#define mmGDS_ATOM_SRC1_BASE_IDX 1
+#define mmGDS_ATOM_SRC1_U 0x2415
+#define mmGDS_ATOM_SRC1_U_BASE_IDX 1
+#define mmGDS_ATOM_READ0 0x2416
+#define mmGDS_ATOM_READ0_BASE_IDX 1
+#define mmGDS_ATOM_READ0_U 0x2417
+#define mmGDS_ATOM_READ0_U_BASE_IDX 1
+#define mmGDS_ATOM_READ1 0x2418
+#define mmGDS_ATOM_READ1_BASE_IDX 1
+#define mmGDS_ATOM_READ1_U 0x2419
+#define mmGDS_ATOM_READ1_U_BASE_IDX 1
+#define mmGDS_GWS_RESOURCE_CNTL 0x241a
+#define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX 1
+#define mmGDS_GWS_RESOURCE 0x241b
+#define mmGDS_GWS_RESOURCE_BASE_IDX 1
+#define mmGDS_GWS_RESOURCE_CNT 0x241c
+#define mmGDS_GWS_RESOURCE_CNT_BASE_IDX 1
+#define mmGDS_OA_CNTL 0x241d
+#define mmGDS_OA_CNTL_BASE_IDX 1
+#define mmGDS_OA_COUNTER 0x241e
+#define mmGDS_OA_COUNTER_BASE_IDX 1
+#define mmGDS_OA_ADDRESS 0x241f
+#define mmGDS_OA_ADDRESS_BASE_IDX 1
+#define mmGDS_OA_INCDEC 0x2420
+#define mmGDS_OA_INCDEC_BASE_IDX 1
+#define mmGDS_OA_RING_SIZE 0x2421
+#define mmGDS_OA_RING_SIZE_BASE_IDX 1
+#define mmSPI_CONFIG_CNTL_REMAP 0x2440
+#define mmSPI_CONFIG_CNTL_REMAP_BASE_IDX 1
+#define mmSPI_CONFIG_CNTL_1_REMAP 0x2441
+#define mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX 1
+#define mmSPI_CONFIG_CNTL_2_REMAP 0x2442
+#define mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX 1
+#define mmSPI_WAVE_LIMIT_CNTL_REMAP 0x2443
+#define mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX 1
+
+
+// addressBlock: gc_cprs64dec
+// base address: 0x32000
+#define mmCP_MES_PRGRM_CNTR_START 0x2800
+#define mmCP_MES_PRGRM_CNTR_START_BASE_IDX 1
+#define mmCP_MES_INTR_ROUTINE_START 0x2801
+#define mmCP_MES_INTR_ROUTINE_START_BASE_IDX 1
+#define mmCP_MES_MTVEC_LO 0x2801
+#define mmCP_MES_MTVEC_LO_BASE_IDX 1
+#define mmCP_MES_MTVEC_HI 0x2802
+#define mmCP_MES_MTVEC_HI_BASE_IDX 1
+#define mmCP_MES_CNTL 0x2807
+#define mmCP_MES_CNTL_BASE_IDX 1
+#define mmCP_MES_PIPE_PRIORITY_CNTS 0x2808
+#define mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1
+#define mmCP_MES_PIPE0_PRIORITY 0x2809
+#define mmCP_MES_PIPE0_PRIORITY_BASE_IDX 1
+#define mmCP_MES_PIPE1_PRIORITY 0x280a
+#define mmCP_MES_PIPE1_PRIORITY_BASE_IDX 1
+#define mmCP_MES_PIPE2_PRIORITY 0x280b
+#define mmCP_MES_PIPE2_PRIORITY_BASE_IDX 1
+#define mmCP_MES_PIPE3_PRIORITY 0x280c
+#define mmCP_MES_PIPE3_PRIORITY_BASE_IDX 1
+#define mmCP_MES_HEADER_DUMP 0x280d
+#define mmCP_MES_HEADER_DUMP_BASE_IDX 1
+#define mmCP_MES_MIE_LO 0x280e
+#define mmCP_MES_MIE_LO_BASE_IDX 1
+#define mmCP_MES_MIE_HI 0x280f
+#define mmCP_MES_MIE_HI_BASE_IDX 1
+#define mmCP_MES_INTERRUPT 0x2810
+#define mmCP_MES_INTERRUPT_BASE_IDX 1
+#define mmCP_MES_SCRATCH_INDEX 0x2811
+#define mmCP_MES_SCRATCH_INDEX_BASE_IDX 1
+#define mmCP_MES_SCRATCH_DATA 0x2812
+#define mmCP_MES_SCRATCH_DATA_BASE_IDX 1
+#define mmCP_MES_INSTR_PNTR 0x2813
+#define mmCP_MES_INSTR_PNTR_BASE_IDX 1
+#define mmCP_MES_MSCRATCH_HI 0x2814
+#define mmCP_MES_MSCRATCH_HI_BASE_IDX 1
+#define mmCP_MES_MSCRATCH_LO 0x2815
+#define mmCP_MES_MSCRATCH_LO_BASE_IDX 1
+#define mmCP_MES_MSTATUS_LO 0x2816
+#define mmCP_MES_MSTATUS_LO_BASE_IDX 1
+#define mmCP_MES_MSTATUS_HI 0x2817
+#define mmCP_MES_MSTATUS_HI_BASE_IDX 1
+#define mmCP_MES_MEPC_LO 0x2818
+#define mmCP_MES_MEPC_LO_BASE_IDX 1
+#define mmCP_MES_MEPC_HI 0x2819
+#define mmCP_MES_MEPC_HI_BASE_IDX 1
+#define mmCP_MES_MCAUSE_LO 0x281a
+#define mmCP_MES_MCAUSE_LO_BASE_IDX 1
+#define mmCP_MES_MCAUSE_HI 0x281b
+#define mmCP_MES_MCAUSE_HI_BASE_IDX 1
+#define mmCP_MES_MBADADDR_LO 0x281c
+#define mmCP_MES_MBADADDR_LO_BASE_IDX 1
+#define mmCP_MES_MBADADDR_HI 0x281d
+#define mmCP_MES_MBADADDR_HI_BASE_IDX 1
+#define mmCP_MES_MIP_LO 0x281e
+#define mmCP_MES_MIP_LO_BASE_IDX 1
+#define mmCP_MES_MIP_HI 0x281f
+#define mmCP_MES_MIP_HI_BASE_IDX 1
+#define mmCP_MES_MCYCLE_LO 0x2826
+#define mmCP_MES_MCYCLE_LO_BASE_IDX 1
+#define mmCP_MES_MCYCLE_HI 0x2827
+#define mmCP_MES_MCYCLE_HI_BASE_IDX 1
+#define mmCP_MES_MTIME_LO 0x2828
+#define mmCP_MES_MTIME_LO_BASE_IDX 1
+#define mmCP_MES_MTIME_HI 0x2829
+#define mmCP_MES_MTIME_HI_BASE_IDX 1
+#define mmCP_MES_MINSTRET_LO 0x282a
+#define mmCP_MES_MINSTRET_LO_BASE_IDX 1
+#define mmCP_MES_MINSTRET_HI 0x282b
+#define mmCP_MES_MINSTRET_HI_BASE_IDX 1
+#define mmCP_MES_MISA_LO 0x282c
+#define mmCP_MES_MISA_LO_BASE_IDX 1
+#define mmCP_MES_MISA_HI 0x282d
+#define mmCP_MES_MISA_HI_BASE_IDX 1
+#define mmCP_MES_MVENDORID_LO 0x282e
+#define mmCP_MES_MVENDORID_LO_BASE_IDX 1
+#define mmCP_MES_MVENDORID_HI 0x282f
+#define mmCP_MES_MVENDORID_HI_BASE_IDX 1
+#define mmCP_MES_MARCHID_LO 0x2830
+#define mmCP_MES_MARCHID_LO_BASE_IDX 1
+#define mmCP_MES_MARCHID_HI 0x2831
+#define mmCP_MES_MARCHID_HI_BASE_IDX 1
+#define mmCP_MES_MIMPID_LO 0x2832
+#define mmCP_MES_MIMPID_LO_BASE_IDX 1
+#define mmCP_MES_MIMPID_HI 0x2833
+#define mmCP_MES_MIMPID_HI_BASE_IDX 1
+#define mmCP_MES_MHARTID_LO 0x2834
+#define mmCP_MES_MHARTID_LO_BASE_IDX 1
+#define mmCP_MES_MHARTID_HI 0x2835
+#define mmCP_MES_MHARTID_HI_BASE_IDX 1
+#define mmCP_MES_DC_BASE_CNTL 0x2836
+#define mmCP_MES_DC_BASE_CNTL_BASE_IDX 1
+#define mmCP_MES_DC_OP_CNTL 0x2837
+#define mmCP_MES_DC_OP_CNTL_BASE_IDX 1
+#define mmCP_MES_MTIMECMP_LO 0x2838
+#define mmCP_MES_MTIMECMP_LO_BASE_IDX 1
+#define mmCP_MES_MTIMECMP_HI 0x2839
+#define mmCP_MES_MTIMECMP_HI_BASE_IDX 1
+#define mmCP_MES_PROCESS_QUANTUM_PIPE0 0x283a
+#define mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX 1
+#define mmCP_MES_PROCESS_QUANTUM_PIPE1 0x283b
+#define mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX 1
+#define mmCP_MES_DOORBELL_CONTROL1 0x283c
+#define mmCP_MES_DOORBELL_CONTROL1_BASE_IDX 1
+#define mmCP_MES_DOORBELL_CONTROL2 0x283d
+#define mmCP_MES_DOORBELL_CONTROL2_BASE_IDX 1
+#define mmCP_MES_DOORBELL_CONTROL3 0x283e
+#define mmCP_MES_DOORBELL_CONTROL3_BASE_IDX 1
+#define mmCP_MES_DOORBELL_CONTROL4 0x283f
+#define mmCP_MES_DOORBELL_CONTROL4_BASE_IDX 1
+#define mmCP_MES_DOORBELL_CONTROL5 0x2840
+#define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
+#define mmCP_MES_DOORBELL_CONTROL6 0x2841
+#define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
+#define mmCP_MES_GP0_LO 0x2843
+#define mmCP_MES_GP0_LO_BASE_IDX 1
+#define mmCP_MES_GP0_HI 0x2844
+#define mmCP_MES_GP0_HI_BASE_IDX 1
+#define mmCP_MES_GP1_LO 0x2845
+#define mmCP_MES_GP1_LO_BASE_IDX 1
+#define mmCP_MES_GP1_HI 0x2846
+#define mmCP_MES_GP1_HI_BASE_IDX 1
+#define mmCP_MES_GP2_LO 0x2847
+#define mmCP_MES_GP2_LO_BASE_IDX 1
+#define mmCP_MES_GP2_HI 0x2848
+#define mmCP_MES_GP2_HI_BASE_IDX 1
+#define mmCP_MES_GP3_LO 0x2849
+#define mmCP_MES_GP3_LO_BASE_IDX 1
+#define mmCP_MES_GP3_HI 0x284a
+#define mmCP_MES_GP3_HI_BASE_IDX 1
+#define mmCP_MES_GP4_LO 0x284b
+#define mmCP_MES_GP4_LO_BASE_IDX 1
+#define mmCP_MES_GP4_HI 0x284c
+#define mmCP_MES_GP4_HI_BASE_IDX 1
+#define mmCP_MES_GP5_LO 0x284d
+#define mmCP_MES_GP5_LO_BASE_IDX 1
+#define mmCP_MES_GP5_HI 0x284e
+#define mmCP_MES_GP5_HI_BASE_IDX 1
+#define mmCP_MES_GP6_LO 0x284f
+#define mmCP_MES_GP6_LO_BASE_IDX 1
+#define mmCP_MES_GP6_HI 0x2850
+#define mmCP_MES_GP6_HI_BASE_IDX 1
+#define mmCP_MES_GP7_LO 0x2851
+#define mmCP_MES_GP7_LO_BASE_IDX 1
+#define mmCP_MES_GP7_HI 0x2852
+#define mmCP_MES_GP7_HI_BASE_IDX 1
+#define mmCP_MES_GP8_LO 0x2853
+#define mmCP_MES_GP8_LO_BASE_IDX 1
+#define mmCP_MES_GP8_HI 0x2854
+#define mmCP_MES_GP8_HI_BASE_IDX 1
+#define mmCP_MES_GP9_LO 0x2855
+#define mmCP_MES_GP9_LO_BASE_IDX 1
+#define mmCP_MES_GP9_HI 0x2856
+#define mmCP_MES_GP9_HI_BASE_IDX 1
+#define mmCP_MES_DM_INDEX_ADDR 0x2880
+#define mmCP_MES_DM_INDEX_ADDR_BASE_IDX 1
+#define mmCP_MES_DM_INDEX_DATA 0x2881
+#define mmCP_MES_DM_INDEX_DATA_BASE_IDX 1
+#define mmCP_MES_DMCONTROL 0x2882
+#define mmCP_MES_DMCONTROL_BASE_IDX 1
+#define mmCP_MES_DMINFO 0x2883
+#define mmCP_MES_DMINFO_BASE_IDX 1
+#define mmCP_MES_SETHALTNOTIFICATION 0x2885
+#define mmCP_MES_SETHALTNOTIFICATION_BASE_IDX 1
+#define mmCP_MES_TSELCT_LOW 0x2886
+#define mmCP_MES_TSELCT_LOW_BASE_IDX 1
+#define mmCP_MES_TSELCT_HIGH 0x2887
+#define mmCP_MES_TSELCT_HIGH_BASE_IDX 1
+#define mmCP_MES_TDATA1_LOW 0x2888
+#define mmCP_MES_TDATA1_LOW_BASE_IDX 1
+#define mmCP_MES_TDATA1_HIGH 0x2889
+#define mmCP_MES_TDATA1_HIGH_BASE_IDX 1
+#define mmCP_MES_TDATA2_LOW 0x288a
+#define mmCP_MES_TDATA2_LOW_BASE_IDX 1
+#define mmCP_MES_TDATA2_HIGH 0x288b
+#define mmCP_MES_TDATA2_HIGH_BASE_IDX 1
+#define mmCP_MES_TDATA3_LOW 0x288c
+#define mmCP_MES_TDATA3_LOW_BASE_IDX 1
+#define mmCP_MES_TDATA3_HIH 0x288d
+#define mmCP_MES_TDATA3_HIH_BASE_IDX 1
+#define mmCP_MES_DCSR 0x288e
+#define mmCP_MES_DCSR_BASE_IDX 1
+#define mmCP_MES_DPC_LOW 0x288f
+#define mmCP_MES_DPC_LOW_BASE_IDX 1
+#define mmCP_MES_DPC_HIGH 0x2890
+#define mmCP_MES_DPC_HIGH_BASE_IDX 1
+#define mmCP_MES_DSCRATCH_LOW 0x2891
+#define mmCP_MES_DSCRATCH_LOW_BASE_IDX 1
+#define mmCP_MES_DSCRATCH_HIGH 0x2892
+#define mmCP_MES_DSCRATCH_HIGH_BASE_IDX 1
+#define mmCP_MES_PERFCOUNT_CNTL 0x2899
+#define mmCP_MES_PERFCOUNT_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_gusdec
+// base address: 0x33000
+#define mmGUS_IO_RD_COMBINE_FLUSH 0x2c00
+#define mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX 1
+#define mmGUS_IO_WR_COMBINE_FLUSH 0x2c01
+#define mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_AGE_RATE 0x2c02
+#define mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_AGE_RATE 0x2c03
+#define mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_AGE_COEFF 0x2c04
+#define mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_AGE_COEFF 0x2c05
+#define mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_QUEUING 0x2c06
+#define mmGUS_IO_RD_PRI_QUEUING_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_QUEUING 0x2c07
+#define mmGUS_IO_WR_PRI_QUEUING_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_FIXED 0x2c08
+#define mmGUS_IO_RD_PRI_FIXED_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_FIXED 0x2c09
+#define mmGUS_IO_WR_PRI_FIXED_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_URGENCY_COEFF 0x2c0a
+#define mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_URGENCY_COEFF 0x2c0b
+#define mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_URGENCY_MODE 0x2c0c
+#define mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_URGENCY_MODE 0x2c0d
+#define mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_QUANT_PRI1 0x2c0e
+#define mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_QUANT_PRI2 0x2c0f
+#define mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_QUANT_PRI3 0x2c10
+#define mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_QUANT_PRI4 0x2c11
+#define mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_QUANT_PRI1 0x2c12
+#define mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_QUANT_PRI2 0x2c13
+#define mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_QUANT_PRI3 0x2c14
+#define mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_QUANT_PRI4 0x2c15
+#define mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_QUANT1_PRI1 0x2c16
+#define mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_QUANT1_PRI2 0x2c17
+#define mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_QUANT1_PRI3 0x2c18
+#define mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX 1
+#define mmGUS_IO_RD_PRI_QUANT1_PRI4 0x2c19
+#define mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_QUANT1_PRI1 0x2c1a
+#define mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_QUANT1_PRI2 0x2c1b
+#define mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_QUANT1_PRI3 0x2c1c
+#define mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX 1
+#define mmGUS_IO_WR_PRI_QUANT1_PRI4 0x2c1d
+#define mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX 1
+#define mmGUS_DRAM_COMBINE_FLUSH 0x2c1e
+#define mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX 1
+#define mmGUS_DRAM_COMBINE_RD_WR_EN 0x2c1f
+#define mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX 1
+#define mmGUS_DRAM_PRI_AGE_RATE 0x2c20
+#define mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX 1
+#define mmGUS_DRAM_PRI_AGE_COEFF 0x2c21
+#define mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUEUING 0x2c22
+#define mmGUS_DRAM_PRI_QUEUING_BASE_IDX 1
+#define mmGUS_DRAM_PRI_FIXED 0x2c23
+#define mmGUS_DRAM_PRI_FIXED_BASE_IDX 1
+#define mmGUS_DRAM_PRI_URGENCY_COEFF 0x2c24
+#define mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX 1
+#define mmGUS_DRAM_PRI_URGENCY_MODE 0x2c25
+#define mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT_PRI1 0x2c26
+#define mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT_PRI2 0x2c27
+#define mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT_PRI3 0x2c28
+#define mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT_PRI4 0x2c29
+#define mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT_PRI5 0x2c2a
+#define mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT1_PRI1 0x2c2b
+#define mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT1_PRI2 0x2c2c
+#define mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT1_PRI3 0x2c2d
+#define mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT1_PRI4 0x2c2e
+#define mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX 1
+#define mmGUS_DRAM_PRI_QUANT1_PRI5 0x2c2f
+#define mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX 1
+#define mmGUS_IO_GROUP_BURST 0x2c30
+#define mmGUS_IO_GROUP_BURST_BASE_IDX 1
+#define mmGUS_DRAM_GROUP_BURST 0x2c31
+#define mmGUS_DRAM_GROUP_BURST_BASE_IDX 1
+#define mmGUS_SDP_ARB_FINAL 0x2c32
+#define mmGUS_SDP_ARB_FINAL_BASE_IDX 1
+#define mmGUS_SDP_QOS_VC_PRIORITY 0x2c33
+#define mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX 1
+#define mmGUS_SDP_CREDITS 0x2c34
+#define mmGUS_SDP_CREDITS_BASE_IDX 1
+#define mmGUS_SDP_TAG_RESERVE0 0x2c35
+#define mmGUS_SDP_TAG_RESERVE0_BASE_IDX 1
+#define mmGUS_SDP_TAG_RESERVE1 0x2c36
+#define mmGUS_SDP_TAG_RESERVE1_BASE_IDX 1
+#define mmGUS_SDP_VCC_RESERVE0 0x2c37
+#define mmGUS_SDP_VCC_RESERVE0_BASE_IDX 1
+#define mmGUS_SDP_VCC_RESERVE1 0x2c38
+#define mmGUS_SDP_VCC_RESERVE1_BASE_IDX 1
+#define mmGUS_SDP_VCD_RESERVE0 0x2c39
+#define mmGUS_SDP_VCD_RESERVE0_BASE_IDX 1
+#define mmGUS_SDP_VCD_RESERVE1 0x2c3a
+#define mmGUS_SDP_VCD_RESERVE1_BASE_IDX 1
+#define mmGUS_SDP_REQ_CNTL 0x2c3b
+#define mmGUS_SDP_REQ_CNTL_BASE_IDX 1
+#define mmGUS_MISC 0x2c3c
+#define mmGUS_MISC_BASE_IDX 1
+#define mmGUS_LATENCY_SAMPLING 0x2c3d
+#define mmGUS_LATENCY_SAMPLING_BASE_IDX 1
+#define mmGUS_PERFCOUNTER_LO 0x2c3e
+#define mmGUS_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGUS_PERFCOUNTER_HI 0x2c3f
+#define mmGUS_PERFCOUNTER_HI_BASE_IDX 1
+#define mmGUS_PERFCOUNTER0_CFG 0x2c40
+#define mmGUS_PERFCOUNTER0_CFG_BASE_IDX 1
+#define mmGUS_PERFCOUNTER1_CFG 0x2c41
+#define mmGUS_PERFCOUNTER1_CFG_BASE_IDX 1
+#define mmGUS_PERFCOUNTER_RSLT_CNTL 0x2c42
+#define mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+#define mmGUS_ERR_STATUS 0x2c43
+#define mmGUS_ERR_STATUS_BASE_IDX 1
+#define mmGUS_MISC2 0x2c44
+#define mmGUS_MISC2_BASE_IDX 1
+#define mmGUS_SDP_BACKDOOR_CMDCREDITS0 0x2c45
+#define mmGUS_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 1
+#define mmGUS_SDP_BACKDOOR_CMDCREDITS1 0x2c46
+#define mmGUS_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 1
+#define mmGUS_SDP_BACKDOOR_DATACREDITS0 0x2c47
+#define mmGUS_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 1
+#define mmGUS_SDP_BACKDOOR_DATACREDITS1 0x2c48
+#define mmGUS_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 1
+#define mmGUS_SDP_BACKDOOR_MISCCREDITS 0x2c49
+#define mmGUS_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 1
+#define mmGUS_SDP_ENABLE 0x2c4a
+#define mmGUS_SDP_ENABLE_BASE_IDX 1
+#define mmGUS_L1_CH0_CMD_IN 0x2c4b
+#define mmGUS_L1_CH0_CMD_IN_BASE_IDX 1
+#define mmGUS_L1_CH0_CMD_OUT 0x2c4c
+#define mmGUS_L1_CH0_CMD_OUT_BASE_IDX 1
+#define mmGUS_L1_CH0_DATA_IN 0x2c4d
+#define mmGUS_L1_CH0_DATA_IN_BASE_IDX 1
+#define mmGUS_L1_CH0_DATA_OUT 0x2c4e
+#define mmGUS_L1_CH0_DATA_OUT_BASE_IDX 1
+#define mmGUS_L1_CH1_CMD_IN 0x2c4f
+#define mmGUS_L1_CH1_CMD_IN_BASE_IDX 1
+#define mmGUS_L1_CH1_CMD_OUT 0x2c50
+#define mmGUS_L1_CH1_CMD_OUT_BASE_IDX 1
+#define mmGUS_L1_CH1_DATA_IN 0x2c51
+#define mmGUS_L1_CH1_DATA_IN_BASE_IDX 1
+#define mmGUS_L1_CH1_DATA_OUT 0x2c52
+#define mmGUS_L1_CH1_DATA_OUT_BASE_IDX 1
+#define mmGUS_L1_SA0_CMD_IN 0x2c53
+#define mmGUS_L1_SA0_CMD_IN_BASE_IDX 1
+#define mmGUS_L1_SA0_CMD_OUT 0x2c54
+#define mmGUS_L1_SA0_CMD_OUT_BASE_IDX 1
+#define mmGUS_L1_SA0_DATA_IN 0x2c55
+#define mmGUS_L1_SA0_DATA_IN_BASE_IDX 1
+#define mmGUS_L1_SA0_DATA_OUT 0x2c56
+#define mmGUS_L1_SA0_DATA_OUT_BASE_IDX 1
+#define mmGUS_L1_SA0_DATA_U_IN 0x2c57
+#define mmGUS_L1_SA0_DATA_U_IN_BASE_IDX 1
+#define mmGUS_L1_SA0_DATA_U_OUT 0x2c58
+#define mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX 1
+#define mmGUS_L1_SA1_CMD_IN 0x2c59
+#define mmGUS_L1_SA1_CMD_IN_BASE_IDX 1
+#define mmGUS_L1_SA1_CMD_OUT 0x2c5a
+#define mmGUS_L1_SA1_CMD_OUT_BASE_IDX 1
+#define mmGUS_L1_SA1_DATA_IN 0x2c5b
+#define mmGUS_L1_SA1_DATA_IN_BASE_IDX 1
+#define mmGUS_L1_SA1_DATA_OUT 0x2c5c
+#define mmGUS_L1_SA1_DATA_OUT_BASE_IDX 1
+#define mmGUS_L1_SA1_DATA_U_IN 0x2c5d
+#define mmGUS_L1_SA1_DATA_U_IN_BASE_IDX 1
+#define mmGUS_L1_SA1_DATA_U_OUT 0x2c5e
+#define mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX 1
+#define mmGUS_L1_SA2_CMD_IN 0x2c5f
+#define mmGUS_L1_SA2_CMD_IN_BASE_IDX 1
+#define mmGUS_L1_SA2_CMD_OUT 0x2c60
+#define mmGUS_L1_SA2_CMD_OUT_BASE_IDX 1
+#define mmGUS_L1_SA2_DATA_IN 0x2c61
+#define mmGUS_L1_SA2_DATA_IN_BASE_IDX 1
+#define mmGUS_L1_SA2_DATA_OUT 0x2c62
+#define mmGUS_L1_SA2_DATA_OUT_BASE_IDX 1
+#define mmGUS_L1_SA2_DATA_U_IN 0x2c63
+#define mmGUS_L1_SA2_DATA_U_IN_BASE_IDX 1
+#define mmGUS_L1_SA2_DATA_U_OUT 0x2c64
+#define mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX 1
+#define mmGUS_L1_SA3_CMD_IN 0x2c65
+#define mmGUS_L1_SA3_CMD_IN_BASE_IDX 1
+#define mmGUS_L1_SA3_CMD_OUT 0x2c66
+#define mmGUS_L1_SA3_CMD_OUT_BASE_IDX 1
+#define mmGUS_L1_SA3_DATA_IN 0x2c67
+#define mmGUS_L1_SA3_DATA_IN_BASE_IDX 1
+#define mmGUS_L1_SA3_DATA_OUT 0x2c68
+#define mmGUS_L1_SA3_DATA_OUT_BASE_IDX 1
+#define mmGUS_L1_SA3_DATA_U_IN 0x2c69
+#define mmGUS_L1_SA3_DATA_U_IN_BASE_IDX 1
+#define mmGUS_L1_SA3_DATA_U_OUT 0x2c6a
+#define mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX 1
+#define mmGUS_MISC3 0x2c6b
+#define mmGUS_MISC3_BASE_IDX 1
+#define mmGUS_WRRSP_FIFO_CNTL 0x2c6c
+#define mmGUS_WRRSP_FIFO_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_gl1dec
+// base address: 0x33400
+#define mmGL1_ARB_CTRL 0x2d00
+#define mmGL1_ARB_CTRL_BASE_IDX 1
+#define mmGL1_DRAM_BURST_MASK 0x2d02
+#define mmGL1_DRAM_BURST_MASK_BASE_IDX 1
+#define mmGL1_ARB_STATUS 0x2d03
+#define mmGL1_ARB_STATUS_BASE_IDX 1
+#define mmGL1_DRAM_BURST_CTRL 0x2d04
+#define mmGL1_DRAM_BURST_CTRL_BASE_IDX 1
+#define mmGL1_PIPE_STEER 0x2d10
+#define mmGL1_PIPE_STEER_BASE_IDX 1
+#define mmGL1C_CTRL 0x2d40
+#define mmGL1C_CTRL_BASE_IDX 1
+#define mmGL1C_STATUS 0x2d41
+#define mmGL1C_STATUS_BASE_IDX 1
+
+
+// addressBlock: gc_chdec
+// base address: 0x33600
+#define mmCH_ARB_CTRL 0x2d80
+#define mmCH_ARB_CTRL_BASE_IDX 1
+#define mmCH_DRAM_BURST_MASK 0x2d82
+#define mmCH_DRAM_BURST_MASK_BASE_IDX 1
+#define mmCH_ARB_STATUS 0x2d83
+#define mmCH_ARB_STATUS_BASE_IDX 1
+#define mmCH_DRAM_BURST_CTRL 0x2d84
+#define mmCH_DRAM_BURST_CTRL_BASE_IDX 1
+#define mmCH_PIPE_STEER 0x2d90
+#define mmCH_PIPE_STEER_BASE_IDX 1
+#define mmCH_VC5_ENABLE 0x2d94
+#define mmCH_VC5_ENABLE_BASE_IDX 1
+#define mmCHC_CTRL 0x2dc0
+#define mmCHC_CTRL_BASE_IDX 1
+#define mmCHC_STATUS 0x2dc1
+#define mmCHC_STATUS_BASE_IDX 1
+#define mmCHCG_CTRL 0x2dc2
+#define mmCHCG_CTRL_BASE_IDX 1
+#define mmCHCG_STATUS 0x2dc3
+#define mmCHCG_STATUS_BASE_IDX 1
+
+
+// addressBlock: gc_gl2dec
+// base address: 0x33800
+#define mmGL2C_CTRL 0x2e00
+#define mmGL2C_CTRL_BASE_IDX 1
+#define mmGL2C_CTRL2 0x2e01
+#define mmGL2C_CTRL2_BASE_IDX 1
+#define mmGL2C_STATUS 0x2e02
+#define mmGL2C_STATUS_BASE_IDX 1
+#define mmGL2C_ADDR_MATCH_MASK 0x2e03
+#define mmGL2C_ADDR_MATCH_MASK_BASE_IDX 1
+#define mmGL2C_ADDR_MATCH_SIZE 0x2e04
+#define mmGL2C_ADDR_MATCH_SIZE_BASE_IDX 1
+#define mmGL2C_WBINVL2 0x2e05
+#define mmGL2C_WBINVL2_BASE_IDX 1
+#define mmGL2C_SOFT_RESET 0x2e06
+#define mmGL2C_SOFT_RESET_BASE_IDX 1
+#define mmGL2C_CM_CTRL0 0x2e07
+#define mmGL2C_CM_CTRL0_BASE_IDX 1
+#define mmGL2C_CM_CTRL1 0x2e08
+#define mmGL2C_CM_CTRL1_BASE_IDX 1
+#define mmGL2C_CM_STALL 0x2e09
+#define mmGL2C_CM_STALL_BASE_IDX 1
+#define mmGL2C_MDC_PF_FLAG_CTRL 0x2e0a
+#define mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX 1
+#define mmGL2C_CM_CTRL2 0x2e0b
+#define mmGL2C_CM_CTRL2_BASE_IDX 1
+#define mmGL2C_CTRL3 0x2e0c
+#define mmGL2C_CTRL3_BASE_IDX 1
+#define mmGL2C_LB_CTR_CTRL 0x2e0d
+#define mmGL2C_LB_CTR_CTRL_BASE_IDX 1
+#define mmGL2C_LB_DATA0 0x2e0e
+#define mmGL2C_LB_DATA0_BASE_IDX 1
+#define mmGL2C_LB_DATA1 0x2e0f
+#define mmGL2C_LB_DATA1_BASE_IDX 1
+#define mmGL2C_LB_DATA2 0x2e10
+#define mmGL2C_LB_DATA2_BASE_IDX 1
+#define mmGL2C_LB_DATA3 0x2e11
+#define mmGL2C_LB_DATA3_BASE_IDX 1
+#define mmGL2C_LB_CTR_SEL0 0x2e12
+#define mmGL2C_LB_CTR_SEL0_BASE_IDX 1
+#define mmGL2C_LB_CTR_SEL1 0x2e13
+#define mmGL2C_LB_CTR_SEL1_BASE_IDX 1
+#define mmGL2A_ADDR_MATCH_CTRL 0x2e20
+#define mmGL2A_ADDR_MATCH_CTRL_BASE_IDX 1
+#define mmGL2A_ADDR_MATCH_MASK 0x2e21
+#define mmGL2A_ADDR_MATCH_MASK_BASE_IDX 1
+#define mmGL2A_ADDR_MATCH_SIZE 0x2e22
+#define mmGL2A_ADDR_MATCH_SIZE_BASE_IDX 1
+#define mmGL2A_PRIORITY_CTRL 0x2e23
+#define mmGL2A_PRIORITY_CTRL_BASE_IDX 1
+#define mmGL2A_CTRL 0x2e24
+#define mmGL2A_CTRL_BASE_IDX 1
+#define mmGL2_PIPE_STEER_0 0x2e25
+#define mmGL2_PIPE_STEER_0_BASE_IDX 1
+#define mmGL2_PIPE_STEER_1 0x2e26
+#define mmGL2_PIPE_STEER_1_BASE_IDX 1
+
+
+// addressBlock: gc_perfddec
+// base address: 0x34000
+#define mmCPG_PERFCOUNTER1_LO 0x3000
+#define mmCPG_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCPG_PERFCOUNTER1_HI 0x3001
+#define mmCPG_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCPG_PERFCOUNTER0_LO 0x3002
+#define mmCPG_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCPG_PERFCOUNTER0_HI 0x3003
+#define mmCPG_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCPC_PERFCOUNTER1_LO 0x3004
+#define mmCPC_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCPC_PERFCOUNTER1_HI 0x3005
+#define mmCPC_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCPC_PERFCOUNTER0_LO 0x3006
+#define mmCPC_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCPC_PERFCOUNTER0_HI 0x3007
+#define mmCPC_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCPF_PERFCOUNTER1_LO 0x3008
+#define mmCPF_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCPF_PERFCOUNTER1_HI 0x3009
+#define mmCPF_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCPF_PERFCOUNTER0_LO 0x300a
+#define mmCPF_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCPF_PERFCOUNTER0_HI 0x300b
+#define mmCPF_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCPF_LATENCY_STATS_DATA 0x300c
+#define mmCPF_LATENCY_STATS_DATA_BASE_IDX 1
+#define mmCPG_LATENCY_STATS_DATA 0x300d
+#define mmCPG_LATENCY_STATS_DATA_BASE_IDX 1
+#define mmCPC_LATENCY_STATS_DATA 0x300e
+#define mmCPC_LATENCY_STATS_DATA_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER0_LO 0x3040
+#define mmGRBM_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER0_HI 0x3041
+#define mmGRBM_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER1_LO 0x3043
+#define mmGRBM_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER1_HI 0x3044
+#define mmGRBM_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGRBM_SE0_PERFCOUNTER_LO 0x3045
+#define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGRBM_SE0_PERFCOUNTER_HI 0x3046
+#define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1
+#define mmGRBM_SE1_PERFCOUNTER_LO 0x3047
+#define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGRBM_SE1_PERFCOUNTER_HI 0x3048
+#define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1
+#define mmGRBM_SE2_PERFCOUNTER_LO 0x3049
+#define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGRBM_SE2_PERFCOUNTER_HI 0x304a
+#define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1
+#define mmGRBM_SE3_PERFCOUNTER_LO 0x304b
+#define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGRBM_SE3_PERFCOUNTER_HI 0x304c
+#define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER0_LO 0x3080
+#define mmGE_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER0_HI 0x3081
+#define mmGE_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER1_LO 0x3082
+#define mmGE_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER1_HI 0x3083
+#define mmGE_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER2_LO 0x3084
+#define mmGE_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER2_HI 0x3085
+#define mmGE_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER3_LO 0x3086
+#define mmGE_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER3_HI 0x3087
+#define mmGE_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER4_LO 0x3088
+#define mmGE_PERFCOUNTER4_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER4_HI 0x3089
+#define mmGE_PERFCOUNTER4_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER5_LO 0x308a
+#define mmGE_PERFCOUNTER5_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER5_HI 0x308b
+#define mmGE_PERFCOUNTER5_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER6_LO 0x308c
+#define mmGE_PERFCOUNTER6_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER6_HI 0x308d
+#define mmGE_PERFCOUNTER6_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER7_LO 0x308e
+#define mmGE_PERFCOUNTER7_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER7_HI 0x308f
+#define mmGE_PERFCOUNTER7_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER8_LO 0x3090
+#define mmGE_PERFCOUNTER8_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER8_HI 0x3091
+#define mmGE_PERFCOUNTER8_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER9_LO 0x3092
+#define mmGE_PERFCOUNTER9_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER9_HI 0x3093
+#define mmGE_PERFCOUNTER9_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER10_LO 0x3094
+#define mmGE_PERFCOUNTER10_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER10_HI 0x3095
+#define mmGE_PERFCOUNTER10_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER11_LO 0x3096
+#define mmGE_PERFCOUNTER11_LO_BASE_IDX 1
+#define mmGE_PERFCOUNTER11_HI 0x3097
+#define mmGE_PERFCOUNTER11_HI_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER0_LO 0x3100
+#define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER0_HI 0x3101
+#define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER1_LO 0x3102
+#define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER1_HI 0x3103
+#define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER2_LO 0x3104
+#define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER2_HI 0x3105
+#define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER3_LO 0x3106
+#define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER3_HI 0x3107
+#define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER0_LO 0x3140
+#define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER0_HI 0x3141
+#define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER1_LO 0x3142
+#define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER1_HI 0x3143
+#define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER2_LO 0x3144
+#define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER2_HI 0x3145
+#define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER3_LO 0x3146
+#define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER3_HI 0x3147
+#define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER4_LO 0x3148
+#define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER4_HI 0x3149
+#define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER5_LO 0x314a
+#define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER5_HI 0x314b
+#define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER6_LO 0x314c
+#define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER6_HI 0x314d
+#define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER7_LO 0x314e
+#define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER7_HI 0x314f
+#define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER0_HI 0x3180
+#define mmSPI_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER0_LO 0x3181
+#define mmSPI_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER1_HI 0x3182
+#define mmSPI_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER1_LO 0x3183
+#define mmSPI_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER2_HI 0x3184
+#define mmSPI_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER2_LO 0x3185
+#define mmSPI_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER3_HI 0x3186
+#define mmSPI_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER3_LO 0x3187
+#define mmSPI_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER4_HI 0x3188
+#define mmSPI_PERFCOUNTER4_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER4_LO 0x3189
+#define mmSPI_PERFCOUNTER4_LO_BASE_IDX 1
+#define mmSPI_PERFCOUNTER5_HI 0x318a
+#define mmSPI_PERFCOUNTER5_HI_BASE_IDX 1
+#define mmSPI_PERFCOUNTER5_LO 0x318b
+#define mmSPI_PERFCOUNTER5_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER0_LO 0x31c0
+#define mmSQ_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER0_HI 0x31c1
+#define mmSQ_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER1_LO 0x31c2
+#define mmSQ_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER1_HI 0x31c3
+#define mmSQ_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER2_LO 0x31c4
+#define mmSQ_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER2_HI 0x31c5
+#define mmSQ_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER3_LO 0x31c6
+#define mmSQ_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER3_HI 0x31c7
+#define mmSQ_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER4_LO 0x31c8
+#define mmSQ_PERFCOUNTER4_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER4_HI 0x31c9
+#define mmSQ_PERFCOUNTER4_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER5_LO 0x31ca
+#define mmSQ_PERFCOUNTER5_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER5_HI 0x31cb
+#define mmSQ_PERFCOUNTER5_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER6_LO 0x31cc
+#define mmSQ_PERFCOUNTER6_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER6_HI 0x31cd
+#define mmSQ_PERFCOUNTER6_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER7_LO 0x31ce
+#define mmSQ_PERFCOUNTER7_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER7_HI 0x31cf
+#define mmSQ_PERFCOUNTER7_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER8_LO 0x31d0
+#define mmSQ_PERFCOUNTER8_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER8_HI 0x31d1
+#define mmSQ_PERFCOUNTER8_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER9_LO 0x31d2
+#define mmSQ_PERFCOUNTER9_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER9_HI 0x31d3
+#define mmSQ_PERFCOUNTER9_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER10_LO 0x31d4
+#define mmSQ_PERFCOUNTER10_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER10_HI 0x31d5
+#define mmSQ_PERFCOUNTER10_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER11_LO 0x31d6
+#define mmSQ_PERFCOUNTER11_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER11_HI 0x31d7
+#define mmSQ_PERFCOUNTER11_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER12_LO 0x31d8
+#define mmSQ_PERFCOUNTER12_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER12_HI 0x31d9
+#define mmSQ_PERFCOUNTER12_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER13_LO 0x31da
+#define mmSQ_PERFCOUNTER13_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER13_HI 0x31db
+#define mmSQ_PERFCOUNTER13_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER14_LO 0x31dc
+#define mmSQ_PERFCOUNTER14_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER14_HI 0x31dd
+#define mmSQ_PERFCOUNTER14_HI_BASE_IDX 1
+#define mmSQ_PERFCOUNTER15_LO 0x31de
+#define mmSQ_PERFCOUNTER15_LO_BASE_IDX 1
+#define mmSQ_PERFCOUNTER15_HI 0x31df
+#define mmSQ_PERFCOUNTER15_HI_BASE_IDX 1
+#define mmSX_PERFCOUNTER0_LO 0x3240
+#define mmSX_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmSX_PERFCOUNTER0_HI 0x3241
+#define mmSX_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmSX_PERFCOUNTER1_LO 0x3242
+#define mmSX_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmSX_PERFCOUNTER1_HI 0x3243
+#define mmSX_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmSX_PERFCOUNTER2_LO 0x3244
+#define mmSX_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmSX_PERFCOUNTER2_HI 0x3245
+#define mmSX_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmSX_PERFCOUNTER3_LO 0x3246
+#define mmSX_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmSX_PERFCOUNTER3_HI 0x3247
+#define mmSX_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmGCEA_PERFCOUNTER2_LO 0x3260
+#define mmGCEA_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGCEA_PERFCOUNTER2_HI 0x3261
+#define mmGCEA_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmGDS_PERFCOUNTER0_LO 0x3280
+#define mmGDS_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGDS_PERFCOUNTER0_HI 0x3281
+#define mmGDS_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGDS_PERFCOUNTER1_LO 0x3282
+#define mmGDS_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGDS_PERFCOUNTER1_HI 0x3283
+#define mmGDS_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGDS_PERFCOUNTER2_LO 0x3284
+#define mmGDS_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGDS_PERFCOUNTER2_HI 0x3285
+#define mmGDS_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmGDS_PERFCOUNTER3_LO 0x3286
+#define mmGDS_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmGDS_PERFCOUNTER3_HI 0x3287
+#define mmGDS_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmTA_PERFCOUNTER0_LO 0x32c0
+#define mmTA_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmTA_PERFCOUNTER0_HI 0x32c1
+#define mmTA_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmTA_PERFCOUNTER1_LO 0x32c2
+#define mmTA_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmTA_PERFCOUNTER1_HI 0x32c3
+#define mmTA_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmTD_PERFCOUNTER0_LO 0x3300
+#define mmTD_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmTD_PERFCOUNTER0_HI 0x3301
+#define mmTD_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmTD_PERFCOUNTER1_LO 0x3302
+#define mmTD_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmTD_PERFCOUNTER1_HI 0x3303
+#define mmTD_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmTCP_PERFCOUNTER0_LO 0x3340
+#define mmTCP_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmTCP_PERFCOUNTER0_HI 0x3341
+#define mmTCP_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmTCP_PERFCOUNTER1_LO 0x3342
+#define mmTCP_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmTCP_PERFCOUNTER1_HI 0x3343
+#define mmTCP_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmTCP_PERFCOUNTER2_LO 0x3344
+#define mmTCP_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmTCP_PERFCOUNTER2_HI 0x3345
+#define mmTCP_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmTCP_PERFCOUNTER3_LO 0x3346
+#define mmTCP_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmTCP_PERFCOUNTER3_HI 0x3347
+#define mmTCP_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER0_LO 0x3380
+#define mmGL2C_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER0_HI 0x3381
+#define mmGL2C_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER1_LO 0x3382
+#define mmGL2C_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER1_HI 0x3383
+#define mmGL2C_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER2_LO 0x3384
+#define mmGL2C_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER2_HI 0x3385
+#define mmGL2C_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER3_LO 0x3386
+#define mmGL2C_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER3_HI 0x3387
+#define mmGL2C_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER0_LO 0x3390
+#define mmGL2A_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER0_HI 0x3391
+#define mmGL2A_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER1_LO 0x3392
+#define mmGL2A_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER1_HI 0x3393
+#define mmGL2A_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER2_LO 0x3394
+#define mmGL2A_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER2_HI 0x3395
+#define mmGL2A_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER3_LO 0x3396
+#define mmGL2A_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER3_HI 0x3397
+#define mmGL2A_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER0_LO 0x33a0
+#define mmGL1C_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER0_HI 0x33a1
+#define mmGL1C_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER1_LO 0x33a2
+#define mmGL1C_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER1_HI 0x33a3
+#define mmGL1C_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER2_LO 0x33a4
+#define mmGL1C_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER2_HI 0x33a5
+#define mmGL1C_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER3_LO 0x33a6
+#define mmGL1C_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER3_HI 0x33a7
+#define mmGL1C_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmCHC_PERFCOUNTER0_LO 0x33c0
+#define mmCHC_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCHC_PERFCOUNTER0_HI 0x33c1
+#define mmCHC_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCHC_PERFCOUNTER1_LO 0x33c2
+#define mmCHC_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCHC_PERFCOUNTER1_HI 0x33c3
+#define mmCHC_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCHC_PERFCOUNTER2_LO 0x33c4
+#define mmCHC_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmCHC_PERFCOUNTER2_HI 0x33c5
+#define mmCHC_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmCHC_PERFCOUNTER3_LO 0x33c6
+#define mmCHC_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmCHC_PERFCOUNTER3_HI 0x33c7
+#define mmCHC_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER0_LO 0x33c8
+#define mmCHCG_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER0_HI 0x33c9
+#define mmCHCG_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER1_LO 0x33ca
+#define mmCHCG_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER1_HI 0x33cb
+#define mmCHCG_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER2_LO 0x33cc
+#define mmCHCG_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER2_HI 0x33cd
+#define mmCHCG_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER3_LO 0x33ce
+#define mmCHCG_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER3_HI 0x33cf
+#define mmCHCG_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmCB_PERFCOUNTER0_LO 0x3406
+#define mmCB_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCB_PERFCOUNTER0_HI 0x3407
+#define mmCB_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCB_PERFCOUNTER1_LO 0x3408
+#define mmCB_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCB_PERFCOUNTER1_HI 0x3409
+#define mmCB_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCB_PERFCOUNTER2_LO 0x340a
+#define mmCB_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmCB_PERFCOUNTER2_HI 0x340b
+#define mmCB_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmCB_PERFCOUNTER3_LO 0x340c
+#define mmCB_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmCB_PERFCOUNTER3_HI 0x340d
+#define mmCB_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmDB_PERFCOUNTER0_LO 0x3440
+#define mmDB_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmDB_PERFCOUNTER0_HI 0x3441
+#define mmDB_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmDB_PERFCOUNTER1_LO 0x3442
+#define mmDB_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmDB_PERFCOUNTER1_HI 0x3443
+#define mmDB_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmDB_PERFCOUNTER2_LO 0x3444
+#define mmDB_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmDB_PERFCOUNTER2_HI 0x3445
+#define mmDB_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmDB_PERFCOUNTER3_LO 0x3446
+#define mmDB_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmDB_PERFCOUNTER3_HI 0x3447
+#define mmDB_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmRLC_PERFCOUNTER0_LO 0x3480
+#define mmRLC_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmRLC_PERFCOUNTER0_HI 0x3481
+#define mmRLC_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmRLC_PERFCOUNTER1_LO 0x3482
+#define mmRLC_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmRLC_PERFCOUNTER1_HI 0x3483
+#define mmRLC_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmRMI_PERFCOUNTER0_LO 0x34c0
+#define mmRMI_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmRMI_PERFCOUNTER0_HI 0x34c1
+#define mmRMI_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmRMI_PERFCOUNTER1_LO 0x34c2
+#define mmRMI_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmRMI_PERFCOUNTER1_HI 0x34c3
+#define mmRMI_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmRMI_PERFCOUNTER2_LO 0x34c4
+#define mmRMI_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmRMI_PERFCOUNTER2_HI 0x34c5
+#define mmRMI_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmRMI_PERFCOUNTER3_LO 0x34c6
+#define mmRMI_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmRMI_PERFCOUNTER3_HI 0x34c7
+#define mmRMI_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmUTCL1_PERFCOUNTER0_LO 0x351c
+#define mmUTCL1_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmUTCL1_PERFCOUNTER0_HI 0x351d
+#define mmUTCL1_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmUTCL1_PERFCOUNTER1_LO 0x351e
+#define mmUTCL1_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmUTCL1_PERFCOUNTER1_HI 0x351f
+#define mmUTCL1_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGCR_PERFCOUNTER0_LO 0x3520
+#define mmGCR_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGCR_PERFCOUNTER0_HI 0x3521
+#define mmGCR_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGCR_PERFCOUNTER1_LO 0x3522
+#define mmGCR_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGCR_PERFCOUNTER1_HI 0x3523
+#define mmGCR_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER0_LO 0x3580
+#define mmPA_PH_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER0_HI 0x3581
+#define mmPA_PH_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER1_LO 0x3582
+#define mmPA_PH_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER1_HI 0x3583
+#define mmPA_PH_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER2_LO 0x3584
+#define mmPA_PH_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER2_HI 0x3585
+#define mmPA_PH_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER3_LO 0x3586
+#define mmPA_PH_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER3_HI 0x3587
+#define mmPA_PH_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER4_LO 0x3588
+#define mmPA_PH_PERFCOUNTER4_LO_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER4_HI 0x3589
+#define mmPA_PH_PERFCOUNTER4_HI_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER5_LO 0x358a
+#define mmPA_PH_PERFCOUNTER5_LO_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER5_HI 0x358b
+#define mmPA_PH_PERFCOUNTER5_HI_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER6_LO 0x358c
+#define mmPA_PH_PERFCOUNTER6_LO_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER6_HI 0x358d
+#define mmPA_PH_PERFCOUNTER6_HI_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER7_LO 0x358e
+#define mmPA_PH_PERFCOUNTER7_LO_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER7_HI 0x358f
+#define mmPA_PH_PERFCOUNTER7_HI_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER0_LO 0x35c0
+#define mmGL1A_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER0_HI 0x35c1
+#define mmGL1A_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER1_LO 0x35c2
+#define mmGL1A_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER1_HI 0x35c3
+#define mmGL1A_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER2_LO 0x35c4
+#define mmGL1A_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER2_HI 0x35c5
+#define mmGL1A_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER3_LO 0x35c6
+#define mmGL1A_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER3_HI 0x35c7
+#define mmGL1A_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmCHA_PERFCOUNTER0_LO 0x3600
+#define mmCHA_PERFCOUNTER0_LO_BASE_IDX 1
+#define mmCHA_PERFCOUNTER0_HI 0x3601
+#define mmCHA_PERFCOUNTER0_HI_BASE_IDX 1
+#define mmCHA_PERFCOUNTER1_LO 0x3602
+#define mmCHA_PERFCOUNTER1_LO_BASE_IDX 1
+#define mmCHA_PERFCOUNTER1_HI 0x3603
+#define mmCHA_PERFCOUNTER1_HI_BASE_IDX 1
+#define mmCHA_PERFCOUNTER2_LO 0x3604
+#define mmCHA_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmCHA_PERFCOUNTER2_HI 0x3605
+#define mmCHA_PERFCOUNTER2_HI_BASE_IDX 1
+#define mmCHA_PERFCOUNTER3_LO 0x3606
+#define mmCHA_PERFCOUNTER3_LO_BASE_IDX 1
+#define mmCHA_PERFCOUNTER3_HI 0x3607
+#define mmCHA_PERFCOUNTER3_HI_BASE_IDX 1
+#define mmGUS_PERFCOUNTER2_LO 0x3640
+#define mmGUS_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGUS_PERFCOUNTER2_HI 0x3641
+#define mmGUS_PERFCOUNTER2_HI_BASE_IDX 1
+
+
+// addressBlock: gc_gcatcl2pfcntrdec
+// base address: 0x35380
+#define mmGC_ATC_L2_PERFCOUNTER_LO 0x34e0
+#define mmGC_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGC_ATC_L2_PERFCOUNTER_HI 0x34e1
+#define mmGC_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: gc_gcvml2prdec
+// base address: 0x353a0
+#define mmGCMC_VM_L2_PERFCOUNTER_LO 0x34e8
+#define mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1
+#define mmGCMC_VM_L2_PERFCOUNTER_HI 0x34e9
+#define mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1
+
+
+// addressBlock: gc_gcvml2perfddec
+// base address: 0x353e0
+#define mmGCVML2_PERFCOUNTER2_0_LO 0x34f8
+#define mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX 1
+#define mmGCVML2_PERFCOUNTER2_1_LO 0x34f9
+#define mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX 1
+#define mmGCVML2_PERFCOUNTER2_0_HI 0x34fa
+#define mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX 1
+#define mmGCVML2_PERFCOUNTER2_1_HI 0x34fb
+#define mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX 1
+
+
+// addressBlock: gc_gcatcl2perfddec
+// base address: 0x353f0
+#define mmGC_ATC_L2_PERFCOUNTER2_LO 0x34fc
+#define mmGC_ATC_L2_PERFCOUNTER2_LO_BASE_IDX 1
+#define mmGC_ATC_L2_PERFCOUNTER2_HI 0x34fd
+#define mmGC_ATC_L2_PERFCOUNTER2_HI_BASE_IDX 1
+
+
+// addressBlock: gc_perfsdec
+// base address: 0x36000
+#define mmCPG_PERFCOUNTER1_SELECT 0x3800
+#define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCPG_PERFCOUNTER0_SELECT1 0x3801
+#define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCPG_PERFCOUNTER0_SELECT 0x3802
+#define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCPC_PERFCOUNTER1_SELECT 0x3803
+#define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCPC_PERFCOUNTER0_SELECT1 0x3804
+#define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCPF_PERFCOUNTER1_SELECT 0x3805
+#define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCPF_PERFCOUNTER0_SELECT1 0x3806
+#define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCPF_PERFCOUNTER0_SELECT 0x3807
+#define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCP_PERFMON_CNTL 0x3808
+#define mmCP_PERFMON_CNTL_BASE_IDX 1
+#define mmCPC_PERFCOUNTER0_SELECT 0x3809
+#define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a
+#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1
+#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b
+#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1
+#define mmCPF_LATENCY_STATS_SELECT 0x380c
+#define mmCPF_LATENCY_STATS_SELECT_BASE_IDX 1
+#define mmCPG_LATENCY_STATS_SELECT 0x380d
+#define mmCPG_LATENCY_STATS_SELECT_BASE_IDX 1
+#define mmCPC_LATENCY_STATS_SELECT 0x380e
+#define mmCPC_LATENCY_STATS_SELECT_BASE_IDX 1
+#define mmCP_DRAW_OBJECT 0x3810
+#define mmCP_DRAW_OBJECT_BASE_IDX 1
+#define mmCP_DRAW_OBJECT_COUNTER 0x3811
+#define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX 1
+#define mmCP_DRAW_WINDOW_MASK_HI 0x3812
+#define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1
+#define mmCP_DRAW_WINDOW_HI 0x3813
+#define mmCP_DRAW_WINDOW_HI_BASE_IDX 1
+#define mmCP_DRAW_WINDOW_LO 0x3814
+#define mmCP_DRAW_WINDOW_LO_BASE_IDX 1
+#define mmCP_DRAW_WINDOW_CNTL 0x3815
+#define mmCP_DRAW_WINDOW_CNTL_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER0_SELECT 0x3840
+#define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER1_SELECT 0x3841
+#define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x3842
+#define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1
+#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x3843
+#define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1
+#define mmGRBM_SE2_PERFCOUNTER_SELECT 0x3844
+#define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1
+#define mmGRBM_SE3_PERFCOUNTER_SELECT 0x3845
+#define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER0_SELECT_HI 0x384d
+#define mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX 1
+#define mmGRBM_PERFCOUNTER1_SELECT_HI 0x384e
+#define mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX 1
+#define mmGE_PERFCOUNTER0_SELECT 0x3880
+#define mmGE_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER0_SELECT1 0x3881
+#define mmGE_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmGE_PERFCOUNTER1_SELECT 0x3882
+#define mmGE_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER1_SELECT1 0x3883
+#define mmGE_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmGE_PERFCOUNTER2_SELECT 0x3884
+#define mmGE_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER2_SELECT1 0x3885
+#define mmGE_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmGE_PERFCOUNTER3_SELECT 0x3886
+#define mmGE_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER3_SELECT1 0x3887
+#define mmGE_PERFCOUNTER3_SELECT1_BASE_IDX 1
+#define mmGE_PERFCOUNTER4_SELECT 0x3888
+#define mmGE_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER5_SELECT 0x388a
+#define mmGE_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER6_SELECT 0x388c
+#define mmGE_PERFCOUNTER6_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER7_SELECT 0x388e
+#define mmGE_PERFCOUNTER7_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER8_SELECT 0x3890
+#define mmGE_PERFCOUNTER8_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER9_SELECT 0x3892
+#define mmGE_PERFCOUNTER9_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER10_SELECT 0x3894
+#define mmGE_PERFCOUNTER10_SELECT_BASE_IDX 1
+#define mmGE_PERFCOUNTER11_SELECT 0x3896
+#define mmGE_PERFCOUNTER11_SELECT_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER0_SELECT 0x3900
+#define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER0_SELECT1 0x3901
+#define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER1_SELECT 0x3902
+#define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER1_SELECT1 0x3903
+#define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER2_SELECT 0x3904
+#define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER2_SELECT1 0x3905
+#define mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER3_SELECT 0x3906
+#define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmPA_SU_PERFCOUNTER3_SELECT1 0x3907
+#define mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER0_SELECT 0x3940
+#define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER0_SELECT1 0x3941
+#define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER1_SELECT 0x3942
+#define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER2_SELECT 0x3943
+#define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER3_SELECT 0x3944
+#define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER4_SELECT 0x3945
+#define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER5_SELECT 0x3946
+#define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER6_SELECT 0x3947
+#define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1
+#define mmPA_SC_PERFCOUNTER7_SELECT 0x3948
+#define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER0_SELECT 0x3980
+#define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER1_SELECT 0x3981
+#define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER2_SELECT 0x3982
+#define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER3_SELECT 0x3983
+#define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER0_SELECT1 0x3984
+#define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmSPI_PERFCOUNTER1_SELECT1 0x3985
+#define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmSPI_PERFCOUNTER2_SELECT1 0x3986
+#define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmSPI_PERFCOUNTER3_SELECT1 0x3987
+#define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1
+#define mmSPI_PERFCOUNTER4_SELECT 0x3988
+#define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER5_SELECT 0x3989
+#define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define mmSPI_PERFCOUNTER_BINS 0x398a
+#define mmSPI_PERFCOUNTER_BINS_BASE_IDX 1
+#define mmSQ_PERFCOUNTER0_SELECT 0x39c0
+#define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER1_SELECT 0x39c1
+#define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER2_SELECT 0x39c2
+#define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER3_SELECT 0x39c3
+#define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER4_SELECT 0x39c4
+#define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER5_SELECT 0x39c5
+#define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER6_SELECT 0x39c6
+#define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER7_SELECT 0x39c7
+#define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER8_SELECT 0x39c8
+#define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER9_SELECT 0x39c9
+#define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER10_SELECT 0x39ca
+#define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER11_SELECT 0x39cb
+#define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER12_SELECT 0x39cc
+#define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER13_SELECT 0x39cd
+#define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER14_SELECT 0x39ce
+#define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER15_SELECT 0x39cf
+#define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX 1
+#define mmSQ_PERFCOUNTER_CTRL 0x39e0
+#define mmSQ_PERFCOUNTER_CTRL_BASE_IDX 1
+#define mmSQ_PERFCOUNTER_CTRL2 0x39e2
+#define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX 1
+#define mmGCEA_PERFCOUNTER2_SELECT 0x3a00
+#define mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGCEA_PERFCOUNTER2_SELECT1 0x3a01
+#define mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmGCEA_PERFCOUNTER2_MODE 0x3a02
+#define mmGCEA_PERFCOUNTER2_MODE_BASE_IDX 1
+#define mmSX_PERFCOUNTER0_SELECT 0x3a40
+#define mmSX_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmSX_PERFCOUNTER1_SELECT 0x3a41
+#define mmSX_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmSX_PERFCOUNTER2_SELECT 0x3a42
+#define mmSX_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmSX_PERFCOUNTER3_SELECT 0x3a43
+#define mmSX_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmSX_PERFCOUNTER0_SELECT1 0x3a44
+#define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmSX_PERFCOUNTER1_SELECT1 0x3a45
+#define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmGDS_PERFCOUNTER0_SELECT 0x3a80
+#define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGDS_PERFCOUNTER1_SELECT 0x3a81
+#define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmGDS_PERFCOUNTER2_SELECT 0x3a82
+#define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGDS_PERFCOUNTER3_SELECT 0x3a83
+#define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmGDS_PERFCOUNTER0_SELECT1 0x3a84
+#define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTA_PERFCOUNTER0_SELECT 0x3ac0
+#define mmTA_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmTA_PERFCOUNTER0_SELECT1 0x3ac1
+#define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTA_PERFCOUNTER1_SELECT 0x3ac2
+#define mmTA_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmTD_PERFCOUNTER0_SELECT 0x3b00
+#define mmTD_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmTD_PERFCOUNTER0_SELECT1 0x3b01
+#define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTD_PERFCOUNTER1_SELECT 0x3b02
+#define mmTD_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmTCP_PERFCOUNTER0_SELECT 0x3b40
+#define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmTCP_PERFCOUNTER0_SELECT1 0x3b41
+#define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmTCP_PERFCOUNTER1_SELECT 0x3b42
+#define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmTCP_PERFCOUNTER1_SELECT1 0x3b43
+#define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmTCP_PERFCOUNTER2_SELECT 0x3b44
+#define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmTCP_PERFCOUNTER3_SELECT 0x3b45
+#define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER0_SELECT 0x3b80
+#define mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER0_SELECT1 0x3b81
+#define mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER1_SELECT 0x3b82
+#define mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER1_SELECT1 0x3b83
+#define mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER2_SELECT 0x3b84
+#define mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGL2C_PERFCOUNTER3_SELECT 0x3b85
+#define mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER0_SELECT 0x3b90
+#define mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER0_SELECT1 0x3b91
+#define mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER1_SELECT 0x3b92
+#define mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER1_SELECT1 0x3b93
+#define mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER2_SELECT 0x3b94
+#define mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGL2A_PERFCOUNTER3_SELECT 0x3b95
+#define mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER0_SELECT 0x3ba0
+#define mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER0_SELECT1 0x3ba1
+#define mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER1_SELECT 0x3ba2
+#define mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER2_SELECT 0x3ba3
+#define mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGL1C_PERFCOUNTER3_SELECT 0x3ba4
+#define mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmCHC_PERFCOUNTER0_SELECT 0x3bc0
+#define mmCHC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCHC_PERFCOUNTER0_SELECT1 0x3bc1
+#define mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCHC_PERFCOUNTER1_SELECT 0x3bc2
+#define mmCHC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCHC_PERFCOUNTER2_SELECT 0x3bc3
+#define mmCHC_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmCHC_PERFCOUNTER3_SELECT 0x3bc4
+#define mmCHC_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER0_SELECT 0x3bc6
+#define mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER0_SELECT1 0x3bc7
+#define mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER1_SELECT 0x3bc8
+#define mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER2_SELECT 0x3bc9
+#define mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmCHCG_PERFCOUNTER3_SELECT 0x3bca
+#define mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmCB_PERFCOUNTER_FILTER 0x3c00
+#define mmCB_PERFCOUNTER_FILTER_BASE_IDX 1
+#define mmCB_PERFCOUNTER0_SELECT 0x3c01
+#define mmCB_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCB_PERFCOUNTER0_SELECT1 0x3c02
+#define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCB_PERFCOUNTER1_SELECT 0x3c03
+#define mmCB_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCB_PERFCOUNTER2_SELECT 0x3c04
+#define mmCB_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmCB_PERFCOUNTER3_SELECT 0x3c05
+#define mmCB_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmDB_PERFCOUNTER0_SELECT 0x3c40
+#define mmDB_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmDB_PERFCOUNTER0_SELECT1 0x3c41
+#define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmDB_PERFCOUNTER1_SELECT 0x3c42
+#define mmDB_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmDB_PERFCOUNTER1_SELECT1 0x3c43
+#define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmDB_PERFCOUNTER2_SELECT 0x3c44
+#define mmDB_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmDB_PERFCOUNTER3_SELECT 0x3c46
+#define mmDB_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_CNTL 0x3c80
+#define mmRLC_SPM_PERFMON_CNTL_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_RING_BASE_LO 0x3c81
+#define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_RING_BASE_HI 0x3c82
+#define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_RING_SIZE 0x3c83
+#define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1
+#define mmRLC_SPM_RING_RDPTR 0x3c85
+#define mmRLC_SPM_RING_RDPTR_BASE_IDX 1
+#define mmRLC_SPM_SEGMENT_THRESHOLD 0x3c86
+#define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1
+#define mmRLC_SPM_SE_MUXSEL_ADDR 0x3c87
+#define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1
+#define mmRLC_SPM_SE_MUXSEL_DATA 0x3c88
+#define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c89
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c8a
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1
+#define mmRLC_SPM_DESER_START_SKEW 0x3c8b
+#define mmRLC_SPM_DESER_START_SKEW_BASE_IDX 1
+#define mmRLC_SPM_GLOBALS_SAMPLE_SKEW 0x3c8c
+#define mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX 1
+#define mmRLC_SPM_GLOBALS_MUXSEL_SKEW 0x3c8d
+#define mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX 1
+#define mmRLC_SPM_SE_SAMPLE_SKEW 0x3c8e
+#define mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX 1
+#define mmRLC_SPM_SE_MUXSEL_SKEW 0x3c8f
+#define mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX 1
+#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR 0x3c90
+#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX 1
+#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA 0x3c91
+#define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX 1
+#define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR 0x3c92
+#define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX 1
+#define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA 0x3c93
+#define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX 1
+#define mmRLC_SPM_RING_WRPTR 0x3c94
+#define mmRLC_SPM_RING_WRPTR_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_DATARAM_ADDR 0x3c95
+#define mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_DATARAM_DATA 0x3c96
+#define mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_CTRLRAM_ADDR 0x3c97
+#define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_CTRLRAM_DATA 0x3c98
+#define mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_STATUS 0x3c99
+#define mmRLC_SPM_ACCUM_STATUS_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_CTRL 0x3c9a
+#define mmRLC_SPM_ACCUM_CTRL_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_MODE 0x3c9b
+#define mmRLC_SPM_ACCUM_MODE_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_THRESHOLD 0x3c9c
+#define mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED 0x3c9d
+#define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX 1
+#define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT 0x3c9e
+#define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE 0x3c9f
+#define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX 1
+#define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE 0x3ca0
+#define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX 1
+#define mmRLC_SPM_VIRT_CTRL 0x3ca1
+#define mmRLC_SPM_VIRT_CTRL_BASE_IDX 1
+#define mmRLC_SPM_VIRT_STATUS 0x3ca3
+#define mmRLC_SPM_VIRT_STATUS_BASE_IDX 1
+#define mmRLC_PERFMON_CNTL 0x3cc0
+#define mmRLC_PERFMON_CNTL_BASE_IDX 1
+#define mmRLC_PERFCOUNTER0_SELECT 0x3cc1
+#define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmRLC_PERFCOUNTER1_SELECT 0x3cc2
+#define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3
+#define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4
+#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5
+#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6
+#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1
+#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7
+#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1
+#define mmRLC_PERFMON_CLK_CNTL 0x3ce4
+#define mmRLC_PERFMON_CLK_CNTL_BASE_IDX 1
+#define mmRLC_PERFMON_CLK_CNTL_UCODE 0x3ce5
+#define mmRLC_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1
+#define mmRMI_PERFCOUNTER0_SELECT 0x3d00
+#define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmRMI_PERFCOUNTER0_SELECT1 0x3d01
+#define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmRMI_PERFCOUNTER1_SELECT 0x3d02
+#define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmRMI_PERFCOUNTER2_SELECT 0x3d03
+#define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmRMI_PERFCOUNTER2_SELECT1 0x3d04
+#define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmRMI_PERFCOUNTER3_SELECT 0x3d05
+#define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmRMI_PERF_COUNTER_CNTL 0x3d06
+#define mmRMI_PERF_COUNTER_CNTL_BASE_IDX 1
+#define mmGCR_PERFCOUNTER0_SELECT 0x3d60
+#define mmGCR_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGCR_PERFCOUNTER0_SELECT1 0x3d61
+#define mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmGCR_PERFCOUNTER1_SELECT 0x3d62
+#define mmGCR_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmUTCL1_PERFCOUNTER0_SELECT 0x3d63
+#define mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmUTCL1_PERFCOUNTER1_SELECT 0x3d64
+#define mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER0_SELECT 0x3d80
+#define mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER0_SELECT1 0x3d81
+#define mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER1_SELECT 0x3d82
+#define mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER2_SELECT 0x3d83
+#define mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER3_SELECT 0x3d84
+#define mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER4_SELECT 0x3d85
+#define mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER5_SELECT 0x3d86
+#define mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER6_SELECT 0x3d87
+#define mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER7_SELECT 0x3d88
+#define mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER1_SELECT1 0x3d90
+#define mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER2_SELECT1 0x3d91
+#define mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmPA_PH_PERFCOUNTER3_SELECT1 0x3d92
+#define mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER0_SELECT 0x3dc0
+#define mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER0_SELECT1 0x3dc1
+#define mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER1_SELECT 0x3dc2
+#define mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER2_SELECT 0x3dc3
+#define mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGL1A_PERFCOUNTER3_SELECT 0x3dc4
+#define mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmCHA_PERFCOUNTER0_SELECT 0x3de0
+#define mmCHA_PERFCOUNTER0_SELECT_BASE_IDX 1
+#define mmCHA_PERFCOUNTER0_SELECT1 0x3de1
+#define mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX 1
+#define mmCHA_PERFCOUNTER1_SELECT 0x3de2
+#define mmCHA_PERFCOUNTER1_SELECT_BASE_IDX 1
+#define mmCHA_PERFCOUNTER2_SELECT 0x3de3
+#define mmCHA_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmCHA_PERFCOUNTER3_SELECT 0x3de4
+#define mmCHA_PERFCOUNTER3_SELECT_BASE_IDX 1
+#define mmGUS_PERFCOUNTER2_SELECT 0x3e00
+#define mmGUS_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGUS_PERFCOUNTER2_SELECT1 0x3e01
+#define mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmGUS_PERFCOUNTER2_MODE 0x3e02
+#define mmGUS_PERFCOUNTER2_MODE_BASE_IDX 1
+
+
+// addressBlock: gc_gcatcl2pfcntldec
+// base address: 0x37480
+#define mmGC_ATC_L2_PERFCOUNTER0_CFG 0x3d20
+#define mmGC_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1
+#define mmGC_ATC_L2_PERFCOUNTER1_CFG 0x3d21
+#define mmGC_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1
+#define mmGC_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d22
+#define mmGC_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_gcvml2pldec
+// base address: 0x374b0
+#define mmGCMC_VM_L2_PERFCOUNTER0_CFG 0x3d2c
+#define mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1
+#define mmGCMC_VM_L2_PERFCOUNTER1_CFG 0x3d2d
+#define mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1
+#define mmGCMC_VM_L2_PERFCOUNTER2_CFG 0x3d2e
+#define mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1
+#define mmGCMC_VM_L2_PERFCOUNTER3_CFG 0x3d2f
+#define mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1
+#define mmGCMC_VM_L2_PERFCOUNTER4_CFG 0x3d30
+#define mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1
+#define mmGCMC_VM_L2_PERFCOUNTER5_CFG 0x3d31
+#define mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1
+#define mmGCMC_VM_L2_PERFCOUNTER6_CFG 0x3d32
+#define mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1
+#define mmGCMC_VM_L2_PERFCOUNTER7_CFG 0x3d33
+#define mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1
+#define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d34
+#define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_gcvml2perfsdec
+// base address: 0x374f0
+#define mmGCVML2_PERFCOUNTER2_0_SELECT 0x3d3c
+#define mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX 1
+#define mmGCVML2_PERFCOUNTER2_1_SELECT 0x3d3d
+#define mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX 1
+#define mmGCVML2_PERFCOUNTER2_0_SELECT1 0x3d3e
+#define mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX 1
+#define mmGCVML2_PERFCOUNTER2_1_SELECT1 0x3d3f
+#define mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX 1
+#define mmGCVML2_PERFCOUNTER2_0_MODE 0x3d40
+#define mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX 1
+#define mmGCVML2_PERFCOUNTER2_1_MODE 0x3d41
+#define mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX 1
+
+
+// addressBlock: gc_gcatcl2perfsdec
+// base address: 0x37530
+#define mmGC_ATC_L2_PERFCOUNTER2_SELECT 0x3d4c
+#define mmGC_ATC_L2_PERFCOUNTER2_SELECT_BASE_IDX 1
+#define mmGC_ATC_L2_PERFCOUNTER2_SELECT1 0x3d4d
+#define mmGC_ATC_L2_PERFCOUNTER2_SELECT1_BASE_IDX 1
+#define mmGC_ATC_L2_PERFCOUNTER2_MODE 0x3d4e
+#define mmGC_ATC_L2_PERFCOUNTER2_MODE_BASE_IDX 1
+
+
+// addressBlock: gc_rlcdec
+// base address: 0x3b000
+#define mmRLC_CNTL 0x4c00
+#define mmRLC_CNTL_BASE_IDX 1
+#define mmRLC_F32_UCODE_VERSION 0x4c03
+#define mmRLC_F32_UCODE_VERSION_BASE_IDX 1
+#define mmRLC_STAT 0x4c04
+#define mmRLC_STAT_BASE_IDX 1
+#define mmRLC_SAFE_MODE 0x4c05
+#define mmRLC_SAFE_MODE_BASE_IDX 1
+#define mmRLC_MEM_SLP_CNTL 0x4c06
+#define mmRLC_MEM_SLP_CNTL_BASE_IDX 1
+#define mmSMU_RLC_RESPONSE 0x4c07
+#define mmSMU_RLC_RESPONSE_BASE_IDX 1
+#define mmRLC_RLCV_SAFE_MODE 0x4c08
+#define mmRLC_RLCV_SAFE_MODE_BASE_IDX 1
+#define mmRLC_SMU_SAFE_MODE 0x4c09
+#define mmRLC_SMU_SAFE_MODE_BASE_IDX 1
+#define mmRLC_RLCV_COMMAND 0x4c0a
+#define mmRLC_RLCV_COMMAND_BASE_IDX 1
+#define mmRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c
+#define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1
+#define mmRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d
+#define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1
+#define mmRLC_GPM_TIMER_INT_0 0x4c0e
+#define mmRLC_GPM_TIMER_INT_0_BASE_IDX 1
+#define mmRLC_GPM_TIMER_INT_1 0x4c0f
+#define mmRLC_GPM_TIMER_INT_1_BASE_IDX 1
+#define mmRLC_GPM_TIMER_INT_2 0x4c10
+#define mmRLC_GPM_TIMER_INT_2_BASE_IDX 1
+#define mmRLC_GPM_TIMER_CTRL 0x4c11
+#define mmRLC_GPM_TIMER_CTRL_BASE_IDX 1
+#define mmRLC_LB_CNTR_MAX_1 0x4c12
+#define mmRLC_LB_CNTR_MAX_1_BASE_IDX 1
+#define mmRLC_GPM_TIMER_STAT 0x4c13
+#define mmRLC_GPM_TIMER_STAT_BASE_IDX 1
+#define mmRLC_GPM_TIMER_INT_3 0x4c15
+#define mmRLC_GPM_TIMER_INT_3_BASE_IDX 1
+#define mmRLC_INT_STAT 0x4c18
+#define mmRLC_INT_STAT_BASE_IDX 1
+#define mmRLC_LB_CNTL 0x4c19
+#define mmRLC_LB_CNTL_BASE_IDX 1
+#define mmRLC_MGCG_CTRL 0x4c1a
+#define mmRLC_MGCG_CTRL_BASE_IDX 1
+#define mmRLC_LB_CNTR_INIT_1 0x4c1b
+#define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
+#define mmRLC_LB_CNTR_1 0x4c1c
+#define mmRLC_LB_CNTR_1_BASE_IDX 1
+#define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
+#define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
+#define mmRLC_PG_DELAY_2 0x4c1f
+#define mmRLC_PG_DELAY_2_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
+#define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
+#define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1
+#define mmRLC_UCODE_CNTL 0x4c27
+#define mmRLC_UCODE_CNTL_BASE_IDX 1
+#define mmRLC_GPM_THREAD_RESET 0x4c28
+#define mmRLC_GPM_THREAD_RESET_BASE_IDX 1
+#define mmRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29
+#define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1
+#define mmRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a
+#define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1
+#define mmRLC_LB_CNTR_INIT_2 0x4c2b
+#define mmRLC_LB_CNTR_INIT_2_BASE_IDX 1
+#define mmRLC_LB_CNTR_MAX_2 0x4c2c
+#define mmRLC_LB_CNTR_MAX_2_BASE_IDX 1
+#define mmRLC_LB_CONFIG_5 0x4c2e
+#define mmRLC_LB_CONFIG_5_BASE_IDX 1
+#define mmRLC_CLK_COUNT_GFXCLK_LSB 0x4c30
+#define mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1
+#define mmRLC_CLK_COUNT_GFXCLK_MSB 0x4c31
+#define mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1
+#define mmRLC_CLK_COUNT_REFCLK_LSB 0x4c32
+#define mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1
+#define mmRLC_CLK_COUNT_REFCLK_MSB 0x4c33
+#define mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1
+#define mmRLC_CLK_COUNT_CTRL 0x4c34
+#define mmRLC_CLK_COUNT_CTRL_BASE_IDX 1
+#define mmRLC_CLK_COUNT_STAT 0x4c35
+#define mmRLC_CLK_COUNT_STAT_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_32_RES_SEL 0x4c41
+#define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_32 0x4c42
+#define mmRLC_GPU_CLOCK_32_BASE_IDX 1
+#define mmRLC_PG_CNTL 0x4c43
+#define mmRLC_PG_CNTL_BASE_IDX 1
+#define mmRLC_GPM_THREAD_PRIORITY 0x4c44
+#define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX 1
+#define mmRLC_GPM_THREAD_ENABLE 0x4c45
+#define mmRLC_GPM_THREAD_ENABLE_BASE_IDX 1
+#define mmRLC_CGTT_MGCG_OVERRIDE 0x4c48
+#define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1
+#define mmRLC_CGCG_CGLS_CTRL 0x4c49
+#define mmRLC_CGCG_CGLS_CTRL_BASE_IDX 1
+#define mmRLC_CGCG_RAMP_CTRL 0x4c4a
+#define mmRLC_CGCG_RAMP_CTRL_BASE_IDX 1
+#define mmRLC_DYN_PG_STATUS 0x4c4b
+#define mmRLC_DYN_PG_STATUS_BASE_IDX 1
+#define mmRLC_DYN_PG_REQUEST 0x4c4c
+#define mmRLC_DYN_PG_REQUEST_BASE_IDX 1
+#define mmRLC_PG_DELAY 0x4c4d
+#define mmRLC_PG_DELAY_BASE_IDX 1
+#define mmRLC_WGP_STATUS 0x4c4e
+#define mmRLC_WGP_STATUS_BASE_IDX 1
+#define mmRLC_LB_INIT_WGP_MASK 0x4c4f
+#define mmRLC_LB_INIT_WGP_MASK_BASE_IDX 1
+#define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK 0x4c50
+#define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX 1
+#define mmRLC_LB_PARAMS 0x4c51
+#define mmRLC_LB_PARAMS_BASE_IDX 1
+#define mmRLC_LB_DELAY 0x4c52
+#define mmRLC_LB_DELAY_BASE_IDX 1
+#define mmRLC_PG_ALWAYS_ON_WGP_MASK 0x4c53
+#define mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX 1
+#define mmRLC_MAX_PG_WGP 0x4c54
+#define mmRLC_MAX_PG_WGP_BASE_IDX 1
+#define mmRLC_AUTO_PG_CTRL 0x4c55
+#define mmRLC_AUTO_PG_CTRL_BASE_IDX 1
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1
+#define mmRLC_SERDES_RD_INDEX 0x4c59
+#define mmRLC_SERDES_RD_INDEX_BASE_IDX 1
+#define mmRLC_SERDES_RD_DATA_0 0x4c5a
+#define mmRLC_SERDES_RD_DATA_0_BASE_IDX 1
+#define mmRLC_SERDES_RD_DATA_1 0x4c5b
+#define mmRLC_SERDES_RD_DATA_1_BASE_IDX 1
+#define mmRLC_SERDES_RD_DATA_2 0x4c5c
+#define mmRLC_SERDES_RD_DATA_2_BASE_IDX 1
+#define mmRLC_SERDES_RD_DATA_3 0x4c5d
+#define mmRLC_SERDES_RD_DATA_3_BASE_IDX 1
+#define mmRLC_SERDES_MASK 0x4c5e
+#define mmRLC_SERDES_MASK_BASE_IDX 1
+#define mmRLC_SERDES_CTRL 0x4c5f
+#define mmRLC_SERDES_CTRL_BASE_IDX 1
+#define mmRLC_SERDES_DATA 0x4c60
+#define mmRLC_SERDES_DATA_BASE_IDX 1
+#define mmRLC_SERDES_BUSY 0x4c61
+#define mmRLC_SERDES_BUSY_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_0 0x4c63
+#define mmRLC_GPM_GENERAL_0_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_1 0x4c64
+#define mmRLC_GPM_GENERAL_1_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_2 0x4c65
+#define mmRLC_GPM_GENERAL_2_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_3 0x4c66
+#define mmRLC_GPM_GENERAL_3_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_4 0x4c67
+#define mmRLC_GPM_GENERAL_4_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_5 0x4c68
+#define mmRLC_GPM_GENERAL_5_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_6 0x4c69
+#define mmRLC_GPM_GENERAL_6_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_7 0x4c6a
+#define mmRLC_GPM_GENERAL_7_BASE_IDX 1
+#define mmRLC_STATIC_PG_STATUS 0x4c6e
+#define mmRLC_STATIC_PG_STATUS_BASE_IDX 1
+#define mmRLC_SPM_INT_INFO_1 0x4c6f
+#define mmRLC_SPM_INT_INFO_1_BASE_IDX 1
+#define mmRLC_SPM_INT_INFO_2 0x4c70
+#define mmRLC_SPM_INT_INFO_2_BASE_IDX 1
+#define mmRLC_SPM_MC_CNTL 0x4c71
+#define mmRLC_SPM_MC_CNTL_BASE_IDX 1
+#define mmRLC_SPM_INT_CNTL 0x4c72
+#define mmRLC_SPM_INT_CNTL_BASE_IDX 1
+#define mmRLC_SPM_INT_STATUS 0x4c73
+#define mmRLC_SPM_INT_STATUS_BASE_IDX 1
+#define mmRLC_SMU_MESSAGE 0x4c76
+#define mmRLC_SMU_MESSAGE_BASE_IDX 1
+#define mmRLC_GPM_LOG_SIZE 0x4c77
+#define mmRLC_GPM_LOG_SIZE_BASE_IDX 1
+#define mmRLC_PG_DELAY_3 0x4c78
+#define mmRLC_PG_DELAY_3_BASE_IDX 1
+#define mmRLC_GPR_REG1 0x4c79
+#define mmRLC_GPR_REG1_BASE_IDX 1
+#define mmRLC_GPR_REG2 0x4c7a
+#define mmRLC_GPR_REG2_BASE_IDX 1
+#define mmRLC_GPM_LOG_CONT 0x4c7b
+#define mmRLC_GPM_LOG_CONT_BASE_IDX 1
+#define mmRLC_GPM_INT_DISABLE_TH0 0x4c7c
+#define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1
+#define mmRLC_GPM_INT_FORCE_TH0 0x4c7e
+#define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX 1
+#define mmRLC_SRM_CNTL 0x4c80
+#define mmRLC_SRM_CNTL_BASE_IDX 1
+#define mmRLC_SRM_GPM_COMMAND 0x4c87
+#define mmRLC_SRM_GPM_COMMAND_BASE_IDX 1
+#define mmRLC_SRM_GPM_COMMAND_STATUS 0x4c88
+#define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1
+#define mmRLC_SRM_RLCV_COMMAND 0x4c89
+#define mmRLC_SRM_RLCV_COMMAND_BASE_IDX 1
+#define mmRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a
+#define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b
+#define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c
+#define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d
+#define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e
+#define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f
+#define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90
+#define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91
+#define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92
+#define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_0 0x4c93
+#define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_1 0x4c94
+#define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_2 0x4c95
+#define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_3 0x4c96
+#define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_4 0x4c97
+#define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_5 0x4c98
+#define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_6 0x4c99
+#define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1
+#define mmRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a
+#define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1
+#define mmRLC_SRM_STAT 0x4c9b
+#define mmRLC_SRM_STAT_BASE_IDX 1
+#define mmRLC_SRM_GPM_ABORT 0x4c9c
+#define mmRLC_SRM_GPM_ABORT_BASE_IDX 1
+#define mmRLC_CSIB_ADDR_LO 0x4ca2
+#define mmRLC_CSIB_ADDR_LO_BASE_IDX 1
+#define mmRLC_CSIB_ADDR_HI 0x4ca3
+#define mmRLC_CSIB_ADDR_HI_BASE_IDX 1
+#define mmRLC_CSIB_LENGTH 0x4ca4
+#define mmRLC_CSIB_LENGTH_BASE_IDX 1
+#define mmRLC_PACE_INT_STAT 0x4ca5
+#define mmRLC_PACE_INT_STAT_BASE_IDX 1
+#define mmRLC_SMU_COMMAND 0x4ca9
+#define mmRLC_SMU_COMMAND_BASE_IDX 1
+#define mmRLC_CP_SCHEDULERS 0x4caa
+#define mmRLC_CP_SCHEDULERS_BASE_IDX 1
+#define mmRLC_SMU_ARGUMENT_1 0x4cab
+#define mmRLC_SMU_ARGUMENT_1_BASE_IDX 1
+#define mmRLC_SMU_ARGUMENT_2 0x4cac
+#define mmRLC_SMU_ARGUMENT_2_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_8 0x4cad
+#define mmRLC_GPM_GENERAL_8_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_9 0x4cae
+#define mmRLC_GPM_GENERAL_9_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_10 0x4caf
+#define mmRLC_GPM_GENERAL_10_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_11 0x4cb0
+#define mmRLC_GPM_GENERAL_11_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_12 0x4cb1
+#define mmRLC_GPM_GENERAL_12_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_CNTL_0 0x4cb2
+#define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_CNTL_1 0x4cb3
+#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4
+#define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1
+#define mmRLC_SPM_UTCL1_CNTL 0x4cb5
+#define mmRLC_SPM_UTCL1_CNTL_BASE_IDX 1
+#define mmRLC_UTCL1_STATUS_2 0x4cb6
+#define mmRLC_UTCL1_STATUS_2_BASE_IDX 1
+#define mmRLC_LB_CONFIG_2 0x4cb8
+#define mmRLC_LB_CONFIG_2_BASE_IDX 1
+#define mmRLC_LB_CONFIG_3 0x4cb9
+#define mmRLC_LB_CONFIG_3_BASE_IDX 1
+#define mmRLC_LB_CONFIG_4 0x4cba
+#define mmRLC_LB_CONFIG_4_BASE_IDX 1
+#define mmRLC_SPM_UTCL1_ERROR_1 0x4cbc
+#define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1
+#define mmRLC_SPM_UTCL1_ERROR_2 0x4cbd
+#define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe
+#define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1
+#define mmRLC_LB_CONFIG_1 0x4cbf
+#define mmRLC_LB_CONFIG_1_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0
+#define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1
+#define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2
+#define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3
+#define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1
+#define mmRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4
+#define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1
+#define mmRLC_CGCG_CGLS_CTRL_3D 0x4cc5
+#define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1
+#define mmRLC_CGCG_RAMP_CTRL_3D 0x4cc6
+#define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1
+#define mmRLC_SEMAPHORE_0 0x4cc7
+#define mmRLC_SEMAPHORE_0_BASE_IDX 1
+#define mmRLC_SEMAPHORE_1 0x4cc8
+#define mmRLC_SEMAPHORE_1_BASE_IDX 1
+#define mmRLC_CP_EOF_INT 0x4cca
+#define mmRLC_CP_EOF_INT_BASE_IDX 1
+#define mmRLC_CP_EOF_INT_CNT 0x4ccb
+#define mmRLC_CP_EOF_INT_CNT_BASE_IDX 1
+#define mmRLC_SPARE_INT 0x4ccc
+#define mmRLC_SPARE_INT_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_CNTL 0x4ccd
+#define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_TRIG 0x4cce
+#define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf
+#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0
+#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1
+#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1
+#define mmRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2
+#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1
+#define mmRLC_UTCL1_STATUS 0x4cd4
+#define mmRLC_UTCL1_STATUS_BASE_IDX 1
+#define mmRLC_R2I_CNTL_0 0x4cd5
+#define mmRLC_R2I_CNTL_0_BASE_IDX 1
+#define mmRLC_R2I_CNTL_1 0x4cd6
+#define mmRLC_R2I_CNTL_1_BASE_IDX 1
+#define mmRLC_R2I_CNTL_2 0x4cd7
+#define mmRLC_R2I_CNTL_2_BASE_IDX 1
+#define mmRLC_R2I_CNTL_3 0x4cd8
+#define mmRLC_R2I_CNTL_3_BASE_IDX 1
+#define mmRLC_LB_WGP_STAT 0x4cda
+#define mmRLC_LB_WGP_STAT_BASE_IDX 1
+#define mmRLC_GPM_INT_STAT_TH0 0x4cdc
+#define mmRLC_GPM_INT_STAT_TH0_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_13 0x4cdd
+#define mmRLC_GPM_GENERAL_13_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_14 0x4cde
+#define mmRLC_GPM_GENERAL_14_BASE_IDX 1
+#define mmRLC_GPM_GENERAL_15 0x4cdf
+#define mmRLC_GPM_GENERAL_15_BASE_IDX 1
+#define mmRLC_SPARE_INT_1 0x4ce0
+#define mmRLC_SPARE_INT_1_BASE_IDX 1
+#define mmRLC_RLCV_SPARE_INT_1 0x4ce1
+#define mmRLC_RLCV_SPARE_INT_1_BASE_IDX 1
+#define mmRLC_PACE_SPARE_INT_1 0x4ce2
+#define mmRLC_PACE_SPARE_INT_1_BASE_IDX 1
+#define mmRLC_SEMAPHORE_2 0x4ce3
+#define mmRLC_SEMAPHORE_2_BASE_IDX 1
+#define mmRLC_SEMAPHORE_3 0x4ce4
+#define mmRLC_SEMAPHORE_3_BASE_IDX 1
+#define mmRLC_SMU_ARGUMENT_3 0x4ce5
+#define mmRLC_SMU_ARGUMENT_3_BASE_IDX 1
+#define mmRLC_SMU_ARGUMENT_4 0x4ce6
+#define mmRLC_SMU_ARGUMENT_4_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_LSB_1 0x4ce8
+#define mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_MSB_1 0x4ce9
+#define mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb
+#define mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec
+#define mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1
+#define mmRLC_PACE_INT_DISABLE 0x4ced
+#define mmRLC_PACE_INT_DISABLE_BASE_IDX 1
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1
+#define mmRLC_RLCV_SPARE_INT 0x4d00
+#define mmRLC_RLCV_SPARE_INT_BASE_IDX 1
+#define mmRLC_PACE_TIMER_INT_0 0x4d04
+#define mmRLC_PACE_TIMER_INT_0_BASE_IDX 1
+#define mmRLC_PACE_TIMER_CTRL 0x4d05
+#define mmRLC_PACE_TIMER_CTRL_BASE_IDX 1
+#define mmRLC_PACE_TIMER_INT_1 0x4d06
+#define mmRLC_PACE_TIMER_INT_1_BASE_IDX 1
+#define mmRLC_PACE_SPARE_INT 0x4d07
+#define mmRLC_PACE_SPARE_INT_BASE_IDX 1
+#define mmRLC_SMU_CLK_REQ 0x4d08
+#define mmRLC_SMU_CLK_REQ_BASE_IDX 1
+#define mmRLC_CP_STAT_INVAL_STAT 0x4d09
+#define mmRLC_CP_STAT_INVAL_STAT_BASE_IDX 1
+#define mmRLC_CP_STAT_INVAL_CTRL 0x4d0a
+#define mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX 1
+#define mmRLC_SPP_CTRL 0x4d0c
+#define mmRLC_SPP_CTRL_BASE_IDX 1
+#define mmRLC_SPP_SHADER_PROFILE_EN 0x4d0d
+#define mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX 1
+#define mmRLC_SPP_SSF_CAPTURE_EN 0x4d0e
+#define mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX 1
+#define mmRLC_SPP_SSF_THRESHOLD_0 0x4d0f
+#define mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX 1
+#define mmRLC_SPP_SSF_THRESHOLD_1 0x4d10
+#define mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX 1
+#define mmRLC_SPP_SSF_THRESHOLD_2 0x4d11
+#define mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX 1
+#define mmRLC_SPP_INFLIGHT_RD_ADDR 0x4d12
+#define mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX 1
+#define mmRLC_SPP_INFLIGHT_RD_DATA 0x4d13
+#define mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX 1
+#define mmRLC_SPP_PROF_INFO_1 0x4d18
+#define mmRLC_SPP_PROF_INFO_1_BASE_IDX 1
+#define mmRLC_SPP_PROF_INFO_2 0x4d19
+#define mmRLC_SPP_PROF_INFO_2_BASE_IDX 1
+#define mmRLC_SPP_GLOBAL_SH_ID 0x4d1a
+#define mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX 1
+#define mmRLC_SPP_GLOBAL_SH_ID_VALID 0x4d1b
+#define mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX 1
+#define mmRLC_SPP_STATUS 0x4d1c
+#define mmRLC_SPP_STATUS_BASE_IDX 1
+#define mmRLC_SPP_PVT_STAT_0 0x4d1d
+#define mmRLC_SPP_PVT_STAT_0_BASE_IDX 1
+#define mmRLC_SPP_PVT_STAT_1 0x4d1e
+#define mmRLC_SPP_PVT_STAT_1_BASE_IDX 1
+#define mmRLC_SPP_PVT_STAT_2 0x4d1f
+#define mmRLC_SPP_PVT_STAT_2_BASE_IDX 1
+#define mmRLC_SPP_PVT_STAT_3 0x4d20
+#define mmRLC_SPP_PVT_STAT_3_BASE_IDX 1
+#define mmRLC_SPP_PVT_LEVEL_MAX 0x4d21
+#define mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX 1
+#define mmRLC_SPP_STALL_STATE_UPDATE 0x4d22
+#define mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX 1
+#define mmRLC_SPP_PBB_INFO 0x4d23
+#define mmRLC_SPP_PBB_INFO_BASE_IDX 1
+#define mmRLC_SPP_RESET 0x4d24
+#define mmRLC_SPP_RESET_BASE_IDX 1
+#define mmRLC_SPM_SAMPLE_CNT 0x4d25
+#define mmRLC_SPM_SAMPLE_CNT_BASE_IDX 1
+#define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL 0x4d44
+#define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_SPM_LSB 0x4de4
+#define mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX 1
+#define mmRLC_GPU_CLOCK_COUNT_SPM_MSB 0x4de5
+#define mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX 1
+#define mmRLC_SPM_THREAD_TRACE_CTRL 0x4de6
+#define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
+#define mmRLC_LB_CNTR_2 0x4de7
+#define mmRLC_LB_CNTR_2_BASE_IDX 1
+#define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
+#define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
+#define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
+#define mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX 1
+#define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB 0x4df3
+#define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX 1
+#define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB 0x4df4
+#define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX 1
+
+
+// addressBlock: gc_rlcrdec
+// base address: 0x3b800
+#define mmRLC_SPP_CAM_ADDR 0x4e00
+#define mmRLC_SPP_CAM_ADDR_BASE_IDX 1
+#define mmRLC_SPP_CAM_DATA 0x4e01
+#define mmRLC_SPP_CAM_DATA_BASE_IDX 1
+#define mmRLC_SPP_CAM_EXT_ADDR 0x4e02
+#define mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX 1
+#define mmRLC_SPP_CAM_EXT_DATA 0x4e03
+#define mmRLC_SPP_CAM_EXT_DATA_BASE_IDX 1
+#define mmRLC_PACE_SCRATCH_ADDR 0x4e04
+#define mmRLC_PACE_SCRATCH_ADDR_BASE_IDX 1
+#define mmRLC_PACE_SCRATCH_DATA 0x4e05
+#define mmRLC_PACE_SCRATCH_DATA_BASE_IDX 1
+
+
+// addressBlock: gc_rlcsdec
+// base address: 0x3b980
+#define mmRLC_RLCS_DEC_START 0x4e60
+#define mmRLC_RLCS_DEC_START_BASE_IDX 1
+#define mmRLC_RLCS_DEC_DUMP_ADDR 0x4e61
+#define mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX 1
+#define mmRLC_RLCS_EXCEPTION_REG_1 0x4e62
+#define mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX 1
+#define mmRLC_RLCS_EXCEPTION_REG_2 0x4e63
+#define mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX 1
+#define mmRLC_RLCS_EXCEPTION_REG_3 0x4e64
+#define mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX 1
+#define mmRLC_RLCS_EXCEPTION_REG_4 0x4e65
+#define mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX 1
+#define mmRLC_RLCS_GENERAL_6 0x4e66
+#define mmRLC_RLCS_GENERAL_6_BASE_IDX 1
+#define mmRLC_RLCS_GENERAL_7 0x4e67
+#define mmRLC_RLCS_GENERAL_7_BASE_IDX 1
+#define mmRLC_RLCS_CGCG_REQUEST 0x4e68
+#define mmRLC_RLCS_CGCG_REQUEST_BASE_IDX 1
+#define mmRLC_RLCS_CGCG_STATUS 0x4e69
+#define mmRLC_RLCS_CGCG_STATUS_BASE_IDX 1
+#define mmRLC_RLCS_SMU_GFXCLK_STATUS 0x4e6a
+#define mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX 1
+#define mmRLC_RLCS_SMU_GFXCLK_CONTROL 0x4e6b
+#define mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX 1
+#define mmRLC_RLCS_SOC_DS_CNTL 0x4e6c
+#define mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX 1
+#define mmRLC_RLCS_GFX_DS_CNTL 0x4e6d
+#define mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX 1
+#define mmRLC_GPM_STAT 0x4e6e
+#define mmRLC_GPM_STAT_BASE_IDX 1
+#define mmRLC_RLCS_GPM_STAT 0x4e6e
+#define mmRLC_RLCS_GPM_STAT_BASE_IDX 1
+#define mmRLC_RLCS_ABORTED_PD_SEQUENCE 0x4e6f
+#define mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX 1
+#define mmRLC_RLCS_DIDT_FORCE_STALL 0x4e70
+#define mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX 1
+#define mmRLC_RLCS_IOV_CMD_STATUS 0x4e71
+#define mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX 1
+#define mmRLC_RLCS_IOV_CNTX_LOC_SIZE 0x4e72
+#define mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX 1
+#define mmRLC_RLCS_IOV_SCH_BLOCK 0x4e73
+#define mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX 1
+#define mmRLC_RLCS_IOV_VM_BUSY_STATUS 0x4e74
+#define mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX 1
+#define mmRLC_RLCS_GPM_STAT_2 0x4e75
+#define mmRLC_RLCS_GPM_STAT_2_BASE_IDX 1
+#define mmRLC_RLCS_GRBM_SOFT_RESET 0x4e76
+#define mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX 1
+#define mmRLC_RLCS_PG_CHANGE_STATUS 0x4e77
+#define mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX 1
+#define mmRLC_RLCS_PG_CHANGE_READ 0x4e78
+#define mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX 1
+#define mmRLC_RLCS_LB_STATUS 0x4e79
+#define mmRLC_RLCS_LB_STATUS_BASE_IDX 1
+#define mmRLC_RLCS_LB_READ 0x4e7a
+#define mmRLC_RLCS_LB_READ_BASE_IDX 1
+#define mmRLC_RLCS_LB_CONTROL 0x4e7b
+#define mmRLC_RLCS_LB_CONTROL_BASE_IDX 1
+#define mmRLC_RLCS_IH_SEMAPHORE 0x4e7c
+#define mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX 1
+#define mmRLC_RLCS_IH_COOKIE_SEMAPHORE 0x4e7d
+#define mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX 1
+#define mmRLC_RLCS_IH_CTRL_1 0x4e7e
+#define mmRLC_RLCS_IH_CTRL_1_BASE_IDX 1
+#define mmRLC_RLCS_IH_CTRL_2 0x4e7f
+#define mmRLC_RLCS_IH_CTRL_2_BASE_IDX 1
+#define mmRLC_RLCS_IH_CTRL_3 0x4e80
+#define mmRLC_RLCS_IH_CTRL_3_BASE_IDX 1
+#define mmRLC_RLCS_IH_STATUS 0x4e81
+#define mmRLC_RLCS_IH_STATUS_BASE_IDX 1
+#define mmRLC_RLCS_WGP_STATUS 0x4e82
+#define mmRLC_RLCS_WGP_STATUS_BASE_IDX 1
+#define mmRLC_RLCS_WGP_READ 0x4e83
+#define mmRLC_RLCS_WGP_READ_BASE_IDX 1
+#define mmRLC_RLCS_CP_INT_CTRL_1 0x4e84
+#define mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX 1
+#define mmRLC_RLCS_CP_INT_CTRL_2 0x4e85
+#define mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX 1
+#define mmRLC_RLCS_CP_INT_INFO_1 0x4e86
+#define mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX 1
+#define mmRLC_RLCS_CP_INT_INFO_2 0x4e87
+#define mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX 1
+#define mmRLC_RLCS_SPM_INT_CTRL 0x4e88
+#define mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX 1
+#define mmRLC_RLCS_SPM_INT_INFO_1 0x4e89
+#define mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX 1
+#define mmRLC_RLCS_SPM_INT_INFO_2 0x4e8a
+#define mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX 1
+#define mmRLC_RLCS_DSM_TRIG 0x4e8b
+#define mmRLC_RLCS_DSM_TRIG_BASE_IDX 1
+#define mmRLC_RLCS_GE_FAST_CLOCK 0x4e8c
+#define mmRLC_RLCS_GE_FAST_CLOCK_BASE_IDX 1
+#define mmRLC_RLCS_BOOTLOAD_STATUS 0x4e8d
+#define mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX 1
+#define mmRLC_RLCS_POWER_BRAKE_CNTL 0x4e8e
+#define mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX 1
+#define mmRLC_RLCS_GENERAL_0 0x4e8f
+#define mmRLC_RLCS_GENERAL_0_BASE_IDX 1
+#define mmRLC_RLCS_GENERAL_1 0x4e90
+#define mmRLC_RLCS_GENERAL_1_BASE_IDX 1
+#define mmRLC_RLCS_GENERAL_2 0x4e91
+#define mmRLC_RLCS_GENERAL_2_BASE_IDX 1
+#define mmRLC_RLCS_GENERAL_3 0x4e92
+#define mmRLC_RLCS_GENERAL_3_BASE_IDX 1
+#define mmRLC_RLCS_GENERAL_4 0x4e93
+#define mmRLC_RLCS_GENERAL_4_BASE_IDX 1
+#define mmRLC_RLCS_GENERAL_5 0x4e94
+#define mmRLC_RLCS_GENERAL_5_BASE_IDX 1
+#define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT 0x4ec1
+#define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX 1
+#define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL 0x4ec2
+#define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX 1
+#define mmRLC_RLCS_CMP_IDLE_CNTL 0x4ec3
+#define mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX 1
+#define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 0x4ec4
+#define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX 1
+#define mmRLC_RLCS_AUXILIARY_REG_1 0x4ec5
+#define mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX 1
+#define mmRLC_RLCS_AUXILIARY_REG_2 0x4ec6
+#define mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX 1
+#define mmRLC_RLCS_AUXILIARY_REG_3 0x4ec7
+#define mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX 1
+#define mmRLC_RLCS_AUXILIARY_REG_4 0x4ec8
+#define mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX 1
+#define mmRLC_RLCS_SPM_SQTT_MODE 0x4ee0
+#define mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX 1
+#define mmRLC_RLCS_CP_DMA_SRCID_OVER 0x4ee4
+#define mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX 1
+#define mmRLC_RLCS_UTCL2_CNTL 0x4ee6
+#define mmRLC_RLCS_UTCL2_CNTL_BASE_IDX 1
+#define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL 0x4ee8
+#define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX 1
+#define mmRLC_RLCS_BOOTLOAD_ID_STATUS1 0x4eec
+#define mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX 1
+#define mmRLC_RLCS_BOOTLOAD_ID_STATUS2 0x4eed
+#define mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX 1
+#define mmRLC_RLCS_EDC_INT_CNTL 0x4eef
+#define mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX 1
+#define mmRLC_RLCS_DEC_END 0x4fff
+#define mmRLC_RLCS_DEC_END_BASE_IDX 1
+
+
+// addressBlock: gc_pwrdec
+// base address: 0x3c000
+#define mmCGTS_SA0_QUAD0_SM_CTRL_REG 0x5000
+#define mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG 0x5001
+#define mmCGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG_BASE_IDX 1
+#define mmCGTS_SA0_QUAD1_SM_CTRL_REG 0x5002
+#define mmCGTS_SA0_QUAD1_SM_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG 0x5003
+#define mmCGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG_BASE_IDX 1
+#define mmCGTS_SA1_QUAD0_SM_CTRL_REG 0x5004
+#define mmCGTS_SA1_QUAD0_SM_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG 0x5005
+#define mmCGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG_BASE_IDX 1
+#define mmCGTS_SA1_QUAD1_SM_CTRL_REG 0x5006
+#define mmCGTS_SA1_QUAD1_SM_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG 0x5007
+#define mmCGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG_BASE_IDX 1
+#define mmCGTS_RD_CTRL_REG 0x5008
+#define mmCGTS_RD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_RD_REG 0x5009
+#define mmCGTS_RD_REG_BASE_IDX 1
+#define mmCGTS_TCC_DISABLE 0x500a
+#define mmCGTS_TCC_DISABLE_BASE_IDX 1
+#define mmCGTS_USER_TCC_DISABLE 0x500b
+#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1
+#define mmCGTS_STATUS_REG 0x500c
+#define mmCGTS_STATUS_REG_BASE_IDX 1
+#define mmCGTT_SPI_CGTSSM_CLK_CTRL 0x500d
+#define mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX 1
+#define mmCGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG 0x5010
+#define mmCGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG 0x5011
+#define mmCGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP00_CU0_TATD_CTRL_REG 0x5012
+#define mmCGTS_SA0_WGP00_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG 0x5013
+#define mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG 0x5014
+#define mmCGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG 0x5015
+#define mmCGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP00_CU1_TATD_CTRL_REG 0x5016
+#define mmCGTS_SA0_WGP00_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG 0x5017
+#define mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG 0x5018
+#define mmCGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG 0x5019
+#define mmCGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP01_CU0_TATD_CTRL_REG 0x501a
+#define mmCGTS_SA0_WGP01_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG 0x501b
+#define mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG 0x501c
+#define mmCGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG 0x501d
+#define mmCGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP01_CU1_TATD_CTRL_REG 0x501e
+#define mmCGTS_SA0_WGP01_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG 0x501f
+#define mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG 0x5020
+#define mmCGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG 0x5021
+#define mmCGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP02_CU0_TATD_CTRL_REG 0x5022
+#define mmCGTS_SA0_WGP02_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG 0x5023
+#define mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG 0x5024
+#define mmCGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG 0x5025
+#define mmCGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP02_CU1_TATD_CTRL_REG 0x5026
+#define mmCGTS_SA0_WGP02_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG 0x5027
+#define mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG 0x5028
+#define mmCGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG 0x5029
+#define mmCGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP10_CU0_TATD_CTRL_REG 0x502a
+#define mmCGTS_SA0_WGP10_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG 0x502b
+#define mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG 0x502c
+#define mmCGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG 0x502d
+#define mmCGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP10_CU1_TATD_CTRL_REG 0x502e
+#define mmCGTS_SA0_WGP10_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG 0x502f
+#define mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG 0x5030
+#define mmCGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG 0x5031
+#define mmCGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP11_CU0_TATD_CTRL_REG 0x5032
+#define mmCGTS_SA0_WGP11_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG 0x5033
+#define mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG 0x5034
+#define mmCGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG 0x5035
+#define mmCGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP11_CU1_TATD_CTRL_REG 0x5036
+#define mmCGTS_SA0_WGP11_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG 0x5037
+#define mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG 0x5038
+#define mmCGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG 0x5039
+#define mmCGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP00_CU0_TATD_CTRL_REG 0x503a
+#define mmCGTS_SA1_WGP00_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG 0x503b
+#define mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG 0x503c
+#define mmCGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG 0x503d
+#define mmCGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP00_CU1_TATD_CTRL_REG 0x503e
+#define mmCGTS_SA1_WGP00_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG 0x503f
+#define mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG 0x5040
+#define mmCGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG 0x5041
+#define mmCGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP01_CU0_TATD_CTRL_REG 0x5042
+#define mmCGTS_SA1_WGP01_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG 0x5043
+#define mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG 0x5044
+#define mmCGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG 0x5045
+#define mmCGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP01_CU1_TATD_CTRL_REG 0x5046
+#define mmCGTS_SA1_WGP01_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG 0x5047
+#define mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG 0x5048
+#define mmCGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG 0x5049
+#define mmCGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP02_CU0_TATD_CTRL_REG 0x504a
+#define mmCGTS_SA1_WGP02_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG 0x504b
+#define mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG 0x504c
+#define mmCGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG 0x504d
+#define mmCGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP02_CU1_TATD_CTRL_REG 0x504e
+#define mmCGTS_SA1_WGP02_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG 0x504f
+#define mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG 0x5050
+#define mmCGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG 0x5051
+#define mmCGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP10_CU0_TATD_CTRL_REG 0x5052
+#define mmCGTS_SA1_WGP10_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG 0x5053
+#define mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG 0x5054
+#define mmCGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG 0x5055
+#define mmCGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP10_CU1_TATD_CTRL_REG 0x5056
+#define mmCGTS_SA1_WGP10_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG 0x5057
+#define mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG 0x5058
+#define mmCGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG 0x5059
+#define mmCGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP11_CU0_TATD_CTRL_REG 0x505a
+#define mmCGTS_SA1_WGP11_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG 0x505b
+#define mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG 0x505c
+#define mmCGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG 0x505d
+#define mmCGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP11_CU1_TATD_CTRL_REG 0x505e
+#define mmCGTS_SA1_WGP11_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG 0x505f
+#define mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG 0x5060
+#define mmCGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG 0x5061
+#define mmCGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP12_CU0_TATD_CTRL_REG 0x5062
+#define mmCGTS_SA0_WGP12_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG 0x5063
+#define mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG 0x5064
+#define mmCGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG 0x5065
+#define mmCGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP12_CU1_TATD_CTRL_REG 0x5066
+#define mmCGTS_SA0_WGP12_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG 0x5067
+#define mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG 0x5068
+#define mmCGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG 0x5069
+#define mmCGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP12_CU0_TATD_CTRL_REG 0x506a
+#define mmCGTS_SA1_WGP12_CU0_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG 0x506b
+#define mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG 0x506c
+#define mmCGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG 0x506d
+#define mmCGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP12_CU1_TATD_CTRL_REG 0x506e
+#define mmCGTS_SA1_WGP12_CU1_TATD_CTRL_REG_BASE_IDX 1
+#define mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 0x506f
+#define mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG_BASE_IDX 1
+#define mmCGTT_SPI_PS_CLK_CTRL 0x507d
+#define mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_SPIS_CLK_CTRL 0x507e
+#define mmCGTT_SPIS_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_SPI_CLK_CTRL 0x5080
+#define mmCGTT_SPI_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_PC_CLK_CTRL 0x5081
+#define mmCGTT_PC_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_BCI_CLK_CTRL 0x5082
+#define mmCGTT_BCI_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_VGT_CLK_CTRL 0x5084
+#define mmCGTT_VGT_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_IA_CLK_CTRL 0x5085
+#define mmCGTT_IA_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_WD_CLK_CTRL 0x5086
+#define mmCGTT_WD_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_PA_CLK_CTRL 0x5088
+#define mmCGTT_PA_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_SC_CLK_CTRL0 0x5089
+#define mmCGTT_SC_CLK_CTRL0_BASE_IDX 1
+#define mmCGTT_SC_CLK_CTRL1 0x508a
+#define mmCGTT_SC_CLK_CTRL1_BASE_IDX 1
+#define mmCGTT_SC_CLK_CTRL2 0x508b
+#define mmCGTT_SC_CLK_CTRL2_BASE_IDX 1
+#define mmCGTT_SQ_CLK_CTRL 0x508c
+#define mmCGTT_SQ_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_SQG_CLK_CTRL 0x508d
+#define mmCGTT_SQG_CLK_CTRL_BASE_IDX 1
+#define mmSQ_ALU_CLK_CTRL 0x508e
+#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1
+#define mmSQ_TEX_CLK_CTRL 0x508f
+#define mmSQ_TEX_CLK_CTRL_BASE_IDX 1
+#define mmSQ_LDS_CLK_CTRL 0x5090
+#define mmSQ_LDS_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL0 0x5094
+#define mmCGTT_SX_CLK_CTRL0_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL1 0x5095
+#define mmCGTT_SX_CLK_CTRL1_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL2 0x5096
+#define mmCGTT_SX_CLK_CTRL2_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL3 0x5097
+#define mmCGTT_SX_CLK_CTRL3_BASE_IDX 1
+#define mmCGTT_SX_CLK_CTRL4 0x5098
+#define mmCGTT_SX_CLK_CTRL4_BASE_IDX 1
+#define mmTD_CGTT_CTRL 0x509c
+#define mmTD_CGTT_CTRL_BASE_IDX 1
+#define mmTA_CGTT_CTRL 0x509d
+#define mmTA_CGTT_CTRL_BASE_IDX 1
+#define mmCGTT_TCPI_CLK_CTRL 0x509e
+#define mmCGTT_TCPI_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_TCI_CLK_CTRL 0x509f
+#define mmCGTT_TCI_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_GDS_CLK_CTRL 0x50a0
+#define mmCGTT_GDS_CLK_CTRL_BASE_IDX 1
+#define mmDB_CGTT_CLK_CTRL_0 0x50a4
+#define mmDB_CGTT_CLK_CTRL_0_BASE_IDX 1
+#define mmCB_CGTT_SCLK_CTRL 0x50a8
+#define mmCB_CGTT_SCLK_CTRL_BASE_IDX 1
+#define mmGL2C_CGTT_SCLK_CTRL 0x50ac
+#define mmGL2C_CGTT_SCLK_CTRL_BASE_IDX 1
+#define mmGL2A_CGTT_SCLK_CTRL 0x50ad
+#define mmGL2A_CGTT_SCLK_CTRL_BASE_IDX 1
+#define mmGL2A_CGTT_SCLK_CTRL_1 0x50ae
+#define mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX 1
+#define mmCGTT_CP_CLK_CTRL 0x50b0
+#define mmCGTT_CP_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_CPF_CLK_CTRL 0x50b1
+#define mmCGTT_CPF_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_CPC_CLK_CTRL 0x50b2
+#define mmCGTT_CPC_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_RLC_CLK_CTRL 0x50b5
+#define mmCGTT_RLC_CLK_CTRL_BASE_IDX 1
+#define mmRLC_GFX_RM_CNTL 0x50b6
+#define mmRLC_GFX_RM_CNTL_BASE_IDX 1
+#define mmRMI_CGTT_SCLK_CTRL 0x50c0
+#define mmRMI_CGTT_SCLK_CTRL_BASE_IDX 1
+#define mmCGTT_TCPF_CLK_CTRL 0x50c1
+#define mmCGTT_TCPF_CLK_CTRL_BASE_IDX 1
+#define mmGCR_CGTT_SCLK_CTRL 0x50c2
+#define mmGCR_CGTT_SCLK_CTRL_BASE_IDX 1
+#define mmUTCL1_CGTT_CLK_CTRL 0x50c3
+#define mmUTCL1_CGTT_CLK_CTRL_BASE_IDX 1
+#define mmGCEA_CGTT_CLK_CTRL 0x50c4
+#define mmGCEA_CGTT_CLK_CTRL_BASE_IDX 1
+#define mmSE_CAC_CGTT_CLK_CTRL 0x50d0
+#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 1
+#define mmGC_CAC_CGTT_CLK_CTRL 0x50d8
+#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 1
+#define mmGRBM_CGTT_CLK_CNTL 0x50e0
+#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 1
+#define mmCGTT_GL1C_CLK_CTRL 0x50ec
+#define mmCGTT_GL1C_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_CHC_CLK_CTRL 0x50ee
+#define mmCGTT_CHC_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_CHCG_CLK_CTRL 0x50ef
+#define mmCGTT_CHCG_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_GL1A_CLK_CTRL 0x50f0
+#define mmCGTT_GL1A_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_CHA_CLK_CTRL 0x50f1
+#define mmCGTT_CHA_CLK_CTRL_BASE_IDX 1
+#define mmGUS_CGTT_CLK_CTRL 0x50f4
+#define mmGUS_CGTT_CLK_CTRL_BASE_IDX 1
+#define mmCGTT_PH_CLK_CTRL0 0x50f8
+#define mmCGTT_PH_CLK_CTRL0_BASE_IDX 1
+#define mmCGTT_PH_CLK_CTRL1 0x50f9
+#define mmCGTT_PH_CLK_CTRL1_BASE_IDX 1
+#define mmCGTT_PH_CLK_CTRL2 0x50fa
+#define mmCGTT_PH_CLK_CTRL2_BASE_IDX 1
+#define mmCGTT_PH_CLK_CTRL3 0x50fb
+#define mmCGTT_PH_CLK_CTRL3_BASE_IDX 1
+
+
+// addressBlock: gc_hypdec
+// base address: 0x3e000
+#define mmCP_PFP_UCODE_ADDR 0x5814
+#define mmCP_PFP_UCODE_ADDR_BASE_IDX 1
+#define mmCP_PFP_UCODE_DATA 0x5815
+#define mmCP_PFP_UCODE_DATA_BASE_IDX 1
+#define mmCP_ME_RAM_RADDR 0x5816
+#define mmCP_ME_RAM_RADDR_BASE_IDX 1
+#define mmCP_ME_RAM_WADDR 0x5816
+#define mmCP_ME_RAM_WADDR_BASE_IDX 1
+#define mmCP_ME_RAM_DATA 0x5817
+#define mmCP_ME_RAM_DATA_BASE_IDX 1
+#define mmCP_CE_UCODE_ADDR 0x5818
+#define mmCP_CE_UCODE_ADDR_BASE_IDX 1
+#define mmCP_CE_UCODE_DATA 0x5819
+#define mmCP_CE_UCODE_DATA_BASE_IDX 1
+#define mmCP_MEC_ME1_UCODE_ADDR 0x581a
+#define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1
+#define mmCP_MEC_ME1_UCODE_DATA 0x581b
+#define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX 1
+#define mmCP_MEC_ME2_UCODE_ADDR 0x581c
+#define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1
+#define mmCP_MEC_ME2_UCODE_DATA 0x581d
+#define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX 1
+#define mmCP_PFP_IC_BASE_LO 0x5840
+#define mmCP_PFP_IC_BASE_LO_BASE_IDX 1
+#define mmCP_PFP_IC_BASE_HI 0x5841
+#define mmCP_PFP_IC_BASE_HI_BASE_IDX 1
+#define mmCP_PFP_IC_BASE_CNTL 0x5842
+#define mmCP_PFP_IC_BASE_CNTL_BASE_IDX 1
+#define mmCP_PFP_IC_OP_CNTL 0x5843
+#define mmCP_PFP_IC_OP_CNTL_BASE_IDX 1
+#define mmCP_ME_IC_BASE_LO 0x5844
+#define mmCP_ME_IC_BASE_LO_BASE_IDX 1
+#define mmCP_ME_IC_BASE_HI 0x5845
+#define mmCP_ME_IC_BASE_HI_BASE_IDX 1
+#define mmCP_ME_IC_BASE_CNTL 0x5846
+#define mmCP_ME_IC_BASE_CNTL_BASE_IDX 1
+#define mmCP_ME_IC_OP_CNTL 0x5847
+#define mmCP_ME_IC_OP_CNTL_BASE_IDX 1
+#define mmCP_CE_IC_BASE_LO 0x5848
+#define mmCP_CE_IC_BASE_LO_BASE_IDX 1
+#define mmCP_CE_IC_BASE_HI 0x5849
+#define mmCP_CE_IC_BASE_HI_BASE_IDX 1
+#define mmCP_CE_IC_BASE_CNTL 0x584a
+#define mmCP_CE_IC_BASE_CNTL_BASE_IDX 1
+#define mmCP_CE_IC_OP_CNTL 0x584b
+#define mmCP_CE_IC_OP_CNTL_BASE_IDX 1
+#define mmCP_CPC_IC_BASE_LO 0x584c
+#define mmCP_CPC_IC_BASE_LO_BASE_IDX 1
+#define mmCP_CPC_IC_BASE_HI 0x584d
+#define mmCP_CPC_IC_BASE_HI_BASE_IDX 1
+#define mmCP_CPC_IC_BASE_CNTL 0x584e
+#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 1
+#define mmCP_CPC_IC_OP_CNTL 0x584f
+#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 1
+#define mmCP_MES_IC_BASE_LO 0x5850
+#define mmCP_MES_IC_BASE_LO_BASE_IDX 1
+#define mmCP_MES_MIBASE_LO 0x5850
+#define mmCP_MES_MIBASE_LO_BASE_IDX 1
+#define mmCP_MES_IC_BASE_HI 0x5851
+#define mmCP_MES_IC_BASE_HI_BASE_IDX 1
+#define mmCP_MES_MIBASE_HI 0x5851
+#define mmCP_MES_MIBASE_HI_BASE_IDX 1
+#define mmCP_MES_IC_BASE_CNTL 0x5852
+#define mmCP_MES_IC_BASE_CNTL_BASE_IDX 1
+#define mmCP_MES_IC_OP_CNTL 0x5853
+#define mmCP_MES_IC_OP_CNTL_BASE_IDX 1
+#define mmCP_MES_DC_BASE_LO 0x5854
+#define mmCP_MES_DC_BASE_LO_BASE_IDX 1
+#define mmCP_MES_MDBASE_LO 0x5854
+#define mmCP_MES_MDBASE_LO_BASE_IDX 1
+#define mmCP_MES_DC_BASE_HI 0x5855
+#define mmCP_MES_DC_BASE_HI_BASE_IDX 1
+#define mmCP_MES_MDBASE_HI 0x5855
+#define mmCP_MES_MDBASE_HI_BASE_IDX 1
+#define mmCP_MES_LOCAL_BASE0_LO 0x5856
+#define mmCP_MES_LOCAL_BASE0_LO_BASE_IDX 1
+#define mmCP_MES_LOCAL_BASE0_HI 0x5857
+#define mmCP_MES_LOCAL_BASE0_HI_BASE_IDX 1
+#define mmCP_MES_LOCAL_MASK0_LO 0x5858
+#define mmCP_MES_LOCAL_MASK0_LO_BASE_IDX 1
+#define mmCP_MES_LOCAL_MASK0_HI 0x5859
+#define mmCP_MES_LOCAL_MASK0_HI_BASE_IDX 1
+#define mmCP_MES_LOCAL_APERTURE 0x585a
+#define mmCP_MES_LOCAL_APERTURE_BASE_IDX 1
+#define mmCP_MES_MIBOUND_LO 0x585b
+#define mmCP_MES_MIBOUND_LO_BASE_IDX 1
+#define mmCP_MES_MIBOUND_HI 0x585c
+#define mmCP_MES_MIBOUND_HI_BASE_IDX 1
+#define mmCP_MES_MDBOUND_LO 0x585d
+#define mmCP_MES_MDBOUND_LO_BASE_IDX 1
+#define mmCP_MES_MDBOUND_HI 0x585e
+#define mmCP_MES_MDBOUND_HI_BASE_IDX 1
+#define mmGFX_PIPE_PRIORITY 0x587f
+#define mmGFX_PIPE_PRIORITY_BASE_IDX 1
+#define mmGRBM_GFX_INDEX_SR_SELECT 0x5a00
+#define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1
+#define mmGRBM_GFX_INDEX_SR_DATA 0x5a01
+#define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1
+#define mmGRBM_GFX_CNTL_SR_SELECT 0x5a02
+#define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1
+#define mmGRBM_GFX_CNTL_SR_DATA 0x5a03
+#define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1
+#define mmGRBM_CAM_INDEX 0x5a04
+#define mmGRBM_CAM_INDEX_BASE_IDX 1
+#define mmGRBM_HYP_CAM_INDEX 0x5a04
+#define mmGRBM_HYP_CAM_INDEX_BASE_IDX 1
+#define mmGRBM_CAM_DATA 0x5a05
+#define mmGRBM_CAM_DATA_BASE_IDX 1
+#define mmGRBM_HYP_CAM_DATA 0x5a05
+#define mmGRBM_HYP_CAM_DATA_BASE_IDX 1
+#define mmGRBM_CAM_DATA_UPPER 0x5a06
+#define mmGRBM_CAM_DATA_UPPER_BASE_IDX 1
+#define mmGRBM_HYP_CAM_DATA_UPPER 0x5a06
+#define mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX 1
+#define mmGC_IH_COOKIE_0_PTR 0x5a07
+#define mmGC_IH_COOKIE_0_PTR_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_ENABLE 0x5b00
+#define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1
+#define mmRLC_GPU_IOV_CFG_REG6 0x5b06
+#define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX 1
+#define mmRLC_GPU_IOV_CFG_REG8 0x5b20
+#define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX 1
+#define mmRLC_RLCV_TIMER_INT_0 0x5b25
+#define mmRLC_RLCV_TIMER_INT_0_BASE_IDX 1
+#define mmRLC_RLCV_TIMER_CTRL 0x5b26
+#define mmRLC_RLCV_TIMER_CTRL_BASE_IDX 1
+#define mmRLC_RLCV_TIMER_STAT 0x5b27
+#define mmRLC_RLCV_TIMER_STAT_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c
+#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1
+#define mmRLC_GPU_IOV_VF_MASK 0x5b2d
+#define mmRLC_GPU_IOV_VF_MASK_BASE_IDX 1
+#define mmRLC_HYP_SEMAPHORE_0 0x5b2e
+#define mmRLC_HYP_SEMAPHORE_0_BASE_IDX 1
+#define mmRLC_HYP_SEMAPHORE_1 0x5b2f
+#define mmRLC_HYP_SEMAPHORE_1_BASE_IDX 1
+#define mmRLC_BUSY_CLK_CNTL 0x5b30
+#define mmRLC_BUSY_CLK_CNTL_BASE_IDX 1
+#define mmRLC_CLK_CNTL 0x5b31
+#define mmRLC_CLK_CNTL_BASE_IDX 1
+#define mmRLC_PACE_TIMER_STAT 0x5b33
+#define mmRLC_PACE_TIMER_STAT_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_BLOCK 0x5b34
+#define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1
+#define mmRLC_GPU_IOV_CFG_REG1 0x5b35
+#define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX 1
+#define mmRLC_GPU_IOV_CFG_REG2 0x5b36
+#define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX 1
+#define mmRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37
+#define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_0 0x5b38
+#define mmRLC_GPU_IOV_SCH_0_BASE_IDX 1
+#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39
+#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_3 0x5b3a
+#define mmRLC_GPU_IOV_SCH_3_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_1 0x5b3b
+#define mmRLC_GPU_IOV_SCH_1_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCH_2 0x5b3c
+#define mmRLC_GPU_IOV_SCH_2_BASE_IDX 1
+#define mmRLC_PACE_INT_FORCE 0x5b3d
+#define mmRLC_PACE_INT_FORCE_BASE_IDX 1
+#define mmRLC_GPU_IOV_INT_STAT 0x5b3f
+#define mmRLC_GPU_IOV_INT_STAT_BASE_IDX 1
+#define mmRLC_RLCV_TIMER_INT_1 0x5b40
+#define mmRLC_RLCV_TIMER_INT_1_BASE_IDX 1
+#define mmRLC_IH_COOKIE 0x5b41
+#define mmRLC_IH_COOKIE_BASE_IDX 1
+#define mmRLC_IH_COOKIE_CNTL 0x5b42
+#define mmRLC_IH_COOKIE_CNTL_BASE_IDX 1
+#define mmRLC_HYP_RLCG_UCODE_CHKSUM 0x5b43
+#define mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX 1
+#define mmRLC_HYP_RLCP_UCODE_CHKSUM 0x5b44
+#define mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX 1
+#define mmRLC_HYP_RLCV_UCODE_CHKSUM 0x5b45
+#define mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX 1
+#define mmRLC_GPU_IOV_F32_CNTL 0x5b46
+#define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX 1
+#define mmRLC_GPU_IOV_F32_RESET 0x5b47
+#define mmRLC_GPU_IOV_F32_RESET_BASE_IDX 1
+#define mmRLC_GPU_IOV_SDMA0_STATUS 0x5b48
+#define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_SDMA1_STATUS 0x5b49
+#define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_SMU_RESPONSE 0x5b4a
+#define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1
+#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c
+#define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1
+#define mmRLC_GPU_IOV_RLC_RESPONSE 0x5b4d
+#define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1
+#define mmRLC_GPU_IOV_INT_DISABLE 0x5b4e
+#define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1
+#define mmRLC_GPU_IOV_INT_FORCE 0x5b4f
+#define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX 1
+#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50
+#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1
+#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51
+#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1
+#define mmRLC_HYP_SEMAPHORE_2 0x5b52
+#define mmRLC_HYP_SEMAPHORE_2_BASE_IDX 1
+#define mmRLC_HYP_SEMAPHORE_3 0x5b53
+#define mmRLC_HYP_SEMAPHORE_3_BASE_IDX 1
+#define mmRLC_HYP_RESET_VECTOR 0x5b54
+#define mmRLC_HYP_RESET_VECTOR_BASE_IDX 1
+#define mmRLC_HYP_BOOTLOAD_SIZE 0x5b5c
+#define mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX 1
+#define mmRLC_HYP_BOOTLOAD_ADDR_LO 0x5b5d
+#define mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX 1
+#define mmRLC_HYP_BOOTLOAD_ADDR_HI 0x5b5e
+#define mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX 1
+#define mmRLC_GPM_IRAM_ADDR 0x5b5f
+#define mmRLC_GPM_IRAM_ADDR_BASE_IDX 1
+#define mmRLC_GPM_IRAM_DATA 0x5b60
+#define mmRLC_GPM_IRAM_DATA_BASE_IDX 1
+#define mmRLC_GPM_UCODE_ADDR 0x5b61
+#define mmRLC_GPM_UCODE_ADDR_BASE_IDX 1
+#define mmRLC_GPM_UCODE_DATA 0x5b62
+#define mmRLC_GPM_UCODE_DATA_BASE_IDX 1
+#define mmRLC_PACE_UCODE_ADDR 0x5b63
+#define mmRLC_PACE_UCODE_ADDR_BASE_IDX 1
+#define mmRLC_PACE_UCODE_DATA 0x5b64
+#define mmRLC_PACE_UCODE_DATA_BASE_IDX 1
+#define mmRLC_GPU_IOV_UCODE_ADDR 0x5b65
+#define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1
+#define mmRLC_GPU_IOV_UCODE_DATA 0x5b66
+#define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCRATCH_ADDR 0x5b67
+#define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1
+#define mmRLC_GPU_IOV_SCRATCH_DATA 0x5b68
+#define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1
+#define mmRLC_RLCV_IRAM_ADDR 0x5b69
+#define mmRLC_RLCV_IRAM_ADDR_BASE_IDX 1
+#define mmRLC_RLCV_IRAM_DATA 0x5b6a
+#define mmRLC_RLCV_IRAM_DATA_BASE_IDX 1
+#define mmRLC_RLCP_IRAM_ADDR 0x5b6b
+#define mmRLC_RLCP_IRAM_ADDR_BASE_IDX 1
+#define mmRLC_RLCP_IRAM_DATA 0x5b6c
+#define mmRLC_RLCP_IRAM_DATA_BASE_IDX 1
+#define mmRLC_SRM_DRAM_ADDR 0x5b71
+#define mmRLC_SRM_DRAM_ADDR_BASE_IDX 1
+#define mmRLC_SRM_DRAM_DATA 0x5b72
+#define mmRLC_SRM_DRAM_DATA_BASE_IDX 1
+#define mmRLC_SRM_ARAM_ADDR 0x5b73
+#define mmRLC_SRM_ARAM_ADDR_BASE_IDX 1
+#define mmRLC_SRM_ARAM_DATA 0x5b74
+#define mmRLC_SRM_ARAM_DATA_BASE_IDX 1
+#define mmRLC_GPM_SCRATCH_ADDR 0x5b75
+#define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX 1
+#define mmRLC_GPM_SCRATCH_DATA 0x5b76
+#define mmRLC_GPM_SCRATCH_DATA_BASE_IDX 1
+#define mmRLC_GTS_OFFSET_LSB 0x5b79
+#define mmRLC_GTS_OFFSET_LSB_BASE_IDX 1
+#define mmRLC_GTS_OFFSET_MSB 0x5b7a
+#define mmRLC_GTS_OFFSET_MSB_BASE_IDX 1
+
+
+// addressBlock: gc_sdma0_sdma0hypdec
+// base address: 0x3e200
+#define mmSDMA0_UCODE_ADDR 0x5880
+#define mmSDMA0_UCODE_ADDR_BASE_IDX 1
+#define mmSDMA0_UCODE_DATA 0x5881
+#define mmSDMA0_UCODE_DATA_BASE_IDX 1
+#define mmSDMA0_VM_CTX_LO 0x5882
+#define mmSDMA0_VM_CTX_LO_BASE_IDX 1
+#define mmSDMA0_VM_CTX_HI 0x5883
+#define mmSDMA0_VM_CTX_HI_BASE_IDX 1
+#define mmSDMA0_ACTIVE_FCN_ID 0x5884
+#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 1
+#define mmSDMA0_VM_CTX_CNTL 0x5885
+#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 1
+#define mmSDMA0_VIRT_RESET_REQ 0x5886
+#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 1
+#define mmSDMA0_VF_ENABLE 0x5887
+#define mmSDMA0_VF_ENABLE_BASE_IDX 1
+#define mmSDMA0_CONTEXT_REG_TYPE0 0x5888
+#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 1
+#define mmSDMA0_CONTEXT_REG_TYPE1 0x5889
+#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 1
+#define mmSDMA0_CONTEXT_REG_TYPE2 0x588a
+#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 1
+#define mmSDMA0_CONTEXT_REG_TYPE3 0x588b
+#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 1
+#define mmSDMA0_VM_CNTL 0x5893
+#define mmSDMA0_VM_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_sdma1_sdma1hypdec
+// base address: 0x3e280
+#define mmSDMA1_UCODE_ADDR 0x58a0
+#define mmSDMA1_UCODE_ADDR_BASE_IDX 1
+#define mmSDMA1_UCODE_DATA 0x58a1
+#define mmSDMA1_UCODE_DATA_BASE_IDX 1
+#define mmSDMA1_VM_CTX_LO 0x58a2
+#define mmSDMA1_VM_CTX_LO_BASE_IDX 1
+#define mmSDMA1_VM_CTX_HI 0x58a3
+#define mmSDMA1_VM_CTX_HI_BASE_IDX 1
+#define mmSDMA1_ACTIVE_FCN_ID 0x58a4
+#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 1
+#define mmSDMA1_VM_CTX_CNTL 0x58a5
+#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 1
+#define mmSDMA1_VIRT_RESET_REQ 0x58a6
+#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 1
+#define mmSDMA1_VF_ENABLE 0x58a7
+#define mmSDMA1_VF_ENABLE_BASE_IDX 1
+#define mmSDMA1_CONTEXT_REG_TYPE0 0x58a8
+#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 1
+#define mmSDMA1_CONTEXT_REG_TYPE1 0x58a9
+#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 1
+#define mmSDMA1_CONTEXT_REG_TYPE2 0x58aa
+#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 1
+#define mmSDMA1_CONTEXT_REG_TYPE3 0x58ab
+#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 1
+#define mmSDMA1_VM_CNTL 0x58b3
+#define mmSDMA1_VM_CNTL_BASE_IDX 1
+
+
+// addressBlock: gc_gcvmsharedhvdec
+// base address: 0x3ea00
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF0 0x5a80
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF1 0x5a81
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF2 0x5a82
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF3 0x5a83
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF4 0x5a84
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF5 0x5a85
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF6 0x5a86
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF7 0x5a87
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF8 0x5a88
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF9 0x5a89
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF16 0x5a90
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF17 0x5a91
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF18 0x5a92
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF19 0x5a93
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF20 0x5a94
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF21 0x5a95
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF22 0x5a96
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF23 0x5a97
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF24 0x5a98
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF25 0x5a99
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF26 0x5a9a
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF27 0x5a9b
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF28 0x5a9c
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF29 0x5a9d
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF30 0x5a9e
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX 1
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF31 0x5a9f
+#define mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX 1
+#define mmGCVM_IOMMU_MMIO_CNTRL_1 0x5aa0
+#define mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1
+#define mmGCMC_VM_MARC_BASE_LO_0 0x5aa1
+#define mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX 1
+#define mmGCMC_VM_MARC_BASE_LO_1 0x5aa2
+#define mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX 1
+#define mmGCMC_VM_MARC_BASE_LO_2 0x5aa3
+#define mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX 1
+#define mmGCMC_VM_MARC_BASE_LO_3 0x5aa4
+#define mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX 1
+#define mmGCMC_VM_MARC_BASE_HI_0 0x5aa5
+#define mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX 1
+#define mmGCMC_VM_MARC_BASE_HI_1 0x5aa6
+#define mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX 1
+#define mmGCMC_VM_MARC_BASE_HI_2 0x5aa7
+#define mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX 1
+#define mmGCMC_VM_MARC_BASE_HI_3 0x5aa8
+#define mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX 1
+#define mmGCMC_VM_MARC_RELOC_LO_0 0x5aa9
+#define mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX 1
+#define mmGCMC_VM_MARC_RELOC_LO_1 0x5aaa
+#define mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX 1
+#define mmGCMC_VM_MARC_RELOC_LO_2 0x5aab
+#define mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX 1
+#define mmGCMC_VM_MARC_RELOC_LO_3 0x5aac
+#define mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX 1
+#define mmGCMC_VM_MARC_RELOC_HI_0 0x5aad
+#define mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX 1
+#define mmGCMC_VM_MARC_RELOC_HI_1 0x5aae
+#define mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX 1
+#define mmGCMC_VM_MARC_RELOC_HI_2 0x5aaf
+#define mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX 1
+#define mmGCMC_VM_MARC_RELOC_HI_3 0x5ab0
+#define mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX 1
+#define mmGCMC_VM_MARC_LEN_LO_0 0x5ab1
+#define mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX 1
+#define mmGCMC_VM_MARC_LEN_LO_1 0x5ab2
+#define mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX 1
+#define mmGCMC_VM_MARC_LEN_LO_2 0x5ab3
+#define mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX 1
+#define mmGCMC_VM_MARC_LEN_LO_3 0x5ab4
+#define mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX 1
+#define mmGCMC_VM_MARC_LEN_HI_0 0x5ab5
+#define mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX 1
+#define mmGCMC_VM_MARC_LEN_HI_1 0x5ab6
+#define mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX 1
+#define mmGCMC_VM_MARC_LEN_HI_2 0x5ab7
+#define mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX 1
+#define mmGCMC_VM_MARC_LEN_HI_3 0x5ab8
+#define mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX 1
+#define mmGCVM_IOMMU_CONTROL_REGISTER 0x5ab9
+#define mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1
+#define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aba
+#define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL 0x5abb
+#define mmGCVM_PCIE_ATS_CNTL_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_0 0x5abc
+#define mmGCVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_1 0x5abd
+#define mmGCVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_2 0x5abe
+#define mmGCVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_3 0x5abf
+#define mmGCVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_4 0x5ac0
+#define mmGCVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_5 0x5ac1
+#define mmGCVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_6 0x5ac2
+#define mmGCVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_7 0x5ac3
+#define mmGCVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_8 0x5ac4
+#define mmGCVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_9 0x5ac5
+#define mmGCVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_10 0x5ac6
+#define mmGCVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_11 0x5ac7
+#define mmGCVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_12 0x5ac8
+#define mmGCVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_13 0x5ac9
+#define mmGCVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_14 0x5aca
+#define mmGCVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_15 0x5acb
+#define mmGCVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_16 0x5acc
+#define mmGCVM_PCIE_ATS_CNTL_VF_16_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_17 0x5acd
+#define mmGCVM_PCIE_ATS_CNTL_VF_17_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_18 0x5ace
+#define mmGCVM_PCIE_ATS_CNTL_VF_18_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_19 0x5acf
+#define mmGCVM_PCIE_ATS_CNTL_VF_19_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_20 0x5ad0
+#define mmGCVM_PCIE_ATS_CNTL_VF_20_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_21 0x5ad1
+#define mmGCVM_PCIE_ATS_CNTL_VF_21_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_22 0x5ad2
+#define mmGCVM_PCIE_ATS_CNTL_VF_22_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_23 0x5ad3
+#define mmGCVM_PCIE_ATS_CNTL_VF_23_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_24 0x5ad4
+#define mmGCVM_PCIE_ATS_CNTL_VF_24_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_25 0x5ad5
+#define mmGCVM_PCIE_ATS_CNTL_VF_25_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_26 0x5ad6
+#define mmGCVM_PCIE_ATS_CNTL_VF_26_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_27 0x5ad7
+#define mmGCVM_PCIE_ATS_CNTL_VF_27_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_28 0x5ad8
+#define mmGCVM_PCIE_ATS_CNTL_VF_28_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_29 0x5ad9
+#define mmGCVM_PCIE_ATS_CNTL_VF_29_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_30 0x5ada
+#define mmGCVM_PCIE_ATS_CNTL_VF_30_BASE_IDX 1
+#define mmGCVM_PCIE_ATS_CNTL_VF_31 0x5adb
+#define mmGCVM_PCIE_ATS_CNTL_VF_31_BASE_IDX 1
+#define mmGCUTCL2_CGTT_CLK_CTRL 0x5adc
+#define mmGCUTCL2_CGTT_CLK_CTRL_BASE_IDX 1
+#define mmGCMC_SHARED_ACTIVE_FCN_ID 0x5add
+#define mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1
+
+
+// addressBlock: gccacind
+// base address: 0x0
+#define ixPCC_STALL_PATTERN_CTRL 0x0000
+#define ixPWRBRK_STALL_PATTERN_CTRL 0x0001
+#define ixPCC_STALL_PATTERN_1_2 0x0006
+#define ixPCC_STALL_PATTERN_3_4 0x0007
+#define ixPCC_STALL_PATTERN_5_6 0x0008
+#define ixPCC_STALL_PATTERN_7 0x0009
+#define ixPWRBRK_STALL_PATTERN_1_2 0x000a
+#define ixPWRBRK_STALL_PATTERN_3_4 0x000b
+#define ixPWRBRK_STALL_PATTERN_5_6 0x000c
+#define ixPWRBRK_STALL_PATTERN_7 0x000d
+#define ixGC_CAC_ID 0x0010
+#define ixGC_CAC_CNTL 0x0011
+#define ixGC_CAC_OVR_SEL 0x0012
+#define ixGC_CAC_OVR_VAL 0x0013
+#define ixGC_CAC_WEIGHT_BCI_0 0x0014
+#define ixGC_CAC_WEIGHT_CB_0 0x0015
+#define ixGC_CAC_WEIGHT_CB_1 0x0016
+#define ixGC_CAC_WEIGHT_CBR_0 0x0017
+#define ixGC_CAC_WEIGHT_CBR_1 0x0018
+#define ixGC_CAC_WEIGHT_CP_0 0x0019
+#define ixGC_CAC_WEIGHT_CP_1 0x001a
+#define ixGC_CAC_WEIGHT_DB_0 0x001b
+#define ixGC_CAC_WEIGHT_DB_1 0x001c
+#define ixGC_CAC_WEIGHT_DBR_0 0x001d
+#define ixGC_CAC_WEIGHT_DBR_1 0x001e
+#define ixGC_CAC_WEIGHT_GDS_0 0x001f
+#define ixGC_CAC_WEIGHT_GDS_1 0x0020
+#define ixGC_CAC_WEIGHT_LDS_0 0x0021
+#define ixGC_CAC_WEIGHT_LDS_1 0x0022
+#define ixGC_CAC_WEIGHT_PA_0 0x0023
+#define ixGC_CAC_WEIGHT_PC_0 0x0024
+#define ixGC_CAC_WEIGHT_SC_0 0x0025
+#define ixGC_CAC_WEIGHT_SPI_0 0x0026
+#define ixGC_CAC_WEIGHT_SPI_1 0x0027
+#define ixGC_CAC_WEIGHT_SPI_2 0x0028
+#define ixGC_CAC_WEIGHT_SQ_0 0x0029
+#define ixGC_CAC_WEIGHT_SQ_1 0x002a
+#define ixGC_CAC_WEIGHT_SQ_2 0x002b
+#define ixGC_CAC_WEIGHT_SX_0 0x002e
+#define ixGC_CAC_WEIGHT_SXRB_0 0x002f
+#define ixGC_CAC_WEIGHT_TA_0 0x0030
+#define ixGC_CAC_WEIGHT_TCP_0 0x0031
+#define ixGC_CAC_WEIGHT_TCP_1 0x0032
+#define ixGC_CAC_WEIGHT_TCP_2 0x0033
+#define ixGC_CAC_WEIGHT_TD_0 0x0034
+#define ixGC_CAC_WEIGHT_TD_1 0x0035
+#define ixGC_CAC_WEIGHT_TD_2 0x0036
+#define ixGC_CAC_WEIGHT_TD_3 0x0037
+#define ixGC_CAC_WEIGHT_TD_4 0x0038
+#define ixGC_CAC_WEIGHT_RMI_0 0x0039
+#define ixGC_CAC_WEIGHT_EA_0 0x003a
+#define ixGC_CAC_WEIGHT_EA_1 0x003b
+#define ixGC_CAC_WEIGHT_EA_2 0x003c
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x003d
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x003e
+#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x003f
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0040
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0041
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0042
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0043
+#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0044
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0045
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0046
+#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0047
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x0048
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x0049
+#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x004a
+#define ixGC_CAC_WEIGHT_CU_0 0x004b
+#define ixGC_CAC_WEIGHT_UTCL1_0 0x004d
+#define ixGC_CAC_WEIGHT_GE_0 0x004f
+#define ixGC_CAC_WEIGHT_PMM_0 0x0050
+#define ixGC_CAC_WEIGHT_GL2C_0 0x0051
+#define ixGC_CAC_WEIGHT_GL2C_1 0x0052
+#define ixGC_CAC_WEIGHT_GL2C_2 0x0053
+#define ixGC_CAC_WEIGHT_GUS_0 0x0054
+#define ixGC_CAC_WEIGHT_GUS_1 0x0055
+#define ixGC_CAC_WEIGHT_PH_0 0x0056
+#define ixGC_CAC_ACC_BCI0 0x0070
+#define ixGC_CAC_ACC_BCI1 0x0071
+#define ixGC_CAC_ACC_CB0 0x0072
+#define ixGC_CAC_ACC_CB1 0x0073
+#define ixGC_CAC_ACC_CB2 0x0074
+#define ixGC_CAC_ACC_CB3 0x0075
+#define ixGC_CAC_ACC_CBR0 0x0076
+#define ixGC_CAC_ACC_CBR1 0x0077
+#define ixGC_CAC_ACC_CBR2 0x0078
+#define ixGC_CAC_ACC_CBR3 0x0079
+#define ixGC_CAC_ACC_CP0 0x007a
+#define ixGC_CAC_ACC_CP1 0x007b
+#define ixGC_CAC_ACC_CP2 0x007c
+#define ixGC_CAC_ACC_DB0 0x007d
+#define ixGC_CAC_ACC_DB1 0x007e
+#define ixGC_CAC_ACC_DB2 0x007f
+#define ixGC_CAC_ACC_DB3 0x0080
+#define ixGC_CAC_ACC_DBR0 0x0081
+#define ixGC_CAC_ACC_DBR1 0x0082
+#define ixGC_CAC_ACC_DBR2 0x0083
+#define ixGC_CAC_ACC_DBR3 0x0084
+#define ixGC_CAC_ACC_GDS0 0x0085
+#define ixGC_CAC_ACC_GDS1 0x0086
+#define ixGC_CAC_ACC_GDS2 0x0087
+#define ixGC_CAC_ACC_GDS3 0x0088
+#define ixGC_CAC_ACC_LDS0 0x0089
+#define ixGC_CAC_ACC_LDS1 0x008a
+#define ixGC_CAC_ACC_LDS2 0x008b
+#define ixGC_CAC_ACC_LDS3 0x008c
+#define ixGC_CAC_ACC_PA0 0x008d
+#define ixGC_CAC_ACC_PA1 0x008e
+#define ixGC_CAC_ACC_PC0 0x008f
+#define ixGC_CAC_ACC_SC0 0x0090
+#define ixGC_CAC_ACC_SPI0 0x0091
+#define ixGC_CAC_ACC_SPI1 0x0092
+#define ixGC_CAC_ACC_SPI2 0x0093
+#define ixGC_CAC_ACC_SPI3 0x0094
+#define ixGC_CAC_ACC_SPI4 0x0095
+#define ixGC_CAC_ACC_SPI5 0x0096
+#define ixGC_CAC_ACC_SQ0_LOWER 0x0097
+#define ixGC_CAC_ACC_SQ0_UPPER 0x0098
+#define ixGC_CAC_ACC_SQ1_LOWER 0x0099
+#define ixGC_CAC_ACC_SQ1_UPPER 0x009a
+#define ixGC_CAC_ACC_SQ2_LOWER 0x009b
+#define ixGC_CAC_ACC_SQ2_UPPER 0x009c
+#define ixGC_CAC_ACC_SQ3_LOWER 0x009d
+#define ixGC_CAC_ACC_SQ3_UPPER 0x009e
+#define ixGC_CAC_ACC_SQ4_LOWER 0x009f
+#define ixGC_CAC_ACC_SQ4_UPPER 0x00a0
+#define ixGC_CAC_ACC_SQ5_LOWER 0x00a1
+#define ixGC_CAC_ACC_SQ5_UPPER 0x00a2
+#define ixGC_CAC_ACC_SQ6_LOWER 0x00a3
+#define ixGC_CAC_ACC_SQ6_UPPER 0x00a4
+#define ixGC_CAC_ACC_SQ7_LOWER 0x00a5
+#define ixGC_CAC_ACC_SQ7_UPPER 0x00a6
+#define ixGC_CAC_ACC_SQ8_LOWER 0x00a7
+#define ixGC_CAC_ACC_SQ8_UPPER 0x00a8
+#define ixGC_CAC_ACC_SX0 0x00a9
+#define ixGC_CAC_ACC_SXRB0 0x00aa
+#define ixGC_CAC_ACC_TA0 0x00ab
+#define ixGC_CAC_ACC_TCP0 0x00ac
+#define ixGC_CAC_ACC_TCP1 0x00ad
+#define ixGC_CAC_ACC_TCP2 0x00ae
+#define ixGC_CAC_ACC_TCP3 0x00af
+#define ixGC_CAC_ACC_TCP4 0x00b0
+#define ixGC_CAC_ACC_TD0 0x00b1
+#define ixGC_CAC_ACC_TD1 0x00b2
+#define ixGC_CAC_ACC_TD2 0x00b3
+#define ixGC_CAC_ACC_TD3 0x00b4
+#define ixGC_CAC_ACC_TD4 0x00b5
+#define ixGC_CAC_ACC_TD5 0x00b6
+#define ixGC_CAC_ACC_TD6 0x00b7
+#define ixGC_CAC_ACC_TD7 0x00b8
+#define ixGC_CAC_ACC_TD8 0x00b9
+#define ixGC_CAC_ACC_TD9 0x00ba
+#define ixGC_CAC_ACC_RMI0 0x00bb
+#define ixGC_CAC_ACC_EA0 0x00bc
+#define ixGC_CAC_ACC_EA1 0x00bd
+#define ixGC_CAC_ACC_EA2 0x00be
+#define ixGC_CAC_ACC_EA3 0x00bf
+#define ixGC_CAC_ACC_EA4 0x00c0
+#define ixGC_CAC_ACC_EA5 0x00c1
+#define ixGC_CAC_ACC_UTCL2_ATCL20 0x00c2
+#define ixGC_CAC_ACC_UTCL2_ATCL21 0x00c3
+#define ixGC_CAC_ACC_UTCL2_ATCL22 0x00c4
+#define ixGC_CAC_ACC_UTCL2_ATCL23 0x00c5
+#define ixGC_CAC_ACC_UTCL2_ATCL24 0x00c6
+#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x00c7
+#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x00c8
+#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x00c9
+#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x00ca
+#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x00cb
+#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x00cc
+#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x00cd
+#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x00ce
+#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x00cf
+#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x00d0
+#define ixGC_CAC_ACC_UTCL2_VML20 0x00d1
+#define ixGC_CAC_ACC_UTCL2_VML21 0x00d2
+#define ixGC_CAC_ACC_UTCL2_VML22 0x00d3
+#define ixGC_CAC_ACC_UTCL2_VML23 0x00d4
+#define ixGC_CAC_ACC_UTCL2_VML24 0x00d5
+#define ixGC_CAC_ACC_UTCL2_WALKER0 0x00d6
+#define ixGC_CAC_ACC_UTCL2_WALKER1 0x00d7
+#define ixGC_CAC_ACC_UTCL2_WALKER2 0x00d8
+#define ixGC_CAC_ACC_UTCL2_WALKER3 0x00d9
+#define ixGC_CAC_ACC_UTCL2_WALKER4 0x00da
+#define ixGC_CAC_ACC_CU0 0x00db
+#define ixGC_CAC_ACC_UTCL10 0x00dd
+#define ixGC_CAC_ACC_CH0 0x00de
+#define ixGC_CAC_ACC_GE0 0x00df
+#define ixGC_CAC_ACC_PMM0 0x00e0
+#define ixGC_CAC_ACC_GL2C0 0x00e1
+#define ixGC_CAC_ACC_GL2C1 0x00e2
+#define ixGC_CAC_ACC_GL2C2 0x00e3
+#define ixGC_CAC_ACC_GL2C3 0x00e4
+#define ixGC_CAC_ACC_GL2C4 0x00e5
+#define ixGC_CAC_ACC_GUS0 0x00e6
+#define ixGC_CAC_ACC_GUS1 0x00e7
+#define ixGC_CAC_ACC_GUS2 0x00e8
+#define ixGC_CAC_ACC_PH0 0x00e9
+#define ixGC_CAC_OVRD_BCI 0x0130
+#define ixGC_CAC_OVRD_CB 0x0131
+#define ixGC_CAC_OVRD_CBR 0x0132
+#define ixGC_CAC_OVRD_CP 0x0133
+#define ixGC_CAC_OVRD_DB 0x0134
+#define ixGC_CAC_OVRD_DBR 0x0135
+#define ixGC_CAC_OVRD_GDS 0x0136
+#define ixGC_CAC_OVRD_LDS 0x0137
+#define ixGC_CAC_OVRD_PA 0x0138
+#define ixGC_CAC_OVRD_PC 0x0139
+#define ixGC_CAC_OVRD_SC 0x013a
+#define ixGC_CAC_OVRD_SPI 0x013b
+#define ixGC_CAC_OVRD_CU 0x013c
+#define ixGC_CAC_OVRD_SQ 0x013d
+#define ixGC_CAC_OVRD_SX 0x013e
+#define ixGC_CAC_OVRD_SXRB 0x013f
+#define ixGC_CAC_OVRD_TA 0x0140
+#define ixGC_CAC_OVRD_TCP 0x0141
+#define ixGC_CAC_OVRD_TD 0x0142
+#define ixGC_CAC_OVRD_RMI 0x0143
+#define ixGC_CAC_OVRD_EA 0x0144
+#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0145
+#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0146
+#define ixGC_CAC_OVRD_UTCL2_VML2 0x0147
+#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0148
+#define ixGC_CAC_OVRD_UTCL1 0x014a
+#define ixGC_CAC_OVRD_GE 0x014c
+#define ixGC_CAC_OVRD_PMM 0x014d
+#define ixGC_CAC_OVRD_GL2C 0x014e
+#define ixGC_CAC_OVRD_GUS 0x014f
+#define ixGC_CAC_OVRD_PH 0x0153
+#define ixRELEASE_TO_STALL_LUT_1_8 0x0154
+#define ixRELEASE_TO_STALL_LUT_9_16 0x0155
+#define ixRELEASE_TO_STALL_LUT_17_20 0x0156
+#define ixSTALL_TO_RELEASE_LUT_1_4 0x0157
+#define ixSTALL_TO_RELEASE_LUT_5_7 0x0158
+#define ixSTALL_TO_PWRBRK_LUT_1_4 0x0159
+#define ixSTALL_TO_PWRBRK_LUT_5_7 0x015a
+#define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 0x015b
+#define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 0x015c
+#define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 0x015d
+#define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 0x015e
+#define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 0x015f
+#define ixFIXED_PATTERN_PERF_COUNTER_1 0x0160
+#define ixFIXED_PATTERN_PERF_COUNTER_2 0x0161
+#define ixFIXED_PATTERN_PERF_COUNTER_3 0x0162
+#define ixFIXED_PATTERN_PERF_COUNTER_4 0x0163
+#define ixFIXED_PATTERN_PERF_COUNTER_5 0x0164
+#define ixFIXED_PATTERN_PERF_COUNTER_6 0x0165
+#define ixFIXED_PATTERN_PERF_COUNTER_7 0x0166
+#define ixFIXED_PATTERN_PERF_COUNTER_8 0x0167
+#define ixFIXED_PATTERN_PERF_COUNTER_9 0x0168
+#define ixFIXED_PATTERN_PERF_COUNTER_10 0x0169
+#define ixHW_LUT_UPDATE_STATUS 0x016a
+
+
+// addressBlock: secacind
+// base address: 0x0
+#define ixSE_CAC_ID 0x0000
+#define ixSE_CAC_CNTL 0x0001
+#define ixSE_CAC_OVR_SEL 0x0002
+#define ixSE_CAC_OVR_VAL 0x0003
+
+
+// addressBlock: spmglbind
+// base address: 0x0
+#define ixGLB_CPG_SAMPLEDELAY 0x0000
+#define ixGLB_CPC_SAMPLEDELAY 0x0001
+#define ixGLB_CPF_SAMPLEDELAY 0x0002
+#define ixGLB_GDS_SAMPLEDELAY 0x0003
+#define ixGLB_GCR_SAMPLEDELAY 0x0004
+#define ixGLB_PH_SAMPLEDELAY 0x0005
+#define ixGLB_GE_SAMPLEDELAY 0x0006
+#define ixGLB_GUS_SAMPLEDELAY 0x0007
+#define ixGLB_CHA_SAMPLEDELAY 0x0008
+#define ixGLB_CHCG_SAMPLEDELAY 0x0009
+#define ixGLB_ATCL2_SAMPLEDELAY 0x000a
+#define ixGLB_VML2_SAMPLEDELAY 0x000b
+#define ixGLB_SDMA0_SAMPLEDELAY 0x000c
+#define ixGLB_SDMA1_SAMPLEDELAY 0x000d
+#define ixGLB_GL2A0_SAMPLEDELAY 0x000e
+#define ixGLB_GL2A1_SAMPLEDELAY 0x000f
+#define ixGLB_GL2A2_SAMPLEDELAY 0x0010
+#define ixGLB_GL2A3_SAMPLEDELAY 0x0011
+#define ixGLB_GL2C0_SAMPLEDELAY 0x0012
+#define ixGLB_GL2C1_SAMPLEDELAY 0x0013
+#define ixGLB_GL2C2_SAMPLEDELAY 0x0014
+#define ixGLB_GL2C3_SAMPLEDELAY 0x0015
+#define ixGLB_GL2C4_SAMPLEDELAY 0x0016
+#define ixGLB_GL2C5_SAMPLEDELAY 0x0017
+#define ixGLB_GL2C6_SAMPLEDELAY 0x0018
+#define ixGLB_GL2C7_SAMPLEDELAY 0x0019
+#define ixGLB_GL2C8_SAMPLEDELAY 0x001a
+#define ixGLB_GL2C9_SAMPLEDELAY 0x001b
+#define ixGLB_GL2C10_SAMPLEDELAY 0x001c
+#define ixGLB_GL2C11_SAMPLEDELAY 0x001d
+#define ixGLB_GL2C12_SAMPLEDELAY 0x001e
+#define ixGLB_GL2C13_SAMPLEDELAY 0x001f
+#define ixGLB_GL2C14_SAMPLEDELAY 0x0020
+#define ixGLB_GL2C15_SAMPLEDELAY 0x0021
+#define ixGLB_EA0_SAMPLEDELAY 0x0022
+#define ixGLB_EA1_SAMPLEDELAY 0x0023
+#define ixGLB_EA2_SAMPLEDELAY 0x0024
+#define ixGLB_EA3_SAMPLEDELAY 0x0025
+#define ixGLB_EA4_SAMPLEDELAY 0x0026
+#define ixGLB_EA5_SAMPLEDELAY 0x0027
+#define ixGLB_EA6_SAMPLEDELAY 0x0028
+#define ixGLB_EA7_SAMPLEDELAY 0x0029
+#define ixGLB_EA8_SAMPLEDELAY 0x002a
+#define ixGLB_EA9_SAMPLEDELAY 0x002b
+#define ixGLB_EA10_SAMPLEDELAY 0x002c
+#define ixGLB_EA11_SAMPLEDELAY 0x002d
+#define ixGLB_EA12_SAMPLEDELAY 0x002e
+#define ixGLB_EA13_SAMPLEDELAY 0x002f
+#define ixGLB_EA14_SAMPLEDELAY 0x0030
+#define ixGLB_EA15_SAMPLEDELAY 0x0031
+#define ixGLB_CHC0_SAMPLEDELAY 0x0032
+#define ixGLB_CHC1_SAMPLEDELAY 0x0033
+#define ixGLB_CHC2_SAMPLEDELAY 0x0034
+#define ixGLB_CHC3_SAMPLEDELAY 0x0035
+
+
+// addressBlock: spmind
+// base address: 0x0
+#define ixSE_SPI_SAMPLEDELAY 0x0000
+#define ixSE_SQG_SAMPLEDELAY 0x0001
+#define ixSE_CBR_SAMPLEDELAY 0x0002
+#define ixSE_DBR_SAMPLEDELAY 0x0003
+#define ixSE_SA0SX_SAMPLEDELAY 0x0004
+#define ixSE_SA0PA_SAMPLEDELAY 0x0005
+#define ixSE_SA0GL1A_SAMPLEDELAY 0x0006
+#define ixSE_SA0GL1CG_SAMPLEDELAY 0x0007
+#define ixSE_SA0CB0_SAMPLEDELAY 0x0008
+#define ixSE_SA0CB1_SAMPLEDELAY 0x0009
+#define ixSE_SA0CB2_SAMPLEDELAY 0x000a
+#define ixSE_SA0CB3_SAMPLEDELAY 0x000b
+#define ixSE_SA0DB0_SAMPLEDELAY 0x000c
+#define ixSE_SA0DB1_SAMPLEDELAY 0x000d
+#define ixSE_SA0DB2_SAMPLEDELAY 0x000e
+#define ixSE_SA0DB3_SAMPLEDELAY 0x000f
+#define ixSE_SA0SC0_SAMPLEDELAY 0x0010
+#define ixSE_SA0SC1_SAMPLEDELAY 0x0011
+#define ixSE_SA0RMI0_SAMPLEDELAY 0x0012
+#define ixSE_SA0RMI1_SAMPLEDELAY 0x0013
+#define ixSE_SA0GL1C0_SAMPLEDELAY 0x0014
+#define ixSE_SA0GL1C1_SAMPLEDELAY 0x0015
+#define ixSE_SA0GL1C2_SAMPLEDELAY 0x0016
+#define ixSE_SA0GL1C3_SAMPLEDELAY 0x0017
+#define ixSE_SA0WGP00TA0_SAMPLEDELAY 0x0018
+#define ixSE_SA0WGP00TA1_SAMPLEDELAY 0x0019
+#define ixSE_SA0WGP00TD0_SAMPLEDELAY 0x001a
+#define ixSE_SA0WGP00TD1_SAMPLEDELAY 0x001b
+#define ixSE_SA0WGP00TCP0_SAMPLEDELAY 0x001c
+#define ixSE_SA0WGP00TCP1_SAMPLEDELAY 0x001d
+#define ixSE_SA0WGP01TA0_SAMPLEDELAY 0x001e
+#define ixSE_SA0WGP01TA1_SAMPLEDELAY 0x001f
+#define ixSE_SA0WGP01TD0_SAMPLEDELAY 0x0020
+#define ixSE_SA0WGP01TD1_SAMPLEDELAY 0x0021
+#define ixSE_SA0WGP01TCP0_SAMPLEDELAY 0x0022
+#define ixSE_SA0WGP01TCP1_SAMPLEDELAY 0x0023
+#define ixSE_SA0WGP02TA0_SAMPLEDELAY 0x0024
+#define ixSE_SA0WGP02TA1_SAMPLEDELAY 0x0025
+#define ixSE_SA0WGP02TD0_SAMPLEDELAY 0x0026
+#define ixSE_SA0WGP02TD1_SAMPLEDELAY 0x0027
+#define ixSE_SA0WGP02TCP0_SAMPLEDELAY 0x0028
+#define ixSE_SA0WGP02TCP1_SAMPLEDELAY 0x0029
+#define ixSE_SA0WGP10TA0_SAMPLEDELAY 0x002a
+#define ixSE_SA0WGP10TA1_SAMPLEDELAY 0x002b
+#define ixSE_SA0WGP10TD0_SAMPLEDELAY 0x002c
+#define ixSE_SA0WGP10TD1_SAMPLEDELAY 0x002d
+#define ixSE_SA0WGP10TCP0_SAMPLEDELAY 0x002e
+#define ixSE_SA0WGP10TCP1_SAMPLEDELAY 0x002f
+#define ixSE_SA0WGP11TA0_SAMPLEDELAY 0x0030
+#define ixSE_SA0WGP11TA1_SAMPLEDELAY 0x0031
+#define ixSE_SA0WGP11TD0_SAMPLEDELAY 0x0032
+#define ixSE_SA0WGP11TD1_SAMPLEDELAY 0x0033
+#define ixSE_SA0WGP11TCP0_SAMPLEDELAY 0x0034
+#define ixSE_SA0WGP11TCP1_SAMPLEDELAY 0x0035
+#define ixSE_SA1SX_SAMPLEDELAY 0x0036
+#define ixSE_SA1PA_SAMPLEDELAY 0x0037
+#define ixSE_SA1GL1A_SAMPLEDELAY 0x0038
+#define ixSE_SA1GL1CG_SAMPLEDELAY 0x0039
+#define ixSE_SA1CB0_SAMPLEDELAY 0x003a
+#define ixSE_SA1CB1_SAMPLEDELAY 0x003b
+#define ixSE_SA1CB2_SAMPLEDELAY 0x003c
+#define ixSE_SA1CB3_SAMPLEDELAY 0x003d
+#define ixSE_SA1DB0_SAMPLEDELAY 0x003e
+#define ixSE_SA1DB1_SAMPLEDELAY 0x003f
+#define ixSE_SA1DB2_SAMPLEDELAY 0x0040
+#define ixSE_SA1DB3_SAMPLEDELAY 0x0041
+#define ixSE_SA1SC0_SAMPLEDELAY 0x0042
+#define ixSE_SA1SC1_SAMPLEDELAY 0x0043
+#define ixSE_SA1RMI0_SAMPLEDELAY 0x0044
+#define ixSE_SA1RMI1_SAMPLEDELAY 0x0045
+#define ixSE_SA1GL1C0_SAMPLEDELAY 0x0046
+#define ixSE_SA1GL1C1_SAMPLEDELAY 0x0047
+#define ixSE_SA1GL1C2_SAMPLEDELAY 0x0048
+#define ixSE_SA1GL1C3_SAMPLEDELAY 0x0049
+#define ixSE_SA1WGP00TA0_SAMPLEDELAY 0x004a
+#define ixSE_SA1WGP00TA1_SAMPLEDELAY 0x004b
+#define ixSE_SA1WGP00TD0_SAMPLEDELAY 0x004c
+#define ixSE_SA1WGP00TD1_SAMPLEDELAY 0x004d
+#define ixSE_SA1WGP00TCP0_SAMPLEDELAY 0x004e
+#define ixSE_SA1WGP00TCP1_SAMPLEDELAY 0x004f
+#define ixSE_SA1WGP01TA0_SAMPLEDELAY 0x0050
+#define ixSE_SA1WGP01TA1_SAMPLEDELAY 0x0051
+#define ixSE_SA1WGP01TD0_SAMPLEDELAY 0x0052
+#define ixSE_SA1WGP01TD1_SAMPLEDELAY 0x0053
+#define ixSE_SA1WGP01TCP0_SAMPLEDELAY 0x0054
+#define ixSE_SA1WGP01TCP1_SAMPLEDELAY 0x0055
+#define ixSE_SA1WGP02TA0_SAMPLEDELAY 0x0056
+#define ixSE_SA1WGP02TA1_SAMPLEDELAY 0x0057
+#define ixSE_SA1WGP02TD0_SAMPLEDELAY 0x0058
+#define ixSE_SA1WGP02TD1_SAMPLEDELAY 0x0059
+#define ixSE_SA1WGP02TCP0_SAMPLEDELAY 0x005a
+#define ixSE_SA1WGP02TCP1_SAMPLEDELAY 0x005b
+#define ixSE_SA1WGP10TA0_SAMPLEDELAY 0x005c
+#define ixSE_SA1WGP10TA1_SAMPLEDELAY 0x005d
+#define ixSE_SA1WGP10TD0_SAMPLEDELAY 0x005e
+#define ixSE_SA1WGP10TD1_SAMPLEDELAY 0x005f
+#define ixSE_SA1WGP10TCP0_SAMPLEDELAY 0x0060
+#define ixSE_SA1WGP10TCP1_SAMPLEDELAY 0x0061
+#define ixSE_SA1WGP11TA0_SAMPLEDELAY 0x0062
+#define ixSE_SA1WGP11TA1_SAMPLEDELAY 0x0063
+#define ixSE_SA1WGP11TD0_SAMPLEDELAY 0x0064
+#define ixSE_SA1WGP11TD1_SAMPLEDELAY 0x0065
+#define ixSE_SA1WGP11TCP0_SAMPLEDELAY 0x0066
+#define ixSE_SA1WGP11TCP1_SAMPLEDELAY 0x0067
+
+
+// addressBlock: sqind
+// base address: 0x0
+#define ixSQ_WAVE_MODE 0x0101
+#define ixSQ_WAVE_STATUS 0x0102
+#define ixSQ_WAVE_TRAPSTS 0x0103
+#define ixSQ_WAVE_HW_ID_LEGACY 0x0104
+#define ixSQ_WAVE_GPR_ALLOC 0x0105
+#define ixSQ_WAVE_LDS_ALLOC 0x0106
+#define ixSQ_WAVE_IB_STS 0x0107
+#define ixSQ_WAVE_PC_LO 0x0108
+#define ixSQ_WAVE_PC_HI 0x0109
+#define ixSQ_WAVE_INST_DW0 0x010a
+#define ixSQ_WAVE_IB_DBG1 0x010d
+#define ixSQ_WAVE_FLUSH_IB 0x010e
+#define ixSQ_WAVE_HW_ID1 0x0117
+#define ixSQ_WAVE_HW_ID2 0x0118
+#define ixSQ_WAVE_POPS_PACKER 0x0119
+#define ixSQ_WAVE_SCHED_MODE 0x011a
+#define ixSQ_WAVE_VGPR_OFFSET 0x011b
+#define ixSQ_WAVE_IB_STS2 0x011c
+#define ixSQ_WAVE_TTMP0 0x026c
+#define ixSQ_WAVE_TTMP1 0x026d
+#define ixSQ_WAVE_TTMP2 0x026e
+#define ixSQ_WAVE_TTMP3 0x026f
+#define ixSQ_WAVE_TTMP4 0x0270
+#define ixSQ_WAVE_TTMP5 0x0271
+#define ixSQ_WAVE_TTMP6 0x0272
+#define ixSQ_WAVE_TTMP7 0x0273
+#define ixSQ_WAVE_TTMP8 0x0274
+#define ixSQ_WAVE_TTMP9 0x0275
+#define ixSQ_WAVE_TTMP10 0x0276
+#define ixSQ_WAVE_TTMP11 0x0277
+#define ixSQ_WAVE_TTMP12 0x0278
+#define ixSQ_WAVE_TTMP13 0x0279
+#define ixSQ_WAVE_TTMP14 0x027a
+#define ixSQ_WAVE_TTMP15 0x027b
+#define ixSQ_WAVE_M0 0x027c
+#define ixSQ_WAVE_EXEC_LO 0x027e
+#define ixSQ_WAVE_EXEC_HI 0x027f
+#define ixSQ_WAVE_FLAT_SCRATCH_LO 0x0280
+#define ixSQ_WAVE_FLAT_SCRATCH_HI 0x0281
+#define ixSQ_WAVE_FLAT_XNACK_MASK 0x0282
+#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0
+#define ixSQ_INTERRUPT_WORD_ERROR 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0
+
+
+// addressBlock: didtind
+// base address: 0x0
+#define ixDIDT_SQ_CTRL0 0x0000
+#define ixDIDT_SQ_CTRL1 0x0001
+#define ixDIDT_SQ_CTRL2 0x0002
+#define ixDIDT_SQ_CTRL_OCP 0x0003
+#define ixDIDT_SQ_STALL_CTRL 0x0004
+#define ixDIDT_SQ_TUNING_CTRL 0x0005
+#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
+#define ixDIDT_SQ_CTRL3 0x0007
+#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008
+#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009
+#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a
+#define ixDIDT_SQ_STALL_PATTERN_7 0x000b
+#define ixDIDT_SQ_MPD_SCALE_FACTOR 0x000c
+#define ixDIDT_SQ_STALL_RELEASE_CNTL0 0x000d
+#define ixDIDT_SQ_STALL_RELEASE_CNTL1 0x000e
+#define ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS 0x000f
+#define ixDIDT_SQ_WEIGHT0_3 0x0010
+#define ixDIDT_SQ_WEIGHT4_7 0x0011
+#define ixDIDT_SQ_WEIGHT8_11 0x0012
+#define ixDIDT_SQ_EDC_CTRL 0x0013
+#define ixDIDT_SQ_EDC_THRESHOLD 0x0014
+#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015
+#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016
+#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017
+#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018
+#define ixDIDT_SQ_EDC_TIMER_PERIOD 0x0019
+#define ixDIDT_SQ_THROTTLE_CTRL 0x001a
+#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001b
+#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001c
+#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001d
+#define ixDIDT_SQ_EDC_STATUS 0x001f
+#define ixDIDT_SQ_EDC_OVERFLOW 0x0020
+#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x0021
+#define ixDIDT_SQ_EDC_PCC_PERF_COUNTER 0x0022
+#define ixDIDT_DB_CTRL0 0x0030
+#define ixDIDT_DB_CTRL1 0x0031
+#define ixDIDT_DB_CTRL2 0x0032
+#define ixDIDT_DB_CTRL_OCP 0x0033
+#define ixDIDT_DB_STALL_CTRL 0x0034
+#define ixDIDT_DB_TUNING_CTRL 0x0035
+#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0036
+#define ixDIDT_DB_CTRL3 0x0037
+#define ixDIDT_DB_STALL_PATTERN_1_2 0x0038
+#define ixDIDT_DB_STALL_PATTERN_3_4 0x0039
+#define ixDIDT_DB_STALL_PATTERN_5_6 0x003a
+#define ixDIDT_DB_STALL_PATTERN_7 0x003b
+#define ixDIDT_DB_MPD_SCALE_FACTOR 0x003c
+#define ixDIDT_DB_STALL_RELEASE_CNTL0 0x003d
+#define ixDIDT_DB_STALL_RELEASE_CNTL1 0x003e
+#define ixDIDT_DB_STALL_RELEASE_CNTL_STATUS 0x003f
+#define ixDIDT_DB_WEIGHT0_3 0x0040
+#define ixDIDT_DB_WEIGHT4_7 0x0041
+#define ixDIDT_DB_WEIGHT8_11 0x0042
+#define ixDIDT_DB_EDC_CTRL 0x0043
+#define ixDIDT_DB_EDC_THRESHOLD 0x0044
+#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0045
+#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0046
+#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0047
+#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0048
+#define ixDIDT_DB_EDC_TIMER_PERIOD 0x0049
+#define ixDIDT_DB_THROTTLE_CTRL 0x004a
+#define ixDIDT_DB_EDC_STALL_DELAY_1 0x004b
+#define ixDIDT_DB_EDC_STATUS 0x004f
+#define ixDIDT_DB_EDC_OVERFLOW 0x0050
+#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x0051
+#define ixDIDT_DB_EDC_PCC_PERF_COUNTER 0x0052
+#define ixDIDT_TD_CTRL0 0x0060
+#define ixDIDT_TD_CTRL1 0x0061
+#define ixDIDT_TD_CTRL2 0x0062
+#define ixDIDT_TD_CTRL_OCP 0x0063
+#define ixDIDT_TD_STALL_CTRL 0x0064
+#define ixDIDT_TD_TUNING_CTRL 0x0065
+#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0066
+#define ixDIDT_TD_CTRL3 0x0067
+#define ixDIDT_TD_STALL_PATTERN_1_2 0x0068
+#define ixDIDT_TD_STALL_PATTERN_3_4 0x0069
+#define ixDIDT_TD_STALL_PATTERN_5_6 0x006a
+#define ixDIDT_TD_STALL_PATTERN_7 0x006b
+#define ixDIDT_TD_MPD_SCALE_FACTOR 0x006c
+#define ixDIDT_TD_STALL_RELEASE_CNTL0 0x006d
+#define ixDIDT_TD_STALL_RELEASE_CNTL1 0x006e
+#define ixDIDT_TD_STALL_RELEASE_CNTL_STATUS 0x006f
+#define ixDIDT_TD_WEIGHT0_3 0x0070
+#define ixDIDT_TD_WEIGHT4_7 0x0071
+#define ixDIDT_TD_WEIGHT8_11 0x0072
+#define ixDIDT_TD_EDC_CTRL 0x0073
+#define ixDIDT_TD_EDC_THRESHOLD 0x0074
+#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0075
+#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0076
+#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0077
+#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0078
+#define ixDIDT_TD_EDC_TIMER_PERIOD 0x0079
+#define ixDIDT_TD_THROTTLE_CTRL 0x007a
+#define ixDIDT_TD_EDC_STALL_DELAY_1 0x007b
+#define ixDIDT_TD_EDC_STALL_DELAY_2 0x007c
+#define ixDIDT_TD_EDC_STALL_DELAY_3 0x007d
+#define ixDIDT_TD_EDC_STATUS 0x007f
+#define ixDIDT_TD_EDC_OVERFLOW 0x0080
+#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0x0081
+#define ixDIDT_TD_EDC_PCC_PERF_COUNTER 0x0082
+#define ixDIDT_TCP_CTRL0 0x0090
+#define ixDIDT_TCP_CTRL1 0x0091
+#define ixDIDT_TCP_CTRL2 0x0092
+#define ixDIDT_TCP_CTRL_OCP 0x0093
+#define ixDIDT_TCP_STALL_CTRL 0x0094
+#define ixDIDT_TCP_TUNING_CTRL 0x0095
+#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0096
+#define ixDIDT_TCP_CTRL3 0x0097
+#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0098
+#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0099
+#define ixDIDT_TCP_STALL_PATTERN_5_6 0x009a
+#define ixDIDT_TCP_STALL_PATTERN_7 0x009b
+#define ixDIDT_TCP_MPD_SCALE_FACTOR 0x009c
+#define ixDIDT_TCP_STALL_RELEASE_CNTL0 0x009d
+#define ixDIDT_TCP_STALL_RELEASE_CNTL1 0x009e
+#define ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS 0x009f
+#define ixDIDT_TCP_WEIGHT0_3 0x00a0
+#define ixDIDT_TCP_WEIGHT4_7 0x00a1
+#define ixDIDT_TCP_WEIGHT8_11 0x00a2
+#define ixDIDT_TCP_EDC_CTRL 0x00a3
+#define ixDIDT_TCP_EDC_THRESHOLD 0x00a4
+#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x00a5
+#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x00a6
+#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x00a7
+#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x00a8
+#define ixDIDT_TCP_EDC_TIMER_PERIOD 0x00a9
+#define ixDIDT_TCP_THROTTLE_CTRL 0x00aa
+#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x00ab
+#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x00ac
+#define ixDIDT_TCP_EDC_STALL_DELAY_3 0x00ad
+#define ixDIDT_TCP_EDC_STATUS 0x00af
+#define ixDIDT_TCP_EDC_OVERFLOW 0x00b0
+#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0x00b1
+#define ixDIDT_TCP_EDC_PCC_PERF_COUNTER 0x00b2
+#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00c0
+#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00c1
+#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00c2
+#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00c3
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
new file mode 100644
index 000000000000..6c2a421fe8b7
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
@@ -0,0 +1,43963 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _gc_10_1_0_SH_MASK_HEADER
+#define _gc_10_1_0_SH_MASK_HEADER
+
+
+// addressBlock: gc_sdma0_sdma0dec
+//SDMA0_DEC_START
+#define SDMA0_DEC_START__START__SHIFT 0x0
+#define SDMA0_DEC_START__START_MASK 0xFFFFFFFFL
+//SDMA0_PG_CNTL
+#define SDMA0_PG_CNTL__CMD__SHIFT 0x0
+#define SDMA0_PG_CNTL__STATUS__SHIFT 0x10
+#define SDMA0_PG_CNTL__CMD_MASK 0x0000000FL
+#define SDMA0_PG_CNTL__STATUS_MASK 0x000F0000L
+//SDMA0_PG_CTX_LO
+#define SDMA0_PG_CTX_LO__ADDR__SHIFT 0x0
+#define SDMA0_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PG_CTX_HI
+#define SDMA0_PG_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA0_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PG_CTX_CNTL
+#define SDMA0_PG_CTX_CNTL__VMID__SHIFT 0x0
+#define SDMA0_PG_CTX_CNTL__VMID_MASK 0x0000000FL
+//SDMA0_POWER_CNTL
+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+//SDMA0_CLK_CTRL
+#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x17
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA0_CLK_CTRL__RESERVED_MASK 0x007FF000L
+#define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00800000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA0_CNTL
+#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA0_CNTL__PAGE_INT_ENABLE__SHIFT 0x7
+#define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA0_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L
+#define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA0_CHICKEN_BITS
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12
+#define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18
+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L
+#define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L
+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
+//SDMA0_GB_ADDR_CONFIG
+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA0_GB_ADDR_CONFIG_READ
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA0_RB_RPTR_FETCH_HI
+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA0_RB_RPTR_FETCH
+#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA0_IB_OFFSET_FETCH
+#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PROGRAM
+#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA0_STATUS_REG
+#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA0_STATUS1_REG
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA0_RD_BURST_CNTL
+#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+//SDMA0_HBM_PAGE_CONFIG
+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
+//SDMA0_UCODE_CHECKSUM
+#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA0_F32_CNTL
+#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA0_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8
+#define SDMA0_F32_CNTL__RESET__SHIFT 0x9
+#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L
+#define SDMA0_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L
+#define SDMA0_F32_CNTL__RESET_MASK 0x00000200L
+//SDMA0_FREEZE
+#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA0_FREEZE__FORCE_PREEMPT__SHIFT 0x1
+#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA0_FREEZE__FORCE_PREEMPT_MASK 0x00000002L
+#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA0_PHASE0_QUANTUM
+#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA0_PHASE1_QUANTUM
+#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA_POWER_GATING
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3
+#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L
+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L
+#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
+//SDMA_PGFSM_CONFIG
+#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
+#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
+#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
+#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
+#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
+#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
+#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
+#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
+//SDMA_PGFSM_WRITE
+#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
+//SDMA_PGFSM_READ
+#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
+//SDMA0_EDC_CONFIG
+#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
+//SDMA0_BA_THRESHOLD
+#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA0_ID
+#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA0_VERSION
+#define SDMA0_VERSION__MINVER__SHIFT 0x0
+#define SDMA0_VERSION__MAJVER__SHIFT 0x8
+#define SDMA0_VERSION__REV__SHIFT 0x10
+#define SDMA0_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA0_VERSION__REV_MASK 0x003F0000L
+//SDMA0_EDC_COUNTER
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
+#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
+#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
+#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
+#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
+#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
+#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
+#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
+#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
+//SDMA0_EDC_COUNTER_CLEAR
+#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
+#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
+//SDMA0_STATUS2_REG
+#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
+#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA0_ATOMIC_CNTL
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA0_ATOMIC_PREOP_LO
+#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA0_ATOMIC_PREOP_HI
+#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_CNTL
+#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6
+#define SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT 0x9
+#define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe
+#define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf
+#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10
+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL
+#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L
+#define SDMA0_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L
+#define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L
+#define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L
+#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L
+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA0_UTCL1_WATERMK
+#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
+#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
+#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
+#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
+#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
+#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
+//SDMA0_UTCL1_RD_STATUS
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb
+#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc
+#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd
+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf
+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10
+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11
+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15
+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18
+#define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a
+#define SDMA0_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b
+#define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c
+#define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d
+#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e
+#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L
+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L
+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L
+#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L
+#define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L
+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L
+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L
+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L
+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L
+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L
+#define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L
+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L
+#define SDMA0_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L
+#define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L
+#define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L
+#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L
+#define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L
+//SDMA0_UTCL1_WR_STATUS
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb
+#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc
+#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd
+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf
+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10
+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11
+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15
+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18
+#define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a
+#define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L
+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L
+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L
+#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L
+#define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L
+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L
+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L
+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L
+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L
+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L
+#define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L
+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L
+#define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA0_UTCL1_INV0
+#define SDMA0_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0
+#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1
+#define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2
+#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3
+#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4
+#define SDMA0_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5
+#define SDMA0_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb
+#define SDMA0_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc
+#define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10
+#define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14
+#define SDMA0_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18
+#define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a
+#define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b
+#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c
+#define SDMA0_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L
+#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L
+#define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L
+#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L
+#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L
+#define SDMA0_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L
+#define SDMA0_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L
+#define SDMA0_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L
+#define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L
+#define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L
+#define SDMA0_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L
+#define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L
+#define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L
+#define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L
+//SDMA0_UTCL1_INV1
+#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_INV2
+#define SDMA0_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0
+#define SDMA0_UTCL1_INV2__RESERVED__SHIFT 0x10
+#define SDMA0_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL
+#define SDMA0_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L
+//SDMA0_UTCL1_RD_XNACK0
+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_RD_XNACK1
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA0_UTCL1_WR_XNACK0
+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA0_UTCL1_WR_XNACK1
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA0_UTCL1_TIMEOUT
+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA0_UTCL1_PAGE
+#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
+#define SDMA0_UTCL1_PAGE__USE_IO__SHIFT 0xb
+#define SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc
+#define SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe
+#define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10
+#define SDMA0_UTCL1_PAGE__USE_BC__SHIFT 0x16
+#define SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17
+#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L
+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L
+#define SDMA0_UTCL1_PAGE__USE_IO_MASK 0x00000800L
+#define SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L
+#define SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L
+#define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L
+#define SDMA0_UTCL1_PAGE__USE_BC_MASK 0x00400000L
+#define SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L
+//SDMA0_POWER_CNTL_IDLE
+#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA0_RELAX_ORDERING_LUT
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA0_CHICKEN_BITS_2
+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4
+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+#define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L
+//SDMA0_STATUS3_REG
+#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15
+#define SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT 0x16
+#define SDMA0_STATUS3_REG__GCR_IDLE__SHIFT 0x17
+#define SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18
+#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19
+#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a
+#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+#define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L
+#define SDMA0_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L
+#define SDMA0_STATUS3_REG__GCR_IDLE_MASK 0x00800000L
+#define SDMA0_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L
+#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L
+#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L
+//SDMA0_PHYSICAL_ADDR_LO
+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA0_PHYSICAL_ADDR_HI
+#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA0_PHASE2_QUANTUM
+#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA0_F32_COUNTER
+#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_PERFMON_CNTL
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
+#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
+#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
+//SDMA0_PERFCOUNTER0_RESULT
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA0_PERFCOUNTER1_RESULT
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
+//SDMA0_CRD_CNTL
+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13
+#define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19
+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+#define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L
+#define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L
+//SDMA0_GPU_IOV_VIOLATION_LOG
+//SDMA0_AQL_STATUS
+#define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0
+#define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1
+#define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L
+#define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L
+//SDMA0_EA_DBIT_ADDR_DATA
+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_EA_DBIT_ADDR_INDEX
+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA0_TLBI_GCR_CNTL
+#define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0
+#define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4
+#define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8
+#define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10
+#define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18
+#define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL
+#define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L
+#define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L
+#define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L
+#define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L
+//SDMA0_TILING_CONFIG
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
+//SDMA0_HASH
+#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA0_HASH__CHANNEL_BITS_MASK 0x00000007L
+#define SDMA0_HASH__BANK_BITS_MASK 0x00000070L
+#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x00000700L
+#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x00007000L
+//SDMA0_PERFCOUNTER0_SELECT
+#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//SDMA0_PERFCOUNTER0_SELECT1
+#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SDMA0_PERFCOUNTER0_LO
+#define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SDMA0_PERFCOUNTER0_HI
+#define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SDMA0_PERFCOUNTER1_SELECT
+#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//SDMA0_PERFCOUNTER1_SELECT1
+#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SDMA0_PERFCOUNTER1_LO
+#define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SDMA0_PERFCOUNTER1_HI
+#define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SDMA0_INT_STATUS
+#define SDMA0_INT_STATUS__DATA__SHIFT 0x0
+#define SDMA0_INT_STATUS__DATA_MASK 0xFFFFFFFFL
+//SDMA0_GPU_IOV_VIOLATION_LOG2
+#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
+#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
+//SDMA0_HOLE_ADDR_LO
+#define SDMA0_HOLE_ADDR_LO__VALUE__SHIFT 0x0
+#define SDMA0_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_HOLE_ADDR_HI
+#define SDMA0_HOLE_ADDR_HI__VALUE__SHIFT 0x0
+#define SDMA0_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_CNTL
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_GFX_RB_BASE
+#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_BASE_HI
+#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_GFX_RB_RPTR
+#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_RPTR_HI
+#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR
+#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_HI
+#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_CNTL
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_GFX_RB_RPTR_ADDR_HI
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_RPTR_ADDR_LO
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_IB_CNTL
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_GFX_IB_RPTR
+#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_GFX_IB_OFFSET
+#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_GFX_IB_BASE_LO
+#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_GFX_IB_BASE_HI
+#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_IB_SIZE
+#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_GFX_SKIP_CNTL
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_GFX_CONTEXT_STATUS
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_GFX_DOORBELL
+#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_GFX_CONTEXT_CNTL
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+//SDMA0_GFX_STATUS
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_GFX_DOORBELL_LOG
+//SDMA0_GFX_WATERMARK
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_GFX_DOORBELL_OFFSET
+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_GFX_CSA_ADDR_LO
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_CSA_ADDR_HI
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_IB_SUB_REMAIN
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_GFX_PREEMPT
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_GFX_DUMMY_REG
+#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_GFX_RB_AQL_CNTL
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_GFX_MINOR_PTR_UPDATE
+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_GFX_MIDCMD_DATA0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA1
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA2
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA3
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA4
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA5
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA6
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA7
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_DATA8
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_GFX_MIDCMD_CNTL
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_PAGE_RB_CNTL
+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_PAGE_RB_BASE
+#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_BASE_HI
+#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_PAGE_RB_RPTR
+#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_RPTR_HI
+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR
+#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_HI
+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_PAGE_RB_RPTR_ADDR_HI
+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_RPTR_ADDR_LO
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_IB_CNTL
+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_PAGE_IB_RPTR
+#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PAGE_IB_OFFSET
+#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_PAGE_IB_BASE_LO
+#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_PAGE_IB_BASE_HI
+#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_IB_SIZE
+#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_PAGE_SKIP_CNTL
+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_PAGE_CONTEXT_STATUS
+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_PAGE_DOORBELL
+#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_PAGE_STATUS
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_PAGE_DOORBELL_LOG
+//SDMA0_PAGE_WATERMARK
+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_PAGE_DOORBELL_OFFSET
+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_PAGE_CSA_ADDR_LO
+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_CSA_ADDR_HI
+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_IB_SUB_REMAIN
+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_PAGE_PREEMPT
+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_PAGE_DUMMY_REG
+#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_PAGE_RB_AQL_CNTL
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_PAGE_MINOR_PTR_UPDATE
+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_PAGE_MIDCMD_DATA0
+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA1
+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA2
+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA3
+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA4
+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA5
+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA6
+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA7
+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_DATA8
+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_PAGE_MIDCMD_CNTL
+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC0_RB_CNTL
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_RLC0_RB_BASE
+#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_BASE_HI
+#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC0_RB_RPTR
+#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_RPTR_HI
+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR
+#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_HI
+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC0_RB_RPTR_ADDR_HI
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_RPTR_ADDR_LO
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_IB_CNTL
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC0_IB_RPTR
+#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC0_IB_OFFSET
+#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC0_IB_BASE_LO
+#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC0_IB_BASE_HI
+#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_IB_SIZE
+#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC0_SKIP_CNTL
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC0_CONTEXT_STATUS
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC0_DOORBELL
+#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC0_STATUS
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC0_DOORBELL_LOG
+//SDMA0_RLC0_WATERMARK
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC0_DOORBELL_OFFSET
+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC0_CSA_ADDR_LO
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_CSA_ADDR_HI
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_IB_SUB_REMAIN
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC0_PREEMPT
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC0_DUMMY_REG
+#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC0_RB_AQL_CNTL
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_RLC0_MINOR_PTR_UPDATE
+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC0_MIDCMD_DATA0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA1
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA2
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA3
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA4
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA5
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA6
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA7
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_DATA8
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC0_MIDCMD_CNTL
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC1_RB_CNTL
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_RLC1_RB_BASE
+#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_BASE_HI
+#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC1_RB_RPTR
+#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_RPTR_HI
+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR
+#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_HI
+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC1_RB_RPTR_ADDR_HI
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_RPTR_ADDR_LO
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_IB_CNTL
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC1_IB_RPTR
+#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC1_IB_OFFSET
+#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC1_IB_BASE_LO
+#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC1_IB_BASE_HI
+#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_IB_SIZE
+#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC1_SKIP_CNTL
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC1_CONTEXT_STATUS
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC1_DOORBELL
+#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC1_STATUS
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC1_DOORBELL_LOG
+//SDMA0_RLC1_WATERMARK
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC1_DOORBELL_OFFSET
+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC1_CSA_ADDR_LO
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_CSA_ADDR_HI
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_IB_SUB_REMAIN
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC1_PREEMPT
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC1_DUMMY_REG
+#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC1_RB_AQL_CNTL
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_RLC1_MINOR_PTR_UPDATE
+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC1_MIDCMD_DATA0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA1
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA2
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA3
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA4
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA5
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA6
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA7
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_DATA8
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC1_MIDCMD_CNTL
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC2_RB_CNTL
+#define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_RLC2_RB_BASE
+#define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_BASE_HI
+#define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC2_RB_RPTR
+#define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_RPTR_HI
+#define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR
+#define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR_HI
+#define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC2_RB_RPTR_ADDR_HI
+#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_RPTR_ADDR_LO
+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC2_IB_CNTL
+#define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC2_IB_RPTR
+#define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC2_IB_OFFSET
+#define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC2_IB_BASE_LO
+#define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC2_IB_BASE_HI
+#define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_IB_SIZE
+#define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC2_SKIP_CNTL
+#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC2_CONTEXT_STATUS
+#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC2_DOORBELL
+#define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC2_STATUS
+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC2_DOORBELL_LOG
+//SDMA0_RLC2_WATERMARK
+#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC2_DOORBELL_OFFSET
+#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC2_CSA_ADDR_LO
+#define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC2_CSA_ADDR_HI
+#define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_IB_SUB_REMAIN
+#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC2_PREEMPT
+#define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC2_DUMMY_REG
+#define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC2_RB_AQL_CNTL
+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_RLC2_MINOR_PTR_UPDATE
+#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC2_MIDCMD_DATA0
+#define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA1
+#define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA2
+#define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA3
+#define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA4
+#define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA5
+#define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA6
+#define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA7
+#define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_DATA8
+#define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC2_MIDCMD_CNTL
+#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC3_RB_CNTL
+#define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_RLC3_RB_BASE
+#define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_BASE_HI
+#define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC3_RB_RPTR
+#define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_RPTR_HI
+#define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR
+#define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR_HI
+#define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC3_RB_RPTR_ADDR_HI
+#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_RPTR_ADDR_LO
+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC3_IB_CNTL
+#define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC3_IB_RPTR
+#define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC3_IB_OFFSET
+#define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC3_IB_BASE_LO
+#define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC3_IB_BASE_HI
+#define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_IB_SIZE
+#define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC3_SKIP_CNTL
+#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC3_CONTEXT_STATUS
+#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC3_DOORBELL
+#define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC3_STATUS
+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC3_DOORBELL_LOG
+//SDMA0_RLC3_WATERMARK
+#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC3_DOORBELL_OFFSET
+#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC3_CSA_ADDR_LO
+#define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC3_CSA_ADDR_HI
+#define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_IB_SUB_REMAIN
+#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC3_PREEMPT
+#define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC3_DUMMY_REG
+#define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC3_RB_AQL_CNTL
+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_RLC3_MINOR_PTR_UPDATE
+#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC3_MIDCMD_DATA0
+#define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA1
+#define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA2
+#define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA3
+#define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA4
+#define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA5
+#define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA6
+#define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA7
+#define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_DATA8
+#define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC3_MIDCMD_CNTL
+#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC4_RB_CNTL
+#define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_RLC4_RB_BASE
+#define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_BASE_HI
+#define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC4_RB_RPTR
+#define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_RPTR_HI
+#define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR
+#define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR_HI
+#define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC4_RB_RPTR_ADDR_HI
+#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_RPTR_ADDR_LO
+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC4_IB_CNTL
+#define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC4_IB_RPTR
+#define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC4_IB_OFFSET
+#define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC4_IB_BASE_LO
+#define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC4_IB_BASE_HI
+#define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_IB_SIZE
+#define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC4_SKIP_CNTL
+#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC4_CONTEXT_STATUS
+#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC4_DOORBELL
+#define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC4_STATUS
+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC4_DOORBELL_LOG
+//SDMA0_RLC4_WATERMARK
+#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC4_DOORBELL_OFFSET
+#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC4_CSA_ADDR_LO
+#define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC4_CSA_ADDR_HI
+#define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_IB_SUB_REMAIN
+#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC4_PREEMPT
+#define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC4_DUMMY_REG
+#define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC4_RB_AQL_CNTL
+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_RLC4_MINOR_PTR_UPDATE
+#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC4_MIDCMD_DATA0
+#define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA1
+#define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA2
+#define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA3
+#define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA4
+#define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA5
+#define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA6
+#define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA7
+#define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_DATA8
+#define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC4_MIDCMD_CNTL
+#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC5_RB_CNTL
+#define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_RLC5_RB_BASE
+#define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_BASE_HI
+#define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC5_RB_RPTR
+#define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_RPTR_HI
+#define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR
+#define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR_HI
+#define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC5_RB_RPTR_ADDR_HI
+#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_RPTR_ADDR_LO
+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC5_IB_CNTL
+#define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC5_IB_RPTR
+#define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC5_IB_OFFSET
+#define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC5_IB_BASE_LO
+#define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC5_IB_BASE_HI
+#define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_IB_SIZE
+#define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC5_SKIP_CNTL
+#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC5_CONTEXT_STATUS
+#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC5_DOORBELL
+#define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC5_STATUS
+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC5_DOORBELL_LOG
+//SDMA0_RLC5_WATERMARK
+#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC5_DOORBELL_OFFSET
+#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC5_CSA_ADDR_LO
+#define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC5_CSA_ADDR_HI
+#define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_IB_SUB_REMAIN
+#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC5_PREEMPT
+#define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC5_DUMMY_REG
+#define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC5_RB_AQL_CNTL
+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_RLC5_MINOR_PTR_UPDATE
+#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC5_MIDCMD_DATA0
+#define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA1
+#define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA2
+#define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA3
+#define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA4
+#define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA5
+#define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA6
+#define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA7
+#define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_DATA8
+#define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC5_MIDCMD_CNTL
+#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC6_RB_CNTL
+#define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_RLC6_RB_BASE
+#define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_BASE_HI
+#define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC6_RB_RPTR
+#define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_RPTR_HI
+#define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR
+#define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR_HI
+#define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC6_RB_RPTR_ADDR_HI
+#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_RPTR_ADDR_LO
+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC6_IB_CNTL
+#define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC6_IB_RPTR
+#define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC6_IB_OFFSET
+#define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC6_IB_BASE_LO
+#define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC6_IB_BASE_HI
+#define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_IB_SIZE
+#define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC6_SKIP_CNTL
+#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC6_CONTEXT_STATUS
+#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC6_DOORBELL
+#define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC6_STATUS
+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC6_DOORBELL_LOG
+//SDMA0_RLC6_WATERMARK
+#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC6_DOORBELL_OFFSET
+#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC6_CSA_ADDR_LO
+#define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC6_CSA_ADDR_HI
+#define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_IB_SUB_REMAIN
+#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC6_PREEMPT
+#define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC6_DUMMY_REG
+#define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC6_RB_AQL_CNTL
+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_RLC6_MINOR_PTR_UPDATE
+#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC6_MIDCMD_DATA0
+#define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA1
+#define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA2
+#define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA3
+#define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA4
+#define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA5
+#define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA6
+#define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA7
+#define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_DATA8
+#define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC6_MIDCMD_CNTL
+#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA0_RLC7_RB_CNTL
+#define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA0_RLC7_RB_BASE
+#define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_BASE_HI
+#define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA0_RLC7_RB_RPTR
+#define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_RPTR_HI
+#define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR
+#define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR_HI
+#define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR_POLL_CNTL
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA0_RLC7_RB_RPTR_ADDR_HI
+#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_RPTR_ADDR_LO
+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC7_IB_CNTL
+#define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA0_RLC7_IB_RPTR
+#define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC7_IB_OFFSET
+#define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA0_RLC7_IB_BASE_LO
+#define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA0_RLC7_IB_BASE_HI
+#define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_IB_SIZE
+#define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA0_RLC7_SKIP_CNTL
+#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA0_RLC7_CONTEXT_STATUS
+#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA0_RLC7_DOORBELL
+#define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA0_RLC7_STATUS
+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA0_RLC7_DOORBELL_LOG
+//SDMA0_RLC7_WATERMARK
+#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA0_RLC7_DOORBELL_OFFSET
+#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA0_RLC7_CSA_ADDR_LO
+#define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC7_CSA_ADDR_HI
+#define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_IB_SUB_REMAIN
+#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA0_RLC7_PREEMPT
+#define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA0_RLC7_DUMMY_REG
+#define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI
+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO
+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_RLC7_RB_AQL_CNTL
+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA0_RLC7_MINOR_PTR_UPDATE
+#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA0_RLC7_MIDCMD_DATA0
+#define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA1
+#define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA2
+#define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA3
+#define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA4
+#define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA5
+#define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA6
+#define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA7
+#define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_DATA8
+#define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA0_RLC7_MIDCMD_CNTL
+#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+
+// addressBlock: gc_sdma1_sdma1dec
+//SDMA1_DEC_START
+#define SDMA1_DEC_START__START__SHIFT 0x0
+#define SDMA1_DEC_START__START_MASK 0xFFFFFFFFL
+//SDMA1_PG_CNTL
+#define SDMA1_PG_CNTL__CMD__SHIFT 0x0
+#define SDMA1_PG_CNTL__STATUS__SHIFT 0x10
+#define SDMA1_PG_CNTL__CMD_MASK 0x0000000FL
+#define SDMA1_PG_CNTL__STATUS_MASK 0x000F0000L
+//SDMA1_PG_CTX_LO
+#define SDMA1_PG_CTX_LO__ADDR__SHIFT 0x0
+#define SDMA1_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PG_CTX_HI
+#define SDMA1_PG_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA1_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PG_CTX_CNTL
+#define SDMA1_PG_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA1_PG_CTX_CNTL__VMID_MASK 0x000000F0L
+//SDMA1_POWER_CNTL
+#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
+#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
+#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
+#define SDMA1_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
+#define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
+#define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
+#define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
+#define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+//SDMA1_CLK_CTRL
+#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SDMA1_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x17
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SDMA1_CLK_CTRL__RESERVED_MASK 0x007FF000L
+#define SDMA1_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00800000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//SDMA1_CNTL
+#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA1_CNTL__PAGE_INT_ENABLE__SHIFT 0x7
+#define SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L
+#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
+#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
+#define SDMA1_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L
+#define SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
+#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
+//SDMA1_CHICKEN_BITS
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
+#define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12
+#define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18
+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
+#define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L
+#define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
+#define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
+#define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L
+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
+//SDMA1_GB_ADDR_CONFIG
+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA1_GB_ADDR_CONFIG_READ
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+//SDMA1_RB_RPTR_FETCH_HI
+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
+//SDMA1_RB_RPTR_FETCH
+#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
+//SDMA1_IB_OFFSET_FETCH
+#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PROGRAM
+#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL
+//SDMA1_STATUS_REG
+#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L
+#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L
+#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L
+#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L
+#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
+#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
+#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
+#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
+#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
+#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L
+#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
+#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L
+#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
+#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
+#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
+#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L
+#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
+#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
+#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L
+#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
+//SDMA1_STATUS1_REG
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf
+#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
+#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
+#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
+#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
+#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
+#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L
+#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
+#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
+//SDMA1_RD_BURST_CNTL
+#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
+//SDMA1_HBM_PAGE_CONFIG
+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L
+//SDMA1_UCODE_CHECKSUM
+#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0
+#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
+//SDMA1_F32_CNTL
+#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA1_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8
+#define SDMA1_F32_CNTL__RESET__SHIFT 0x9
+#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L
+#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L
+#define SDMA1_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L
+#define SDMA1_F32_CNTL__RESET_MASK 0x00000200L
+//SDMA1_FREEZE
+#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0
+#define SDMA1_FREEZE__FORCE_PREEMPT__SHIFT 0x1
+#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L
+#define SDMA1_FREEZE__FORCE_PREEMPT_MASK 0x00000002L
+#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L
+#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L
+#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L
+//SDMA1_PHASE0_QUANTUM
+#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_PHASE1_QUANTUM
+#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_EDC_CONFIG
+#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
+//SDMA1_BA_THRESHOLD
+#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
+#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
+//SDMA1_ID
+#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL
+//SDMA1_VERSION
+#define SDMA1_VERSION__MINVER__SHIFT 0x0
+#define SDMA1_VERSION__MAJVER__SHIFT 0x8
+#define SDMA1_VERSION__REV__SHIFT 0x10
+#define SDMA1_VERSION__MINVER_MASK 0x0000007FL
+#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L
+#define SDMA1_VERSION__REV_MASK 0x003F0000L
+//SDMA1_EDC_COUNTER
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
+#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
+#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
+#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
+#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
+#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
+#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
+#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
+#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
+#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
+#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
+//SDMA1_EDC_COUNTER_CLEAR
+#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
+#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
+//SDMA1_STATUS2_REG
+#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
+#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
+//SDMA1_ATOMIC_CNTL
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
+//SDMA1_ATOMIC_PREOP_LO
+#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
+//SDMA1_ATOMIC_PREOP_HI
+#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_CNTL
+#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6
+#define SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT 0x9
+#define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe
+#define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf
+#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10
+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
+#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
+#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL
+#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L
+#define SDMA1_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L
+#define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L
+#define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L
+#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L
+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
+//SDMA1_UTCL1_WATERMK
+#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
+#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
+#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
+#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
+#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
+#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
+//SDMA1_UTCL1_RD_STATUS
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb
+#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc
+#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd
+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf
+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10
+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11
+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15
+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18
+#define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a
+#define SDMA1_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b
+#define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c
+#define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d
+#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e
+#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L
+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L
+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L
+#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L
+#define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L
+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L
+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L
+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L
+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L
+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L
+#define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L
+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L
+#define SDMA1_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L
+#define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L
+#define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L
+#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L
+#define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L
+//SDMA1_UTCL1_WR_STATUS
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb
+#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc
+#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd
+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf
+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10
+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11
+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15
+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18
+#define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a
+#define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L
+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L
+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L
+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L
+#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L
+#define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L
+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L
+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L
+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L
+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L
+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L
+#define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L
+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L
+#define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
+//SDMA1_UTCL1_INV0
+#define SDMA1_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0
+#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1
+#define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2
+#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3
+#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4
+#define SDMA1_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5
+#define SDMA1_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb
+#define SDMA1_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc
+#define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10
+#define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14
+#define SDMA1_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18
+#define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a
+#define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b
+#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c
+#define SDMA1_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L
+#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L
+#define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L
+#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L
+#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L
+#define SDMA1_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L
+#define SDMA1_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L
+#define SDMA1_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L
+#define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L
+#define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L
+#define SDMA1_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L
+#define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L
+#define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L
+#define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L
+//SDMA1_UTCL1_INV1
+#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_INV2
+#define SDMA1_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0
+#define SDMA1_UTCL1_INV2__RESERVED__SHIFT 0x10
+#define SDMA1_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL
+#define SDMA1_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L
+//SDMA1_UTCL1_RD_XNACK0
+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_RD_XNACK1
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA1_UTCL1_WR_XNACK0
+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
+//SDMA1_UTCL1_WR_XNACK1
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
+//SDMA1_UTCL1_TIMEOUT
+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
+//SDMA1_UTCL1_PAGE
+#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
+#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
+#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa
+#define SDMA1_UTCL1_PAGE__USE_IO__SHIFT 0xb
+#define SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc
+#define SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe
+#define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10
+#define SDMA1_UTCL1_PAGE__USE_BC__SHIFT 0x16
+#define SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17
+#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
+#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
+#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L
+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L
+#define SDMA1_UTCL1_PAGE__USE_IO_MASK 0x00000800L
+#define SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L
+#define SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L
+#define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L
+#define SDMA1_UTCL1_PAGE__USE_BC_MASK 0x00400000L
+#define SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L
+//SDMA1_POWER_CNTL_IDLE
+#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
+#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
+#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
+//SDMA1_RELAX_ORDERING_LUT
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
+#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
+#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
+#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
+#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
+#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
+#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
+#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
+//SDMA1_CHICKEN_BITS_2
+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4
+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
+#define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L
+//SDMA1_STATUS3_REG
+#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
+#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
+#define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15
+#define SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT 0x16
+#define SDMA1_STATUS3_REG__GCR_IDLE__SHIFT 0x17
+#define SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18
+#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19
+#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a
+#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
+#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
+#define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L
+#define SDMA1_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L
+#define SDMA1_STATUS3_REG__GCR_IDLE_MASK 0x00800000L
+#define SDMA1_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L
+#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L
+#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L
+//SDMA1_PHYSICAL_ADDR_LO
+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
+#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
+#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//SDMA1_PHYSICAL_ADDR_HI
+#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//SDMA1_PHASE2_QUANTUM
+#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL
+#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L
+#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L
+//SDMA1_F32_COUNTER
+#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0
+#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_PERFMON_CNTL
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
+#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
+#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
+//SDMA1_PERFCOUNTER0_RESULT
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA1_PERFCOUNTER1_RESULT
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
+//SDMA1_CRD_CNTL
+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13
+#define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19
+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
+#define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L
+#define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L
+//SDMA1_GPU_IOV_VIOLATION_LOG
+//SDMA1_AQL_STATUS
+#define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0
+#define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1
+#define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L
+#define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L
+//SDMA1_EA_DBIT_ADDR_DATA
+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_EA_DBIT_ADDR_INDEX
+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
+//SDMA1_TLBI_GCR_CNTL
+#define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0
+#define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4
+#define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8
+#define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10
+#define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18
+#define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL
+#define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L
+#define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L
+#define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L
+#define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L
+//SDMA1_TILING_CONFIG
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
+//SDMA1_HASH
+#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA1_HASH__CHANNEL_BITS_MASK 0x00000007L
+#define SDMA1_HASH__BANK_BITS_MASK 0x00000070L
+#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x00000700L
+#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x00007000L
+//SDMA1_PERFCOUNTER0_SELECT
+#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//SDMA1_PERFCOUNTER0_SELECT1
+#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SDMA1_PERFCOUNTER0_LO
+#define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SDMA1_PERFCOUNTER0_HI
+#define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SDMA1_PERFCOUNTER1_SELECT
+#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//SDMA1_PERFCOUNTER1_SELECT1
+#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SDMA1_PERFCOUNTER1_LO
+#define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SDMA1_PERFCOUNTER1_HI
+#define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SDMA1_INT_STATUS
+#define SDMA1_INT_STATUS__DATA__SHIFT 0x0
+#define SDMA1_INT_STATUS__DATA_MASK 0xFFFFFFFFL
+//SDMA1_GPU_IOV_VIOLATION_LOG2
+#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
+#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
+//SDMA1_HOLE_ADDR_LO
+#define SDMA1_HOLE_ADDR_LO__VALUE__SHIFT 0x0
+#define SDMA1_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_HOLE_ADDR_HI
+#define SDMA1_HOLE_ADDR_HI__VALUE__SHIFT 0x0
+#define SDMA1_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_CNTL
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_GFX_RB_BASE
+#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_BASE_HI
+#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_GFX_RB_RPTR
+#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_RPTR_HI
+#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR
+#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_HI
+#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_CNTL
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_GFX_RB_RPTR_ADDR_HI
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_RPTR_ADDR_LO
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_IB_CNTL
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_GFX_IB_RPTR
+#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_GFX_IB_OFFSET
+#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_GFX_IB_BASE_LO
+#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_GFX_IB_BASE_HI
+#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_IB_SIZE
+#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_GFX_SKIP_CNTL
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_GFX_CONTEXT_STATUS
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_GFX_DOORBELL
+#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_GFX_CONTEXT_CNTL
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
+//SDMA1_GFX_STATUS
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_GFX_DOORBELL_LOG
+//SDMA1_GFX_WATERMARK
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_GFX_DOORBELL_OFFSET
+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_GFX_CSA_ADDR_LO
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_CSA_ADDR_HI
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_IB_SUB_REMAIN
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_GFX_PREEMPT
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_GFX_DUMMY_REG
+#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_GFX_RB_AQL_CNTL
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_GFX_MINOR_PTR_UPDATE
+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_GFX_MIDCMD_DATA0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA1
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA2
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA3
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA4
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA5
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA6
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA7
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_DATA8
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_GFX_MIDCMD_CNTL
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_PAGE_RB_CNTL
+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_PAGE_RB_BASE
+#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_BASE_HI
+#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_PAGE_RB_RPTR
+#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_RPTR_HI
+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR
+#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_HI
+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_CNTL
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_PAGE_RB_RPTR_ADDR_HI
+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_RPTR_ADDR_LO
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_IB_CNTL
+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_PAGE_IB_RPTR
+#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PAGE_IB_OFFSET
+#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_PAGE_IB_BASE_LO
+#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_PAGE_IB_BASE_HI
+#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_IB_SIZE
+#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_PAGE_SKIP_CNTL
+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_PAGE_CONTEXT_STATUS
+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_PAGE_DOORBELL
+#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_PAGE_STATUS
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_PAGE_DOORBELL_LOG
+//SDMA1_PAGE_WATERMARK
+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_PAGE_DOORBELL_OFFSET
+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_PAGE_CSA_ADDR_LO
+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_CSA_ADDR_HI
+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_IB_SUB_REMAIN
+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_PAGE_PREEMPT
+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_PAGE_DUMMY_REG
+#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_PAGE_RB_AQL_CNTL
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_PAGE_MINOR_PTR_UPDATE
+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_PAGE_MIDCMD_DATA0
+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA1
+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA2
+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA3
+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA4
+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA5
+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA6
+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA7
+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_DATA8
+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_PAGE_MIDCMD_CNTL
+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC0_RB_CNTL
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_RLC0_RB_BASE
+#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_BASE_HI
+#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC0_RB_RPTR
+#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_RPTR_HI
+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR
+#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_HI
+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC0_RB_RPTR_ADDR_HI
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_RPTR_ADDR_LO
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_IB_CNTL
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC0_IB_RPTR
+#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC0_IB_OFFSET
+#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC0_IB_BASE_LO
+#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC0_IB_BASE_HI
+#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_IB_SIZE
+#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC0_SKIP_CNTL
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC0_CONTEXT_STATUS
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC0_DOORBELL
+#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC0_STATUS
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC0_DOORBELL_LOG
+//SDMA1_RLC0_WATERMARK
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC0_DOORBELL_OFFSET
+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC0_CSA_ADDR_LO
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_CSA_ADDR_HI
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_IB_SUB_REMAIN
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC0_PREEMPT
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC0_DUMMY_REG
+#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC0_RB_AQL_CNTL
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_RLC0_MINOR_PTR_UPDATE
+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC0_MIDCMD_DATA0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA1
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA2
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA3
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA4
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA5
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA6
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA7
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_DATA8
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC0_MIDCMD_CNTL
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC1_RB_CNTL
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_RLC1_RB_BASE
+#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_BASE_HI
+#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC1_RB_RPTR
+#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_RPTR_HI
+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR
+#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_HI
+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC1_RB_RPTR_ADDR_HI
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_RPTR_ADDR_LO
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_IB_CNTL
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC1_IB_RPTR
+#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC1_IB_OFFSET
+#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC1_IB_BASE_LO
+#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC1_IB_BASE_HI
+#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_IB_SIZE
+#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC1_SKIP_CNTL
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC1_CONTEXT_STATUS
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC1_DOORBELL
+#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC1_STATUS
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC1_DOORBELL_LOG
+//SDMA1_RLC1_WATERMARK
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC1_DOORBELL_OFFSET
+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC1_CSA_ADDR_LO
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_CSA_ADDR_HI
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_IB_SUB_REMAIN
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC1_PREEMPT
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC1_DUMMY_REG
+#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC1_RB_AQL_CNTL
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_RLC1_MINOR_PTR_UPDATE
+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC1_MIDCMD_DATA0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA1
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA2
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA3
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA4
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA5
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA6
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA7
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_DATA8
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC1_MIDCMD_CNTL
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC2_RB_CNTL
+#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_RLC2_RB_BASE
+#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_BASE_HI
+#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC2_RB_RPTR
+#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_RPTR_HI
+#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR
+#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR_HI
+#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC2_RB_RPTR_ADDR_HI
+#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_RPTR_ADDR_LO
+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC2_IB_CNTL
+#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC2_IB_RPTR
+#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC2_IB_OFFSET
+#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC2_IB_BASE_LO
+#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC2_IB_BASE_HI
+#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_IB_SIZE
+#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC2_SKIP_CNTL
+#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC2_CONTEXT_STATUS
+#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC2_DOORBELL
+#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC2_STATUS
+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC2_DOORBELL_LOG
+//SDMA1_RLC2_WATERMARK
+#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC2_DOORBELL_OFFSET
+#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC2_CSA_ADDR_LO
+#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC2_CSA_ADDR_HI
+#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_IB_SUB_REMAIN
+#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC2_PREEMPT
+#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC2_DUMMY_REG
+#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC2_RB_AQL_CNTL
+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_RLC2_MINOR_PTR_UPDATE
+#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC2_MIDCMD_DATA0
+#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA1
+#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA2
+#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA3
+#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA4
+#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA5
+#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA6
+#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA7
+#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_DATA8
+#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC2_MIDCMD_CNTL
+#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC3_RB_CNTL
+#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_RLC3_RB_BASE
+#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_BASE_HI
+#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC3_RB_RPTR
+#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_RPTR_HI
+#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR
+#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR_HI
+#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC3_RB_RPTR_ADDR_HI
+#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_RPTR_ADDR_LO
+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC3_IB_CNTL
+#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC3_IB_RPTR
+#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC3_IB_OFFSET
+#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC3_IB_BASE_LO
+#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC3_IB_BASE_HI
+#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_IB_SIZE
+#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC3_SKIP_CNTL
+#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC3_CONTEXT_STATUS
+#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC3_DOORBELL
+#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC3_STATUS
+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC3_DOORBELL_LOG
+//SDMA1_RLC3_WATERMARK
+#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC3_DOORBELL_OFFSET
+#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC3_CSA_ADDR_LO
+#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC3_CSA_ADDR_HI
+#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_IB_SUB_REMAIN
+#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC3_PREEMPT
+#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC3_DUMMY_REG
+#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC3_RB_AQL_CNTL
+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_RLC3_MINOR_PTR_UPDATE
+#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC3_MIDCMD_DATA0
+#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA1
+#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA2
+#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA3
+#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA4
+#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA5
+#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA6
+#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA7
+#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_DATA8
+#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC3_MIDCMD_CNTL
+#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC4_RB_CNTL
+#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_RLC4_RB_BASE
+#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_BASE_HI
+#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC4_RB_RPTR
+#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_RPTR_HI
+#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR
+#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR_HI
+#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC4_RB_RPTR_ADDR_HI
+#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_RPTR_ADDR_LO
+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC4_IB_CNTL
+#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC4_IB_RPTR
+#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC4_IB_OFFSET
+#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC4_IB_BASE_LO
+#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC4_IB_BASE_HI
+#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_IB_SIZE
+#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC4_SKIP_CNTL
+#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC4_CONTEXT_STATUS
+#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC4_DOORBELL
+#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC4_STATUS
+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC4_DOORBELL_LOG
+//SDMA1_RLC4_WATERMARK
+#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC4_DOORBELL_OFFSET
+#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC4_CSA_ADDR_LO
+#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC4_CSA_ADDR_HI
+#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_IB_SUB_REMAIN
+#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC4_PREEMPT
+#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC4_DUMMY_REG
+#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC4_RB_AQL_CNTL
+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_RLC4_MINOR_PTR_UPDATE
+#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC4_MIDCMD_DATA0
+#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA1
+#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA2
+#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA3
+#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA4
+#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA5
+#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA6
+#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA7
+#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_DATA8
+#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC4_MIDCMD_CNTL
+#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC5_RB_CNTL
+#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_RLC5_RB_BASE
+#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_BASE_HI
+#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC5_RB_RPTR
+#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_RPTR_HI
+#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR
+#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR_HI
+#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC5_RB_RPTR_ADDR_HI
+#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_RPTR_ADDR_LO
+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC5_IB_CNTL
+#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC5_IB_RPTR
+#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC5_IB_OFFSET
+#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC5_IB_BASE_LO
+#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC5_IB_BASE_HI
+#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_IB_SIZE
+#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC5_SKIP_CNTL
+#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC5_CONTEXT_STATUS
+#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC5_DOORBELL
+#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC5_STATUS
+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC5_DOORBELL_LOG
+//SDMA1_RLC5_WATERMARK
+#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC5_DOORBELL_OFFSET
+#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC5_CSA_ADDR_LO
+#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC5_CSA_ADDR_HI
+#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_IB_SUB_REMAIN
+#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC5_PREEMPT
+#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC5_DUMMY_REG
+#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC5_RB_AQL_CNTL
+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_RLC5_MINOR_PTR_UPDATE
+#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC5_MIDCMD_DATA0
+#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA1
+#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA2
+#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA3
+#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA4
+#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA5
+#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA6
+#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA7
+#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_DATA8
+#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC5_MIDCMD_CNTL
+#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC6_RB_CNTL
+#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_RLC6_RB_BASE
+#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_BASE_HI
+#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC6_RB_RPTR
+#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_RPTR_HI
+#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR
+#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR_HI
+#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC6_RB_RPTR_ADDR_HI
+#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_RPTR_ADDR_LO
+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC6_IB_CNTL
+#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC6_IB_RPTR
+#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC6_IB_OFFSET
+#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC6_IB_BASE_LO
+#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC6_IB_BASE_HI
+#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_IB_SIZE
+#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC6_SKIP_CNTL
+#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC6_CONTEXT_STATUS
+#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC6_DOORBELL
+#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC6_STATUS
+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC6_DOORBELL_LOG
+//SDMA1_RLC6_WATERMARK
+#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC6_DOORBELL_OFFSET
+#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC6_CSA_ADDR_LO
+#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC6_CSA_ADDR_HI
+#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_IB_SUB_REMAIN
+#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC6_PREEMPT
+#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC6_DUMMY_REG
+#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC6_RB_AQL_CNTL
+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_RLC6_MINOR_PTR_UPDATE
+#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC6_MIDCMD_DATA0
+#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA1
+#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA2
+#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA3
+#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA4
+#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA5
+#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA6
+#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA7
+#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_DATA8
+#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC6_MIDCMD_CNTL
+#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+//SDMA1_RLC7_RB_CNTL
+#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f
+#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
+#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L
+#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L
+#define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L
+//SDMA1_RLC7_RB_BASE
+#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_BASE_HI
+#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
+//SDMA1_RLC7_RB_RPTR
+#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_RPTR_HI
+#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR
+#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0
+#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR_HI
+#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0
+#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR_POLL_CNTL
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//SDMA1_RLC7_RB_RPTR_ADDR_HI
+#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_RPTR_ADDR_LO
+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC7_IB_CNTL
+#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
+#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
+#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L
+//SDMA1_RLC7_IB_RPTR
+#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC7_IB_OFFSET
+#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
+//SDMA1_RLC7_IB_BASE_LO
+#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
+//SDMA1_RLC7_IB_BASE_HI
+#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_IB_SIZE
+#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL
+//SDMA1_RLC7_SKIP_CNTL
+#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
+//SDMA1_RLC7_CONTEXT_STATUS
+#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
+#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L
+#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
+#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
+//SDMA1_RLC7_DOORBELL
+#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L
+#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L
+//SDMA1_RLC7_STATUS
+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
+//SDMA1_RLC7_DOORBELL_LOG
+//SDMA1_RLC7_WATERMARK
+#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
+#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
+//SDMA1_RLC7_DOORBELL_OFFSET
+#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
+//SDMA1_RLC7_CSA_ADDR_LO
+#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC7_CSA_ADDR_HI
+#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_IB_SUB_REMAIN
+#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
+//SDMA1_RLC7_PREEMPT
+#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L
+//SDMA1_RLC7_DUMMY_REG
+#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI
+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO
+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_RLC7_RB_AQL_CNTL
+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
+#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
+#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10
+#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11
+#define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12
+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
+#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
+#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L
+#define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L
+#define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L
+//SDMA1_RLC7_MINOR_PTR_UPDATE
+#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
+#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
+//SDMA1_RLC7_MIDCMD_DATA0
+#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA1
+#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA2
+#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA3
+#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA4
+#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA5
+#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA6
+#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA7
+#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_DATA8
+#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
+//SDMA1_RLC7_MIDCMD_CNTL
+#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
+#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
+#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
+#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
+
+
+// addressBlock: gc_grbmdec
+//GRBM_CNTL
+#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
+#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
+#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
+//GRBM_SKEW_CNTL
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
+#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
+#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
+//GRBM_STATUS2
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
+#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
+#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
+#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
+#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
+#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
+#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
+#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
+#define GRBM_STATUS2__SDMA_BUSY__SHIFT 0x15
+#define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT 0x16
+#define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x17
+#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
+#define GRBM_STATUS2__TCP_BUSY__SHIFT 0x19
+#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
+#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
+#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
+#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
+#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
+#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
+#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
+#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
+#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
+#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
+#define GRBM_STATUS2__SDMA_BUSY_MASK 0x00200000L
+#define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK 0x00400000L
+#define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x00800000L
+#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
+#define GRBM_STATUS2__TCP_BUSY_MASK 0x02000000L
+#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
+#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
+#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
+//GRBM_PWR_CNTL
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
+#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
+#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
+#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
+#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
+//GRBM_STATUS
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
+#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
+#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
+#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
+#define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT 0x10
+#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
+#define GRBM_STATUS__GE_BUSY__SHIFT 0x15
+#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
+#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
+#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
+#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
+#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
+#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
+#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
+#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
+#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
+#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
+#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
+#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
+#define GRBM_STATUS__GE_BUSY_NO_DMA_MASK 0x00010000L
+#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
+#define GRBM_STATUS__GE_BUSY_MASK 0x00200000L
+#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
+#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
+#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
+#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
+#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
+#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
+//GRBM_STATUS_SE0
+#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT 0x3
+#define GRBM_STATUS_SE0__TCP_BUSY__SHIFT 0x4
+#define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT 0x5
+#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE0__UTCL1_BUSY_MASK 0x00000008L
+#define GRBM_STATUS_SE0__TCP_BUSY_MASK 0x00000010L
+#define GRBM_STATUS_SE0__GL1CC_BUSY_MASK 0x00000020L
+#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
+//GRBM_STATUS_SE1
+#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT 0x3
+#define GRBM_STATUS_SE1__TCP_BUSY__SHIFT 0x4
+#define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT 0x5
+#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE1__UTCL1_BUSY_MASK 0x00000008L
+#define GRBM_STATUS_SE1__TCP_BUSY_MASK 0x00000010L
+#define GRBM_STATUS_SE1__GL1CC_BUSY_MASK 0x00000020L
+#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
+//GRBM_STATUS3
+#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT 0x5
+#define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING__SHIFT 0x6
+#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT 0x7
+#define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS3__MESPIPE2_RQ_PENDING__SHIFT 0xa
+#define GRBM_STATUS3__MESPIPE3_RQ_PENDING__SHIFT 0xb
+#define GRBM_STATUS3__PH_BUSY__SHIFT 0xd
+#define GRBM_STATUS3__CH_BUSY__SHIFT 0xe
+#define GRBM_STATUS3__GL2CC_BUSY__SHIFT 0xf
+#define GRBM_STATUS3__GL1CC_BUSY__SHIFT 0x10
+#define GRBM_STATUS3__GUS_LINK_BUSY__SHIFT 0x1c
+#define GRBM_STATUS3__GUS_BUSY__SHIFT 0x1d
+#define GRBM_STATUS3__UTCL1_BUSY__SHIFT 0x1e
+#define GRBM_STATUS3__PMM_BUSY__SHIFT 0x1f
+#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK 0x00000020L
+#define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING_MASK 0x00000040L
+#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK 0x00000080L
+#define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK 0x00000100L
+#define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK 0x00000200L
+#define GRBM_STATUS3__MESPIPE2_RQ_PENDING_MASK 0x00000400L
+#define GRBM_STATUS3__MESPIPE3_RQ_PENDING_MASK 0x00000800L
+#define GRBM_STATUS3__PH_BUSY_MASK 0x00002000L
+#define GRBM_STATUS3__CH_BUSY_MASK 0x00004000L
+#define GRBM_STATUS3__GL2CC_BUSY_MASK 0x00008000L
+#define GRBM_STATUS3__GL1CC_BUSY_MASK 0x00010000L
+#define GRBM_STATUS3__GUS_LINK_BUSY_MASK 0x10000000L
+#define GRBM_STATUS3__GUS_BUSY_MASK 0x20000000L
+#define GRBM_STATUS3__UTCL1_BUSY_MASK 0x40000000L
+#define GRBM_STATUS3__PMM_BUSY_MASK 0x80000000L
+//GRBM_SOFT_RESET
+#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
+#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15
+#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
+#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT 0x17
+#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x18
+#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
+#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L
+#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
+#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK 0x00800000L
+#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x01000000L
+//GRBM_GFX_CLKEN_CNTL
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
+//GRBM_WAIT_IDLE_CLOCKS
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
+//GRBM_STATUS_SE2
+#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT 0x3
+#define GRBM_STATUS_SE2__TCP_BUSY__SHIFT 0x4
+#define GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT 0x5
+#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE2__UTCL1_BUSY_MASK 0x00000008L
+#define GRBM_STATUS_SE2__TCP_BUSY_MASK 0x00000010L
+#define GRBM_STATUS_SE2__GL1CC_BUSY_MASK 0x00000020L
+#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
+//GRBM_STATUS_SE3
+#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT 0x3
+#define GRBM_STATUS_SE3__TCP_BUSY__SHIFT 0x4
+#define GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT 0x5
+#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
+#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
+#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
+#define GRBM_STATUS_SE3__UTCL1_BUSY_MASK 0x00000008L
+#define GRBM_STATUS_SE3__TCP_BUSY_MASK 0x00000010L
+#define GRBM_STATUS_SE3__GL1CC_BUSY_MASK 0x00000020L
+#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
+#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
+#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
+#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
+#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
+#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
+#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
+#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
+#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
+//GRBM_PM_CNTL
+#define GRBM_PM_CNTL__PM_READY__SHIFT 0x0
+#define GRBM_PM_CNTL__PM_START__SHIFT 0x10
+#define GRBM_PM_CNTL__PM_READY_MASK 0x00000001L
+#define GRBM_PM_CNTL__PM_START_MASK 0x00010000L
+//GRBM_READ_ERROR
+#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
+#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
+#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
+#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
+#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
+#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
+//GRBM_READ_ERROR2
+#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
+#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
+//GRBM_INT_CNTL
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
+//GRBM_TRAP_OP
+#define GRBM_TRAP_OP__RW__SHIFT 0x0
+#define GRBM_TRAP_OP__RW_MASK 0x00000001L
+//GRBM_TRAP_ADDR
+#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
+#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
+//GRBM_TRAP_ADDR_MSK
+#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
+#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
+//GRBM_TRAP_WD
+#define GRBM_TRAP_WD__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
+//GRBM_TRAP_WD_MSK
+#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
+//GRBM_DSM_BYPASS
+#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
+#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
+#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L
+#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L
+//GRBM_WRITE_ERROR
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
+#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
+#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
+#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
+#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
+#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
+#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
+#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
+#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
+#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000007E0L
+#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
+#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
+#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
+#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
+#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
+//GRBM_IOV_ERROR
+#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2
+#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14
+#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a
+#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b
+#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f
+#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL
+#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L
+#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L
+#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L
+#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L
+//GRBM_CHIP_REVISION
+#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
+#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
+//GRBM_GFX_CNTL
+#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
+#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
+#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
+#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
+#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
+#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
+#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
+#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
+//GRBM_IH_CREDIT
+#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
+#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
+//GRBM_PWR_CNTL2
+#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
+#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
+#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
+#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
+//GRBM_UTCL2_INVAL_RANGE_START
+#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
+#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
+//GRBM_UTCL2_INVAL_RANGE_END
+#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
+#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
+//GRBM_IOV_READ_ERROR
+#define GRBM_IOV_READ_ERROR__IOV_ADDR__SHIFT 0x2
+#define GRBM_IOV_READ_ERROR__IOV_VFID__SHIFT 0x14
+#define GRBM_IOV_READ_ERROR__IOV_VF__SHIFT 0x1a
+#define GRBM_IOV_READ_ERROR__IOV_OP__SHIFT 0x1b
+#define GRBM_IOV_READ_ERROR__IOV_ERROR__SHIFT 0x1f
+#define GRBM_IOV_READ_ERROR__IOV_ADDR_MASK 0x000FFFFCL
+#define GRBM_IOV_READ_ERROR__IOV_VFID_MASK 0x03F00000L
+#define GRBM_IOV_READ_ERROR__IOV_VF_MASK 0x04000000L
+#define GRBM_IOV_READ_ERROR__IOV_OP_MASK 0x08000000L
+#define GRBM_IOV_READ_ERROR__IOV_ERROR_MASK 0x80000000L
+//GRBM_FENCE_RANGE0
+#define GRBM_FENCE_RANGE0__START__SHIFT 0x0
+#define GRBM_FENCE_RANGE0__END__SHIFT 0x10
+#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL
+#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L
+//GRBM_FENCE_RANGE1
+#define GRBM_FENCE_RANGE1__START__SHIFT 0x0
+#define GRBM_FENCE_RANGE1__END__SHIFT 0x10
+#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL
+#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L
+//GRBM_NOWHERE
+#define GRBM_NOWHERE__DATA__SHIFT 0x0
+#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG0
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG1
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG2
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG3
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG4
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG5
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG6
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
+//GRBM_SCRATCH_REG7
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_cpdec
+//CP_CPC_STATUS
+#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
+#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
+#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
+#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
+#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
+#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
+#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
+#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
+#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
+#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
+#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
+#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
+#define CP_CPC_STATUS__GCRIU_BUSY__SHIFT 0xf
+#define CP_CPC_STATUS__MES_BUSY__SHIFT 0x10
+#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11
+#define CP_CPC_STATUS__RCIU3_BUSY__SHIFT 0x12
+#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13
+#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
+#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
+#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
+#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
+#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
+#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
+#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
+#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
+#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
+#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
+#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
+#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
+#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
+#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
+#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
+#define CP_CPC_STATUS__GCRIU_BUSY_MASK 0x00008000L
+#define CP_CPC_STATUS__MES_BUSY_MASK 0x00010000L
+#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L
+#define CP_CPC_STATUS__RCIU3_BUSY_MASK 0x00040000L
+#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L
+#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
+#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
+#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
+//CP_CPC_BUSY_STAT
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
+//CP_CPC_STALLED_STAT1
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
+#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
+#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
+#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
+#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
+#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L
+//CP_CPF_STATUS
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
+#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
+#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
+#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
+#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
+#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
+#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
+#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
+#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
+#define CP_CPF_STATUS__RCIU_BUSY__SHIFT 0x12
+#define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT 0x13
+#define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT 0x14
+#define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT 0x15
+#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT 0x16
+#define CP_CPF_STATUS__GCRIU_BUSY__SHIFT 0x17
+#define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT 0x18
+#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
+#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
+#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
+#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
+#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
+#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
+#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
+#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
+#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
+#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
+#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
+#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
+#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
+#define CP_CPF_STATUS__RCIU_BUSY_MASK 0x00040000L
+#define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK 0x00080000L
+#define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK 0x00100000L
+#define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK 0x00200000L
+#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK 0x00400000L
+#define CP_CPF_STATUS__GCRIU_BUSY_MASK 0x00800000L
+#define CP_CPF_STATUS__MES_HQD_BUSY_MASK 0x01000000L
+#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
+#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
+#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
+#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
+//CP_CPF_BUSY_STAT
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
+#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT 0x9
+#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
+#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK 0x00000200L
+#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK 0x00000400L
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
+//CP_CPF_STALLED_STAT1
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
+#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
+#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
+#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
+#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT 0xc
+#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT 0xd
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
+#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
+#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
+#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
+#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
+#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK 0x00001000L
+#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK 0x00002000L
+//CP_CPC_BUSY_STAT2
+#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0
+#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2
+#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3
+#define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7
+#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8
+#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa
+#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb
+#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc
+#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd
+#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L
+#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L
+#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L
+#define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L
+#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L
+#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L
+#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L
+#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L
+#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L
+//CP_CPC_GRBM_FREE_COUNT
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
+//CP_MEC_CNTL
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
+#define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT 0x16
+#define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT 0x17
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x1b
+#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
+#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
+#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
+#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
+#define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK 0x00400000L
+#define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK 0x00800000L
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x08000000L
+#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
+#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
+#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
+#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
+//CP_MEC_ME1_HEADER_DUMP
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_MEC_ME2_HEADER_DUMP
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_CPC_SCRATCH_INDEX
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L
+//CP_CPC_SCRATCH_DATA
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
+//CP_CPF_GRBM_FREE_COUNT
+#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
+//CP_CPF_BUSY_STAT2
+#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT 0xc
+#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
+#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT 0x11
+#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT 0x12
+#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
+#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT 0x17
+#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
+#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT 0x1b
+#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT 0x1e
+#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK 0x00001000L
+#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
+#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK 0x00020000L
+#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
+#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
+#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
+#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
+#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK 0x08000000L
+#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK 0x40000000L
+//CP_CPC_HALT_HYST_COUNT
+#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
+#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
+//CP_CE_COMPARE_COUNT
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
+//CP_CE_DE_COUNT
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_DE_CE_COUNT
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_DE_LAST_INVAL_COUNT
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
+//CP_DE_DE_COUNT
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_STALLED_STAT3
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
+#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
+#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT 0x15
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
+#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
+#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
+#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK 0x00200000L
+//CP_STALLED_STAT1
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
+//CP_STALLED_STAT2
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
+#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT 0x6
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
+#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK 0x00000040L
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
+//CP_BUSY_STAT
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
+#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
+#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
+#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
+#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
+#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
+#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
+#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
+#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
+#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
+#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
+#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
+#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
+#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
+#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
+#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
+#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
+#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
+#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
+//CP_STAT
+#define CP_STAT__ROQ_DB_BUSY__SHIFT 0x5
+#define CP_STAT__ROQ_CE_DB_BUSY__SHIFT 0x6
+#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
+#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
+#define CP_STAT__DC_BUSY__SHIFT 0xd
+#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
+#define CP_STAT__PFP_BUSY__SHIFT 0xf
+#define CP_STAT__MEQ_BUSY__SHIFT 0x10
+#define CP_STAT__ME_BUSY__SHIFT 0x11
+#define CP_STAT__QUERY_BUSY__SHIFT 0x12
+#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
+#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
+#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
+#define CP_STAT__DMA_BUSY__SHIFT 0x16
+#define CP_STAT__RCIU_BUSY__SHIFT 0x17
+#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
+#define CP_STAT__GCRIU_BUSY__SHIFT 0x19
+#define CP_STAT__CE_BUSY__SHIFT 0x1a
+#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
+#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
+#define CP_STAT__CP_BUSY__SHIFT 0x1f
+#define CP_STAT__ROQ_DB_BUSY_MASK 0x00000020L
+#define CP_STAT__ROQ_CE_DB_BUSY_MASK 0x00000040L
+#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
+#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
+#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
+#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
+#define CP_STAT__DC_BUSY_MASK 0x00002000L
+#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
+#define CP_STAT__PFP_BUSY_MASK 0x00008000L
+#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
+#define CP_STAT__ME_BUSY_MASK 0x00020000L
+#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
+#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
+#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
+#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
+#define CP_STAT__DMA_BUSY_MASK 0x00400000L
+#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
+#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
+#define CP_STAT__GCRIU_BUSY_MASK 0x02000000L
+#define CP_STAT__CE_BUSY_MASK 0x04000000L
+#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
+#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
+#define CP_STAT__CP_BUSY_MASK 0x80000000L
+//CP_ME_HEADER_DUMP
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_PFP_HEADER_DUMP
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_GRBM_FREE_COUNT
+#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
+//CP_CE_HEADER_DUMP
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_PFP_INSTR_PNTR
+#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_ME_INSTR_PNTR
+#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_CE_INSTR_PNTR
+#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_MEC1_INSTR_PNTR
+#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_MEC2_INSTR_PNTR
+#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
+//CP_CSF_STAT
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
+//CP_ME_CNTL
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
+#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
+#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
+#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
+#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
+#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
+#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
+#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
+#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
+#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
+#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
+#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
+#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
+#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
+#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
+#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
+#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
+#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
+#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
+#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
+#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
+#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
+#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
+#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
+#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
+//CP_CNTX_STAT
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
+//CP_ME_PREEMPTION
+#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
+#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
+//CP_ROQ_THRESHOLDS
+#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
+#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
+#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
+#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
+//CP_MEQ_STQ_THRESHOLD
+#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
+#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
+//CP_RB2_RPTR
+#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB1_RPTR
+#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB0_RPTR
+#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB_RPTR
+#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_RB_WPTR_DELAY
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
+//CP_RB_WPTR_POLL_CNTL
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//CP_ROQ1_THRESHOLDS
+#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x14
+#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000003FFL
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x000FFC00L
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0x3FF00000L
+//CP_ROQ2_THRESHOLDS
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x0
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x000003FFL
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x000FFC00L
+//CP_STQ_THRESHOLDS
+#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
+#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
+#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
+#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
+#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
+#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
+//CP_QUEUE_THRESHOLDS
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
+//CP_MEQ_THRESHOLDS
+#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
+#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
+#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
+#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
+//CP_ROQ_AVAIL
+#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
+#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x00000FFFL
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x0FFF0000L
+//CP_STQ_AVAIL
+#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
+#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
+//CP_ROQ2_AVAIL
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
+#define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT 0x10
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x00000FFFL
+#define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK 0x0FFF0000L
+//CP_MEQ_AVAIL
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
+//CP_CMD_INDEX
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
+#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
+#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
+#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
+//CP_CMD_DATA
+#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
+#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
+//CP_ROQ_RB_STAT
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x00000FFFL
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x0FFF0000L
+//CP_ROQ_IB1_STAT
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x00000FFFL
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x0FFF0000L
+//CP_ROQ_IB2_STAT
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x00000FFFL
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x0FFF0000L
+//CP_STQ_STAT
+#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
+#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
+//CP_STQ_WR_STAT
+#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
+#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
+//CP_MEQ_STAT
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
+#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
+#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
+//CP_CEQ1_AVAIL
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x00000FFFL
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x0FFF0000L
+//CP_CEQ2_AVAIL
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
+#define CP_CEQ2_AVAIL__CEQ_CNT_DB__SHIFT 0x10
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x00000FFFL
+#define CP_CEQ2_AVAIL__CEQ_CNT_DB_MASK 0x0FFF0000L
+//CP_CE_ROQ_RB_STAT
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x00000FFFL
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x0FFF0000L
+//CP_CE_ROQ_IB1_STAT
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x00000FFFL
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x0FFF0000L
+//CP_CE_ROQ_IB2_STAT
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x00000FFFL
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x0FFF0000L
+//CP_CE_ROQ_DB_STAT
+#define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB__SHIFT 0x0
+#define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB__SHIFT 0x10
+#define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB_MASK 0x00000FFFL
+#define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB_MASK 0x0FFF0000L
+//CP_ROQ3_THRESHOLDS
+#define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT 0x0
+#define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa
+#define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK 0x000003FFL
+#define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK 0x000FFC00L
+//CP_ROQ_DB_STAT
+#define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT 0x0
+#define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT 0x10
+#define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK 0x00000FFFL
+#define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK 0x0FFF0000L
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
+
+
+// addressBlock: gc_padec
+//VGT_VTX_VECT_EJECT_REG
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x000003FFL
+//VGT_DMA_DATA_FIFO_DEPTH
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000003FFL
+//VGT_DMA_REQ_FIFO_DEPTH
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
+//VGT_DRAW_INIT_FIFO_DEPTH
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
+//VGT_LAST_COPY_STATE
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
+//VGT_CACHE_INVALIDATION
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
+#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
+#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
+#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
+#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
+#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
+#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
+//VGT_ESGS_RING_SIZE
+#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
+//VGT_GSVS_RING_SIZE
+#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
+//VGT_FIFO_DEPTHS
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
+#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
+#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x16
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x17
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
+#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
+#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0x00400000L
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x1F800000L
+//VGT_GS_VERTEX_REUSE
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
+//VGT_MC_LAT_CNTL
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
+//IA_UTCL1_STATUS_2
+#define IA_UTCL1_STATUS_2__IA_BUSY__SHIFT 0x0
+#define IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT 0x1
+#define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT 0x2
+#define IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT 0x3
+#define IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT 0x4
+#define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT 0x5
+#define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT 0x6
+#define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT 0x7
+#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT 0x8
+#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT 0x10
+#define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT 0x18
+#define IA_UTCL1_STATUS_2__IA_BUSY_MASK 0x00000001L
+#define IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK 0x00000002L
+#define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK 0x00000004L
+#define IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK 0x00000008L
+#define IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK 0x00000010L
+#define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK 0x00000020L
+#define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK 0x00000040L
+#define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK 0x00000080L
+#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK 0x00003F00L
+#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK 0x003F0000L
+#define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK 0x3F000000L
+//VGT_CNTL_STATUS
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
+#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
+#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
+#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
+#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
+#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
+#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
+#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
+#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
+#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
+#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
+//WD_CNTL_STATUS
+#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
+#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
+#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
+#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
+//CC_GC_PRIM_CONFIG
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
+//GC_USER_PRIM_CONFIG
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
+//WD_QOS
+#define WD_QOS__DRAW_STALL__SHIFT 0x0
+#define WD_QOS__DRAW_STALL_MASK 0x00000001L
+//WD_UTCL1_CNTL
+#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d
+#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L
+//WD_UTCL1_STATUS
+#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//GE_PC_CNTL
+#define GE_PC_CNTL__PC_SIZE__SHIFT 0x0
+#define GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC__SHIFT 0x10
+#define GE_PC_CNTL__PC_SIZE_MASK 0x0000FFFFL
+#define GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC_MASK 0x00010000L
+//IA_UTCL1_CNTL
+#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d
+#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L
+//IA_UTCL1_STATUS
+#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//GE_FAST_CLKS
+#define GE_FAST_CLKS__HYSTERESIS__SHIFT 0x0
+#define GE_FAST_CLKS__LOCK__SHIFT 0x1e
+#define GE_FAST_CLKS__FORCE_FAST_CLK__SHIFT 0x1f
+#define GE_FAST_CLKS__HYSTERESIS_MASK 0x3FFFFFFFL
+#define GE_FAST_CLKS__LOCK_MASK 0x40000000L
+#define GE_FAST_CLKS__FORCE_FAST_CLK_MASK 0x80000000L
+//VGT_TF_RING_SIZE
+#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
+#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL
+//VGT_SYS_CONFIG
+#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
+#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
+//GE_PRIV_CONTROL
+#define GE_PRIV_CONTROL__DISCARD_LEGACY__SHIFT 0x0
+#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT 0x1
+#define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT 0xa
+#define GE_PRIV_CONTROL__DISCARD_LEGACY_MASK 0x00000001L
+#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK 0x000003FEL
+#define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK 0x00000400L
+//GE_STATUS
+#define GE_STATUS__PERFCOUNTER_STATUS__SHIFT 0x0
+#define GE_STATUS__THREAD_TRACE_STATUS__SHIFT 0x1
+#define GE_STATUS__PERFCOUNTER_STATUS_MASK 0x00000001L
+#define GE_STATUS__THREAD_TRACE_STATUS_MASK 0x00000002L
+//VGT_VS_MAX_WAVE_ID
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+//VGT_GS_MAX_WAVE_ID
+#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+//CC_GC_SHADER_ARRAY_CONFIG_GEN0
+#define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU__SHIFT 0x10
+#define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU_MASK 0x03FF0000L
+//VGT_HS_OFFCHIP_PARAM
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L
+//GFX_PIPE_CONTROL
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
+#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
+#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
+//VGT_TF_MEMORY_BASE
+#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
+#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL
+//CC_GC_SHADER_ARRAY_CONFIG
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L
+//GC_USER_SHADER_ARRAY_CONFIG
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L
+//VGT_DMA_PRIMITIVE_TYPE
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
+//VGT_DMA_CONTROL
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
+#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
+#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
+//VGT_DMA_LS_HS_CONFIG
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
+//VGT_STRMOUT_DELAY
+#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
+#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
+//WD_BUF_RESOURCE_1
+#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
+#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
+#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
+#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
+//WD_BUF_RESOURCE_2
+#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
+#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
+#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
+#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
+#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
+#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
+//VGT_TF_MEMORY_BASE_HI
+#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0
+#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL
+//PA_CL_CNTL_STATUS
+#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
+#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
+#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
+#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
+#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
+#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L
+//PA_CL_ENHANCE
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
+#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
+#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
+#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
+#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
+#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
+#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
+#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
+#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11
+#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12
+#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13
+#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14
+#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15
+#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT 0x16
+#define PA_CL_ENHANCE__EN_32BIT_OBJPRIMID__SHIFT 0x17
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
+#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
+#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
+#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
+#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
+#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
+#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
+#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
+#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L
+#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L
+#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L
+#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L
+#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L
+#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK 0x00400000L
+#define PA_CL_ENHANCE__EN_32BIT_OBJPRIMID_MASK 0x00800000L
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
+//PA_SU_CNTL_STATUS
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
+//PA_SC_FIFO_DEPTH_CNTL
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
+//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
+//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
+//PA_SC_TRAP_SCREEN_HV_LOCK
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
+//PA_SC_FORCE_EOV_MAX_CNTS
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
+//PA_SC_BINNER_EVENT_CNTL_0
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
+//PA_SC_BINNER_EVENT_CNTL_1
+#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
+//PA_SC_BINNER_EVENT_CNTL_2
+#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
+//PA_SC_BINNER_EVENT_CNTL_3
+#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
+#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
+#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT 0x4
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT 0xc
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
+#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
+#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
+#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT 0x1e
+#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
+#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
+#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK 0x00000030L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK 0x00003000L
+#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
+#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
+#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
+#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
+#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
+#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK 0xC0000000L
+//PA_SC_BINNER_TIMEOUT_COUNTER
+#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
+//PA_SC_BINNER_PERF_CNTL_0
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
+#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
+#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
+//PA_SC_BINNER_PERF_CNTL_1
+#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
+#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
+#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
+//PA_SC_BINNER_PERF_CNTL_2
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
+#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
+//PA_SC_BINNER_PERF_CNTL_3
+#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
+#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
+//PA_SC_ENHANCE_2
+#define PA_SC_ENHANCE_2__ECO_SPARE0__SHIFT 0x0
+#define PA_SC_ENHANCE_2__ECO_SPARE1__SHIFT 0x1
+#define PA_SC_ENHANCE_2__ECO_SPARE2__SHIFT 0x2
+#define PA_SC_ENHANCE_2__ECO_SPARE3__SHIFT 0x3
+#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT 0x4
+#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT 0x5
+#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT 0x6
+#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT 0x7
+#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT 0x8
+#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x9
+#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa
+#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT 0xb
+#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xc
+#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT 0xd
+#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT 0xe
+#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT 0xf
+#define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT 0x10
+#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT 0x11
+#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT 0x12
+#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG__SHIFT 0x13
+#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG__SHIFT 0x14
+#define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT 0x15
+#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT 0x17
+#define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE__SHIFT 0x18
+#define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH__SHIFT 0x19
+#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT 0x1a
+#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT 0x1b
+#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x1e
+#define PA_SC_ENHANCE_2__ECO_SPARE0_MASK 0x00000001L
+#define PA_SC_ENHANCE_2__ECO_SPARE1_MASK 0x00000002L
+#define PA_SC_ENHANCE_2__ECO_SPARE2_MASK 0x00000004L
+#define PA_SC_ENHANCE_2__ECO_SPARE3_MASK 0x00000008L
+#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK 0x00000010L
+#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK 0x00000020L
+#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK 0x00000040L
+#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK 0x00000080L
+#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK 0x00000100L
+#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00000200L
+#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK 0x00000400L
+#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK 0x00000800L
+#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00001000L
+#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK 0x00002000L
+#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK 0x00004000L
+#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK 0x00008000L
+#define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK 0x00010000L
+#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK 0x00020000L
+#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK 0x00040000L
+#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG_MASK 0x00080000L
+#define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG_MASK 0x00100000L
+#define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK 0x00200000L
+#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK 0x00800000L
+#define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE_MASK 0x01000000L
+#define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH_MASK 0x02000000L
+#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK 0x04000000L
+#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK 0x38000000L
+#define PA_SC_ENHANCE_2__RSVD_MASK 0xC0000000L
+//PA_SC_ENHANCE_INTERNAL
+#define PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x0
+#define PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000001L
+//PA_SC_BINNER_CNTL_OVERRIDE
+#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT 0x0
+#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa
+#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT 0xd
+#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT 0x13
+#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT 0x1b
+#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT 0x1c
+#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK 0x00000003L
+#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L
+#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L
+#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK 0x07F80000L
+#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK 0x08000000L
+#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK 0xF0000000L
+//PA_SC_PBB_OVERRIDE_FLAG
+#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT 0x0
+#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT 0x1
+#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK 0x00000001L
+#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK 0x00000002L
+//PA_PH_INTERFACE_FIFO_SIZE
+#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT 0x0
+#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT 0x10
+#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK 0x000003FFL
+#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK 0x003F0000L
+//PA_PH_ENHANCE
+#define PA_PH_ENHANCE__ECO_SPARE0__SHIFT 0x0
+#define PA_PH_ENHANCE__ECO_SPARE1__SHIFT 0x1
+#define PA_PH_ENHANCE__ECO_SPARE2__SHIFT 0x2
+#define PA_PH_ENHANCE__ECO_SPARE3__SHIFT 0x3
+#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT 0x4
+#define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT 0x5
+#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT 0x6
+#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT 0x7
+#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT 0x9
+#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa
+#define PA_PH_ENHANCE__ECO_SPARE0_MASK 0x00000001L
+#define PA_PH_ENHANCE__ECO_SPARE1_MASK 0x00000002L
+#define PA_PH_ENHANCE__ECO_SPARE2_MASK 0x00000004L
+#define PA_PH_ENHANCE__ECO_SPARE3_MASK 0x00000008L
+#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK 0x00000010L
+#define PA_PH_ENHANCE__DISABLE_FOPKT_MASK 0x00000020L
+#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK 0x00000040L
+#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK 0x00000080L
+#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK 0x00000200L
+#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK 0x00001C00L
+//PA_SC_BC_WAVE_BREAK
+#define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0
+#define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE__SHIFT 0x10
+#define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL
+#define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L
+//PA_SC_FIFO_SIZE
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
+//PA_SC_IF_FIFO_SIZE
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
+//PA_SC_PKR_WAVE_TABLE_CNTL
+#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
+#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
+//PA_SIDEBAND_REQUEST_DELAYS
+#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
+#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
+#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
+#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
+//PA_SC_ENHANCE
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
+#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
+#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
+#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
+#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
+//PA_SC_ENHANCE_1
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
+#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
+#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
+#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
+#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
+#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
+#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
+#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
+#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
+#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
+#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
+#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
+#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
+#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
+#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
+#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
+#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17
+#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
+#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19
+#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a
+#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b
+#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c
+#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d
+#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
+#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
+#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
+#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
+#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
+#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
+#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
+#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
+#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
+#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
+#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
+#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
+#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
+#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
+#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
+#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L
+#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
+#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L
+#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L
+#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L
+#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L
+#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L
+//PA_SC_DSM_CNTL
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
+#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
+//PA_SC_TILE_STEERING_CREST_OVERRIDE
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT 0x8
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT 0x1f
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK 0x00000700L
+#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK 0x80000000L
+
+
+// addressBlock: gc_sqdec
+//SQ_CONFIG
+#define SQ_CONFIG__UNUSED__SHIFT 0x0
+#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
+#define SQ_CONFIG__VGPR_SWIZZLE_EN__SHIFT 0xc
+#define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT__SHIFT 0xd
+#define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT__SHIFT 0xf
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
+#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
+#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
+#define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT__SHIFT 0x1e
+#define SQ_CONFIG__UNUSED_MASK 0x0000007FL
+#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
+#define SQ_CONFIG__VGPR_SWIZZLE_EN_MASK 0x00001000L
+#define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT_MASK 0x00006000L
+#define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT_MASK 0x00018000L
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
+#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
+#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
+#define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT_MASK 0xC0000000L
+//SQC_CONFIG
+#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
+#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
+#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
+#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
+#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
+#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
+#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
+#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
+#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
+#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
+#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
+#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
+#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
+#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
+#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
+#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
+#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
+#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
+#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
+#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
+#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
+#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
+#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
+#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
+#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
+#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
+//LDS_CONFIG
+#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
+#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
+//SQ_RANDOM_WAVE_PRI
+#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
+#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
+#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
+#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
+#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
+#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x00FFFC00L
+//SQG_STATUS
+#define SQG_STATUS__REG_BUSY__SHIFT 0x0
+#define SQG_STATUS__REG_BUSY_MASK 0x00000001L
+//SQ_FIFO_SIZES
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
+#define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED__SHIFT 0xc
+#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT 0xe
+#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT 0x10
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000300L
+#define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED_MASK 0x00003000L
+#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK 0x0000C000L
+#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK 0x00030000L
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
+//SQ_DSM_CNTL
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
+//SQ_DSM_CNTL2
+#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
+#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
+#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
+#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
+#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
+#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
+#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
+#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
+#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
+//SQ_RUNTIME_CONFIG
+#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT 0x0
+#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK 0x00000001L
+//SH_MEM_BASES
+#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
+#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
+#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
+#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
+//SP_CONFIG
+#define SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT 0x0
+#define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT 0x2
+#define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT 0x3
+#define SP_CONFIG__TRANS_MGCG_OVERRIDE__SHIFT 0x4
+#define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT 0x5
+#define SP_CONFIG__DPMACC_MGCG_OVERRIDE__SHIFT 0x6
+#define SP_CONFIG__SMACC_MGCG_OVERRIDE__SHIFT 0x7
+#define SP_CONFIG__UNUSED__SHIFT 0x8
+#define SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK 0x00000003L
+#define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK 0x00000004L
+#define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK 0x00000008L
+#define SP_CONFIG__TRANS_MGCG_OVERRIDE_MASK 0x00000010L
+#define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK 0x00000020L
+#define SP_CONFIG__DPMACC_MGCG_OVERRIDE_MASK 0x00000040L
+#define SP_CONFIG__SMACC_MGCG_OVERRIDE_MASK 0x00000080L
+#define SP_CONFIG__UNUSED_MASK 0x00000100L
+//SQ_ARB_CONFIG
+#define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT 0x0
+#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT 0x4
+#define SQ_ARB_CONFIG__DISABLE_SECOND_TRY__SHIFT 0x8
+#define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK 0x00000003L
+#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK 0x00000030L
+#define SQ_ARB_CONFIG__DISABLE_SECOND_TRY_MASK 0x00000100L
+//SH_MEM_CONFIG
+#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
+#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2
+#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x4
+#define SH_MEM_CONFIG__RETRY_MODE__SHIFT 0xc
+#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT 0xe
+#define SH_MEM_CONFIG__NO_PREFETCH_ACROSS_PAGE__SHIFT 0x10
+#define SH_MEM_CONFIG__ILLEGAL_INST_CHECK_DISABLE__SHIFT 0x11
+#define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT 0x12
+#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
+#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x0000000CL
+#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0x00000070L
+#define SH_MEM_CONFIG__RETRY_MODE_MASK 0x00003000L
+#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK 0x0000C000L
+#define SH_MEM_CONFIG__NO_PREFETCH_ACROSS_PAGE_MASK 0x00010000L
+#define SH_MEM_CONFIG__ILLEGAL_INST_CHECK_DISABLE_MASK 0x00020000L
+#define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK 0x00040000L
+//CC_GC_SHADER_RATE_CONFIG
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
+//GC_USER_SHADER_RATE_CONFIG
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
+//SQ_INTERRUPT_AUTO_MASK
+#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
+#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
+//SQ_INTERRUPT_MSG_CTRL
+#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
+#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
+//SQG_UTCL0_CNTL1
+#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define SQG_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define SQG_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3
+#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define SQG_UTCL0_CNTL1__CLIENTID__SHIFT 0x7
+#define SQG_UTCL0_CNTL1__RESERVED__SHIFT 0x10
+#define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define SQG_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define SQG_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define SQG_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define SQG_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L
+#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define SQG_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define SQG_UTCL0_CNTL1__RESERVED_MASK 0x00010000L
+#define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define SQG_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define SQG_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//SQG_UTCL0_CNTL2
+#define SQG_UTCL0_CNTL2__SPARE__SHIFT 0x0
+#define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
+#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define SQG_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa
+#define SQG_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb
+#define SQG_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define SQG_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define SQG_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10
+#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
+#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
+#define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ__SHIFT 0x19
+#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define SQG_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b
+#define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c
+#define SQG_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d
+#define SQG_UTCL0_CNTL2__RESERVED__SHIFT 0x1e
+#define SQG_UTCL0_CNTL2__SPARE_MASK 0x000000FFL
+#define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
+#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define SQG_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L
+#define SQG_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L
+#define SQG_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define SQG_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define SQG_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
+#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
+#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
+#define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ_MASK 0x02000000L
+#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+#define SQG_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L
+#define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L
+#define SQG_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L
+#define SQG_UTCL0_CNTL2__RESERVED_MASK 0xC0000000L
+//SQG_UTCL0_STATUS
+#define SQG_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define SQG_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define SQG_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2
+#define SQG_UTCL0_STATUS__RESERVED__SHIFT 0x3
+#define SQG_UTCL0_STATUS__UNUSED__SHIFT 0x8
+#define SQG_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define SQG_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define SQG_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define SQG_UTCL0_STATUS__RESERVED_MASK 0x000000F8L
+#define SQG_UTCL0_STATUS__UNUSED_MASK 0xFFFFFF00L
+//SQG_CONFIG
+#define SQG_CONFIG__UTCL0_PREFETCH_PAGE__SHIFT 0x0
+#define SQG_CONFIG__UTCL0_RETRY_TIMER__SHIFT 0x4
+#define SQG_CONFIG__UTCL0_PREFETCH_PAGE_MASK 0x0000000FL
+#define SQG_CONFIG__UTCL0_RETRY_TIMER_MASK 0x000007F0L
+//SQ_SHADER_TBA_LO
+#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//SQ_SHADER_TBA_HI
+#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT 0x1f
+#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
+#define SQ_SHADER_TBA_HI__TRAP_EN_MASK 0x80000000L
+//SQ_SHADER_TMA_LO
+#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//SQ_SHADER_TMA_HI
+#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
+//SQ_WATCH0_ADDR_H
+#define SQ_WATCH0_ADDR_H__ADDR__SHIFT 0x0
+#define SQ_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL
+//SQ_WATCH0_ADDR_L
+#define SQ_WATCH0_ADDR_L__ADDR__SHIFT 0x6
+#define SQ_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//SQ_WATCH0_CNTL
+#define SQ_WATCH0_CNTL__MASK__SHIFT 0x0
+#define SQ_WATCH0_CNTL__VMID__SHIFT 0x18
+#define SQ_WATCH0_CNTL__MODE__SHIFT 0x1d
+#define SQ_WATCH0_CNTL__VALID__SHIFT 0x1f
+#define SQ_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL
+#define SQ_WATCH0_CNTL__VMID_MASK 0x0F000000L
+#define SQ_WATCH0_CNTL__MODE_MASK 0x60000000L
+#define SQ_WATCH0_CNTL__VALID_MASK 0x80000000L
+//SQ_WATCH1_ADDR_H
+#define SQ_WATCH1_ADDR_H__ADDR__SHIFT 0x0
+#define SQ_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL
+//SQ_WATCH1_ADDR_L
+#define SQ_WATCH1_ADDR_L__ADDR__SHIFT 0x6
+#define SQ_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//SQ_WATCH1_CNTL
+#define SQ_WATCH1_CNTL__MASK__SHIFT 0x0
+#define SQ_WATCH1_CNTL__VMID__SHIFT 0x18
+#define SQ_WATCH1_CNTL__MODE__SHIFT 0x1d
+#define SQ_WATCH1_CNTL__VALID__SHIFT 0x1f
+#define SQ_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL
+#define SQ_WATCH1_CNTL__VMID_MASK 0x0F000000L
+#define SQ_WATCH1_CNTL__MODE_MASK 0x60000000L
+#define SQ_WATCH1_CNTL__VALID_MASK 0x80000000L
+//SQ_WATCH2_ADDR_H
+#define SQ_WATCH2_ADDR_H__ADDR__SHIFT 0x0
+#define SQ_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL
+//SQ_WATCH2_ADDR_L
+#define SQ_WATCH2_ADDR_L__ADDR__SHIFT 0x6
+#define SQ_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//SQ_WATCH2_CNTL
+#define SQ_WATCH2_CNTL__MASK__SHIFT 0x0
+#define SQ_WATCH2_CNTL__VMID__SHIFT 0x18
+#define SQ_WATCH2_CNTL__MODE__SHIFT 0x1d
+#define SQ_WATCH2_CNTL__VALID__SHIFT 0x1f
+#define SQ_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL
+#define SQ_WATCH2_CNTL__VMID_MASK 0x0F000000L
+#define SQ_WATCH2_CNTL__MODE_MASK 0x60000000L
+#define SQ_WATCH2_CNTL__VALID_MASK 0x80000000L
+//SQ_WATCH3_ADDR_H
+#define SQ_WATCH3_ADDR_H__ADDR__SHIFT 0x0
+#define SQ_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL
+//SQ_WATCH3_ADDR_L
+#define SQ_WATCH3_ADDR_L__ADDR__SHIFT 0x6
+#define SQ_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L
+//SQ_WATCH3_CNTL
+#define SQ_WATCH3_CNTL__MASK__SHIFT 0x0
+#define SQ_WATCH3_CNTL__VMID__SHIFT 0x18
+#define SQ_WATCH3_CNTL__MODE__SHIFT 0x1d
+#define SQ_WATCH3_CNTL__VALID__SHIFT 0x1f
+#define SQ_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL
+#define SQ_WATCH3_CNTL__VMID_MASK 0x0F000000L
+#define SQ_WATCH3_CNTL__MODE_MASK 0x60000000L
+#define SQ_WATCH3_CNTL__VALID_MASK 0x80000000L
+//SQ_THREAD_TRACE_BUF0_BASE
+#define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT 0x0
+#define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_BUF0_SIZE
+#define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT 0x8
+#define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK 0x3FFFFF00L
+//SQ_THREAD_TRACE_BUF1_BASE
+#define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT 0x0
+#define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_BUF1_SIZE
+#define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT 0x8
+#define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK 0x0000000FL
+#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK 0x3FFFFF00L
+//SQ_THREAD_TRACE_WPTR
+#define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT 0x0
+#define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT 0x1f
+#define SQ_THREAD_TRACE_WPTR__OFFSET_MASK 0x1FFFFFFFL
+#define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK 0x80000000L
+//SQ_THREAD_TRACE_MASK
+#define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT 0x0
+#define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT 0x4
+#define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT 0x9
+#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa
+#define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK 0x00000003L
+#define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK 0x000000F0L
+#define SQ_THREAD_TRACE_MASK__SA_SEL_MASK 0x00000200L
+#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK 0x0001FC00L
+//SQ_THREAD_TRACE_TOKEN_MASK
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT 0x0
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT 0x10
+#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT 0x18
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT 0x1f
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK 0x00000FFFL
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK 0x00FF0000L
+#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK 0x03000000L
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK 0x80000000L
+//SQ_THREAD_TRACE_CTRL
+#define SQ_THREAD_TRACE_CTRL__MODE__SHIFT 0x0
+#define SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT 0x2
+#define SQ_THREAD_TRACE_CTRL__CH_PERF_EN__SHIFT 0x3
+#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT 0x4
+#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT 0x5
+#define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT 0x6
+#define SQ_THREAD_TRACE_CTRL__REG_STALL_EN__SHIFT 0x9
+#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT 0xa
+#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT 0xb
+#define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL__SHIFT 0xc
+#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT 0xd
+#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT 0xe
+#define SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT 0x10
+#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT 0x12
+#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT 0x13
+#define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL__SHIFT 0x1e
+#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT 0x1f
+#define SQ_THREAD_TRACE_CTRL__MODE_MASK 0x00000003L
+#define SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK 0x00000004L
+#define SQ_THREAD_TRACE_CTRL__CH_PERF_EN_MASK 0x00000008L
+#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK 0x00000010L
+#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK 0x00000020L
+#define SQ_THREAD_TRACE_CTRL__HIWATER_MASK 0x000001C0L
+#define SQ_THREAD_TRACE_CTRL__REG_STALL_EN_MASK 0x00000200L
+#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK 0x00000400L
+#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK 0x00000800L
+#define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL_MASK 0x00001000L
+#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK 0x00002000L
+#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK 0x0000C000L
+#define SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK 0x00030000L
+#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK 0x00040000L
+#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK 0x00080000L
+#define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL_MASK 0x40000000L
+#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK 0x80000000L
+//SQ_THREAD_TRACE_STATUS
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0xc
+#define SQ_THREAD_TRACE_STATUS__UTC_ERR__SHIFT 0x18
+#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x19
+#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW__SHIFT 0x1a
+#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL__SHIFT 0x1b
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000FFFL
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00FFF000L
+#define SQ_THREAD_TRACE_STATUS__UTC_ERR_MASK 0x01000000L
+#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x02000000L
+#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW_MASK 0x04000000L
+#define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL_MASK 0x08000000L
+//SQ_THREAD_TRACE_DROPPED_CNTR
+#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_GFX_DRAW_CNTR
+#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_GFX_MARKER_CNTR
+#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_HP3D_DRAW_CNTR
+#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_HP3D_MARKER_CNTR
+#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL
+//SQ_IND_INDEX
+#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
+#define SQ_IND_INDEX__WORKITEM_ID__SHIFT 0x5
+#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xb
+#define SQ_IND_INDEX__INDEX__SHIFT 0x10
+#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000001FL
+#define SQ_IND_INDEX__WORKITEM_ID_MASK 0x000007E0L
+#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00000800L
+#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
+//SQ_IND_DATA
+#define SQ_IND_DATA__DATA__SHIFT 0x0
+#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
+//SQ_CMD
+#define SQ_CMD__CMD__SHIFT 0x0
+#define SQ_CMD__MODE__SHIFT 0x4
+#define SQ_CMD__CHECK_VMID__SHIFT 0x7
+#define SQ_CMD__DATA__SHIFT 0x8
+#define SQ_CMD__WAVE_ID__SHIFT 0x10
+#define SQ_CMD__QUEUE_ID__SHIFT 0x18
+#define SQ_CMD__VM_ID__SHIFT 0x1c
+#define SQ_CMD__CMD_MASK 0x0000000FL
+#define SQ_CMD__MODE_MASK 0x00000070L
+#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
+#define SQ_CMD__DATA_MASK 0x00000F00L
+#define SQ_CMD__WAVE_ID_MASK 0x001F0000L
+#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
+#define SQ_CMD__VM_ID_MASK 0xF0000000L
+//SQ_TIME_HI
+#define SQ_TIME_HI__TIME__SHIFT 0x0
+#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
+//SQ_TIME_LO
+#define SQ_TIME_LO__TIME__SHIFT 0x0
+#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
+//SQ_LB_CTR_CTRL
+#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
+#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
+#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
+#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
+#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
+#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
+//SQ_LB_DATA0
+#define SQ_LB_DATA0__DATA__SHIFT 0x0
+#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_DATA1
+#define SQ_LB_DATA1__DATA__SHIFT 0x0
+#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_DATA2
+#define SQ_LB_DATA2__DATA__SHIFT 0x0
+#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_DATA3
+#define SQ_LB_DATA3__DATA__SHIFT 0x0
+#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
+//SQ_LB_CTR_SEL0
+#define SQ_LB_CTR_SEL0__SEL0__SHIFT 0x0
+#define SQ_LB_CTR_SEL0__DIV0__SHIFT 0xf
+#define SQ_LB_CTR_SEL0__SEL1__SHIFT 0x10
+#define SQ_LB_CTR_SEL0__DIV1__SHIFT 0x1f
+#define SQ_LB_CTR_SEL0__SEL0_MASK 0x000000FFL
+#define SQ_LB_CTR_SEL0__DIV0_MASK 0x00008000L
+#define SQ_LB_CTR_SEL0__SEL1_MASK 0x00FF0000L
+#define SQ_LB_CTR_SEL0__DIV1_MASK 0x80000000L
+//SQ_LB_CTR_SEL1
+#define SQ_LB_CTR_SEL1__SEL2__SHIFT 0x0
+#define SQ_LB_CTR_SEL1__DIV2__SHIFT 0xf
+#define SQ_LB_CTR_SEL1__SEL3__SHIFT 0x10
+#define SQ_LB_CTR_SEL1__DIV3__SHIFT 0x1f
+#define SQ_LB_CTR_SEL1__SEL2_MASK 0x000000FFL
+#define SQ_LB_CTR_SEL1__DIV2_MASK 0x00008000L
+#define SQ_LB_CTR_SEL1__SEL3_MASK 0x00FF0000L
+#define SQ_LB_CTR_SEL1__DIV3_MASK 0x80000000L
+//SQ_EDC_CNT
+#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0
+#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2
+#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4
+#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6
+#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8
+#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
+#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc
+#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe
+#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10
+#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12
+#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
+#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16
+#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18
+#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a
+#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L
+#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL
+#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L
+#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L
+#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L
+#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L
+#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L
+#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L
+#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L
+#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L
+#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L
+#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L
+#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L
+#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L
+//SQ_EDC_FUE_CNTL
+#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
+#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
+#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
+#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
+//SQ_WREXEC_EXEC_HI
+#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
+#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
+#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
+#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
+#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
+#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
+//SQ_WREXEC_EXEC_LO
+#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//SQC_ICACHE_UTCL0_CNTL1
+#define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3
+#define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define SQC_ICACHE_UTCL0_CNTL1__CLIENTID__SHIFT 0x7
+#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L
+#define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define SQC_ICACHE_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//SQC_ICACHE_UTCL0_CNTL2
+#define SQC_ICACHE_UTCL0_CNTL2__SPARE__SHIFT 0x0
+#define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
+#define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa
+#define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb
+#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10
+#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
+#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
+#define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b
+#define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c
+#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d
+#define SQC_ICACHE_UTCL0_CNTL2__SPARE_MASK 0x000000FFL
+#define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
+#define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L
+#define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L
+#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
+#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
+#define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
+#define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+#define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L
+#define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L
+#define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L
+//SQC_DCACHE_UTCL0_CNTL1
+#define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3
+#define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define SQC_DCACHE_UTCL0_CNTL1__CLIENTID__SHIFT 0x7
+#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L
+#define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define SQC_DCACHE_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//SQC_DCACHE_UTCL0_CNTL2
+#define SQC_DCACHE_UTCL0_CNTL2__SPARE__SHIFT 0x0
+#define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
+#define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa
+#define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb
+#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10
+#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
+#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
+#define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b
+#define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c
+#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d
+#define SQC_DCACHE_UTCL0_CNTL2__SPARE_MASK 0x000000FFL
+#define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
+#define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L
+#define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L
+#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
+#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
+#define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
+#define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+#define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L
+#define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L
+#define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L
+//SQC_ICACHE_UTCL0_STATUS
+#define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2
+#define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L
+//SQC_DCACHE_UTCL0_STATUS
+#define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2
+#define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L
+//SQC_MISC_CONFIG
+#define SQC_MISC_CONFIG__PERFTOKEN_DELAY__SHIFT 0x0
+#define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE__SHIFT 0x5
+#define SQC_MISC_CONFIG__PERFTOKEN_DELAY_MASK 0x0000001FL
+#define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE_MASK 0x00000020L
+
+
+// addressBlock: gc_shsdec
+//SX_DEBUG_1
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
+#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
+#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
+#define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd
+#define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT 0xe
+#define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT 0xf
+#define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT 0x10
+#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT 0x11
+#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x12
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
+#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
+#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
+#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
+#define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L
+#define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK 0x00004000L
+#define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK 0x00008000L
+#define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK 0x00010000L
+#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK 0x00020000L
+#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFC0000L
+//SPI_PS_MAX_WAVE_ID
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
+//SPI_START_PHASE
+#define SPI_START_PHASE__PC_X_PHASE_SE0__SHIFT 0x0
+#define SPI_START_PHASE__PC_X_PHASE_SE1__SHIFT 0x2
+#define SPI_START_PHASE__PC_X_PHASE_SE2__SHIFT 0x4
+#define SPI_START_PHASE__PC_X_PHASE_SE3__SHIFT 0x6
+#define SPI_START_PHASE__PC_X_PHASE_SE0_MASK 0x00000003L
+#define SPI_START_PHASE__PC_X_PHASE_SE1_MASK 0x0000000CL
+#define SPI_START_PHASE__PC_X_PHASE_SE2_MASK 0x00000030L
+#define SPI_START_PHASE__PC_X_PHASE_SE3_MASK 0x000000C0L
+//SPI_GFX_CNTL
+#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
+#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
+//SPI_USER_ACCUM_VMID_CNTL
+#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT 0x0
+#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK 0x0000000FL
+//SPI_CONFIG_CNTL
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
+#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c
+#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d
+#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L
+#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L
+#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L
+#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L
+//SPI_DSM_CNTL
+#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+//SPI_DSM_CNTL2
+#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x3
+#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000001F8L
+//SPI_EDC_CNT
+#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0
+#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L
+//SPI_WAVE_LIMIT_CNTL
+#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0
+#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2
+#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4
+#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6
+#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L
+#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL
+#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L
+#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L
+//SPI_CONFIG_CNTL_2
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L
+//SPI_CONFIG_CNTL_1
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x5
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
+#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe
+#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf
+#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT 0x10
+#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT 0x15
+#define SPI_CONFIG_CNTL_1__RESERVED__SHIFT 0x16
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000060L
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L
+#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L
+#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L
+#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK 0x001F0000L
+#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK 0x00200000L
+#define SPI_CONFIG_CNTL_1__RESERVED_MASK 0xFFC00000L
+//SPI_WF_LIFETIME_CNTL
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
+#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
+#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
+//SPI_WF_LIFETIME_LIMIT_0
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_1
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_2
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_3
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_4
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_5
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_6
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_7
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_8
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_LIMIT_9
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_0
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_1
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_2
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_3
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_4
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_5
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_6
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_7
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_8
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_9
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_10
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_11
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_12
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_13
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_14
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_15
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_16
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_17
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_18
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_19
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
+//SPI_WF_LIFETIME_STATUS_20
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
+//SPI_LB_CTR_CTRL
+#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
+#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
+#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
+#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
+#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
+#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
+#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
+#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
+//SPI_LB_WGP_MASK
+#define SPI_LB_WGP_MASK__WGP_MASK__SHIFT 0x0
+#define SPI_LB_WGP_MASK__WGP_MASK_MASK 0xFFFFL
+//SPI_LB_DATA_REG
+#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
+#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
+//SPI_PG_ENABLE_STATIC_WGP_MASK
+#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT 0x0
+#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK 0xFFFFL
+//SPI_GDS_CREDITS
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
+//SPI_SX_EXPORT_BUFFER_SIZES
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
+//SPI_SX_SCOREBOARD_BUFFER_SIZES
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
+//SPI_CSQ_WF_ACTIVE_STATUS
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
+//SPI_CSQ_WF_ACTIVE_COUNT_0
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_1
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_2
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_3
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_4
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_5
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_6
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L
+//SPI_CSQ_WF_ACTIVE_COUNT_7
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L
+//SPI_LB_DATA_WAVES
+#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
+#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
+#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
+#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
+//SPI_LB_DATA_PERWGP_WAVE_HSGS
+#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS__SHIFT 0x0
+#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS__SHIFT 0x10
+#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS_MASK 0x0000FFFFL
+#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS_MASK 0xFFFF0000L
+//SPI_LB_DATA_PERWGP_WAVE_VSPS
+#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS__SHIFT 0x0
+#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS__SHIFT 0x10
+#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS_MASK 0x0000FFFFL
+#define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS_MASK 0xFFFF0000L
+//SPI_LB_DATA_PERWGP_WAVE_CS
+#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE__SHIFT 0x0
+#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE_MASK 0xFFFFL
+//SPI_P0_TRAP_SCREEN_PSBA_LO
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P0_TRAP_SCREEN_PSBA_HI
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P0_TRAP_SCREEN_PSMA_LO
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P0_TRAP_SCREEN_PSMA_HI
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P0_TRAP_SCREEN_GPR_MIN
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
+//SPI_P1_TRAP_SCREEN_PSBA_LO
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P1_TRAP_SCREEN_PSBA_HI
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P1_TRAP_SCREEN_PSMA_LO
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_P1_TRAP_SCREEN_PSMA_HI
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
+//SPI_P1_TRAP_SCREEN_GPR_MIN
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
+
+
+// addressBlock: gc_tpdec
+//TD_CNTL
+#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
+#define TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP__SHIFT 0x3
+#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
+#define TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP__SHIFT 0x6
+#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
+#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
+#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
+#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
+#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
+#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
+#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
+#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
+#define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT__SHIFT 0x16
+#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
+#define TD_CNTL__ARBITER_OLDEST_PRIORITY__SHIFT 0x19
+#define TD_CNTL__DONE_SCOREBOARD_DEPTH__SHIFT 0x1a
+#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
+#define TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP_MASK 0x00000008L
+#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
+#define TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP_MASK 0x00000040L
+#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
+#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
+#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
+#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
+#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
+#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
+#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
+#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L
+#define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT_MASK 0x00400000L
+#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L
+#define TD_CNTL__ARBITER_OLDEST_PRIORITY_MASK 0x02000000L
+#define TD_CNTL__DONE_SCOREBOARD_DEPTH_MASK 0x7C000000L
+//TD_STATUS
+#define TD_STATUS__BUSY__SHIFT 0x1f
+#define TD_STATUS__BUSY_MASK 0x80000000L
+//TD_POWER_CNTL
+#define TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE__SHIFT 0x0
+#define TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE__SHIFT 0x1
+#define TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT 0x2
+#define TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY__SHIFT 0x5
+#define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT__SHIFT 0x8
+#define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON__SHIFT 0x9
+#define TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE_MASK 0x00000001L
+#define TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE_MASK 0x00000002L
+#define TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK 0x0000001CL
+#define TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY_MASK 0x000000E0L
+#define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT_MASK 0x00000100L
+#define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON_MASK 0x00000200L
+//TD_DSM_CNTL
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+//TD_DSM_CNTL2
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
+#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
+#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
+//TD_SCRATCH
+#define TD_SCRATCH__SCRATCH__SHIFT 0x0
+#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+//TA_POWER_CNTL
+#define TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT 0x0
+#define TA_POWER_CNTL__SAMPLER_CLK_EN_MODE__SHIFT 0x3
+#define TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY__SHIFT 0x10
+#define TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE__SHIFT 0x13
+#define TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK 0x00000007L
+#define TA_POWER_CNTL__SAMPLER_CLK_EN_MODE_MASK 0x00000008L
+#define TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY_MASK 0x00070000L
+#define TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE_MASK 0x00080000L
+//TA_CNTL
+#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
+#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
+#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
+#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
+#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
+#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
+//TA_CNTL_AUX
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
+#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
+#define TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT 0x4
+#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
+#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
+#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
+#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT 0x8
+#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT 0x9
+#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
+#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
+#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
+#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
+#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
+#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
+#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
+#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
+#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
+#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
+#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
+#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
+#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
+#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
+#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
+#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
+#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
+#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
+#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
+#define TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK 0x00000010L
+#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
+#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
+#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
+#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK 0x00000100L
+#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK 0x00000200L
+#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
+#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
+#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
+#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
+#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
+#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
+#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
+#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
+#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
+#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
+#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
+#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
+#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
+#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
+#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
+#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
+#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
+#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
+//TA_RESERVED_010C
+#define TA_RESERVED_010C__Unused__SHIFT 0x0
+#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
+//TA_STATUS
+#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
+#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
+#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
+#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
+#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
+#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
+#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
+#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
+#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
+#define TA_STATUS__IN_BUSY__SHIFT 0x18
+#define TA_STATUS__FG_BUSY__SHIFT 0x19
+#define TA_STATUS__LA_BUSY__SHIFT 0x1a
+#define TA_STATUS__FL_BUSY__SHIFT 0x1b
+#define TA_STATUS__TA_BUSY__SHIFT 0x1c
+#define TA_STATUS__FA_BUSY__SHIFT 0x1d
+#define TA_STATUS__AL_BUSY__SHIFT 0x1e
+#define TA_STATUS__BUSY__SHIFT 0x1f
+#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
+#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
+#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
+#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
+#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
+#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
+#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
+#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
+#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
+#define TA_STATUS__IN_BUSY_MASK 0x01000000L
+#define TA_STATUS__FG_BUSY_MASK 0x02000000L
+#define TA_STATUS__LA_BUSY_MASK 0x04000000L
+#define TA_STATUS__FL_BUSY_MASK 0x08000000L
+#define TA_STATUS__TA_BUSY_MASK 0x10000000L
+#define TA_STATUS__FA_BUSY_MASK 0x20000000L
+#define TA_STATUS__AL_BUSY_MASK 0x40000000L
+#define TA_STATUS__BUSY_MASK 0x80000000L
+//TA_SCRATCH
+#define TA_SCRATCH__SCRATCH__SHIFT 0x0
+#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_gdsdec
+//GDS_CONFIG
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
+#define GDS_CONFIG__UNUSED__SHIFT 0x9
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
+#define GDS_CONFIG__UNUSED_MASK 0xFFFFFE00L
+//GDS_CNTL_STATUS
+#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
+#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
+#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
+#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
+#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
+#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
+#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
+#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
+#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
+#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
+#define GDS_CNTL_STATUS__UNUSED__SHIFT 0xf
+#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
+#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
+#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
+#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
+#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
+#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
+#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
+#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
+#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
+#define GDS_CNTL_STATUS__UNUSED_MASK 0xFFFF8000L
+//GDS_ENHANCE
+#define GDS_ENHANCE__MISC__SHIFT 0x0
+#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
+#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
+#define GDS_ENHANCE__UNUSED__SHIFT 0x12
+#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL
+#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L
+#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L
+#define GDS_ENHANCE__UNUSED_MASK 0xFFFC0000L
+//GDS_PROTECTION_FAULT
+#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
+#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
+#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
+#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
+#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
+#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
+#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
+#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
+#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
+#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
+#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
+#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
+//GDS_VM_PROTECTION_FAULT
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
+#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
+#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
+#define GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT 0x6
+#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
+#define GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT 0xc
+#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
+#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
+#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
+#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
+#define GDS_VM_PROTECTION_FAULT__UNUSED1_MASK 0x000000C0L
+#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
+#define GDS_VM_PROTECTION_FAULT__UNUSED2_MASK 0x0000F000L
+#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
+//GDS_EDC_CNT
+#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
+#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2
+#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
+#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
+#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
+#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL
+#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
+#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
+//GDS_EDC_GRBM_CNT
+#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
+#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
+#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
+#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
+#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
+#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
+//GDS_EDC_OA_DED
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
+#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
+#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
+#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
+#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L
+//GDS_DSM_CNTL
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
+#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
+#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
+#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
+#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
+#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
+#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
+#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
+#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
+#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
+#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
+#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
+//GDS_EDC_OA_PHY_CNT
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6
+#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8
+#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L
+#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L
+#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L
+#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L
+#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L
+//GDS_EDC_OA_PIPE_CNT
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe
+#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L
+#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L
+#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L
+//GDS_DSM_CNTL2
+#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
+#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
+#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
+#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
+//GDS_WD_GDS_CSB
+#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
+#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
+#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
+#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
+
+
+// addressBlock: gc_rbdec
+//DB_DEBUG
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
+#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
+#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
+#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
+#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
+#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
+#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
+#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
+#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
+//DB_DEBUG2
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
+#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
+#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
+#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
+#define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0xf
+#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
+#define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE__SHIFT 0x14
+#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL__SHIFT 0x16
+#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW__SHIFT 0x17
+#define DB_DEBUG2__FORCE_ITERATE_256__SHIFT 0x18
+#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT 0x1a
+#define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT 0x1b
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L
+#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L
+#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L
+#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L
+#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
+#define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x00008000L
+#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
+#define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE_MASK 0x00300000L
+#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL_MASK 0x00400000L
+#define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW_MASK 0x00800000L
+#define DB_DEBUG2__FORCE_ITERATE_256_MASK 0x03000000L
+#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK 0x04000000L
+#define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK 0x08000000L
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
+//DB_DEBUG3
+#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0
+#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT 0x1
+#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
+#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT 0x10
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
+#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
+#define DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
+#define DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT 0x1e
+#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT 0x1f
+#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L
+#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK 0x00000002L
+#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L
+#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK 0x00010000L
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
+#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
+#define DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
+#define DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK 0x40000000L
+#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK 0x80000000L
+//DB_DEBUG4
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
+#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT 0x4
+#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0x5
+#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x6
+#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x7
+#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8
+#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9
+#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
+#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb
+#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0xc
+#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd
+#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe
+#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0xf
+#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT 0x10
+#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT__SHIFT 0x11
+#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT 0x12
+#define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT 0x13
+#define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING__SHIFT 0x14
+#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT 0x15
+#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT 0x16
+#define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK__SHIFT 0x17
+#define DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT 0x18
+#define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT 0x1b
+#define DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT 0x1c
+#define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW__SHIFT 0x1d
+#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT 0x1e
+#define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD__SHIFT 0x1f
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L
+#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK 0x00000010L
+#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00000020L
+#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000040L
+#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000080L
+#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L
+#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L
+#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L
+#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L
+#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00001000L
+#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L
+#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L
+#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00008000L
+#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK 0x00010000L
+#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT_MASK 0x00020000L
+#define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK 0x00040000L
+#define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK 0x00080000L
+#define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING_MASK 0x00100000L
+#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK 0x00200000L
+#define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK 0x00400000L
+#define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK_MASK 0x00800000L
+#define DB_DEBUG4__WR_MEM_BURST_CTL_MASK 0x07000000L
+#define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK 0x08000000L
+#define DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK 0x10000000L
+#define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW_MASK 0x20000000L
+#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK 0x40000000L
+#define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD_MASK 0x80000000L
+//DB_ETILE_STUTTER_CONTROL
+#define DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0
+#define DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10
+#define DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL
+#define DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L
+//DB_LTILE_STUTTER_CONTROL
+#define DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0
+#define DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10
+#define DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL
+#define DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L
+//DB_EQUAD_STUTTER_CONTROL
+#define DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0
+#define DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10
+#define DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL
+#define DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L
+//DB_LQUAD_STUTTER_CONTROL
+#define DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0
+#define DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10
+#define DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL
+#define DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L
+//DB_CREDIT_LIMIT
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L
+//DB_WATERMARKS
+#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
+#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x8
+#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x10
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x18
+#define DB_WATERMARKS__DEPTH_FREE_MASK 0x000000FFL
+#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x0000FF00L
+#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x00FF0000L
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0xFF000000L
+//DB_SUBTILE_CONTROL
+#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
+#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
+#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
+#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
+#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
+#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
+#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
+#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
+#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
+#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
+#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
+#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL
+#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
+#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L
+#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
+#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L
+#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
+#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L
+#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
+#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L
+//DB_FREE_CACHELINES
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x8
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x10
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x18
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x000000FFL
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x0000FF00L
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x00FF0000L
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0xFF000000L
+//DB_FIFO_DEPTH1
+#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x8
+#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x10
+#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x18
+#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x000000FFL
+#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x0000FF00L
+#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x00FF0000L
+#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0xFF000000L
+//DB_FIFO_DEPTH2
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x10
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x0000FF00L
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF0000L
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L
+//DB_LAST_OF_BURST_CONFIG
+#define DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT 0x0
+#define DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT 0x8
+#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT 0xb
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT 0x12
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT 0x13
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT 0x14
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT 0x15
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT 0x16
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN__SHIFT 0x17
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN__SHIFT 0x18
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN__SHIFT 0x19
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT 0x1a
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT 0x1b
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM__SHIFT 0x1c
+#define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT 0x1d
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT 0x1e
+#define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT 0x1f
+#define DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK 0x000000FFL
+#define DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK 0x00000700L
+#define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK 0x0003F800L
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK 0x00040000L
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK 0x00080000L
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK 0x00100000L
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK 0x00200000L
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK 0x00400000L
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN_MASK 0x00800000L
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN_MASK 0x01000000L
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN_MASK 0x02000000L
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK 0x04000000L
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK 0x08000000L
+#define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM_MASK 0x10000000L
+#define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK 0x20000000L
+#define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK 0x40000000L
+#define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK 0x80000000L
+//DB_RING_CONTROL
+#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
+#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L
+//DB_MEM_ARB_WATERMARKS
+#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0
+#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8
+#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10
+#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18
+#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L
+#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L
+#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L
+#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L
+//DB_FIFO_DEPTH3
+#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT 0x18
+#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK 0x000000FFL
+#define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK 0xFF000000L
+//DB_RMI_BC_GL2_CACHE_CONTROL
+#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY__SHIFT 0x0
+#define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY__SHIFT 0x2
+#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT 0x4
+#define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT 0x6
+#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY__SHIFT 0x10
+#define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY__SHIFT 0x12
+#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT 0x14
+#define DB_RMI_BC_GL2_CACHE_CONTROL__VOL__SHIFT 0x1f
+#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY_MASK 0x00000003L
+#define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY_MASK 0x0000000CL
+#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY_MASK 0x00000030L
+#define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK 0x000000C0L
+#define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY_MASK 0x00030000L
+#define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY_MASK 0x000C0000L
+#define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY_MASK 0x00300000L
+#define DB_RMI_BC_GL2_CACHE_CONTROL__VOL_MASK 0x80000000L
+//DB_EXCEPTION_CONTROL
+#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0
+#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1
+#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2
+#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT 0x3
+#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT 0x4
+#define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_A__SHIFT 0x5
+#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT 0x8
+#define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_B__SHIFT 0xc
+#define DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT 0x18
+#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L
+#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L
+#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L
+#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK 0x00000008L
+#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK 0x00000010L
+#define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_A_MASK 0x000000E0L
+#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK 0x00000F00L
+#define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_B_MASK 0x00FFF000L
+#define DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK 0x7F000000L
+//DB_DFSM_CONFIG
+#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0
+#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1
+#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2
+#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3
+#define DB_DFSM_CONFIG__SQUAD_WATERMARK__SHIFT 0x4
+#define DB_DFSM_CONFIG__CAM_WATERMARK__SHIFT 0x10
+#define DB_DFSM_CONFIG__OUTPUT_WATCHDOG__SHIFT 0x18
+#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L
+#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L
+#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L
+#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L
+#define DB_DFSM_CONFIG__SQUAD_WATERMARK_MASK 0x00003FF0L
+#define DB_DFSM_CONFIG__CAM_WATERMARK_MASK 0x00FF0000L
+#define DB_DFSM_CONFIG__OUTPUT_WATCHDOG_MASK 0xFF000000L
+//DB_DFSM_TILES_IN_FLIGHT
+#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
+#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
+//DB_DFSM_PRIMS_IN_FLIGHT
+#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
+#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
+//DB_DFSM_WATCHDOG
+#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0
+#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL
+//DB_DFSM_FLUSH_ENABLE
+#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0
+#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18
+#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c
+#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000007FFL
+#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L
+#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L
+//DB_DFSM_FLUSH_AUX_EVENT
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L
+#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L
+//DB_FGCG_SRAMS_CLK_CTRL
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT 0x0
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT 0x1
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT 0x2
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT 0x3
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT 0x4
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT 0x5
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT 0x6
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT 0x7
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT 0x8
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT 0x9
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT 0xb
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT 0xc
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT 0xd
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT 0xe
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT 0xf
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT 0x10
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT 0x11
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT 0x12
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT 0x13
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT 0x14
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT 0x15
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT 0x16
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT 0x17
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT 0x18
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT 0x19
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT 0x1a
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK 0x00000001L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK 0x00000002L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK 0x00000004L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK 0x00000008L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK 0x00000010L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK 0x00000020L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK 0x00000040L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK 0x00000080L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK 0x00000100L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK 0x00000200L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK 0x00000400L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK 0x00000800L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK 0x00001000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK 0x00002000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK 0x00004000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK 0x00008000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK 0x00010000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK 0x00020000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK 0x00040000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK 0x00080000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK 0x00100000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK 0x00200000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK 0x00400000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK 0x00800000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK 0x01000000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK 0x02000000L
+#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK 0x04000000L
+//DB_FGCG_INTERFACES_CLK_CTRL
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT 0x0
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE__SHIFT 0x1
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE__SHIFT 0x2
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT 0x3
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT 0x4
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT 0x5
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT 0x6
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK 0x00000001L
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE_MASK 0x00000002L
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE_MASK 0x00000004L
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK 0x00000008L
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK 0x00000010L
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK 0x00000020L
+#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK 0x00000040L
+//CC_RB_REDUNDANCY
+#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
+#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
+//CC_RB_BACKEND_DISABLE
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
+//GB_ADDR_CONFIG
+#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
+#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
+//GB_BACKEND_MAP
+#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
+#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL
+//GB_GPU_ID
+#define GB_GPU_ID__GPU_ID__SHIFT 0x0
+#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL
+//CC_RB_DAISY_CHAIN
+#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
+#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
+#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
+#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
+#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
+#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
+#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
+#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
+#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL
+#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L
+#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L
+#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L
+#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L
+#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L
+#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L
+#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L
+//GB_ADDR_CONFIG_READ
+#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
+#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
+#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
+#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
+#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
+#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
+#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
+#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
+//GB_TILE_MODE0
+#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE1
+#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE2
+#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE3
+#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE4
+#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE5
+#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE6
+#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE7
+#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE8
+#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE9
+#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE10
+#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE11
+#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE12
+#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE13
+#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE14
+#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE15
+#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE16
+#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE17
+#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE18
+#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE19
+#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE20
+#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE21
+#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE22
+#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE23
+#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE24
+#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE25
+#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE26
+#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE27
+#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE28
+#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE29
+#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE30
+#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_TILE_MODE31
+#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL
+#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L
+#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
+#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
+//GB_MACROTILE_MODE0
+#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE1
+#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE2
+#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE3
+#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE4
+#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE5
+#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE6
+#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE7
+#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE8
+#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE9
+#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE10
+#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE11
+#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE12
+#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE13
+#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE14
+#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L
+//GB_MACROTILE_MODE15
+#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L
+#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L
+//CB_HW_CONTROL_4
+#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2__SHIFT 0x0
+#define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2__SHIFT 0x3
+#define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD__SHIFT 0x5
+#define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING__SHIFT 0x6
+#define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING__SHIFT 0x7
+#define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING__SHIFT 0x8
+#define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE__SHIFT 0x9
+#define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE__SHIFT 0xa
+#define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0__SHIFT 0xb
+#define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY__SHIFT 0xc
+#define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS__SHIFT 0xd
+#define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH__SHIFT 0xe
+#define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT 0xf
+#define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE__SHIFT 0x10
+#define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE__SHIFT 0x11
+#define CB_HW_CONTROL_4__DISABLE_TILE_FGCG__SHIFT 0x16
+#define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG__SHIFT 0x17
+#define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH__SHIFT 0x18
+#define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2_MASK 0x00000007L
+#define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2_MASK 0x00000018L
+#define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD_MASK 0x00000020L
+#define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING_MASK 0x00000040L
+#define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING_MASK 0x00000080L
+#define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING_MASK 0x00000100L
+#define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE_MASK 0x00000200L
+#define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE_MASK 0x00000400L
+#define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0_MASK 0x00000800L
+#define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY_MASK 0x00001000L
+#define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS_MASK 0x00002000L
+#define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH_MASK 0x00004000L
+#define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK 0x00008000L
+#define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE_MASK 0x00010000L
+#define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE_MASK 0x003E0000L
+#define CB_HW_CONTROL_4__DISABLE_TILE_FGCG_MASK 0x00400000L
+#define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG_MASK 0x00800000L
+#define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH_MASK 0xFF000000L
+//CB_HW_CONTROL_3
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
+#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
+#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
+#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
+#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe
+#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf
+#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18
+#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19
+#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a
+#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b
+#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x1e
+#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC__SHIFT 0x1f
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L
+#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L
+#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L
+#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L
+#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L
+#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L
+#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L
+#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L
+#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L
+#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L
+#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L
+#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L
+#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_MASK 0x40000000L
+#define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC_MASK 0x80000000L
+//CB_HW_CONTROL
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x0
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
+#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00000001L
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
+#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
+//CB_HW_CONTROL_1
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
+#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L
+#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L
+//CB_HW_CONTROL_2
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
+#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1e
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x3F000000L
+#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xC0000000L
+//CB_DCC_CONFIG
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
+#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7
+#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1a
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L
+#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L
+#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x01FF0000L
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xFC000000L
+//CB_HW_MEM_ARBITER_RD
+#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0
+#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2
+#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16
+#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17
+#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a
+#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
+#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L
+#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL
+#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
+#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L
+#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L
+#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L
+#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
+//CB_HW_MEM_ARBITER_WR
+#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0
+#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2
+#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16
+#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17
+#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a
+#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
+#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L
+#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL
+#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
+#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L
+#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L
+#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L
+#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
+//CB_RMI_BC_GL2_CACHE_CONTROL
+#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT 0x0
+#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT 0x2
+#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT 0x4
+#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x6
+#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT 0x10
+#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT 0x12
+#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT 0x14
+#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16
+#define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT__SHIFT 0x1f
+#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK 0x00000003L
+#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK 0x0000000CL
+#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK 0x00000030L
+#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x000000C0L
+#define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK 0x00030000L
+#define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK 0x000C0000L
+#define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK 0x00300000L
+#define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L
+#define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT_MASK 0x80000000L
+//CB_STUTTER_CONTROL_CMASK_RDLAT
+#define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD__SHIFT 0x0
+#define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT__SHIFT 0x8
+#define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD_MASK 0x000000FFL
+#define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT_MASK 0x0000FF00L
+//CB_STUTTER_CONTROL_FMASK_RDLAT
+#define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD__SHIFT 0x0
+#define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT__SHIFT 0x8
+#define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD_MASK 0x000000FFL
+#define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT_MASK 0x0000FF00L
+//CB_STUTTER_CONTROL_COLOR_RDLAT
+#define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD__SHIFT 0x0
+#define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT__SHIFT 0x8
+#define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD_MASK 0x000000FFL
+#define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT_MASK 0x0000FF00L
+//CB_CACHE_EVICT_POINTS
+#define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT__SHIFT 0x0
+#define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT__SHIFT 0x8
+#define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT 0x10
+#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT 0x18
+#define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT_MASK 0x000000FFL
+#define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT_MASK 0x0000FF00L
+#define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK 0x00FF0000L
+#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK 0xFF000000L
+//GC_USER_RB_REDUNDANCY
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
+//GC_USER_RB_BACKEND_DISABLE
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
+
+
+// addressBlock: gc_gceadec2
+//GCEA_SDP_VCD_RESERVE1
+#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//GCEA_SDP_REQ_CNTL
+#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
+#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
+//GCEA_MISC
+#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
+#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
+#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
+#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
+#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
+#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
+#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
+#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
+#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
+#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
+#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
+#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
+#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
+#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
+#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
+#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
+#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
+#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
+#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
+#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
+#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
+#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
+#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
+#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
+#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
+//GCEA_LATENCY_SAMPLING
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//GCEA_PERFCOUNTER_LO
+#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//GCEA_PERFCOUNTER_HI
+#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//GCEA_PERFCOUNTER0_CFG
+#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//GCEA_PERFCOUNTER1_CFG
+#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//GCEA_PERFCOUNTER_RSLT_CNTL
+#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//GCEA_EDC_CNT
+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
+#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
+#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
+#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
+#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
+#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
+#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
+#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
+#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
+//GCEA_EDC_CNT2
+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+//GCEA_DSM_CNTL
+#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//GCEA_DSM_CNTLA
+#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//GCEA_DSM_CNTLB
+//GCEA_DSM_CNTL2
+#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//GCEA_DSM_CNTL2A
+#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//GCEA_DSM_CNTL2B
+//GCEA_GL2C_XBR_CREDITS
+#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0
+#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6
+#define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8
+#define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe
+#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10
+#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16
+#define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18
+#define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e
+#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL
+#define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L
+#define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L
+#define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L
+#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L
+#define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L
+#define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L
+#define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L
+//GCEA_GL2C_XBR_MAXBURST
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT 0x0
+#define GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT 0x4
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT 0x8
+#define GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT 0xc
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT 0x10
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT 0x13
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT 0x14
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT 0x17
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL
+#define GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK 0x000000F0L
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L
+#define GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK 0x0000F000L
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK 0x00070000L
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK 0x00080000L
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK 0x00700000L
+#define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK 0x00800000L
+//GCEA_PROBE_CNTL
+#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0
+#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5
+#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL
+#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L
+//GCEA_PROBE_MAP
+#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT 0x0
+#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT 0x1
+#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT 0x2
+#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT 0x3
+#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT 0x4
+#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT 0x5
+#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT 0x6
+#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT 0x7
+#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT 0x8
+#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT 0x9
+#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT 0xa
+#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT 0xb
+#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT 0xc
+#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT 0xd
+#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT 0xe
+#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT 0xf
+#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10
+#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK 0x00000001L
+#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK 0x00000002L
+#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK 0x00000004L
+#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK 0x00000008L
+#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK 0x00000010L
+#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK 0x00000020L
+#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK 0x00000040L
+#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK 0x00000080L
+#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK 0x00000100L
+#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK 0x00000200L
+#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK 0x00000400L
+#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK 0x00000800L
+#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK 0x00001000L
+#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK 0x00002000L
+#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK 0x00004000L
+#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK 0x00008000L
+#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L
+//GCEA_ERR_STATUS
+#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+//GCEA_MISC2
+#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
+#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
+
+
+// addressBlock: gc_spipdec2
+//SPI_PQEV_CTRL
+#define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT 0x0
+#define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa
+#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT 0x10
+#define SPI_PQEV_CTRL__SCAN_PERIOD_MASK 0x000003FFL
+#define SPI_PQEV_CTRL__QUEUE_DURATION_MASK 0x0000FC00L
+#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK 0x00FF0000L
+//SPI_SYS_COMPUTE
+#define SPI_SYS_COMPUTE__PIPE__SHIFT 0x0
+#define SPI_SYS_COMPUTE__PIPE_MASK 0x000000FFL
+//SPI_SYS_WIF_CNTL
+#define SPI_SYS_WIF_CNTL__THRESHOLD__SHIFT 0x0
+#define SPI_SYS_WIF_CNTL__THRESHOLD_MASK 0x000000FFL
+
+
+// addressBlock: gc_gceadec3
+//GCEA_DRAM_BANK_ARB
+#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT 0x0
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT 0x1
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT 0x8
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT 0xe
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE__SHIFT 0xf
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE__SHIFT 0x11
+#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK 0x00000001L
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK 0x000000FEL
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK 0x00003F00L
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK 0x00004000L
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE_MASK 0x00018000L
+#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE_MASK 0x00060000L
+//GCEA_DRAM_BANK_ARB_RFSH
+#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL__SHIFT 0x0
+#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE__SHIFT 0xc
+#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE__SHIFT 0x15
+#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB__SHIFT 0x16
+#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL_MASK 0x00000FFFL
+#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE_MASK 0x001FF000L
+#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE_MASK 0x00200000L
+#define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB_MASK 0x00400000L
+//GCEA_SDP_BACKDOOR_CMDCREDITS0
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L
+#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L
+//GCEA_SDP_BACKDOOR_CMDCREDITS1
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L
+#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L
+//GCEA_SDP_BACKDOOR_DATACREDITS0
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L
+#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L
+//GCEA_SDP_BACKDOOR_DATACREDITS1
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L
+#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L
+//GCEA_SDP_BACKDOOR_MISCCREDITS
+#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0
+#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8
+#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10
+#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17
+#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL
+#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L
+#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L
+#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L
+//GCEA_ADDRDECDRAM_ADDR_HASH_PACH
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR_MASK 0xFFFFFFFEL
+//GCEA_RRET_MEM_RESERVE
+#define GCEA_RRET_MEM_RESERVE__VC0__SHIFT 0x0
+#define GCEA_RRET_MEM_RESERVE__VC1__SHIFT 0x4
+#define GCEA_RRET_MEM_RESERVE__VC2__SHIFT 0x8
+#define GCEA_RRET_MEM_RESERVE__VC3__SHIFT 0xc
+#define GCEA_RRET_MEM_RESERVE__VC4__SHIFT 0x10
+#define GCEA_RRET_MEM_RESERVE__VC5__SHIFT 0x14
+#define GCEA_RRET_MEM_RESERVE__VC6__SHIFT 0x18
+#define GCEA_RRET_MEM_RESERVE__VC7__SHIFT 0x1c
+#define GCEA_RRET_MEM_RESERVE__VC0_MASK 0x0000000FL
+#define GCEA_RRET_MEM_RESERVE__VC1_MASK 0x000000F0L
+#define GCEA_RRET_MEM_RESERVE__VC2_MASK 0x00000F00L
+#define GCEA_RRET_MEM_RESERVE__VC3_MASK 0x0000F000L
+#define GCEA_RRET_MEM_RESERVE__VC4_MASK 0x000F0000L
+#define GCEA_RRET_MEM_RESERVE__VC5_MASK 0x00F00000L
+#define GCEA_RRET_MEM_RESERVE__VC6_MASK 0x0F000000L
+#define GCEA_RRET_MEM_RESERVE__VC7_MASK 0xF0000000L
+//GCEA_ADDRDEC_SELECT
+#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
+#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
+#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
+#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
+#define GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT 0x14
+#define GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT 0x15
+#define GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT 0x16
+#define GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT 0x17
+#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
+#define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
+#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
+#define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
+#define GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK 0x00100000L
+#define GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK 0x00200000L
+#define GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK 0x00400000L
+#define GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK 0x00800000L
+//GCEA_SDP_ENABLE
+#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0
+#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L
+
+
+// addressBlock: gc_rmi_rmidec
+//RMI_GENERAL_CNTL
+#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0
+#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11
+#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13
+#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14
+#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d
+#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e
+#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L
+#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L
+#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L
+#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L
+#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L
+#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L
+#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L
+//RMI_GENERAL_CNTL1
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0
+#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4
+#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xb
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xc
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xd
+#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT 0xe
+#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT 0xf
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL
+#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L
+#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L
+#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000600L
+#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000800L
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00001000L
+#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00002000L
+#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK 0x00004000L
+#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK 0x00008000L
+//RMI_GENERAL_STATUS
+#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4
+#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5
+#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6
+#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7
+#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8
+#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc
+#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd
+#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11
+#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12
+#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13
+#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14
+#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15
+#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d
+#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e
+#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f
+#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L
+#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L
+#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L
+#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L
+#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L
+#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L
+#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L
+#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L
+#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L
+#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L
+#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L
+#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L
+#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L
+#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L
+#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L
+#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L
+#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L
+#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L
+#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L
+#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L
+//RMI_SUBBLOCK_STATUS0
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11
+#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L
+#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L
+#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L
+//RMI_SUBBLOCK_STATUS1
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
+#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL
+#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L
+#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L
+//RMI_SUBBLOCK_STATUS2
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL
+#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L
+//RMI_SUBBLOCK_STATUS3
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL
+#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L
+//RMI_XBAR_CONFIG
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6
+#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL
+#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L
+#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L
+#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L
+//RMI_PROBE_POP_LOGIC_CNTL
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
+#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L
+#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L
+#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L
+#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L
+//RMI_UTC_XNACK_N_MISC_CNTL
+#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0
+#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8
+#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc
+#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd
+#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL
+#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L
+#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L
+#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L
+//RMI_DEMUX_CNTL
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT 0x2
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT 0x12
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK 0x00000004L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L
+#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK 0x00040000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L
+#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L
+//RMI_UTCL1_CNTL1
+#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
+#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
+#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
+#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
+#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
+#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
+#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
+#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
+#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
+#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
+#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
+#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
+#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
+#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//RMI_UTCL1_CNTL2
+#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0
+#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
+#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
+#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
+#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15
+#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19
+#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b
+#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c
+#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d
+#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL
+#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
+#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
+#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
+#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L
+#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
+#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L
+#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L
+#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L
+#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L
+#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L
+//RMI_TCIW_FORMATTER0_CNTL
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c
+#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
+#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L
+#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
+#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L
+#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L
+#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
+#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L
+//RMI_TCIW_FORMATTER1_CNTL
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c
+#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
+#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L
+#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
+#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L
+#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L
+#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
+#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L
+//RMI_SCOREBOARD_CNTL
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L
+#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L
+#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L
+#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L
+#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L
+#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L
+//RMI_SCOREBOARD_STATUS0
+#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14
+#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15
+#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT 0x16
+#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L
+#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L
+#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L
+#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK 0x07C00000L
+//RMI_SCOREBOARD_STATUS1
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd
+#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L
+#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L
+#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L
+#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L
+//RMI_SCOREBOARD_STATUS2
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L
+#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L
+#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L
+#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L
+//RMI_XBAR_ARBITER_CONFIG
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT 0x5
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT 0x15
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK 0x00000020L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK 0x00200000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L
+#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L
+//RMI_XBAR_ARBITER_CONFIG_1
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L
+#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L
+//RMI_CLOCK_CNTRL
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L
+#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L
+#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L
+//RMI_UTCL1_STATUS
+#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+//RMI_RB_GLX_CID_MAP
+#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT 0x0
+#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT 0x4
+#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT 0x8
+#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT 0xc
+#define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT 0x10
+#define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT 0x14
+#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT 0x18
+#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT 0x1c
+#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK 0x0000000FL
+#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK 0x000000F0L
+#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK 0x00000F00L
+#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK 0x0000F000L
+#define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK 0x000F0000L
+#define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK 0x00F00000L
+#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK 0x0F000000L
+#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK 0xF0000000L
+//RMI_SPARE
+#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0
+#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT 0x1
+#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT 0x2
+#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT 0x3
+#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT 0x4
+#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT 0x5
+#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6
+#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7
+#define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT 0x8
+#define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT 0x9
+#define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa
+#define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT 0xb
+#define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT 0xc
+#define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT 0xd
+#define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT 0xe
+#define RMI_SPARE__SPARE_BIT_15_0__SHIFT 0xf
+#define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT 0x10
+#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L
+#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK 0x00000002L
+#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK 0x00000004L
+#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK 0x00000008L
+#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK 0x00000010L
+#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK 0x00000020L
+#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L
+#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L
+#define RMI_SPARE__NOFILL_RMI_CID_CC_MASK 0x00000100L
+#define RMI_SPARE__NOFILL_RMI_CID_FC_MASK 0x00000200L
+#define RMI_SPARE__NOFILL_RMI_CID_CM_MASK 0x00000400L
+#define RMI_SPARE__NOFILL_RMI_CID_DC_MASK 0x00000800L
+#define RMI_SPARE__NOFILL_RMI_CID_Z_MASK 0x00001000L
+#define RMI_SPARE__NOFILL_RMI_CID_S_MASK 0x00002000L
+#define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK 0x00004000L
+#define RMI_SPARE__SPARE_BIT_15_0_MASK 0x00008000L
+#define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK 0xFFFF0000L
+//RMI_SPARE_1
+#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0
+#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1
+#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2
+#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3
+#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4
+#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5
+#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6
+#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7
+#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT 0x8
+#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10
+#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L
+#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L
+#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L
+#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L
+#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L
+#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L
+#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L
+#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L
+#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK 0x0000FF00L
+#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L
+//RMI_SPARE_2
+#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0
+#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1
+#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2
+#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3
+#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4
+#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5
+#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6
+#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7
+#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8
+#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc
+#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10
+#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18
+#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L
+#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L
+#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L
+#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L
+#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L
+#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L
+#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L
+#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L
+#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L
+#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L
+#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L
+#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L
+//CC_RMI_REDUNDANCY
+#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1
+#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2
+#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3
+#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4
+#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L
+#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L
+#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L
+#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L
+//GC_USER_RMI_REDUNDANCY
+#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1
+#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2
+#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3
+#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4
+#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L
+#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L
+#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L
+#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L
+
+
+// addressBlock: gc_pmmdec
+//PMM_GENERAL_CNTL
+#define PMM_GENERAL_CNTL__PMM_MODE__SHIFT 0x0
+#define PMM_GENERAL_CNTL__PMM_DISABLE__SHIFT 0x1
+#define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE__SHIFT 0x2
+#define PMM_GENERAL_CNTL__PMM_MODE_MASK 0x00000001L
+#define PMM_GENERAL_CNTL__PMM_DISABLE_MASK 0x00000002L
+#define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE_MASK 0x00000004L
+//GCR_PIO_CNTL
+#define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT 0x0
+#define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT 0x2
+#define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT 0x3
+#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT 0x10
+#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT 0x1e
+#define GCR_PIO_CNTL__GCR_READY__SHIFT 0x1f
+#define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK 0x00000003L
+#define GCR_PIO_CNTL__GCR_REG_DONE_MASK 0x00000004L
+#define GCR_PIO_CNTL__GCR_REG_RESET_MASK 0x00000008L
+#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK 0x00FF0000L
+#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK 0x40000000L
+#define GCR_PIO_CNTL__GCR_READY_MASK 0x80000000L
+//GCR_PIO_DATA
+#define GCR_PIO_DATA__GCR_DATA__SHIFT 0x0
+#define GCR_PIO_DATA__GCR_DATA_MASK 0xFFFFFFFFL
+//GCR_GENERAL_CNTL
+#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT 0x0
+#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT 0x1
+#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT 0x2
+#define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT 0x3
+#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT 0x4
+#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT 0x6
+#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT 0x7
+#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT 0x8
+#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT 0x9
+#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa
+#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT 0xd
+#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT 0xe
+#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT 0xf
+#define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT 0x14
+#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK 0x00000002L
+#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK 0x00000004L
+#define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK 0x00000008L
+#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK 0x00000030L
+#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK 0x00000040L
+#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK 0x00000080L
+#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK 0x00000100L
+#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK 0x00000200L
+#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK 0x00001C00L
+#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK 0x00002000L
+#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK 0x00004000L
+#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK 0x00008000L
+#define GCR_GENERAL_CNTL__CLIENT_ID_MASK 0x1FF00000L
+//GCR_TARGET_DISABLE
+#define GCR_TARGET_DISABLE__DISABLE_SA0_PHY__SHIFT 0x0
+#define GCR_TARGET_DISABLE__DISABLE_SA0_VIRT__SHIFT 0x1
+#define GCR_TARGET_DISABLE__DISABLE_SA1_PHY__SHIFT 0x2
+#define GCR_TARGET_DISABLE__DISABLE_SA1_VIRT__SHIFT 0x3
+#define GCR_TARGET_DISABLE__DISABLE_SA2_PHY__SHIFT 0x4
+#define GCR_TARGET_DISABLE__DISABLE_SA2_VIRT__SHIFT 0x5
+#define GCR_TARGET_DISABLE__DISABLE_SA3_PHY__SHIFT 0x6
+#define GCR_TARGET_DISABLE__DISABLE_SA3_VIRT__SHIFT 0x7
+#define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY__SHIFT 0x8
+#define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY__SHIFT 0x9
+#define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY__SHIFT 0xa
+#define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY__SHIFT 0xb
+#define GCR_TARGET_DISABLE__DISABLE_SA0_PHY_MASK 0x00000001L
+#define GCR_TARGET_DISABLE__DISABLE_SA0_VIRT_MASK 0x00000002L
+#define GCR_TARGET_DISABLE__DISABLE_SA1_PHY_MASK 0x00000004L
+#define GCR_TARGET_DISABLE__DISABLE_SA1_VIRT_MASK 0x00000008L
+#define GCR_TARGET_DISABLE__DISABLE_SA2_PHY_MASK 0x00000010L
+#define GCR_TARGET_DISABLE__DISABLE_SA2_VIRT_MASK 0x00000020L
+#define GCR_TARGET_DISABLE__DISABLE_SA3_PHY_MASK 0x00000040L
+#define GCR_TARGET_DISABLE__DISABLE_SA3_VIRT_MASK 0x00000080L
+#define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY_MASK 0x00000100L
+#define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY_MASK 0x00000200L
+#define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY_MASK 0x00000400L
+#define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY_MASK 0x00000800L
+//GCR_CMD_STATUS
+#define GCR_CMD_STATUS__GCR_CONTROL__SHIFT 0x0
+#define GCR_CMD_STATUS__GCR_SRC__SHIFT 0x14
+#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT 0x17
+#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT 0x18
+#define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT 0x1c
+#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT 0x1e
+#define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT 0x1f
+#define GCR_CMD_STATUS__GCR_CONTROL_MASK 0x0007FFFFL
+#define GCR_CMD_STATUS__GCR_SRC_MASK 0x00700000L
+#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK 0x00800000L
+#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK 0x0F000000L
+#define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK 0x30000000L
+#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK 0x40000000L
+#define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK 0x80000000L
+//GCR_SPARE
+#define GCR_SPARE__SPARE_BIT_1__SHIFT 0x1
+#define GCR_SPARE__SPARE_BIT_2__SHIFT 0x2
+#define GCR_SPARE__SPARE_BIT_3__SHIFT 0x3
+#define GCR_SPARE__SPARE_BIT_4__SHIFT 0x4
+#define GCR_SPARE__SPARE_BIT_5__SHIFT 0x5
+#define GCR_SPARE__SPARE_BIT_6__SHIFT 0x6
+#define GCR_SPARE__SPARE_BIT_7__SHIFT 0x7
+#define GCR_SPARE__SPARE_BIT_8_0__SHIFT 0x8
+#define GCR_SPARE__SPARE_BIT_31_16__SHIFT 0x10
+#define GCR_SPARE__SPARE_BIT_1_MASK 0x00000002L
+#define GCR_SPARE__SPARE_BIT_2_MASK 0x00000004L
+#define GCR_SPARE__SPARE_BIT_3_MASK 0x00000008L
+#define GCR_SPARE__SPARE_BIT_4_MASK 0x00000010L
+#define GCR_SPARE__SPARE_BIT_5_MASK 0x00000020L
+#define GCR_SPARE__SPARE_BIT_6_MASK 0x00000040L
+#define GCR_SPARE__SPARE_BIT_7_MASK 0x00000080L
+#define GCR_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L
+#define GCR_SPARE__SPARE_BIT_31_16_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_utcl1dec
+//UTCL1_CTRL
+#define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE__SHIFT 0x0
+#define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE__SHIFT 0x1
+#define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS__SHIFT 0x2
+#define UTCL1_CTRL__UTCL1_TCP_BYPASS__SHIFT 0x3
+#define UTCL1_CTRL__UTCL1_SQCI_BYPASS__SHIFT 0x4
+#define UTCL1_CTRL__UTCL1_SQCD_BYPASS__SHIFT 0x5
+#define UTCL1_CTRL__UTCL1_RMI_BYPASS__SHIFT 0x6
+#define UTCL1_CTRL__UTCL1_SQG_BYPASS__SHIFT 0x7
+#define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE__SHIFT 0x8
+#define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT 0x9
+#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL__SHIFT 0xa
+#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE__SHIFT 0xb
+#define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT 0xc
+#define UTCL1_CTRL__UTCL1_INV_FILTER_2M__SHIFT 0xd
+#define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT 0xe
+#define UTCL1_CTRL__RESERVED__SHIFT 0xf
+#define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE__SHIFT 0x12
+#define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM__SHIFT 0x13
+#define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER__SHIFT 0x14
+#define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES__SHIFT 0x15
+#define UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT 0x16
+#define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT 0x17
+#define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY__SHIFT 0x18
+#define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE__SHIFT 0x1a
+#define UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE__SHIFT 0x1c
+#define UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE__SHIFT 0x1e
+#define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE_MASK 0x00000001L
+#define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE_MASK 0x00000002L
+#define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS_MASK 0x00000004L
+#define UTCL1_CTRL__UTCL1_TCP_BYPASS_MASK 0x00000008L
+#define UTCL1_CTRL__UTCL1_SQCI_BYPASS_MASK 0x00000010L
+#define UTCL1_CTRL__UTCL1_SQCD_BYPASS_MASK 0x00000020L
+#define UTCL1_CTRL__UTCL1_RMI_BYPASS_MASK 0x00000040L
+#define UTCL1_CTRL__UTCL1_SQG_BYPASS_MASK 0x00000080L
+#define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE_MASK 0x00000100L
+#define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK 0x00000200L
+#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_MASK 0x00000400L
+#define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE_MASK 0x00000800L
+#define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK 0x00001000L
+#define UTCL1_CTRL__UTCL1_INV_FILTER_2M_MASK 0x00002000L
+#define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK 0x00004000L
+#define UTCL1_CTRL__RESERVED_MASK 0x00038000L
+#define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE_MASK 0x00040000L
+#define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM_MASK 0x00080000L
+#define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER_MASK 0x00100000L
+#define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES_MASK 0x00200000L
+#define UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK 0x00400000L
+#define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK 0x00800000L
+#define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY_MASK 0x03000000L
+#define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE_MASK 0x0C000000L
+#define UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE_MASK 0x30000000L
+#define UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE_MASK 0xC0000000L
+//UTCL1_ALOG
+#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x0
+#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT 0x3
+#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT 0x4
+#define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT 0x5
+#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT 0x6
+#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT 0x9
+#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa
+#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT 0xc
+#define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT 0xf
+#define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT 0x10
+#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT 0x11
+#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT 0x17
+#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT 0x18
+#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000007L
+#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000008L
+#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK 0x00000010L
+#define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK 0x00000020L
+#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK 0x000001C0L
+#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK 0x00000200L
+#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000C00L
+#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK 0x00007000L
+#define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK 0x00008000L
+#define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK 0x00010000L
+#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK 0x007E0000L
+#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK 0x00800000L
+#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK 0x01000000L
+//UTCL1_UTCL0_INVREQ_DISABLE
+#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT 0x0
+#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK 0x01FFFFFFL
+//GCRD_SA_TARGETS_DISABLE
+#define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE__SHIFT 0x0
+#define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE_MASK 0x0007FFFFL
+
+
+// addressBlock: gc_gcatcl2dec
+//GC_ATC_L2_CNTL
+#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
+#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
+#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
+#define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
+#define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
+#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
+#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
+#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
+#define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
+#define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+//GC_ATC_L2_CNTL2
+#define GC_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
+#define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
+#define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
+#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
+#define GC_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
+#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
+#define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
+#define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
+#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
+//GC_ATC_L2_CACHE_DATA0
+#define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
+#define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
+#define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
+#define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18
+#define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
+#define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
+#define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL
+#define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L
+//GC_ATC_L2_CACHE_DATA1
+#define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//GC_ATC_L2_CACHE_DATA2
+#define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
+#define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
+//GC_ATC_L2_CNTL3
+#define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
+#define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
+#define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9
+#define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0xc
+#define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
+#define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
+#define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L
+#define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x00001000L
+//GC_ATC_L2_STATUS
+#define GC_ATC_L2_STATUS__BUSY__SHIFT 0x0
+#define GC_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
+#define GC_ATC_L2_STATUS__BUSY_MASK 0x00000001L
+#define GC_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
+//GC_ATC_L2_STATUS2
+#define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
+#define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
+#define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
+#define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
+//GC_ATC_L2_MISC_CG
+#define GC_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
+#define GC_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
+#define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define GC_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
+#define GC_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
+#define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
+//GC_ATC_L2_MEM_POWER_LS
+#define GC_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define GC_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define GC_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define GC_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//GC_ATC_L2_CGTT_CLK_CTRL
+#define GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//GC_ATC_L2_SDPPORT_CTRL
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L
+#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L
+
+
+// addressBlock: gc_gcvml2pfdec
+//GCVM_L2_CNTL
+#define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
+#define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
+#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
+#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
+#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
+#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
+#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
+#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
+#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
+#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
+#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
+#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
+#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
+#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
+//GCVM_L2_CNTL2
+#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
+#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
+#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
+#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
+#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
+#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
+#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
+#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
+//GCVM_L2_CNTL3
+#define GCVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
+#define GCVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
+#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
+#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
+#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
+#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
+#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
+#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
+#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
+#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
+#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
+//GCVM_L2_STATUS
+#define GCVM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
+#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
+#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
+#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
+#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
+#define GCVM_L2_STATUS__L2_BUSY_MASK 0x00000001L
+#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
+#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
+#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
+#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
+#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
+#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
+//GCVM_DUMMY_PAGE_FAULT_CNTL
+#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
+#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
+#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
+#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
+//GCVM_DUMMY_PAGE_FAULT_ADDR_LO32
+#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
+#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//GCVM_DUMMY_PAGE_FAULT_ADDR_HI32
+#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
+#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
+//GCVM_INVALIDATE_CNTL
+#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0
+#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8
+#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL
+#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L
+//GCVM_L2_PROTECTION_FAULT_CNTL
+#define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
+#define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
+#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
+#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
+#define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
+#define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
+#define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
+#define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
+#define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
+#define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
+#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
+#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
+#define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
+#define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
+//GCVM_L2_PROTECTION_FAULT_CNTL2
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
+#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
+//GCVM_L2_PROTECTION_FAULT_MM_CNTL3
+#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//GCVM_L2_PROTECTION_FAULT_MM_CNTL4
+#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//GCVM_L2_PROTECTION_FAULT_STATUS
+#define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
+#define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
+#define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
+#define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
+#define GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
+#define GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
+#define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
+#define GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
+#define GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
+#define GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
+#define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
+#define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
+#define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
+#define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
+#define GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
+#define GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
+#define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
+#define GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
+#define GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
+#define GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x3E000000L
+//GCVM_L2_PROTECTION_FAULT_ADDR_LO32
+#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//GCVM_L2_PROTECTION_FAULT_ADDR_HI32
+#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
+#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
+#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
+#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
+#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
+#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
+#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
+#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
+#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
+//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
+#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
+#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
+//GCVM_L2_CNTL4
+#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
+#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
+#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
+#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
+#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d
+#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
+#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
+#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
+#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
+#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
+#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
+#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L
+//GCVM_L2_MM_GROUP_RT_CLASSES
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
+#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
+//GCVM_L2_BANK_SELECT_RESERVED_CID
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L
+//GCVM_L2_BANK_SELECT_RESERVED_CID2
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L
+//GCVM_L2_CACHE_PARITY_CNTL
+#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
+#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
+#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
+#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
+#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
+#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
+#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
+//GCVM_L2_CGTT_CLK_CTRL
+#define GCVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define GCVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//GCVM_L2_CNTL5
+#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5
+#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L
+//GCVM_L2_GCR_CNTL
+#define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0
+#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1
+#define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L
+#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL
+//GCVML2_WALKER_MACRO_THROTTLE_TIME
+#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0
+#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL
+//GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT
+#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1
+#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL
+//GCVML2_WALKER_MICRO_THROTTLE_TIME
+#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0
+#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL
+//GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT
+#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1
+#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL
+
+
+// addressBlock: gc_gcvml2vcdec
+//GCVM_CONTEXT0_CNTL
+#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT1_CNTL
+#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT2_CNTL
+#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT3_CNTL
+#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT4_CNTL
+#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT5_CNTL
+#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT6_CNTL
+#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT7_CNTL
+#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT8_CNTL
+#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT9_CNTL
+#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT10_CNTL
+#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT11_CNTL
+#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT12_CNTL
+#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT13_CNTL
+#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT14_CNTL
+#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXT15_CNTL
+#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//GCVM_CONTEXTS_DISABLE
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
+#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
+//GCVM_INVALIDATE_ENG0_SEM
+#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG1_SEM
+#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG2_SEM
+#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG3_SEM
+#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG4_SEM
+#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG5_SEM
+#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG6_SEM
+#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG7_SEM
+#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG8_SEM
+#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG9_SEM
+#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG10_SEM
+#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG11_SEM
+#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG12_SEM
+#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG13_SEM
+#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG14_SEM
+#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG15_SEM
+#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG16_SEM
+#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG17_SEM
+#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
+//GCVM_INVALIDATE_ENG0_REQ
+#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG1_REQ
+#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG2_REQ
+#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG3_REQ
+#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG4_REQ
+#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG5_REQ
+#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG6_REQ
+#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG7_REQ
+#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG8_REQ
+#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG9_REQ
+#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG10_REQ
+#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG11_REQ
+#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG12_REQ
+#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG13_REQ
+#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG14_REQ
+#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG15_REQ
+#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG16_REQ
+#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG17_REQ
+#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//GCVM_INVALIDATE_ENG0_ACK
+#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG1_ACK
+#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG2_ACK
+#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG3_ACK
+#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG4_ACK
+#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG5_ACK
+#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG6_ACK
+#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG7_ACK
+#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG8_ACK
+#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG9_ACK
+#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG10_ACK
+#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG11_ACK
+#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG12_ACK
+#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG13_ACK
+#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG14_ACK
+#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG15_ACK
+#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG16_ACK
+#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG17_ACK
+#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
+#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
+//GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32
+#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32
+#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+
+
+// addressBlock: gc_gcvmsharedpfdec
+//GCMC_VM_NB_MMIOBASE
+#define GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
+#define GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
+//GCMC_VM_NB_MMIOLIMIT
+#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
+#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
+//GCMC_VM_NB_PCI_CTRL
+#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
+#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
+//GCMC_VM_NB_PCI_ARB
+#define GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
+//GCMC_VM_NB_TOP_OF_DRAM_SLOT1
+#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
+//GCMC_VM_NB_LOWER_TOP_OF_DRAM2
+#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
+#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
+#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
+#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
+//GCMC_VM_NB_UPPER_TOP_OF_DRAM2
+#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
+#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
+//GCMC_VM_FB_OFFSET
+#define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
+//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
+#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
+//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
+#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
+//GCMC_VM_STEERING
+#define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define GCMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
+//GCMC_SHARED_VIRT_RESET_REQ
+#define GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define GCMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
+#define GCMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//GCMC_MEM_POWER_LS
+#define GCMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define GCMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define GCMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define GCMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//GCMC_VM_CACHEABLE_DRAM_ADDRESS_START
+#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//GCMC_VM_CACHEABLE_DRAM_ADDRESS_END
+#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//GCMC_VM_APT_CNTL
+#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
+#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
+#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
+#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
+//GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
+#define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
+//GCMC_VM_LOCAL_HBM_ADDRESS_START
+#define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//GCMC_VM_LOCAL_HBM_ADDRESS_END
+#define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//GCMC_SHARED_VIRT_RESET_REQ2
+#define GCMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT 0x0
+#define GCMC_SHARED_VIRT_RESET_REQ2__VF_MASK 0x00000001L
+
+
+// addressBlock: gc_gcvmsharedvcdec
+//GCMC_VM_FB_LOCATION_BASE
+#define GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
+//GCMC_VM_FB_LOCATION_TOP
+#define GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
+#define GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
+//GCMC_VM_AGP_TOP
+#define GCMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define GCMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
+//GCMC_VM_AGP_BOT
+#define GCMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define GCMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
+//GCMC_VM_AGP_BASE
+#define GCMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define GCMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
+//GCMC_VM_SYSTEM_APERTURE_LOW_ADDR
+#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//GCMC_VM_MX_L1_TLB_CNTL
+#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
+#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
+#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L
+
+
+// addressBlock: gc_gceadec
+//GCEA_DRAM_RD_CLI2GRP_MAP0
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//GCEA_DRAM_RD_CLI2GRP_MAP1
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//GCEA_DRAM_WR_CLI2GRP_MAP0
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//GCEA_DRAM_WR_CLI2GRP_MAP1
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//GCEA_DRAM_RD_GRP2VC_MAP
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//GCEA_DRAM_WR_GRP2VC_MAP
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//GCEA_DRAM_RD_LAZY
+#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//GCEA_DRAM_WR_LAZY
+#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//GCEA_DRAM_RD_CAM_CNTL
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//GCEA_DRAM_WR_CAM_CNTL
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//GCEA_DRAM_PAGE_BURST
+#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//GCEA_DRAM_RD_PRI_AGE
+#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//GCEA_DRAM_WR_PRI_AGE
+#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//GCEA_DRAM_RD_PRI_QUEUING
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//GCEA_DRAM_WR_PRI_QUEUING
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//GCEA_DRAM_RD_PRI_FIXED
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//GCEA_DRAM_WR_PRI_FIXED
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//GCEA_DRAM_RD_PRI_URGENCY
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//GCEA_DRAM_WR_PRI_URGENCY
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//GCEA_DRAM_RD_PRI_QUANT_PRI1
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_RD_PRI_QUANT_PRI2
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_RD_PRI_QUANT_PRI3
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_WR_PRI_QUANT_PRI1
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_WR_PRI_QUANT_PRI2
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_DRAM_WR_PRI_QUANT_PRI3
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_ADDRNORM_BASE_ADDR0
+#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_LIMIT_ADDR0
+#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_BASE_ADDR1
+#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_LIMIT_ADDR1
+#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//GCEA_ADDRNORM_OFFSET_ADDR1
+#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
+#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
+//GCEA_ADDRNORMDRAM_HOLE_CNTL
+#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0
+#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6
+#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL
+#define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L
+//GCEA_ADDRDEC_BANK_CFG
+#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
+#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
+#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
+#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
+//GCEA_ADDRDEC_MISC_CFG
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
+#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
+#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
+#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
+#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
+#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
+#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
+#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
+#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
+#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
+#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
+#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
+#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
+//GCEA_ADDRDECDRAM_ADDR_HASH_BANK0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
+//GCEA_ADDRDECDRAM_ADDR_HASH_BANK1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
+//GCEA_ADDRDECDRAM_ADDR_HASH_BANK2
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
+//GCEA_ADDRDECDRAM_ADDR_HASH_BANK3
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
+//GCEA_ADDRDECDRAM_ADDR_HASH_BANK4
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
+#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
+//GCEA_ADDRDECDRAM_ADDR_HASH_PC
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
+//GCEA_ADDRDECDRAM_ADDR_HASH_PC2
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
+//GCEA_ADDRDECDRAM_ADDR_HASH_CS0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDECDRAM_ADDR_HASH_CS1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDECDRAM_HARVEST_ENABLE
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+//GCEA_ADDRDECDRAM_HARVNA_ADDR_START0
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT 0x1c
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK 0x000FFFFFL
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK 0xF0000000L
+//GCEA_ADDRDECDRAM_HARVNA_ADDR_END0
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK 0x000FFFFFL
+//GCEA_ADDRDECDRAM_HARVNA_ADDR_START1
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT 0x1c
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK 0x000FFFFFL
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK 0xF0000000L
+//GCEA_ADDRDECDRAM_HARVNA_ADDR_END1
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT 0x0
+#define GCEA_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK 0x000FFFFFL
+//GCEA_ADDRDEC0_BASE_ADDR_CS0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_CS1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_CS2
+#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_CS3
+#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_SECCS0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_SECCS1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_SECCS2
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_BASE_ADDR_SECCS3
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_MASK_CS01
+#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_MASK_CS23
+#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_MASK_SECCS01
+#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_MASK_SECCS23
+#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC0_ADDR_CFG_CS01
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC0_ADDR_CFG_CS23
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC0_ADDR_SEL_CS01
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC0_ADDR_SEL_CS23
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC0_COL_SEL_LO_CS01
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC0_COL_SEL_LO_CS23
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC0_COL_SEL_HI_CS01
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC0_COL_SEL_HI_CS23
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC0_RM_SEL_CS01
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC0_RM_SEL_CS23
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC0_RM_SEL_SECCS01
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC0_RM_SEL_SECCS23
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC1_BASE_ADDR_CS0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_CS1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_CS2
+#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_CS3
+#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_SECCS0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_SECCS1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_SECCS2
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_BASE_ADDR_SECCS3
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_MASK_CS01
+#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_MASK_CS23
+#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_MASK_SECCS01
+#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_MASK_SECCS23
+#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//GCEA_ADDRDEC1_ADDR_CFG_CS01
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC1_ADDR_CFG_CS23
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//GCEA_ADDRDEC1_ADDR_SEL_CS01
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC1_ADDR_SEL_CS23
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//GCEA_ADDRDEC1_COL_SEL_LO_CS01
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC1_COL_SEL_LO_CS23
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//GCEA_ADDRDEC1_COL_SEL_HI_CS01
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC1_COL_SEL_HI_CS23
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//GCEA_ADDRDEC1_RM_SEL_CS01
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC1_RM_SEL_CS23
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC1_RM_SEL_SECCS01
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_ADDRDEC1_RM_SEL_SECCS23
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//GCEA_IO_RD_CLI2GRP_MAP0
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//GCEA_IO_RD_CLI2GRP_MAP1
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//GCEA_IO_WR_CLI2GRP_MAP0
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//GCEA_IO_WR_CLI2GRP_MAP1
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//GCEA_IO_RD_COMBINE_FLUSH
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+//GCEA_IO_WR_COMBINE_FLUSH
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+//GCEA_IO_GROUP_BURST
+#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//GCEA_IO_RD_PRI_AGE
+#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//GCEA_IO_WR_PRI_AGE
+#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//GCEA_IO_RD_PRI_QUEUING
+#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//GCEA_IO_WR_PRI_QUEUING
+#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//GCEA_IO_RD_PRI_FIXED
+#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//GCEA_IO_WR_PRI_FIXED
+#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//GCEA_IO_RD_PRI_URGENCY
+#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//GCEA_IO_WR_PRI_URGENCY
+#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//GCEA_IO_RD_PRI_URGENCY_MASKING
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//GCEA_IO_WR_PRI_URGENCY_MASKING
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//GCEA_IO_RD_PRI_QUANT_PRI1
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_RD_PRI_QUANT_PRI2
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_RD_PRI_QUANT_PRI3
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_WR_PRI_QUANT_PRI1
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_WR_PRI_QUANT_PRI2
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_IO_WR_PRI_QUANT_PRI3
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GCEA_SDP_ARB_DRAM
+#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT 0x16
+#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+#define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+#define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK 0x00400000L
+//GCEA_SDP_ARB_FINAL
+#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+//GCEA_SDP_DRAM_PRIORITY
+#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//GCEA_SDP_IO_PRIORITY
+#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//GCEA_SDP_CREDITS
+#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18
+#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L
+//GCEA_SDP_TAG_RESERVE0
+#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//GCEA_SDP_TAG_RESERVE1
+#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//GCEA_SDP_VCC_RESERVE0
+#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//GCEA_SDP_VCC_RESERVE1
+#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//GCEA_SDP_VCD_RESERVE0
+#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+
+
+// addressBlock: gc_tcdec
+//TCP_INVALIDATE
+#define TCP_INVALIDATE__START__SHIFT 0x0
+#define TCP_INVALIDATE__START_MASK 0x00000001L
+//TCP_STATUS
+#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
+#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
+#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
+#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
+#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
+#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
+#define TCP_STATUS__READ_BUSY__SHIFT 0x6
+#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
+#define TCP_STATUS__VM_BUSY__SHIFT 0x8
+#define TCP_STATUS__OFIFO_BUSY__SHIFT 0x9
+#define TCP_STATUS__MEMIF_BUSY__SHIFT 0xa
+#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L
+#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L
+#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L
+#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L
+#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L
+#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L
+#define TCP_STATUS__READ_BUSY_MASK 0x00000040L
+#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L
+#define TCP_STATUS__VM_BUSY_MASK 0x00000100L
+#define TCP_STATUS__OFIFO_BUSY_MASK 0x00000200L
+#define TCP_STATUS__MEMIF_BUSY_MASK 0x00000400L
+//TCP_CNTL
+#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
+#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
+#define TCP_CNTL__L0_SIZE__SHIFT 0x2
+#define TCP_CNTL__BIG_PAGE_ADDR_COMBINE_DISABLE__SHIFT 0x4
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
+#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
+#define TCP_CNTL__LFIFO_SIZE__SHIFT 0x1d
+#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1f
+#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L
+#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L
+#define TCP_CNTL__L0_SIZE_MASK 0x0000000CL
+#define TCP_CNTL__BIG_PAGE_ADDR_COMBINE_DISABLE_MASK 0x00000010L
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L
+#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L
+#define TCP_CNTL__LFIFO_SIZE_MASK 0x60000000L
+#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x80000000L
+//TCP_CREDIT
+#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
+#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
+#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L
+#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L
+//TCP_BUFFER_ADDR_HASH_CNTL
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L
+//TCP_EDC_CNT
+#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
+#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
+#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
+#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL
+#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L
+#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L
+//TCI_STATUS
+#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
+#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L
+//TCI_CNTL_1
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
+#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
+#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL
+#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L
+#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L
+//TCI_CNTL_2
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
+#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L
+#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL
+
+
+// addressBlock: gc_shdec
+//SPI_SHADER_PGM_RSRC4_PS
+#define SPI_SHADER_PGM_RSRC4_PS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC4_PS__CU_EN_MASK 0x0000FFFFL
+//SPI_SHADER_PGM_CHKSUM_PS
+#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT 0x0
+#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC3_PS
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+//SPI_SHADER_PGM_LO_PS
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_PS
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_PS
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED_MASK 0x02000000L
+#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L
+//SPI_SHADER_PGM_RSRC2_PS
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L
+#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK 0xF0000000L
+//SPI_SHADER_USER_DATA_PS_0
+#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_1
+#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_2
+#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_3
+#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_4
+#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_5
+#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_6
+#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_7
+#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_8
+#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_9
+#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_10
+#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_11
+#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_12
+#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_13
+#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_14
+#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_15
+#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_16
+#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_17
+#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_18
+#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_19
+#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_20
+#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_21
+#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_22
+#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_23
+#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_24
+#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_25
+#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_26
+#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_27
+#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_28
+#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_29
+#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_30
+#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_PS_31
+#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_REQ_CTRL_PS
+#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT 0x0
+#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1
+#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5
+#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT 0x9
+#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
+#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf
+#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT 0x10
+#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11
+#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK 0x00000001L
+#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL
+#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L
+#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L
+#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L
+#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L
+#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK 0x00010000L
+#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L
+//SPI_SHADER_PREF_PRI_CNTR_CTRL_PS
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT 0x3
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__GROUP_UPDATE_EN__SHIFT 0x6
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT 0x8
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT 0x10
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK 0x00000007L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK 0x00000038L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__GROUP_UPDATE_EN_MASK 0x00000040L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK 0x0000FF00L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK 0x00FF0000L
+//SPI_SHADER_PREF_PRI_ACCUM_PS_0
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_PS_0
+#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_PS_1
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_PS_1
+#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_PS_2
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_PS_2
+#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_PS_3
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_PS_3
+#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PGM_RSRC4_VS
+#define SPI_SHADER_PGM_RSRC4_VS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC4_VS__CU_EN_MASK 0x0000FFFFL
+//SPI_SHADER_PGM_CHKSUM_VS
+#define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM__SHIFT 0x0
+#define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC3_VS
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+//SPI_SHADER_LATE_ALLOC_VS
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL
+//SPI_SHADER_PGM_LO_VS
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_VS
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_VS
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS_MASK 0x10000000L
+#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L
+//SPI_SHADER_PGM_RSRC2_VS
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
+#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L
+#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT_MASK 0xF0000000L
+//SPI_SHADER_USER_DATA_VS_0
+#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_1
+#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_2
+#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_3
+#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_4
+#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_5
+#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_6
+#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_7
+#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_8
+#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_9
+#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_10
+#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_11
+#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_12
+#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_13
+#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_14
+#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_15
+#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_16
+#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_17
+#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_18
+#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_19
+#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_20
+#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_21
+#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_22
+#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_23
+#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_24
+#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_25
+#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_26
+#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_27
+#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_28
+#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_29
+#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_30
+#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_VS_31
+#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_REQ_CTRL_VS
+#define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN__SHIFT 0x0
+#define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1
+#define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5
+#define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS__SHIFT 0x9
+#define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
+#define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf
+#define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN__SHIFT 0x10
+#define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11
+#define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN_MASK 0x00000001L
+#define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL
+#define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L
+#define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L
+#define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L
+#define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L
+#define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN_MASK 0x00010000L
+#define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L
+//SPI_SHADER_PREF_PRI_CNTR_CTRL_VS
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT 0x3
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__GROUP_UPDATE_EN__SHIFT 0x6
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT 0x8
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT 0x10
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK 0x00000007L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK 0x00000038L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__GROUP_UPDATE_EN_MASK 0x00000040L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK 0x0000FF00L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK 0x00FF0000L
+//SPI_SHADER_PREF_PRI_ACCUM_VS_0
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_VS_0
+#define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_VS_1
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_VS_1
+#define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_VS_2
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_VS_2
+#define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_VS_3
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_VS_3
+#define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PGM_RSRC2_GS_VS
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12
+#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L
+//SPI_SHADER_PGM_RSRC2_ES_VS
+#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x0001FF00L
+#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1FF00000L
+//SPI_SHADER_PGM_RSRC2_LS_VS
+#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x01FF0000L
+//SPI_SHADER_PGM_CHKSUM_GS
+#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT 0x0
+#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC4_GS
+#define SPI_SHADER_PGM_RSRC4_GS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC4_GS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x007F0000L
+//SPI_SHADER_USER_DATA_ADDR_LO_GS
+#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ADDR_HI_GS
+#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_LO_ES_GS
+#define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_ES_GS
+#define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC3_GS
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xFC000000L
+//SPI_SHADER_PGM_LO_GS
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_GS
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_GS
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d
+#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED_MASK 0x02000000L
+#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L
+#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L
+//SPI_SHADER_PGM_RSRC2_GS
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12
+#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L
+#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L
+#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK 0xF0000000L
+//SPI_SHADER_USER_DATA_GS_0
+#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_1
+#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_2
+#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_3
+#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_4
+#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_5
+#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_6
+#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_7
+#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_8
+#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_9
+#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_10
+#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_11
+#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_12
+#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_13
+#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_14
+#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_15
+#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_16
+#define SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_17
+#define SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_18
+#define SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_19
+#define SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_20
+#define SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_21
+#define SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_22
+#define SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_23
+#define SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_24
+#define SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_25
+#define SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_26
+#define SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_27
+#define SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_28
+#define SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_29
+#define SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_30
+#define SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_GS_31
+#define SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_REQ_CTRL_ESGS
+#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT 0x0
+#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1
+#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5
+#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT 0x9
+#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
+#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf
+#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT 0x10
+#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11
+#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK 0x00000001L
+#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL
+#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L
+#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L
+#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L
+#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L
+#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK 0x00010000L
+#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L
+//SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT 0x3
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__GROUP_UPDATE_EN__SHIFT 0x6
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT 0x8
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT 0x10
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK 0x00000007L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK 0x00000038L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__GROUP_UPDATE_EN_MASK 0x00000040L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK 0x0000FF00L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK 0x00FF0000L
+//SPI_SHADER_PREF_PRI_ACCUM_ESGS_0
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_ESGS_0
+#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_ESGS_1
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_ESGS_1
+#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_ESGS_2
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_ESGS_2
+#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_ESGS_3
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_ESGS_3
+#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PGM_RSRC2_ES_GS
+#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x0001FF00L
+#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1FF00000L
+//SPI_SHADER_PGM_RSRC3_ES
+#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xFC000000L
+//SPI_SHADER_PGM_LO_ES
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_ES
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_ES
+#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_ES__FP16_OVFL__SHIFT 0x1f
+#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x03000000L
+#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC1_ES__FP16_OVFL_MASK 0x80000000L
+//SPI_SHADER_PGM_RSRC2_ES
+#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x0001FF00L
+#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1FF00000L
+//SPI_SHADER_USER_DATA_ES_0
+#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_1
+#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_2
+#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_3
+#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_4
+#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_5
+#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_6
+#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_7
+#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_8
+#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_9
+#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_10
+#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_11
+#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_12
+#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_13
+#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_14
+#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ES_15
+#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC2_LS_ES
+#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x01FF0000L
+//SPI_SHADER_PGM_CHKSUM_HS
+#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT 0x0
+#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_RSRC4_HS
+#define SPI_SHADER_PGM_RSRC4_HS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC4_HS__CU_EN_MASK 0x0000FFFFL
+//SPI_SHADER_USER_DATA_ADDR_LO_HS
+#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_ADDR_HI_HS
+#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_LO_LS_HS
+#define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_LS_HS
+#define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC3_HS
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0x0000FC00L
+#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L
+//SPI_SHADER_PGM_LO_HS
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_HS
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_HS
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED_MASK 0x01000000L
+#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK 0x02000000L
+#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK 0x04000000L
+#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L
+#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L
+//SPI_SHADER_PGM_RSRC2_HS
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x12
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L
+#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0003FE00L
+#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x07FC0000L
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x08000000L
+#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK 0xF0000000L
+//SPI_SHADER_USER_DATA_HS_0
+#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_1
+#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_2
+#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_3
+#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_4
+#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_5
+#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_6
+#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_7
+#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_8
+#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_9
+#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_10
+#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_11
+#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_12
+#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_13
+#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_14
+#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_15
+#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_16
+#define SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_16__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_17
+#define SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_17__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_18
+#define SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_18__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_19
+#define SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_19__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_20
+#define SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_20__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_21
+#define SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_21__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_22
+#define SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_22__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_23
+#define SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_23__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_24
+#define SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_24__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_25
+#define SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_25__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_26
+#define SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_26__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_27
+#define SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_27__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_28
+#define SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_28__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_29
+#define SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_29__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_30
+#define SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_30__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_HS_31
+#define SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_31__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_REQ_CTRL_LSHS
+#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT 0x0
+#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1
+#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5
+#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT 0x9
+#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
+#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf
+#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT 0x10
+#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11
+#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK 0x00000001L
+#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL
+#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L
+#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L
+#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L
+#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L
+#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK 0x00010000L
+#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L
+//SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT 0x3
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__GROUP_UPDATE_EN__SHIFT 0x6
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT 0x8
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT 0x10
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK 0x00000007L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK 0x00000038L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__GROUP_UPDATE_EN_MASK 0x00000040L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK 0x0000FF00L
+#define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK 0x00FF0000L
+//SPI_SHADER_PREF_PRI_ACCUM_LSHS_0
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_LSHS_0
+#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_LSHS_1
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_LSHS_1
+#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_LSHS_2
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_LSHS_2
+#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PREF_PRI_ACCUM_LSHS_3
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__GROUP_UPDATE_EN__SHIFT 0xd
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__RESERVED__SHIFT 0xe
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT__SHIFT 0xf
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_MASK 0x0000007FL
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__GROUP_UPDATE_EN_MASK 0x00002000L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__RESERVED_MASK 0x00004000L
+#define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT_MASK 0x007F8000L
+//SPI_SHADER_USER_ACCUM_LSHS_3
+#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT 0x0
+#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK 0x0000007FL
+//SPI_SHADER_PGM_RSRC2_LS_HS
+#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x01FF0000L
+//SPI_SHADER_PGM_RSRC3_LS
+#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0x0000FFFFL
+#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x003F0000L
+#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
+#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xFC000000L
+//SPI_SHADER_PGM_LO_LS
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL
+//SPI_SHADER_PGM_HI_LS
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL
+//SPI_SHADER_PGM_RSRC1_LS
+#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_LS__FP16_OVFL__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x0000003FL
+#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x000003C0L
+#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0x00000C00L
+#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0x000FF000L
+#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x00100000L
+#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x00200000L
+#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x00800000L
+#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x03000000L
+#define SPI_SHADER_PGM_RSRC1_LS__FP16_OVFL_MASK 0x40000000L
+//SPI_SHADER_PGM_RSRC2_LS
+#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x00000001L
+#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x0000003EL
+#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x00000040L
+#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0x0000FF80L
+#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x01FF0000L
+//SPI_SHADER_USER_DATA_LS_0
+#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_1
+#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_2
+#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_3
+#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_4
+#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_5
+#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_6
+#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_7
+#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_8
+#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_9
+#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_10
+#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_11
+#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_12
+#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_13
+#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_14
+#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL
+//SPI_SHADER_USER_DATA_LS_15
+#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_INITIATOR
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
+#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc
+#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT 0xd
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
+#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT 0xf
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
+#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L
+#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK 0x00002000L
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
+#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK 0x00008000L
+//COMPUTE_DIM_X
+#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL
+//COMPUTE_DIM_Y
+#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL
+//COMPUTE_DIM_Z
+#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL
+//COMPUTE_START_X
+#define COMPUTE_START_X__START__SHIFT 0x0
+#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL
+//COMPUTE_START_Y
+#define COMPUTE_START_Y__START__SHIFT 0x0
+#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL
+//COMPUTE_START_Z
+#define COMPUTE_START_Z__START__SHIFT 0x0
+#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL
+//COMPUTE_NUM_THREAD_X
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
+//COMPUTE_NUM_THREAD_Y
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
+//COMPUTE_NUM_THREAD_Z
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
+//COMPUTE_PIPELINESTAT_ENABLE
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L
+//COMPUTE_PERFCOUNT_ENABLE
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L
+//COMPUTE_PGM_LO
+#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
+#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_PGM_HI
+#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
+#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL
+//COMPUTE_DISPATCH_PKT_ADDR_LO
+#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_PKT_ADDR_HI
+#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL
+//COMPUTE_DISPATCH_SCRATCH_BASE_LO
+#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_SCRATCH_BASE_HI
+#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL
+//COMPUTE_PGM_RSRC1
+#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
+#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
+#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
+#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
+#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
+#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
+#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a
+#define COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT 0x1d
+#define COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT 0x1e
+#define COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT 0x1f
+#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL
+#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L
+#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L
+#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
+#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
+#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
+#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L
+#define COMPUTE_PGM_RSRC1__WGP_MODE_MASK 0x20000000L
+#define COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK 0x40000000L
+#define COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK 0x80000000L
+//COMPUTE_PGM_RSRC2
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
+#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
+#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
+#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
+#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
+#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
+#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
+#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L
+//COMPUTE_VMID
+#define COMPUTE_VMID__DATA__SHIFT 0x0
+#define COMPUTE_VMID__DATA_MASK 0x0000000FL
+//COMPUTE_RESOURCE_LIMITS
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
+//COMPUTE_DESTINATION_EN_SE0
+#define COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT 0x0
+#define COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK 0xFFFFFFFFL
+//COMPUTE_STATIC_THREAD_MGMT_SE0
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_DESTINATION_EN_SE1
+#define COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT 0x0
+#define COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK 0xFFFFFFFFL
+//COMPUTE_STATIC_THREAD_MGMT_SE1
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_TMPRING_SIZE
+#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
+#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
+//COMPUTE_DESTINATION_EN_SE2
+#define COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT 0x0
+#define COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK 0xFFFFFFFFL
+//COMPUTE_STATIC_THREAD_MGMT_SE2
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_DESTINATION_EN_SE3
+#define COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT 0x0
+#define COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK 0xFFFFFFFFL
+//COMPUTE_STATIC_THREAD_MGMT_SE3
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK 0x0000FFFFL
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK 0xFFFF0000L
+//COMPUTE_RESTART_X
+#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_RESTART_Y
+#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_RESTART_Z
+#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL
+//COMPUTE_THREAD_TRACE_ENABLE
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L
+//COMPUTE_MISC_RESERVED
+#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
+#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
+#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
+#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
+#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L
+#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L
+#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L
+#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L
+//COMPUTE_DISPATCH_ID
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL
+//COMPUTE_THREADGROUP_ID
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL
+//COMPUTE_REQ_CTRL
+#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT 0x0
+#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1
+#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5
+#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT 0x9
+#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa
+#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf
+#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT 0x10
+#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11
+#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT 0x14
+#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK 0x00000001L
+#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL
+#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L
+#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK 0x00000200L
+#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L
+#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L
+#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK 0x00010000L
+#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L
+#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK 0x07F00000L
+//COMPUTE_PREF_PRI_ACCUM_0
+#define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION__SHIFT 0x0
+#define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define COMPUTE_PREF_PRI_ACCUM_0__GROUP_UPDATE_EN__SHIFT 0xd
+#define COMPUTE_PREF_PRI_ACCUM_0__RESERVED__SHIFT 0xe
+#define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT__SHIFT 0xf
+#define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL
+#define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define COMPUTE_PREF_PRI_ACCUM_0__GROUP_UPDATE_EN_MASK 0x00002000L
+#define COMPUTE_PREF_PRI_ACCUM_0__RESERVED_MASK 0x00004000L
+#define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT_MASK 0x007F8000L
+//COMPUTE_USER_ACCUM_0
+#define COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT 0x0
+#define COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL
+//COMPUTE_PREF_PRI_ACCUM_1
+#define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION__SHIFT 0x0
+#define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define COMPUTE_PREF_PRI_ACCUM_1__GROUP_UPDATE_EN__SHIFT 0xd
+#define COMPUTE_PREF_PRI_ACCUM_1__RESERVED__SHIFT 0xe
+#define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT__SHIFT 0xf
+#define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL
+#define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define COMPUTE_PREF_PRI_ACCUM_1__GROUP_UPDATE_EN_MASK 0x00002000L
+#define COMPUTE_PREF_PRI_ACCUM_1__RESERVED_MASK 0x00004000L
+#define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT_MASK 0x007F8000L
+//COMPUTE_USER_ACCUM_1
+#define COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT 0x0
+#define COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL
+//COMPUTE_PREF_PRI_ACCUM_2
+#define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION__SHIFT 0x0
+#define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define COMPUTE_PREF_PRI_ACCUM_2__GROUP_UPDATE_EN__SHIFT 0xd
+#define COMPUTE_PREF_PRI_ACCUM_2__RESERVED__SHIFT 0xe
+#define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT__SHIFT 0xf
+#define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL
+#define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define COMPUTE_PREF_PRI_ACCUM_2__GROUP_UPDATE_EN_MASK 0x00002000L
+#define COMPUTE_PREF_PRI_ACCUM_2__RESERVED_MASK 0x00004000L
+#define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT_MASK 0x007F8000L
+//COMPUTE_USER_ACCUM_2
+#define COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT 0x0
+#define COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL
+//COMPUTE_PREF_PRI_ACCUM_3
+#define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION__SHIFT 0x0
+#define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7
+#define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa
+#define COMPUTE_PREF_PRI_ACCUM_3__GROUP_UPDATE_EN__SHIFT 0xd
+#define COMPUTE_PREF_PRI_ACCUM_3__RESERVED__SHIFT 0xe
+#define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT__SHIFT 0xf
+#define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL
+#define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L
+#define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L
+#define COMPUTE_PREF_PRI_ACCUM_3__GROUP_UPDATE_EN_MASK 0x00002000L
+#define COMPUTE_PREF_PRI_ACCUM_3__RESERVED_MASK 0x00004000L
+#define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT_MASK 0x007F8000L
+//COMPUTE_USER_ACCUM_3
+#define COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT 0x0
+#define COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL
+//COMPUTE_PGM_RSRC3
+#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT 0x0
+#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK 0x0000000FL
+//COMPUTE_DDID_INDEX
+#define COMPUTE_DDID_INDEX__INDEX__SHIFT 0x0
+#define COMPUTE_DDID_INDEX__INDEX_MASK 0x000007FFL
+//COMPUTE_SHADER_CHKSUM
+#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0
+#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL
+//COMPUTE_RELAUNCH
+#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
+#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
+#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
+#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL
+#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L
+#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L
+//COMPUTE_WAVE_RESTORE_ADDR_LO
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL
+//COMPUTE_WAVE_RESTORE_ADDR_HI
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL
+//COMPUTE_RELAUNCH2
+#define COMPUTE_RELAUNCH2__PAYLOAD__SHIFT 0x0
+#define COMPUTE_RELAUNCH2__IS_EVENT__SHIFT 0x1e
+#define COMPUTE_RELAUNCH2__IS_STATE__SHIFT 0x1f
+#define COMPUTE_RELAUNCH2__PAYLOAD_MASK 0x3FFFFFFFL
+#define COMPUTE_RELAUNCH2__IS_EVENT_MASK 0x40000000L
+#define COMPUTE_RELAUNCH2__IS_STATE_MASK 0x80000000L
+//COMPUTE_USER_DATA_0
+#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_1
+#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_2
+#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_3
+#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_4
+#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_5
+#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_6
+#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_7
+#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_8
+#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_9
+#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_10
+#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_11
+#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_12
+#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_13
+#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_14
+#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_USER_DATA_15
+#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_DISPATCH_TUNNEL
+#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT 0x0
+#define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT 0xa
+#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK 0x000003FFL
+#define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE_MASK 0x00000400L
+//COMPUTE_DISPATCH_END
+#define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0
+#define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL
+//COMPUTE_NOWHERE
+#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
+#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_cppdec
+//CP_EOPQ_WAIT_TIME
+#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0
+#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
+#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL
+#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L
+//CP_CPC_MGCG_SYNC_CNTL
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L
+//CPC_INT_INFO
+#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0
+#define CPC_INT_INFO__TYPE__SHIFT 0x10
+#define CPC_INT_INFO__VMID__SHIFT 0x14
+#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c
+#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL
+#define CPC_INT_INFO__TYPE_MASK 0x00010000L
+#define CPC_INT_INFO__VMID_MASK 0x00F00000L
+#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L
+//CP_VIRT_STATUS
+#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
+#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL
+//CPC_INT_ADDR
+#define CPC_INT_ADDR__ADDR__SHIFT 0x0
+#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL
+//CPC_INT_PASID
+#define CPC_INT_PASID__PASID__SHIFT 0x0
+#define CPC_INT_PASID__BYPASS_PASID__SHIFT 0x10
+#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL
+#define CPC_INT_PASID__BYPASS_PASID_MASK 0x00010000L
+//CP_GFX_ERROR
+#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0
+#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4
+#define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR__SHIFT 0x5
+#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT 0x6
+#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7
+#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8
+#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9
+#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
+#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb
+#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc
+#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd
+#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe
+#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf
+#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10
+#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11
+#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12
+#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13
+#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14
+#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15
+#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16
+#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17
+#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18
+#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19
+#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a
+#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b
+#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c
+#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d
+#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e
+#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f
+#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
+#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L
+#define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR_MASK 0x00000020L
+#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK 0x00000040L
+#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L
+#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L
+#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L
+#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L
+#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L
+#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L
+#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L
+#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L
+#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L
+#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L
+#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L
+#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L
+#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L
+#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L
+#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L
+#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L
+#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L
+#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L
+#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L
+#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L
+#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L
+#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L
+#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L
+#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L
+#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L
+//CPG_UTCL1_CNTL
+#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
+#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
+//CPC_UTCL1_CNTL
+#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
+#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
+//CPF_UTCL1_CNTL
+#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
+#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
+#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f
+#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
+#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
+#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L
+//CP_AQL_SMM_STATUS
+#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0
+#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL
+//CP_RB0_BASE
+#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB_BASE
+#define CP_RB_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB0_CNTL
+#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10
+#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB0_CNTL__RB_EXE__SHIFT 0x1c
+#define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00030000L
+#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L
+#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L
+#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB0_CNTL__RB_EXE_MASK 0x10000000L
+#define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB_CNTL
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10
+#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB_CNTL__RB_EXE__SHIFT 0x1c
+#define CP_RB_CNTL__KMD_QUEUE__SHIFT 0x1d
+#define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L
+#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L
+#define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB_CNTL__RB_EXE_MASK 0x10000000L
+#define CP_RB_CNTL__KMD_QUEUE_MASK 0x20000000L
+#define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB_RPTR_WR
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL
+//CP_RB0_RPTR_ADDR
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB_RPTR_ADDR
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB0_RPTR_ADDR_HI
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB_RPTR_ADDR_HI
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB0_BUFSZ_MASK
+#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0
+#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
+//CP_RB_BUFSZ_MASK
+#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0
+#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
+//CP_INT_CNTL
+#define CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT 0x8
+#define CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT 0x9
+#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT 0xa
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL__RESUME_INT_ENABLE_MASK 0x00000100L
+#define CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK 0x00000200L
+#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK 0x00000400L
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_STATUS
+#define CP_INT_STATUS__RESUME_INT_STAT__SHIFT 0x8
+#define CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT 0x9
+#define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT 0xa
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS__RESUME_INT_STAT_MASK 0x00000100L
+#define CP_INT_STATUS__SUSPEND_INT_STAT_MASK 0x00000200L
+#define CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK 0x00000400L
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_DEVICE_ID
+#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL
+//CP_ME0_PIPE_PRIORITY_CNTS
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_RING_PRIORITY_CNTS
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_ME0_PIPE0_PRIORITY
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_RING0_PRIORITY
+#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME0_PIPE1_PRIORITY
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_RING1_PRIORITY
+#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME0_PIPE2_PRIORITY
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_RING2_PRIORITY
+#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_FATAL_ERROR
+#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0
+#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1
+#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2
+#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3
+#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4
+#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L
+#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L
+#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L
+#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L
+#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L
+//CP_RB_VMID
+#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
+#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
+#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
+#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL
+#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L
+#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L
+//CP_ME0_PIPE0_VMID
+#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
+#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL
+//CP_ME0_PIPE1_VMID
+#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
+#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL
+//CP_RB0_WPTR
+#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB_WPTR
+#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB0_WPTR_HI
+#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB_WPTR_HI
+#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB1_WPTR
+#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB1_WPTR_HI
+#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_RB2_WPTR
+#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL
+//CP_PROCESS_QUANTUM
+#define CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT 0x0
+#define CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT 0x1c
+#define CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT 0x1d
+#define CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT 0x1f
+#define CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK 0x0FFFFFFFL
+#define CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK 0x10000000L
+#define CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK 0x60000000L
+#define CP_PROCESS_QUANTUM__QUANTUM_EN_MASK 0x80000000L
+//CP_RB_DOORBELL_RANGE_LOWER
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
+//CP_RB_DOORBELL_RANGE_UPPER
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
+//CP_MEC_DOORBELL_RANGE_LOWER
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
+//CP_MEC_DOORBELL_RANGE_UPPER
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
+//CPG_UTCL1_ERROR
+#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
+#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
+//CPC_UTCL1_ERROR
+#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
+#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
+//CP_RB1_BASE
+#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB1_CNTL
+#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB1_CNTL__RB_EXE__SHIFT 0x1c
+#define CP_RB1_CNTL__KMD_QUEUE__SHIFT 0x1d
+#define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L
+#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L
+#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB1_CNTL__RB_EXE_MASK 0x10000000L
+#define CP_RB1_CNTL__KMD_QUEUE_MASK 0x20000000L
+#define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB1_RPTR_ADDR
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB1_RPTR_ADDR_HI
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB1_BUFSZ_MASK
+#define CP_RB1_BUFSZ_MASK__DATA__SHIFT 0x0
+#define CP_RB1_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
+//CP_RB2_BASE
+#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_RB2_CNTL
+#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB2_CNTL__RB_EXE__SHIFT 0x1c
+#define CP_RB2_CNTL__KMD_QUEUE__SHIFT 0x1d
+#define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x03000000L
+#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x04000000L
+#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_RB2_CNTL__RB_EXE_MASK 0x10000000L
+#define CP_RB2_CNTL__KMD_QUEUE_MASK 0x20000000L
+#define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_RB2_RPTR_ADDR
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_RB2_RPTR_ADDR_HI
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_INT_CNTL_RING0
+#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT 0x8
+#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT 0x9
+#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT 0xa
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK 0x00000100L
+#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK 0x00000200L
+#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK 0x00000400L
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_CNTL_RING1
+#define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE__SHIFT 0xa
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE_MASK 0x00000400L
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_CNTL_RING2
+#define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE__SHIFT 0xa
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE_MASK 0x00000400L
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_INT_STATUS_RING0
+#define CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT 0x8
+#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT 0x9
+#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT 0xa
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK 0x00000100L
+#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK 0x00000200L
+#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK 0x00000400L
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_INT_STATUS_RING1
+#define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT__SHIFT 0xa
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT_MASK 0x00000400L
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
+//CP_INT_STATUS_RING2
+#define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT__SHIFT 0xa
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT_MASK 0x00000400L
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
+#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
+//CP_PWR_CNTL
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT 0x14
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT 0x15
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT 0x16
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT 0x17
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK 0x00100000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK 0x00200000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK 0x00400000L
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK 0x00800000L
+//CP_MEM_SLP_CNTL
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
+#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
+#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
+#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
+//CP_ECC_FIRSTOCCURRENCE
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
+#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
+#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
+#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L
+#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L
+#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L
+#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L
+//CP_ECC_FIRSTOCCURRENCE_RING0
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_ECC_FIRSTOCCURRENCE_RING1
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_ECC_FIRSTOCCURRENCE_RING2
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL
+//GB_EDC_MODE
+#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf
+#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
+#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
+#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L
+#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define GB_EDC_MODE__BYPASS_MASK 0x80000000L
+//CP_FETCHER_SOURCE
+#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0
+#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x00000001L
+//CP_PQ_WPTR_POLL_CNTL
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
+#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL
+#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L
+#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L
+//CP_PQ_WPTR_POLL_CNTL1
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL
+//CP_ME1_PIPE0_INT_CNTL
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE1_INT_CNTL
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE2_INT_CNTL
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE3_INT_CNTL
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE0_INT_CNTL
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE1_INT_CNTL
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE2_INT_CNTL
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME2_PIPE3_INT_CNTL
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CP_ME1_PIPE0_INT_STATUS
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_PIPE1_INT_STATUS
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_PIPE2_INT_STATUS
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME1_PIPE3_INT_STATUS
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE0_INT_STATUS
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE1_INT_STATUS
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE2_INT_STATUS
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_ME2_PIPE3_INT_STATUS
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
+//CP_GFX_QUEUE_INDEX
+#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT 0x0
+#define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT 0x4
+#define CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT 0x8
+#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK 0x00000001L
+#define CP_GFX_QUEUE_INDEX__PIPE_ID_MASK 0x00000030L
+#define CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK 0x00000700L
+//CC_GC_EDC_CONFIG
+#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//CP_ME1_PIPE_PRIORITY_CNTS
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_ME1_PIPE0_PRIORITY
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME1_PIPE1_PRIORITY
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME1_PIPE2_PRIORITY
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME1_PIPE3_PRIORITY
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE_PRIORITY_CNTS
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_ME2_PIPE0_PRIORITY
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE1_PRIORITY
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE2_PRIORITY
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_ME2_PIPE3_PRIORITY
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_CE_PRGRM_CNTR_START
+#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL
+//CP_PFP_PRGRM_CNTR_START
+#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL
+//CP_ME_PRGRM_CNTR_START
+#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL
+//CP_MEC1_PRGRM_CNTR_START
+#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL
+//CP_MEC2_PRGRM_CNTR_START
+#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL
+//CP_CE_INTR_ROUTINE_START
+#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL
+//CP_PFP_INTR_ROUTINE_START
+#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL
+//CP_ME_INTR_ROUTINE_START
+#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL
+//CP_MEC1_INTR_ROUTINE_START
+#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL
+//CP_MEC2_INTR_ROUTINE_START
+#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL
+//CP_CONTEXT_CNTL
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT 0x0
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT 0x10
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK 0x00000007L
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK 0x00070000L
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L
+//CP_MAX_CONTEXT
+#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
+#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L
+//CP_IQ_WAIT_TIME1
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
+#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L
+#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L
+//CP_IQ_WAIT_TIME2
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
+#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
+#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL
+#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L
+#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L
+//CP_RB0_BASE_HI
+#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
+//CP_RB1_BASE_HI
+#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
+//CP_VMID_RESET
+#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
+#define CP_VMID_RESET__PIPE0_QUEUES__SHIFT 0x10
+#define CP_VMID_RESET__PIPE1_QUEUES__SHIFT 0x18
+#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL
+#define CP_VMID_RESET__PIPE0_QUEUES_MASK 0x00FF0000L
+#define CP_VMID_RESET__PIPE1_QUEUES_MASK 0xFF000000L
+//CPC_INT_CNTL
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
+#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
+//CPC_INT_STATUS
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
+#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
+//CP_VMID_PREEMPT
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
+#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL
+#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L
+//CPC_INT_CNTX_ID
+#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
+//CP_PQ_STATUS
+#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
+#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
+#define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT 0x2
+#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT 0x3
+#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
+#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
+#define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK 0x00000004L
+#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK 0x00000008L
+//CP_CE_CS_PARTITION_INDEX
+#define CP_CE_CS_PARTITION_INDEX__CS1_INDEX__SHIFT 0x0
+#define CP_CE_CS_PARTITION_INDEX__CS1_INDEX_MASK 0x0001FFFFL
+//CP_MEC1_F32_INT_DIS
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
+#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
+#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
+#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
+#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
+#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
+#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
+#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
+#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
+#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
+//CP_MEC2_F32_INT_DIS
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
+#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
+#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
+#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
+#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
+#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
+#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
+#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
+#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
+#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
+//CP_VMID_STATUS
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L
+//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO
+#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
+#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI
+#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CPC_SUSPEND_CTX_SAVE_CONTROL
+#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
+#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L
+#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L
+//CPC_SUSPEND_CNTL_STACK_OFFSET
+#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
+#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL
+//CPC_SUSPEND_CNTL_STACK_SIZE
+#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
+#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L
+//CPC_SUSPEND_WG_STATE_OFFSET
+#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
+#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL
+//CPC_SUSPEND_CTX_SAVE_SIZE
+#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
+#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L
+//CPC_OS_PIPES
+#define CPC_OS_PIPES__OS_PIPES__SHIFT 0x0
+#define CPC_OS_PIPES__OS_PIPES_MASK 0x000000FFL
+//CP_SUSPEND_RESUME_REQ
+#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT 0x0
+#define CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT 0x1
+#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK 0x00000001L
+#define CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK 0x00000002L
+//CP_SUSPEND_CNTL
+#define CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT 0x0
+#define CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT 0x1
+#define CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT 0x2
+#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT 0x3
+#define CP_SUSPEND_CNTL__SUSPEND_MODE_MASK 0x00000001L
+#define CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK 0x00000002L
+#define CP_SUSPEND_CNTL__RESUME_LOCK_MASK 0x00000004L
+#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK 0x00000008L
+//CP_IQ_WAIT_TIME3
+#define CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT 0x0
+#define CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK 0x000000FFL
+//CPC_DDID_BASE_ADDR_LO
+#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6
+#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L
+//CP_DDID_BASE_ADDR_LO
+#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6
+#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L
+//CPC_DDID_BASE_ADDR_HI
+#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
+//CP_DDID_BASE_ADDR_HI
+#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
+//CPC_DDID_CNTL
+#define CPC_DDID_CNTL__THRESHOLD__SHIFT 0x0
+#define CPC_DDID_CNTL__SIZE__SHIFT 0x10
+#define CPC_DDID_CNTL__POLICY__SHIFT 0x1c
+#define CPC_DDID_CNTL__MODE__SHIFT 0x1e
+#define CPC_DDID_CNTL__ENABLE__SHIFT 0x1f
+#define CPC_DDID_CNTL__THRESHOLD_MASK 0x000000FFL
+#define CPC_DDID_CNTL__SIZE_MASK 0x00010000L
+#define CPC_DDID_CNTL__POLICY_MASK 0x30000000L
+#define CPC_DDID_CNTL__MODE_MASK 0x40000000L
+#define CPC_DDID_CNTL__ENABLE_MASK 0x80000000L
+//CP_DDID_CNTL
+#define CP_DDID_CNTL__THRESHOLD__SHIFT 0x0
+#define CP_DDID_CNTL__SIZE__SHIFT 0x10
+#define CP_DDID_CNTL__VMID__SHIFT 0x14
+#define CP_DDID_CNTL__VMID_SEL__SHIFT 0x18
+#define CP_DDID_CNTL__POLICY__SHIFT 0x1c
+#define CP_DDID_CNTL__MODE__SHIFT 0x1e
+#define CP_DDID_CNTL__ENABLE__SHIFT 0x1f
+#define CP_DDID_CNTL__THRESHOLD_MASK 0x000000FFL
+#define CP_DDID_CNTL__SIZE_MASK 0x00010000L
+#define CP_DDID_CNTL__VMID_MASK 0x00F00000L
+#define CP_DDID_CNTL__VMID_SEL_MASK 0x01000000L
+#define CP_DDID_CNTL__POLICY_MASK 0x30000000L
+#define CP_DDID_CNTL__MODE_MASK 0x40000000L
+#define CP_DDID_CNTL__ENABLE_MASK 0x80000000L
+//CP_GFX_DDID_INFLIGHT_COUNT
+#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0
+#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL
+//CP_GFX_DDID_WPTR
+#define CP_GFX_DDID_WPTR__COUNT__SHIFT 0x0
+#define CP_GFX_DDID_WPTR__COUNT_MASK 0x0000FFFFL
+//CP_GFX_DDID_RPTR
+#define CP_GFX_DDID_RPTR__COUNT__SHIFT 0x0
+#define CP_GFX_DDID_RPTR__COUNT_MASK 0x0000FFFFL
+//CP_GFX_DDID_DELTA_RPT_COUNT
+#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0
+#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL
+//CP_GFX_HPD_STATUS0
+#define CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
+#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
+#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
+#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT 0x10
+#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14
+#define CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT 0x1c
+#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT 0x1d
+#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT 0x1e
+#define CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f
+#define CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL
+#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L
+#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L
+#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK 0x00070000L
+#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L
+#define CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK 0x10000000L
+#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK 0x20000000L
+#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK 0x40000000L
+#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L
+//CP_GFX_HPD_CONTROL0
+#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT 0x0
+#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT 0x4
+#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK 0x00000001L
+#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK 0x00000010L
+//CP_GFX_HPD_OSPRE_FENCE_ADDR_LO
+#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
+//CP_GFX_HPD_OSPRE_FENCE_ADDR_HI
+#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT 0x10
+#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK 0xFFFF0000L
+//CP_GFX_HPD_OSPRE_FENCE_DATA_LO
+#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT 0x0
+#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL
+//CP_GFX_HPD_OSPRE_FENCE_DATA_HI
+#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT 0x0
+#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL
+//CP_GFX_INDEX_MUTEX
+#define CP_GFX_INDEX_MUTEX__REQUEST__SHIFT 0x0
+#define CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT 0x1
+#define CP_GFX_INDEX_MUTEX__REQUEST_MASK 0x00000001L
+#define CP_GFX_INDEX_MUTEX__CLIENTID_MASK 0x0000000EL
+//CP_GFX_MQD_BASE_ADDR
+#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
+#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
+//CP_GFX_MQD_BASE_ADDR_HI
+#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT 0x1c
+#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
+#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK 0xF0000000L
+//CP_GFX_HQD_ACTIVE
+#define CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_GFX_HQD_ACTIVE__ACTIVE_MASK 0x00000001L
+//CP_GFX_HQD_VMID
+#define CP_GFX_HQD_VMID__VMID__SHIFT 0x0
+#define CP_GFX_HQD_VMID__VMID_MASK 0x0000000FL
+//CP_GFX_HQD_QUEUE_PRIORITY
+#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
+#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL
+//CP_GFX_HQD_QUANTUM
+#define CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
+#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x3
+#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
+#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
+#define CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L
+#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000018L
+#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x0000FF00L
+#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L
+//CP_GFX_HQD_BASE
+#define CP_GFX_HQD_BASE__RB_BASE__SHIFT 0x0
+#define CP_GFX_HQD_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_GFX_HQD_BASE_HI
+#define CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
+//CP_GFX_HQD_RPTR
+#define CP_GFX_HQD_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_GFX_HQD_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_GFX_HQD_RPTR_ADDR
+#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_GFX_HQD_RPTR_ADDR_HI
+#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB_WPTR_POLL_ADDR_LO
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_RB_WPTR_POLL_ADDR_HI
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL
+//CP_RB_DOORBELL_CONTROL
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
+//CP_GFX_HQD_OFFSET
+#define CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f
+#define CP_GFX_HQD_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
+#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L
+//CP_GFX_HQD_CNTL
+#define CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT 0x10
+#define CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_GFX_HQD_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_GFX_HQD_CNTL__RB_EXE__SHIFT 0x1c
+#define CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT 0x1d
+#define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e
+#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_GFX_HQD_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_GFX_HQD_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_GFX_HQD_CNTL__BUF_SWAP_MASK 0x00030000L
+#define CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_GFX_HQD_CNTL__CACHE_POLICY_MASK 0x03000000L
+#define CP_GFX_HQD_CNTL__RB_VOLATILE_MASK 0x04000000L
+#define CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_GFX_HQD_CNTL__RB_EXE_MASK 0x10000000L
+#define CP_GFX_HQD_CNTL__KMD_QUEUE_MASK 0x20000000L
+#define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L
+#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_GFX_HQD_CSMD_RPTR
+#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_GFX_HQD_WPTR
+#define CP_GFX_HQD_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_GFX_HQD_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_GFX_HQD_WPTR_HI
+#define CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_GFX_HQD_DEQUEUE_REQUEST
+#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
+#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
+#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
+#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
+#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000001L
+#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L
+#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L
+#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L
+//CP_GFX_HQD_MAPPED
+#define CP_GFX_HQD_MAPPED__MAPPED__SHIFT 0x0
+#define CP_GFX_HQD_MAPPED__MAPPED_MASK 0x00000001L
+//CP_GFX_HQD_QUE_MGR_CONTROL
+#define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL__SHIFT 0x0
+#define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL_MASK 0x00FFFFFFL
+//CP_GFX_HQD_HQ_STATUS0
+#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
+#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT 0x4
+#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT 0x6
+#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e
+#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000001L
+#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK 0x00000030L
+#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK 0x00000040L
+#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L
+//CP_GFX_HQD_HQ_CONTROL0
+#define CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT 0x0
+#define CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK 0x0000000FL
+//CP_GFX_MQD_CONTROL
+#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0
+#define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
+#define CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
+#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
+#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL
+#define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L
+#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L
+#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L
+#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L
+//CP_HQD_GFX_CONTROL
+#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0
+#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4
+#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf
+#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL
+#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L
+#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L
+//CP_HQD_GFX_STATUS
+#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0
+#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL
+//CP_GFX_HQD_CE_RPTR_WR
+#define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
+#define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL
+//CP_GFX_HQD_CE_BASE
+#define CP_GFX_HQD_CE_BASE__RB_BASE__SHIFT 0x0
+#define CP_GFX_HQD_CE_BASE__RB_BASE_MASK 0xFFFFFFFFL
+//CP_GFX_HQD_CE_BASE_HI
+#define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
+//CP_GFX_HQD_CE_RPTR
+#define CP_GFX_HQD_CE_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_GFX_HQD_CE_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_GFX_HQD_CE_RPTR_ADDR
+#define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
+//CP_GFX_HQD_CE_RPTR_ADDR_HI
+#define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO
+#define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
+#define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI
+#define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
+#define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL
+//CP_GFX_HQD_CE_OFFSET
+#define CP_GFX_HQD_CE_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f
+#define CP_GFX_HQD_CE_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
+#define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L
+//CP_GFX_HQD_CE_CNTL
+#define CP_GFX_HQD_CE_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_GFX_HQD_CE_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_GFX_HQD_CE_CNTL__BUF_SWAP__SHIFT 0x10
+#define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_GFX_HQD_CE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_GFX_HQD_CE_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_GFX_HQD_CE_CNTL__RB_EXE__SHIFT 0x1c
+#define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_GFX_HQD_CE_CNTL__RB_BUFSZ_MASK 0x0000003FL
+#define CP_GFX_HQD_CE_CNTL__RB_BLKSZ_MASK 0x00003F00L
+#define CP_GFX_HQD_CE_CNTL__BUF_SWAP_MASK 0x00030000L
+#define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ_MASK 0x00300000L
+#define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
+#define CP_GFX_HQD_CE_CNTL__CACHE_POLICY_MASK 0x03000000L
+#define CP_GFX_HQD_CE_CNTL__RB_VOLATILE_MASK 0x04000000L
+#define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE_MASK 0x08000000L
+#define CP_GFX_HQD_CE_CNTL__RB_EXE_MASK 0x10000000L
+#define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
+//CP_GFX_HQD_CE_CSMD_RPTR
+#define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL
+//CP_GFX_HQD_CE_WPTR
+#define CP_GFX_HQD_CE_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_GFX_HQD_CE_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_GFX_HQD_CE_WPTR_HI
+#define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR__SHIFT 0x0
+#define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
+//CP_CE_DOORBELL_CONTROL
+#define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
+#define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_CE_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
+#define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_CE_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
+#define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
+//CP_DMA_WATCH0_ADDR_LO
+#define CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT 0x0
+#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT 0x7
+#define CP_DMA_WATCH0_ADDR_LO__RSVD_MASK 0x0000007FL
+#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L
+//CP_DMA_WATCH0_ADDR_HI
+#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT 0x10
+#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+#define CP_DMA_WATCH0_ADDR_HI__RSVD_MASK 0xFFFF0000L
+//CP_DMA_WATCH0_MASK
+#define CP_DMA_WATCH0_MASK__RSVD__SHIFT 0x0
+#define CP_DMA_WATCH0_MASK__MASK__SHIFT 0x7
+#define CP_DMA_WATCH0_MASK__RSVD_MASK 0x0000007FL
+#define CP_DMA_WATCH0_MASK__MASK_MASK 0xFFFFFF80L
+//CP_DMA_WATCH0_CNTL
+#define CP_DMA_WATCH0_CNTL__VMID__SHIFT 0x0
+#define CP_DMA_WATCH0_CNTL__RSVD1__SHIFT 0x4
+#define CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT 0x8
+#define CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT 0x9
+#define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT 0xa
+#define CP_DMA_WATCH0_CNTL__RSVD2__SHIFT 0xb
+#define CP_DMA_WATCH0_CNTL__VMID_MASK 0x0000000FL
+#define CP_DMA_WATCH0_CNTL__RSVD1_MASK 0x000000F0L
+#define CP_DMA_WATCH0_CNTL__WATCH_READS_MASK 0x00000100L
+#define CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK 0x00000200L
+#define CP_DMA_WATCH0_CNTL__ANY_VMID_MASK 0x00000400L
+#define CP_DMA_WATCH0_CNTL__RSVD2_MASK 0xFFFFF800L
+//CP_DMA_WATCH1_ADDR_LO
+#define CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT 0x0
+#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT 0x7
+#define CP_DMA_WATCH1_ADDR_LO__RSVD_MASK 0x0000007FL
+#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L
+//CP_DMA_WATCH1_ADDR_HI
+#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT 0x10
+#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+#define CP_DMA_WATCH1_ADDR_HI__RSVD_MASK 0xFFFF0000L
+//CP_DMA_WATCH1_MASK
+#define CP_DMA_WATCH1_MASK__RSVD__SHIFT 0x0
+#define CP_DMA_WATCH1_MASK__MASK__SHIFT 0x7
+#define CP_DMA_WATCH1_MASK__RSVD_MASK 0x0000007FL
+#define CP_DMA_WATCH1_MASK__MASK_MASK 0xFFFFFF80L
+//CP_DMA_WATCH1_CNTL
+#define CP_DMA_WATCH1_CNTL__VMID__SHIFT 0x0
+#define CP_DMA_WATCH1_CNTL__RSVD1__SHIFT 0x4
+#define CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT 0x8
+#define CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT 0x9
+#define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT 0xa
+#define CP_DMA_WATCH1_CNTL__RSVD2__SHIFT 0xb
+#define CP_DMA_WATCH1_CNTL__VMID_MASK 0x0000000FL
+#define CP_DMA_WATCH1_CNTL__RSVD1_MASK 0x000000F0L
+#define CP_DMA_WATCH1_CNTL__WATCH_READS_MASK 0x00000100L
+#define CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK 0x00000200L
+#define CP_DMA_WATCH1_CNTL__ANY_VMID_MASK 0x00000400L
+#define CP_DMA_WATCH1_CNTL__RSVD2_MASK 0xFFFFF800L
+//CP_DMA_WATCH2_ADDR_LO
+#define CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT 0x0
+#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT 0x7
+#define CP_DMA_WATCH2_ADDR_LO__RSVD_MASK 0x0000007FL
+#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L
+//CP_DMA_WATCH2_ADDR_HI
+#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT 0x10
+#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+#define CP_DMA_WATCH2_ADDR_HI__RSVD_MASK 0xFFFF0000L
+//CP_DMA_WATCH2_MASK
+#define CP_DMA_WATCH2_MASK__RSVD__SHIFT 0x0
+#define CP_DMA_WATCH2_MASK__MASK__SHIFT 0x7
+#define CP_DMA_WATCH2_MASK__RSVD_MASK 0x0000007FL
+#define CP_DMA_WATCH2_MASK__MASK_MASK 0xFFFFFF80L
+//CP_DMA_WATCH2_CNTL
+#define CP_DMA_WATCH2_CNTL__VMID__SHIFT 0x0
+#define CP_DMA_WATCH2_CNTL__RSVD1__SHIFT 0x4
+#define CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT 0x8
+#define CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT 0x9
+#define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT 0xa
+#define CP_DMA_WATCH2_CNTL__RSVD2__SHIFT 0xb
+#define CP_DMA_WATCH2_CNTL__VMID_MASK 0x0000000FL
+#define CP_DMA_WATCH2_CNTL__RSVD1_MASK 0x000000F0L
+#define CP_DMA_WATCH2_CNTL__WATCH_READS_MASK 0x00000100L
+#define CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK 0x00000200L
+#define CP_DMA_WATCH2_CNTL__ANY_VMID_MASK 0x00000400L
+#define CP_DMA_WATCH2_CNTL__RSVD2_MASK 0xFFFFF800L
+//CP_DMA_WATCH3_ADDR_LO
+#define CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT 0x0
+#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT 0x7
+#define CP_DMA_WATCH3_ADDR_LO__RSVD_MASK 0x0000007FL
+#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L
+//CP_DMA_WATCH3_ADDR_HI
+#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT 0x10
+#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+#define CP_DMA_WATCH3_ADDR_HI__RSVD_MASK 0xFFFF0000L
+//CP_DMA_WATCH3_MASK
+#define CP_DMA_WATCH3_MASK__RSVD__SHIFT 0x0
+#define CP_DMA_WATCH3_MASK__MASK__SHIFT 0x7
+#define CP_DMA_WATCH3_MASK__RSVD_MASK 0x0000007FL
+#define CP_DMA_WATCH3_MASK__MASK_MASK 0xFFFFFF80L
+//CP_DMA_WATCH3_CNTL
+#define CP_DMA_WATCH3_CNTL__VMID__SHIFT 0x0
+#define CP_DMA_WATCH3_CNTL__RSVD1__SHIFT 0x4
+#define CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT 0x8
+#define CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT 0x9
+#define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT 0xa
+#define CP_DMA_WATCH3_CNTL__RSVD2__SHIFT 0xb
+#define CP_DMA_WATCH3_CNTL__VMID_MASK 0x0000000FL
+#define CP_DMA_WATCH3_CNTL__RSVD1_MASK 0x000000F0L
+#define CP_DMA_WATCH3_CNTL__WATCH_READS_MASK 0x00000100L
+#define CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK 0x00000200L
+#define CP_DMA_WATCH3_CNTL__ANY_VMID_MASK 0x00000400L
+#define CP_DMA_WATCH3_CNTL__RSVD2_MASK 0xFFFFF800L
+//CP_DMA_WATCH_STAT_ADDR_LO
+#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
+//CP_DMA_WATCH_STAT_ADDR_HI
+#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_WATCH_STAT
+#define CP_DMA_WATCH_STAT__VMID__SHIFT 0x0
+#define CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT 0x8
+#define CP_DMA_WATCH_STAT__PIPE__SHIFT 0xc
+#define CP_DMA_WATCH_STAT__WATCH_ID__SHIFT 0x10
+#define CP_DMA_WATCH_STAT__RD_WR__SHIFT 0x14
+#define CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT 0x1f
+#define CP_DMA_WATCH_STAT__VMID_MASK 0x0000000FL
+#define CP_DMA_WATCH_STAT__CLIENT_ID_MASK 0x00000700L
+#define CP_DMA_WATCH_STAT__PIPE_MASK 0x00003000L
+#define CP_DMA_WATCH_STAT__WATCH_ID_MASK 0x00030000L
+#define CP_DMA_WATCH_STAT__RD_WR_MASK 0x00100000L
+#define CP_DMA_WATCH_STAT__TRAP_FLAG_MASK 0x80000000L
+//CP_PFP_JT_STAT
+#define CP_PFP_JT_STAT__JT_LOADED__SHIFT 0x0
+#define CP_PFP_JT_STAT__WR_MASK__SHIFT 0x10
+#define CP_PFP_JT_STAT__JT_LOADED_MASK 0x00000003L
+#define CP_PFP_JT_STAT__WR_MASK_MASK 0x00030000L
+//CP_CE_JT_STAT
+#define CP_CE_JT_STAT__JT_LOADED__SHIFT 0x0
+#define CP_CE_JT_STAT__WR_MASK__SHIFT 0x10
+#define CP_CE_JT_STAT__JT_LOADED_MASK 0x00000003L
+#define CP_CE_JT_STAT__WR_MASK_MASK 0x00030000L
+//CP_MEC_JT_STAT
+#define CP_MEC_JT_STAT__JT_LOADED__SHIFT 0x0
+#define CP_MEC_JT_STAT__WR_MASK__SHIFT 0x10
+#define CP_MEC_JT_STAT__JT_LOADED_MASK 0x000000FFL
+#define CP_MEC_JT_STAT__WR_MASK_MASK 0x00FF0000L
+//CP_RB_DOORBELL_CLEAR
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L
+#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L
+#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L
+#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L
+//CP_RB0_ACTIVE
+#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L
+//CP_RB_ACTIVE
+#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L
+//CP_RB1_ACTIVE
+#define CP_RB1_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_RB1_ACTIVE__ACTIVE_MASK 0x00000001L
+//CP_RB_STATUS
+#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0
+#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1
+#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
+#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
+//CPG_RCIU_CAM_INDEX
+#define CPG_RCIU_CAM_INDEX__INDEX__SHIFT 0x0
+#define CPG_RCIU_CAM_INDEX__INDEX_MASK 0x0000001FL
+//CPG_RCIU_CAM_DATA
+#define CPG_RCIU_CAM_DATA__DATA__SHIFT 0x0
+#define CPG_RCIU_CAM_DATA__DATA_MASK 0xFFFFFFFFL
+//CPG_RCIU_CAM_DATA_PHASE0
+#define CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT 0x0
+#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT 0x18
+#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT 0x19
+#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT 0x1f
+#define CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK 0x0003FFFFL
+#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK 0x01000000L
+#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK 0x02000000L
+#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK 0x80000000L
+//CPG_RCIU_CAM_DATA_PHASE1
+#define CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT 0x0
+#define CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK 0xFFFFFFFFL
+//CPG_RCIU_CAM_DATA_PHASE2
+#define CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT 0x0
+#define CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK 0xFFFFFFFFL
+//CPF_GCR_CNTL
+#define CPF_GCR_CNTL__GCR_GL_CMD__SHIFT 0x0
+#define CPF_GCR_CNTL__GCR_GL_CMD_MASK 0x0007FFFFL
+//CPG_UTCL1_STATUS
+#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//CPC_UTCL1_STATUS
+#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//CPF_UTCL1_STATUS
+#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+//CP_SD_CNTL
+#define CP_SD_CNTL__CPF_EN__SHIFT 0x0
+#define CP_SD_CNTL__CPG_EN__SHIFT 0x1
+#define CP_SD_CNTL__CPC_EN__SHIFT 0x2
+#define CP_SD_CNTL__RLC_EN__SHIFT 0x3
+#define CP_SD_CNTL__SPI_EN__SHIFT 0x4
+#define CP_SD_CNTL__GE_EN__SHIFT 0x5
+#define CP_SD_CNTL__UTCL1_EN__SHIFT 0x6
+#define CP_SD_CNTL__RMI_EN__SHIFT 0x8
+#define CP_SD_CNTL__EA_EN__SHIFT 0x9
+#define CP_SD_CNTL__SDMA_EN__SHIFT 0xa
+#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT 0x1f
+#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L
+#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L
+#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L
+#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L
+#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L
+#define CP_SD_CNTL__GE_EN_MASK 0x00000020L
+#define CP_SD_CNTL__UTCL1_EN_MASK 0x00000040L
+#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L
+#define CP_SD_CNTL__EA_EN_MASK 0x00000200L
+#define CP_SD_CNTL__SDMA_EN_MASK 0x00000400L
+#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK 0x80000000L
+//CP_SOFT_RESET_CNTL
+#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0
+#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1
+#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2
+#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3
+#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4
+#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5
+#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6
+#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L
+#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L
+#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L
+#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L
+#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L
+#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L
+#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L
+//CP_CPC_GFX_CNTL
+#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0
+#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3
+#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5
+#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7
+#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L
+#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L
+#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L
+#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L
+
+
+// addressBlock: gc_spipdec
+//SPI_ARB_PRIORITY
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L
+//SPI_ARB_CYCLES_0
+#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
+#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL
+#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L
+//SPI_ARB_CYCLES_1
+#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
+#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL
+#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L
+//SPI_WCL_PIPE_PERCENT_GFX
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L
+//SPI_WCL_PIPE_PERCENT_HP3D
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L
+//SPI_WCL_PIPE_PERCENT_CS0
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS1
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS2
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS3
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS4
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS5
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS6
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL
+//SPI_WCL_PIPE_PERCENT_CS7
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL
+//SPI_COMPUTE_QUEUE_RESET
+#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
+#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L
+//SPI_RESOURCE_RESERVE_CU_0
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_1
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_2
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_3
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_4
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_5
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_6
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_7
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_8
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_9
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_EN_CU_0
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_2
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_3
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_4
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_5
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_6
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_7
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_8
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_9
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_CU_10
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_11
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_EN_CU_10
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_11
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_CU_12
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_13
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_14
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_CU_15
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L
+#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L
+//SPI_RESOURCE_RESERVE_EN_CU_12
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_13
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_14
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_RESOURCE_RESERVE_EN_CU_15
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L
+//SPI_COMPUTE_WF_CTX_SAVE
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L
+//SPI_ARB_CNTL_0
+#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0
+#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4
+#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8
+#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL
+#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L
+#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L
+//SPI_FEATURE_CTRL
+#define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE__SHIFT 0x0
+#define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD__SHIFT 0x2
+#define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT__SHIFT 0x7
+#define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD__SHIFT 0xc
+#define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN__SHIFT 0x12
+#define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN__SHIFT 0x13
+#define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD__SHIFT 0x14
+#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT 0x1c
+#define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE_MASK 0x00000001L
+#define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD_MASK 0x0000007CL
+#define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT_MASK 0x00000F80L
+#define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD_MASK 0x0003F000L
+#define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN_MASK 0x00040000L
+#define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN_MASK 0x00080000L
+#define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_MASK 0x0FF00000L
+#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK 0xF0000000L
+//SPI_SHADER_RSRC_LIMIT_CTRL
+#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT 0x0
+#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT 0x5
+#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT 0xc
+#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT 0xd
+#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT 0x13
+#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT__SHIFT 0x14
+#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL__SHIFT 0x1c
+#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT 0x1f
+#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK 0x0000001FL
+#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK 0x00000FE0L
+#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK 0x00001000L
+#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK 0x0007E000L
+#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK 0x00080000L
+#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_MASK 0x0FF00000L
+#define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL_MASK 0x10000000L
+#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: gc_cpphqddec
+//CP_HPD_MES_ROQ_OFFSETS
+#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
+#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
+#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
+#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L
+#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L
+#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L
+//CP_HPD_ROQ_OFFSETS
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L
+//CP_HPD_STATUS0
+#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
+#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
+#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12
+#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14
+#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT 0x1b
+#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT 0x1c
+#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT 0x1e
+#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f
+#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL
+#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L
+#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L
+#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L
+#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L
+#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK 0x08000000L
+#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK 0x30000000L
+#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK 0x40000000L
+#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L
+//CP_HPD_UTCL1_CNTL
+#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0
+#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL
+//CP_HPD_UTCL1_ERROR
+#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0
+#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10
+#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14
+#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL
+#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L
+#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L
+//CP_HPD_UTCL1_ERROR_ADDR
+#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc
+#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L
+//CP_MQD_BASE_ADDR
+#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
+#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
+//CP_MQD_BASE_ADDR_HI
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_ACTIVE
+#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
+#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L
+#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L
+//CP_HQD_VMID
+#define CP_HQD_VMID__VMID__SHIFT 0x0
+#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
+#define CP_HQD_VMID__VQID__SHIFT 0x10
+#define CP_HQD_VMID__VMID_MASK 0x0000000FL
+#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L
+#define CP_HQD_VMID__VQID_MASK 0x03FF0000L
+//CP_HQD_PERSISTENT_STATE
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
+#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT 0x7
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
+#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT 0x14
+#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15
+#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16
+#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17
+#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18
+#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19
+#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a
+#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L
+#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK 0x00000080L
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L
+#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK 0x00100000L
+#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L
+#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L
+#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L
+#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L
+#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L
+#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L
+#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L
+//CP_HQD_PIPE_PRIORITY
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L
+//CP_HQD_QUEUE_PRIORITY
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL
+//CP_HQD_QUANTUM
+#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
+#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
+#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
+#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L
+#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L
+#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L
+//CP_HQD_PQ_BASE
+#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
+#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL
+//CP_HQD_PQ_BASE_HI
+#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL
+//CP_HQD_PQ_RPTR
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL
+//CP_HQD_PQ_RPTR_REPORT_ADDR
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL
+//CP_HQD_PQ_RPTR_REPORT_ADDR_HI
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_PQ_WPTR_POLL_ADDR
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L
+//CP_HQD_PQ_WPTR_POLL_ADDR_HI
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_PQ_DOORBELL_CONTROL
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
+//CP_HQD_PQ_CONTROL
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
+#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6
+#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
+#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe
+#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
+#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT 0x1d
+#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL
+#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L
+#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L
+#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L
+#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00030000L
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x000C0000L
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L
+#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x03000000L
+#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x04000000L
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L
+#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK 0x20000000L
+#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L
+//CP_HQD_IB_BASE_ADDR
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL
+//CP_HQD_IB_BASE_ADDR_HI
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_IB_RPTR
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL
+//CP_HQD_IB_CONTROL
+#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a
+#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
+#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L
+#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x03000000L
+#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x04000000L
+#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L
+//CP_HQD_IQ_TIMER
+#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
+#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
+#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a
+#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b
+#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
+#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
+#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL
+#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L
+#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x03000000L
+#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x04000000L
+#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L
+#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L
+#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L
+//CP_HQD_IQ_RPTR
+#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
+#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL
+//CP_HQD_DEQUEUE_REQUEST
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x0000000FL
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L
+//CP_HQD_DMA_OFFLOAD
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
+//CP_HQD_OFFLOAD
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L
+#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L
+//CP_HQD_SEMA_CMD
+#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
+#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
+#define CP_HQD_SEMA_CMD__POLLING_DIS__SHIFT 0x8
+#define CP_HQD_SEMA_CMD__MESSAGE_EN__SHIFT 0x9
+#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L
+#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L
+#define CP_HQD_SEMA_CMD__POLLING_DIS_MASK 0x00000100L
+#define CP_HQD_SEMA_CMD__MESSAGE_EN_MASK 0x00000200L
+//CP_HQD_MSG_TYPE
+#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
+#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
+#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L
+#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L
+//CP_HQD_ATOMIC0_PREOP_LO
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_HQD_ATOMIC0_PREOP_HI
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_HQD_ATOMIC1_PREOP_LO
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_HQD_ATOMIC1_PREOP_HI
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_SCHEDULER0
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_STATUS0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
+#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
+#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
+#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e
+#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL
+#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L
+#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L
+#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L
+#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L
+//CP_HQD_HQ_CONTROL0
+#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_SCHEDULER1
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL
+//CP_MQD_CONTROL
+#define CP_MQD_CONTROL__VMID__SHIFT 0x0
+#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
+#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
+#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a
+#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL
+#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L
+#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L
+#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L
+#define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x04000000L
+//CP_HQD_HQ_STATUS1
+#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
+#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL
+//CP_HQD_HQ_CONTROL1
+#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL
+//CP_HQD_EOP_BASE_ADDR
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//CP_HQD_EOP_BASE_ADDR_HI
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL
+//CP_HQD_EOP_CONTROL
+#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16
+#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
+#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L
+#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L
+#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x03000000L
+#define CP_HQD_EOP_CONTROL__EOP_VOLATILE_MASK 0x04000000L
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L
+//CP_HQD_EOP_RPTR
+#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
+#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c
+#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
+#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
+#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL
+#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L
+#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L
+#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L
+//CP_HQD_EOP_WPTR
+#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf
+#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
+#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL
+#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L
+#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L
+//CP_HQD_EOP_EVENTS
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L
+//CP_HQD_CTX_SAVE_BASE_ADDR_LO
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L
+//CP_HQD_CTX_SAVE_BASE_ADDR_HI
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_HQD_CTX_SAVE_CONTROL
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
+#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L
+#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L
+//CP_HQD_CNTL_STACK_OFFSET
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL
+//CP_HQD_CNTL_STACK_SIZE
+#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L
+//CP_HQD_WG_STATE_OFFSET
+#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL
+//CP_HQD_CTX_SAVE_SIZE
+#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L
+//CP_HQD_GDS_RESOURCE_STATE
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L
+//CP_HQD_ERROR
+#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
+#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
+#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5
+#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8
+#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9
+#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
+#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb
+#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc
+#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd
+#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe
+#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf
+#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10
+#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11
+#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12
+#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13
+#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
+#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L
+#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L
+#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L
+#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L
+#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L
+#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L
+#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L
+#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L
+#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L
+#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L
+#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L
+#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L
+#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L
+#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L
+//CP_HQD_EOP_WPTR_MEM
+#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL
+//CP_HQD_AQL_CONTROL
+#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0
+#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf
+#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10
+#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f
+#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL
+#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L
+#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L
+#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L
+//CP_HQD_PQ_WPTR_LO
+#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL
+//CP_HQD_PQ_WPTR_HI
+#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL
+//CP_HQD_SUSPEND_CNTL_STACK_OFFSET
+#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL
+//CP_HQD_SUSPEND_CNTL_STACK_DW_CNT
+#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT 0x0
+#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK 0x00001FFFL
+//CP_HQD_SUSPEND_WG_STATE_OFFSET
+#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL
+//CP_HQD_DDID_RPTR
+#define CP_HQD_DDID_RPTR__RPTR__SHIFT 0x0
+#define CP_HQD_DDID_RPTR__RPTR_MASK 0x000007FFL
+//CP_HQD_DDID_WPTR
+#define CP_HQD_DDID_WPTR__WPTR__SHIFT 0x0
+#define CP_HQD_DDID_WPTR__WPTR_MASK 0x000007FFL
+//CP_HQD_DDID_INFLIGHT_COUNT
+#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0
+#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL
+//CP_HQD_DDID_DELTA_RPT_COUNT
+#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0
+#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL
+//CP_HQD_DEQUEUE_STATUS
+#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT 0x0
+#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT 0x4
+#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT 0x9
+#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT 0xa
+#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK 0x0000000FL
+#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK 0x00000010L
+#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK 0x00000200L
+#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK 0x00000400L
+
+
+// addressBlock: gc_didtdec
+//DIDT_IND_INDEX
+#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
+#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL
+//DIDT_IND_DATA
+#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
+#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL
+//DIDT_INDEX_AUTO_INCR_EN
+#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0
+#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L
+
+
+// addressBlock: gc_gccacdec
+//GC_CAC_CTRL_1
+#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0
+#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18
+#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL
+#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L
+//GC_CAC_CTRL_2
+#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0
+#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1
+#define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x2
+#define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x3
+#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x4
+#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L
+#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L
+#define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000004L
+#define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000008L
+#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000010L
+//GC_CAC_AGGR_LOWER
+#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0
+#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_AGGR_UPPER
+#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0
+#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL
+//GC_CAC_SOFT_CTRL
+#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0
+#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1
+#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L
+#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL
+//GC_DIDT_CTRL0
+#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3
+#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5
+#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L
+#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L
+//GC_DIDT_CTRL1
+#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0
+#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10
+#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//GC_DIDT_CTRL2
+#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe
+#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a
+#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f
+#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L
+#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L
+#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L
+//GC_DIDT_WEIGHT
+#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0
+#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8
+#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10
+#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18
+#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL
+#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L
+#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L
+#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L
+//GC_THROTTLE_CTRL
+#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0
+#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1
+#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2
+#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT 0x3
+#define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x4
+#define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x5
+#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x6
+#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x7
+#define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x8
+#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT 0x9
+#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0xa
+#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0xb
+#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT 0xc
+#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0xd
+#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x17
+#define GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT 0x1d
+#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT 0x1e
+#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L
+#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L
+#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L
+#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK 0x00000008L
+#define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000010L
+#define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000020L
+#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000040L
+#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000080L
+#define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000100L
+#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK 0x00000200L
+#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000400L
+#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000800L
+#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK 0x00001000L
+#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK 0x007FE000L
+#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00800000L
+#define GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK 0x20000000L
+#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK 0x40000000L
+//GC_EDC_CTRL
+#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9
+#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xa
+#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xe
+#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L
+#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00003C00L
+#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00004000L
+//GC_EDC_THRESHOLD
+#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//GC_EDC_STATUS
+#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0
+#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L
+//GC_EDC_OVERFLOW
+#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12
+#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L
+//GC_EDC_ROLLING_POWER_DELTA
+#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//GC_THROTTLE_CTRL1
+#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa
+#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0xd
+#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0xe
+#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x12
+#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x17
+#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L
+#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L
+#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00002000L
+#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0003C000L
+#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK 0x007C0000L
+#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x03800000L
+//GC_THROTTLE_STATUS
+#define GC_THROTTLE_STATUS__FSM_STATE__SHIFT 0x0
+#define GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT 0x4
+#define GC_THROTTLE_STATUS__FSM_STATE_MASK 0x0000000FL
+#define GC_THROTTLE_STATUS__PATTERN_INDEX_MASK 0x000003F0L
+//EDC_PERF_COUNTER
+#define EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0
+#define EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL
+//PCC_PERF_COUNTER
+#define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0
+#define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL
+//PWRBRK_PERF_COUNTER
+#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0
+#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL
+//GC_CAC_IND_INDEX
+#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0
+#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL
+//GC_CAC_IND_DATA
+#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0
+#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL
+//SE_CAC_IND_INDEX
+#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0
+#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL
+//SE_CAC_IND_DATA
+#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0
+#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_tcpdec
+//TCP_WATCH0_ADDR_H
+#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH0_ADDR_L
+#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x7
+#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFF80L
+//TCP_WATCH0_CNTL
+#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH0_CNTL__MASK_MASK 0x007FFFFFL
+#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L
+//TCP_WATCH1_ADDR_H
+#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH1_ADDR_L
+#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x7
+#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFF80L
+//TCP_WATCH1_CNTL
+#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH1_CNTL__MASK_MASK 0x007FFFFFL
+#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L
+//TCP_WATCH2_ADDR_H
+#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH2_ADDR_L
+#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x7
+#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFF80L
+//TCP_WATCH2_CNTL
+#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH2_CNTL__MASK_MASK 0x007FFFFFL
+#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L
+//TCP_WATCH3_ADDR_H
+#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL
+//TCP_WATCH3_ADDR_L
+#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x7
+#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFF80L
+//TCP_WATCH3_CNTL
+#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH3_CNTL__MASK_MASK 0x007FFFFFL
+#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L
+#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L
+#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L
+//TCP_CNTL2
+#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
+#define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT 0x8
+#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT 0x9
+#define TCP_CNTL2__TCPI_WRITE_DATA_MGCG_DISABLE__SHIFT 0xa
+#define TCP_CNTL2__TCPI_INNER_BLOCK_MGCG_DISABLE__SHIFT 0xb
+#define TCP_CNTL2__TCPI_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT 0xc
+#define TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT 0xd
+#define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT 0xe
+#define TCP_CNTL2__RETURN_ORDER_OVERRIDE__SHIFT 0xf
+#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL
+#define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK 0x00000100L
+#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK 0x00000200L
+#define TCP_CNTL2__TCPI_WRITE_DATA_MGCG_DISABLE_MASK 0x00000400L
+#define TCP_CNTL2__TCPI_INNER_BLOCK_MGCG_DISABLE_MASK 0x00000800L
+#define TCP_CNTL2__TCPI_ADRS_IMG_CALC_MGCG_DISABLE_MASK 0x00001000L
+#define TCP_CNTL2__V64_COMBINE_ENABLE_MASK 0x00002000L
+#define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK 0x00004000L
+#define TCP_CNTL2__RETURN_ORDER_OVERRIDE_MASK 0x00008000L
+//TCP_UTCL0_CNTL1
+#define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
+#define TCP_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
+#define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
+#define TCP_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3
+#define TCP_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
+#define TCP_UTCL0_CNTL1__CLIENTID__SHIFT 0x7
+#define TCP_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13
+#define TCP_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
+#define TCP_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
+#define TCP_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define TCP_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a
+#define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
+#define TCP_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
+#define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
+#define TCP_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L
+#define TCP_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
+#define TCP_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L
+#define TCP_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L
+#define TCP_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
+#define TCP_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
+#define TCP_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
+#define TCP_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L
+#define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
+#define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
+//TCP_UTCL0_CNTL2
+#define TCP_UTCL0_CNTL2__SPARE__SHIFT 0x0
+#define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
+#define TCP_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa
+#define TCP_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
+#define TCP_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe
+#define TCP_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
+#define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
+#define TCP_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b
+#define TCP_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c
+#define TCP_UTCL0_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d
+#define TCP_UTCL0_CNTL2__SPARE_MASK 0x000000FFL
+#define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
+#define TCP_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L
+#define TCP_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
+#define TCP_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L
+#define TCP_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
+#define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
+#define TCP_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L
+#define TCP_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L
+#define TCP_UTCL0_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L
+//TCP_UTCL0_STATUS
+#define TCP_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define TCP_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define TCP_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2
+#define TCP_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define TCP_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define TCP_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L
+//TCP_PERFCOUNTER_FILTER
+#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0
+#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1
+#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2
+#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5
+#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xd
+#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0x11
+#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x16
+#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x18
+#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1b
+#define TCP_PERFCOUNTER_FILTER__DLC__SHIFT 0x1c
+#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x1d
+#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1e
+#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L
+#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L
+#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL
+#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x00000FE0L
+#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x0001E000L
+#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x003E0000L
+#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00C00000L
+#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x07000000L
+#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x08000000L
+#define TCP_PERFCOUNTER_FILTER__DLC_MASK 0x10000000L
+#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x20000000L
+#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x40000000L
+//TCP_PERFCOUNTER_FILTER_EN
+#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0
+#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1
+#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2
+#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4
+#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6
+#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7
+#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x8
+#define TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT 0x9
+#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0xa
+#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xb
+#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT 0xc
+#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L
+#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L
+#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L
+#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L
+#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L
+#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L
+#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L
+#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000100L
+#define TCP_PERFCOUNTER_FILTER_EN__DLC_MASK 0x00000200L
+#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000400L
+#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000800L
+#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK 0x00001000L
+//TCP_PERFCOUNTER_FILTER2
+#define TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT 0x0
+#define TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK 0x00000007L
+
+
+// addressBlock: gc_gdspdec
+//GDS_VMID0_BASE
+#define GDS_VMID0_BASE__BASE__SHIFT 0x0
+#define GDS_VMID0_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID0_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID0_SIZE
+#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID0_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID0_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID1_BASE
+#define GDS_VMID1_BASE__BASE__SHIFT 0x0
+#define GDS_VMID1_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID1_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID1_SIZE
+#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID1_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID1_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID2_BASE
+#define GDS_VMID2_BASE__BASE__SHIFT 0x0
+#define GDS_VMID2_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID2_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID2_SIZE
+#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID2_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID2_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID3_BASE
+#define GDS_VMID3_BASE__BASE__SHIFT 0x0
+#define GDS_VMID3_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID3_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID3_SIZE
+#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID3_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID3_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID4_BASE
+#define GDS_VMID4_BASE__BASE__SHIFT 0x0
+#define GDS_VMID4_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID4_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID4_SIZE
+#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID4_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID4_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID5_BASE
+#define GDS_VMID5_BASE__BASE__SHIFT 0x0
+#define GDS_VMID5_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID5_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID5_SIZE
+#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID5_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID5_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID6_BASE
+#define GDS_VMID6_BASE__BASE__SHIFT 0x0
+#define GDS_VMID6_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID6_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID6_SIZE
+#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID6_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID6_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID7_BASE
+#define GDS_VMID7_BASE__BASE__SHIFT 0x0
+#define GDS_VMID7_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID7_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID7_SIZE
+#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID7_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID7_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID8_BASE
+#define GDS_VMID8_BASE__BASE__SHIFT 0x0
+#define GDS_VMID8_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID8_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID8_SIZE
+#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID8_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID8_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID9_BASE
+#define GDS_VMID9_BASE__BASE__SHIFT 0x0
+#define GDS_VMID9_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID9_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID9_SIZE
+#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID9_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID9_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID10_BASE
+#define GDS_VMID10_BASE__BASE__SHIFT 0x0
+#define GDS_VMID10_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID10_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID10_SIZE
+#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID10_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID10_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID11_BASE
+#define GDS_VMID11_BASE__BASE__SHIFT 0x0
+#define GDS_VMID11_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID11_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID11_SIZE
+#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID11_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID11_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID12_BASE
+#define GDS_VMID12_BASE__BASE__SHIFT 0x0
+#define GDS_VMID12_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID12_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID12_SIZE
+#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID12_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID12_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID13_BASE
+#define GDS_VMID13_BASE__BASE__SHIFT 0x0
+#define GDS_VMID13_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID13_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID13_SIZE
+#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID13_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID13_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID14_BASE
+#define GDS_VMID14_BASE__BASE__SHIFT 0x0
+#define GDS_VMID14_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID14_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID14_SIZE
+#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID14_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID14_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_VMID15_BASE
+#define GDS_VMID15_BASE__BASE__SHIFT 0x0
+#define GDS_VMID15_BASE__UNUSED__SHIFT 0x10
+#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_VMID15_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_VMID15_SIZE
+#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID15_SIZE__UNUSED__SHIFT 0x11
+#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL
+#define GDS_VMID15_SIZE__UNUSED_MASK 0xFFFE0000L
+//GDS_GWS_VMID0
+#define GDS_GWS_VMID0__BASE__SHIFT 0x0
+#define GDS_GWS_VMID0__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID0__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID0__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID0__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID1
+#define GDS_GWS_VMID1__BASE__SHIFT 0x0
+#define GDS_GWS_VMID1__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID1__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID1__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID1__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID2
+#define GDS_GWS_VMID2__BASE__SHIFT 0x0
+#define GDS_GWS_VMID2__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID2__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID2__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID2__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID3
+#define GDS_GWS_VMID3__BASE__SHIFT 0x0
+#define GDS_GWS_VMID3__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID3__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID3__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID3__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID4
+#define GDS_GWS_VMID4__BASE__SHIFT 0x0
+#define GDS_GWS_VMID4__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID4__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID4__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID4__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID5
+#define GDS_GWS_VMID5__BASE__SHIFT 0x0
+#define GDS_GWS_VMID5__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID5__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID5__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID5__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID6
+#define GDS_GWS_VMID6__BASE__SHIFT 0x0
+#define GDS_GWS_VMID6__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID6__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID6__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID6__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID7
+#define GDS_GWS_VMID7__BASE__SHIFT 0x0
+#define GDS_GWS_VMID7__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID7__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID7__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID7__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID8
+#define GDS_GWS_VMID8__BASE__SHIFT 0x0
+#define GDS_GWS_VMID8__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID8__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID8__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID8__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID9
+#define GDS_GWS_VMID9__BASE__SHIFT 0x0
+#define GDS_GWS_VMID9__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID9__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID9__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID9__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID10
+#define GDS_GWS_VMID10__BASE__SHIFT 0x0
+#define GDS_GWS_VMID10__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID10__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID10__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID10__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID11
+#define GDS_GWS_VMID11__BASE__SHIFT 0x0
+#define GDS_GWS_VMID11__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID11__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID11__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID11__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID12
+#define GDS_GWS_VMID12__BASE__SHIFT 0x0
+#define GDS_GWS_VMID12__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID12__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID12__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID12__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID13
+#define GDS_GWS_VMID13__BASE__SHIFT 0x0
+#define GDS_GWS_VMID13__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID13__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID13__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID13__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID14
+#define GDS_GWS_VMID14__BASE__SHIFT 0x0
+#define GDS_GWS_VMID14__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID14__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID14__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID14__UNUSED2_MASK 0xFF800000L
+//GDS_GWS_VMID15
+#define GDS_GWS_VMID15__BASE__SHIFT 0x0
+#define GDS_GWS_VMID15__UNUSED1__SHIFT 0x6
+#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID15__UNUSED2__SHIFT 0x17
+#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL
+#define GDS_GWS_VMID15__UNUSED1_MASK 0x0000FFC0L
+#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L
+#define GDS_GWS_VMID15__UNUSED2_MASK 0xFF800000L
+//GDS_OA_VMID0
+#define GDS_OA_VMID0__MASK__SHIFT 0x0
+#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID1
+#define GDS_OA_VMID1__MASK__SHIFT 0x0
+#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID2
+#define GDS_OA_VMID2__MASK__SHIFT 0x0
+#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID3
+#define GDS_OA_VMID3__MASK__SHIFT 0x0
+#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID4
+#define GDS_OA_VMID4__MASK__SHIFT 0x0
+#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID5
+#define GDS_OA_VMID5__MASK__SHIFT 0x0
+#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID6
+#define GDS_OA_VMID6__MASK__SHIFT 0x0
+#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID7
+#define GDS_OA_VMID7__MASK__SHIFT 0x0
+#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID8
+#define GDS_OA_VMID8__MASK__SHIFT 0x0
+#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID9
+#define GDS_OA_VMID9__MASK__SHIFT 0x0
+#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID10
+#define GDS_OA_VMID10__MASK__SHIFT 0x0
+#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID11
+#define GDS_OA_VMID11__MASK__SHIFT 0x0
+#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID12
+#define GDS_OA_VMID12__MASK__SHIFT 0x0
+#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID13
+#define GDS_OA_VMID13__MASK__SHIFT 0x0
+#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID14
+#define GDS_OA_VMID14__MASK__SHIFT 0x0
+#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_VMID15
+#define GDS_OA_VMID15__MASK__SHIFT 0x0
+#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL
+#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L
+//GDS_GWS_RESET0
+#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
+#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
+#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
+#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
+#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
+#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
+#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
+#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
+#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
+#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
+#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
+#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
+#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
+#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
+#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
+#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
+#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
+#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
+#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
+#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
+#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
+#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
+#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
+#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
+#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
+#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
+#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
+#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L
+#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L
+#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L
+#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L
+#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L
+#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L
+#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L
+#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L
+#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L
+#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L
+#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L
+#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L
+#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L
+#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L
+#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L
+#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L
+#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L
+#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L
+#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L
+#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L
+#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L
+#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L
+#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L
+#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L
+#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L
+#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L
+#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L
+#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L
+#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L
+#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L
+#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L
+#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L
+//GDS_GWS_RESET1
+#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
+#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
+#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
+#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
+#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
+#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
+#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
+#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
+#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
+#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
+#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
+#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
+#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
+#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
+#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
+#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
+#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
+#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
+#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
+#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
+#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
+#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
+#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
+#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
+#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
+#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
+#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
+#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L
+#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L
+#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L
+#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L
+#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L
+#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L
+#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L
+#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L
+#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L
+#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L
+#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L
+#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L
+#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L
+#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L
+#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L
+#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L
+#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L
+#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L
+#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L
+#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L
+#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L
+#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L
+#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L
+#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L
+#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L
+#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L
+#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L
+#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L
+#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L
+#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L
+#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L
+#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L
+//GDS_GWS_RESOURCE_RESET
+#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
+#define GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT 0x10
+#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L
+#define GDS_GWS_RESOURCE_RESET__UNUSED_MASK 0xFFFF0000L
+//GDS_COMPUTE_MAX_WAVE_ID
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT 0xc
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
+#define GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK 0xFFFFF000L
+//GDS_OA_RESET_MASK
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
+#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
+#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L
+#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L
+#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L
+//GDS_OA_RESET
+#define GDS_OA_RESET__RESET__SHIFT 0x0
+#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
+#define GDS_OA_RESET__UNUSED__SHIFT 0x10
+#define GDS_OA_RESET__RESET_MASK 0x00000001L
+#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L
+#define GDS_OA_RESET__UNUSED_MASK 0xFFFF0000L
+//GDS_ENHANCE2
+#define GDS_ENHANCE2__MISC__SHIFT 0x0
+#define GDS_ENHANCE2__RD_BUF_TAG_MISS__SHIFT 0x12
+#define GDS_ENHANCE2__GDSA_PC_CGTS_DIS__SHIFT 0x13
+#define GDS_ENHANCE2__GDSO_PC_CGTS_DIS__SHIFT 0x14
+#define GDS_ENHANCE2__WD_GDS_CSB_OVERRIDE__SHIFT 0x15
+#define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS__SHIFT 0x16
+#define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP__SHIFT 0x17
+#define GDS_ENHANCE2__UNUSED__SHIFT 0x18
+#define GDS_ENHANCE2__MISC_MASK 0x0003FFFFL
+#define GDS_ENHANCE2__RD_BUF_TAG_MISS_MASK 0x00040000L
+#define GDS_ENHANCE2__GDSA_PC_CGTS_DIS_MASK 0x00080000L
+#define GDS_ENHANCE2__GDSO_PC_CGTS_DIS_MASK 0x00100000L
+#define GDS_ENHANCE2__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L
+#define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MASK 0x00400000L
+#define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP_MASK 0x00800000L
+#define GDS_ENHANCE2__UNUSED_MASK 0xFF000000L
+//GDS_OA_CGPG_RESTORE
+#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
+#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
+#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
+#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
+#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
+#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL
+#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L
+#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L
+#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L
+#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L
+//GDS_CS_CTXSW_STATUS
+#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L
+#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L
+#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
+//GDS_CS_CTXSW_CNT0
+#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_CS_CTXSW_CNT1
+#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_CS_CTXSW_CNT2
+#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_CS_CTXSW_CNT3
+#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_GFX_CTXSW_STATUS
+#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L
+#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L
+#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
+//GDS_VS_CTXSW_CNT0
+#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_VS_CTXSW_CNT1
+#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_VS_CTXSW_CNT2
+#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_VS_CTXSW_CNT3
+#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS_CTXSW_CNT0
+#define GDS_PS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_PS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_PS_CTXSW_CNT1
+#define GDS_PS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_PS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_PS_CTXSW_CNT2
+#define GDS_PS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_PS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_PS_CTXSW_CNT3
+#define GDS_PS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_PS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+//GDS_PS_CTXSW_IDX
+#define GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT 0x0
+#define GDS_PS_CTXSW_IDX__UNUSED__SHIFT 0x4
+#define GDS_PS_CTXSW_IDX__PACKER_ID_MASK 0x0000000FL
+#define GDS_PS_CTXSW_IDX__UNUSED_MASK 0xFFFFFFF0L
+//GDS_GS_CTXSW_CNT0
+#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT1
+#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT2
+#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
+//GDS_GS_CTXSW_CNT3
+#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
+#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_gfxdec0
+//DB_RENDER_CONTROL
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
+#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
+#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
+#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
+#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L
+#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L
+#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L
+#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L
+#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L
+//DB_COUNT_CONTROL
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
+#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x2
+#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x3
+#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
+#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
+#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L
+#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000004L
+#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000008L
+#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L
+#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L
+#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L
+//DB_DEPTH_VIEW
+#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
+#define DB_DEPTH_VIEW__SLICE_START_HI__SHIFT 0xb
+#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
+#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
+#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a
+#define DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT 0x1e
+#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL
+#define DB_DEPTH_VIEW__SLICE_START_HI_MASK 0x00001800L
+#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L
+#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L
+#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L
+#define DB_DEPTH_VIEW__SLICE_MAX_HI_MASK 0xC0000000L
+//DB_RENDER_OVERRIDE
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L
+//DB_RENDER_OVERRIDE2
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
+#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L
+#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L
+//DB_HTILE_DATA_BASE
+#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
+#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_DEPTH_SIZE_XY
+#define DB_DEPTH_SIZE_XY__X_MAX__SHIFT 0x0
+#define DB_DEPTH_SIZE_XY__Y_MAX__SHIFT 0x10
+#define DB_DEPTH_SIZE_XY__X_MAX_MASK 0x00003FFFL
+#define DB_DEPTH_SIZE_XY__Y_MAX_MASK 0x3FFF0000L
+//DB_DEPTH_BOUNDS_MIN
+#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
+#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL
+//DB_DEPTH_BOUNDS_MAX
+#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
+#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL
+//DB_STENCIL_CLEAR
+#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
+#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL
+//DB_DEPTH_CLEAR
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL
+//PA_SC_SCREEN_SCISSOR_TL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_SCISSOR_BR
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L
+//DB_DFSM_CONTROL
+#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0
+#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2
+#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3
+#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L
+#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L
+#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L
+//DB_RESERVED_REG_2
+#define DB_RESERVED_REG_2__FIELD_1__SHIFT 0x0
+#define DB_RESERVED_REG_2__FIELD_2__SHIFT 0x4
+#define DB_RESERVED_REG_2__FIELD_3__SHIFT 0x8
+#define DB_RESERVED_REG_2__FIELD_4__SHIFT 0xd
+#define DB_RESERVED_REG_2__FIELD_5__SHIFT 0xf
+#define DB_RESERVED_REG_2__FIELD_6__SHIFT 0x11
+#define DB_RESERVED_REG_2__FIELD_7__SHIFT 0x13
+#define DB_RESERVED_REG_2__FIELD_8__SHIFT 0x1c
+#define DB_RESERVED_REG_2__FIELD_1_MASK 0x0000000FL
+#define DB_RESERVED_REG_2__FIELD_2_MASK 0x000000F0L
+#define DB_RESERVED_REG_2__FIELD_3_MASK 0x00001F00L
+#define DB_RESERVED_REG_2__FIELD_4_MASK 0x00006000L
+#define DB_RESERVED_REG_2__FIELD_5_MASK 0x00018000L
+#define DB_RESERVED_REG_2__FIELD_6_MASK 0x00060000L
+#define DB_RESERVED_REG_2__FIELD_7_MASK 0x00180000L
+#define DB_RESERVED_REG_2__FIELD_8_MASK 0xF0000000L
+//DB_Z_INFO
+#define DB_Z_INFO__FORMAT__SHIFT 0x0
+#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
+#define DB_Z_INFO__SW_MODE__SHIFT 0x4
+#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0x9
+#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xb
+#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
+#define DB_Z_INFO__RESERVED_FIELD_1__SHIFT 0xd
+#define DB_Z_INFO__MAXMIP__SHIFT 0x10
+#define DB_Z_INFO__ITERATE_256__SHIFT 0x14
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
+#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
+#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
+#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
+#define DB_Z_INFO__FORMAT_MASK 0x00000003L
+#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL
+#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L
+#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00000600L
+#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00000800L
+#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
+#define DB_Z_INFO__RESERVED_FIELD_1_MASK 0x0000E000L
+#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L
+#define DB_Z_INFO__ITERATE_256_MASK 0x00100000L
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L
+#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
+#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L
+#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L
+#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L
+//DB_STENCIL_INFO
+#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
+#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4
+#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0x9
+#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xb
+#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
+#define DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT 0xd
+#define DB_STENCIL_INFO__ITERATE_256__SHIFT 0x14
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
+#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L
+#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L
+#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00000600L
+#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00000800L
+#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
+#define DB_STENCIL_INFO__RESERVED_FIELD_1_MASK 0x0000E000L
+#define DB_STENCIL_INFO__ITERATE_256_MASK 0x00100000L
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L
+//DB_Z_READ_BASE
+#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_STENCIL_READ_BASE
+#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_Z_WRITE_BASE
+#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_STENCIL_WRITE_BASE
+#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//DB_RESERVED_REG_1
+#define DB_RESERVED_REG_1__FIELD_1__SHIFT 0x0
+#define DB_RESERVED_REG_1__FIELD_2__SHIFT 0xb
+#define DB_RESERVED_REG_1__FIELD_1_MASK 0x000007FFL
+#define DB_RESERVED_REG_1__FIELD_2_MASK 0x003FF800L
+//DB_RESERVED_REG_3
+#define DB_RESERVED_REG_3__FIELD_1__SHIFT 0x0
+#define DB_RESERVED_REG_3__FIELD_1_MASK 0x003FFFFFL
+//DB_Z_READ_BASE_HI
+#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_STENCIL_READ_BASE_HI
+#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_Z_WRITE_BASE_HI
+#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_STENCIL_WRITE_BASE_HI
+#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_HTILE_DATA_BASE_HI
+#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0
+#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL
+//DB_RMI_L2_CACHE_CONTROL
+#define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT 0x0
+#define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT 0x2
+#define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT 0x4
+#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT 0x6
+#define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT 0x10
+#define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT 0x12
+#define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT 0x14
+#define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT 0x18
+#define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT 0x19
+#define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK 0x00000003L
+#define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK 0x0000000CL
+#define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK 0x00000030L
+#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK 0x000000C0L
+#define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK 0x00030000L
+#define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK 0x000C0000L
+#define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK 0x00300000L
+#define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK 0x01000000L
+#define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK 0x02000000L
+//TA_BC_BASE_ADDR
+#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
+//TA_BC_BASE_ADDR_HI
+#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_0
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_1
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_2
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_HI_3
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL
+//COHER_DEST_BASE_2
+#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//COHER_DEST_BASE_3
+#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//PA_SC_WINDOW_OFFSET
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L
+//PA_SC_WINDOW_SCISSOR_TL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_WINDOW_SCISSOR_BR
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_RULE
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL
+//PA_SC_CLIPRECT_0_TL
+#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_0_BR
+#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_1_TL
+#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_1_BR
+#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_2_TL
+#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_2_BR
+#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_3_TL
+#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L
+//PA_SC_CLIPRECT_3_BR
+#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_EDGERULE
+#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
+#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
+#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
+#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
+#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
+#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
+#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
+#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL
+#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L
+#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L
+#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L
+#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L
+#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L
+#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L
+//PA_SU_HARDWARE_SCREEN_OFFSET
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L
+//CB_TARGET_MASK
+#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
+#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
+#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
+#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
+#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
+#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
+#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
+#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
+#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL
+#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L
+#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L
+#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L
+#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L
+#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L
+#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L
+#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L
+//CB_SHADER_MASK
+#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
+#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
+#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
+#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
+#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
+#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
+#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
+#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
+#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL
+#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L
+#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L
+#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L
+#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L
+#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L
+#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L
+#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L
+//PA_SC_GENERIC_SCISSOR_TL
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_GENERIC_SCISSOR_BR
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
+//COHER_DEST_BASE_0
+#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//COHER_DEST_BASE_1
+#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_SCISSOR_0_TL
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_0_BR
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_1_TL
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_1_BR
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_2_TL
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_2_BR
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_3_TL
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_3_BR
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_4_TL
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_4_BR
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_5_TL
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_5_BR
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_6_TL
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_6_BR
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_7_TL
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_7_BR
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_8_TL
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_8_BR
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_9_TL
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_9_BR
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_10_TL
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_10_BR
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_11_TL
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_11_BR
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_12_TL
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_12_BR
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_13_TL
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_13_BR
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_14_TL
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_14_BR
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_SCISSOR_15_TL
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
+//PA_SC_VPORT_SCISSOR_15_BR
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L
+//PA_SC_VPORT_ZMIN_0
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_0
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_1
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_1
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_2
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_2
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_3
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_3
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_4
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_4
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_5
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_5
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_6
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_6
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_7
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_7
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_8
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_8
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_9
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_9
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_10
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_10
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_11
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_11
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_12
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_12
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_13
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_13
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_14
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_14
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMIN_15
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL
+//PA_SC_VPORT_ZMAX_15
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL
+//PA_SC_RASTER_CONFIG
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
+#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
+#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
+#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
+#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
+#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
+#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
+#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
+#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
+#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
+#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
+#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL
+#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L
+#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L
+#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L
+#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L
+#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L
+#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L
+#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L
+#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L
+#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L
+#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L
+#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0C000000L
+#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L
+//PA_SC_RASTER_CONFIG_1
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000CL
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L
+//PA_SC_SCREEN_EXTENT_CONTROL
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL
+//PA_SC_TILE_STEERING_OVERRIDE
+#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5
+#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT 0xc
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT 0x10
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT 0x14
+#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L
+#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK 0x00003000L
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK 0x00030000L
+#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK 0x00100000L
+//CP_PERFMON_CNTX_CNTL
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
+//CP_PIPEID
+#define CP_PIPEID__PIPE_ID__SHIFT 0x0
+#define CP_PIPEID__PIPE_ID_MASK 0x00000003L
+//CP_RINGID
+#define CP_RINGID__RINGID__SHIFT 0x0
+#define CP_RINGID__RINGID_MASK 0x00000003L
+//CP_VMID
+#define CP_VMID__VMID__SHIFT 0x0
+#define CP_VMID__VMID_MASK 0x0000000FL
+//PA_SC_RIGHT_VERT_GRID
+#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0
+#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
+#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
+#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
+#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
+//PA_SC_LEFT_VERT_GRID
+#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0
+#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8
+#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
+#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
+#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
+#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
+#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
+#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
+//PA_SC_HORIZ_GRID
+#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0
+#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8
+#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10
+#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18
+#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL
+#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L
+#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L
+#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L
+//VGT_MAX_VTX_INDX
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL
+//VGT_MIN_VTX_INDX
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL
+//VGT_INDX_OFFSET
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL
+//VGT_MULTI_PRIM_IB_RESET_INDX
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL
+//CB_RMI_GL2_CACHE_CONTROL
+#define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT 0x0
+#define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT 0x2
+#define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT 0x4
+#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x6
+#define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT 0x10
+#define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT 0x12
+#define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT 0x14
+#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16
+#define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE__SHIFT 0x1e
+#define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE__SHIFT 0x1f
+#define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK 0x00000003L
+#define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK 0x0000000CL
+#define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK 0x00000030L
+#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x000000C0L
+#define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK 0x00030000L
+#define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK 0x000C0000L
+#define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK 0x00300000L
+#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L
+#define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE_MASK 0x40000000L
+#define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE_MASK 0x80000000L
+//CB_BLEND_RED
+#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
+#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL
+//CB_BLEND_GREEN
+#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
+#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL
+//CB_BLEND_BLUE
+#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
+#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL
+//CB_BLEND_ALPHA
+#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
+#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL
+//CB_DCC_CONTROL
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa
+#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc
+#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd
+#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L
+#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L
+#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L
+#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L
+#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L
+//CB_COVERAGE_OUT_CONTROL
+#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE__SHIFT 0x0
+#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT__SHIFT 0x1
+#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL__SHIFT 0x4
+#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES__SHIFT 0x8
+#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE_MASK 0x00000001L
+#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT_MASK 0x0000000EL
+#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL_MASK 0x00000030L
+#define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES_MASK 0x00000F00L
+//DB_STENCIL_CONTROL
+#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
+#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
+#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
+#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL
+#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L
+#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L
+//DB_STENCILREFMASK
+#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
+#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
+#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
+#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
+#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL
+#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L
+#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L
+#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L
+//DB_STENCILREFMASK_BF
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L
+//PA_CL_VPORT_XSCALE
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_1
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_1
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_1
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_1
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_1
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_1
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_2
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_2
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_2
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_2
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_2
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_2
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_3
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_3
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_3
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_3
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_3
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_3
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_4
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_4
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_4
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_4
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_4
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_4
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_5
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_5
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_5
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_5
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_5
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_5
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_6
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_6
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_6
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_6
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_6
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_6
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_7
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_7
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_7
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_7
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_7
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_7
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_8
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_8
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_8
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_8
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_8
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_8
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_9
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_9
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_9
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_9
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_9
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_9
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_10
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_10
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_10
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_10
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_10
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_10
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_11
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_11
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_11
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_11
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_11
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_11
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_12
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_12
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_12
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_12
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_12
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_12
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_13
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_13
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_13
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_13
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_13
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_13
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_14
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_14
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_14
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_14
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_14
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_14
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XSCALE_15
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_XOFFSET_15
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YSCALE_15
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_YOFFSET_15
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZSCALE_15
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL
+//PA_CL_VPORT_ZOFFSET_15
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_X
+#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_Y
+#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_Z
+#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_0_W
+#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_X
+#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_Y
+#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_Z
+#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_1_W
+#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_X
+#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_Y
+#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_Z
+#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_2_W
+#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_X
+#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_Y
+#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_Z
+#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_3_W
+#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_X
+#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_Y
+#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_Z
+#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_4_W
+#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_X
+#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_Y
+#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_Z
+#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_UCP_5_W
+#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_PROG_NEAR_CLIP_Z
+#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
+//SPI_PS_INPUT_CNTL_0
+#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_1
+#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_2
+#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_3
+#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_4
+#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_5
+#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_6
+#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_7
+#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_8
+#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_9
+#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_10
+#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_11
+#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_12
+#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_13
+#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_14
+#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_15
+#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_16
+#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_17
+#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_18
+#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_19
+#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L
+#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_20
+#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_21
+#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_22
+#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_23
+#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_24
+#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_25
+#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_26
+#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_27
+#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_28
+#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_29
+#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_30
+#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L
+//SPI_PS_INPUT_CNTL_31
+#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L
+#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L
+//SPI_VS_OUT_CONFIG
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
+#define SPI_VS_OUT_CONFIG__NO_PC_EXPORT__SHIFT 0x7
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L
+#define SPI_VS_OUT_CONFIG__NO_PC_EXPORT_MASK 0x00000080L
+//SPI_PS_INPUT_ENA
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L
+//SPI_PS_INPUT_ADDR
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L
+//SPI_INTERP_CONTROL_0
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L
+//SPI_PS_IN_CONTROL
+#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
+#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
+#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7
+#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
+#define SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT 0xf
+#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL
+#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L
+#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L
+#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L
+#define SPI_PS_IN_CONTROL__PS_W32_EN_MASK 0x00008000L
+//SPI_BARYC_CNTL
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L
+//SPI_TMPRING_SIZE
+#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
+#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
+//SPI_SHADER_IDX_FORMAT
+#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK 0x0000000FL
+//SPI_SHADER_POS_FORMAT
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT 0x10
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L
+#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK 0x000F0000L
+//SPI_SHADER_Z_FORMAT
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL
+//SPI_SHADER_COL_FORMAT
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L
+//SX_PS_DOWNCONVERT
+#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0
+#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4
+#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8
+#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc
+#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10
+#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14
+#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18
+#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c
+#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL
+#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L
+#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L
+#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L
+#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L
+#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L
+#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L
+#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L
+//SX_BLEND_OPT_EPSILON
+#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0
+#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4
+#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8
+#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc
+#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10
+#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14
+#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18
+#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c
+#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL
+#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L
+#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L
+#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L
+#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L
+#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L
+#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L
+#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L
+//SX_BLEND_OPT_CONTROL
+#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0
+#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1
+#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4
+#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5
+#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8
+#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9
+#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc
+#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd
+#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10
+#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11
+#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14
+#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15
+#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18
+#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19
+#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c
+#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d
+#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f
+#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L
+#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L
+#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L
+#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L
+#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L
+#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L
+#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L
+#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L
+#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L
+#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L
+#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L
+#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L
+#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L
+#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L
+#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L
+#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L
+#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L
+//SX_MRT0_BLEND_OPT
+#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT1_BLEND_OPT
+#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT2_BLEND_OPT
+#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT3_BLEND_OPT
+#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT4_BLEND_OPT
+#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT5_BLEND_OPT
+#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT6_BLEND_OPT
+#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//SX_MRT7_BLEND_OPT
+#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
+#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
+#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
+#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
+#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
+#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
+#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
+#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
+#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
+#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
+#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
+#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
+//CB_BLEND0_CONTROL
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND1_CONTROL
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND2_CONTROL
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND3_CONTROL
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND4_CONTROL
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND5_CONTROL
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND6_CONTROL
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CB_BLEND7_CONTROL
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
+#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
+#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
+//CS_COPY_STATE
+#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
+//GFX_COPY_STATE
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
+//PA_CL_POINT_X_RAD
+#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_POINT_Y_RAD
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_POINT_SIZE
+#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_POINT_CULL_RAD
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
+//VGT_DMA_BASE_HI
+#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL
+//VGT_DMA_BASE
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL
+//VGT_DRAW_INITIATOR
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
+#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
+#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
+#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7
+#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8
+#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L
+#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L
+#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L
+#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L
+#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L
+#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L
+//VGT_IMMED_DATA
+#define VGT_IMMED_DATA__DATA__SHIFT 0x0
+#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL
+//VGT_EVENT_ADDRESS_REG
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL
+//GE_MAX_OUTPUT_PER_SUBGROUP
+#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT 0x0
+#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK 0x000003FFL
+//DB_DEPTH_CONTROL
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
+#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
+#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
+#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L
+#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L
+#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L
+#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L
+//DB_EQAA
+#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
+#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
+#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
+#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
+#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
+#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L
+#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L
+#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L
+#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L
+#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L
+//CB_COLOR_CONTROL
+#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
+#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
+#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
+#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
+#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
+#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L
+//DB_SHADER_CONTROL
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
+#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
+#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
+#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf
+#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10
+#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11
+#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14
+#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT 0x17
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L
+#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L
+#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L
+#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L
+#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L
+#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L
+#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L
+#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK 0x00800000L
+//PA_CL_CLIP_CNTL
+#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
+#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
+#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
+#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
+#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
+#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
+#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c
+#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L
+#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L
+#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L
+#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L
+#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L
+#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L
+#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L
+//PA_SU_SC_MODE_CNTL
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
+#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16
+#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17
+#define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT 0x18
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L
+#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L
+#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L
+#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L
+#define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK 0x01000000L
+//PA_CL_VTE_CNTL
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L
+//PA_CL_VS_OUT_CNTL
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
+#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1a
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1b
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x04000000L
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x08000000L
+//PA_CL_NANINF_CNTL
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L
+//PA_SU_LINE_STIPPLE_CNTL
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L
+//PA_SU_LINE_STIPPLE_SCALE
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL
+//PA_SU_PRIM_FILTER_CNTL
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L
+//PA_SU_SMALL_PRIM_FILTER_CNTL
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT 0x6
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L
+#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK 0x00000040L
+//PA_CL_OBJPRIM_ID_CNTL
+#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0
+#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1
+#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L
+#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L
+//PA_CL_NGG_CNTL
+#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0
+#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1
+#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L
+#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L
+//PA_SU_OVER_RASTERIZATION_CNTL
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3
+#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L
+#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L
+#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L
+//PA_STEREO_CNTL
+#define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1
+#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5
+#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8
+#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0x10
+#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0x13
+#define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL
+#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L
+#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000F00L
+#define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00070000L
+#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x00780000L
+//PA_STATE_STEREO_X
+#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0
+#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL
+//PA_SU_POINT_SIZE
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
+#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL
+#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L
+//PA_SU_POINT_MINMAX
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L
+//PA_SU_LINE_CNTL
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
+#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL
+//PA_SC_LINE_STIPPLE
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L
+//VGT_OUTPUT_PATH_CNTL
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L
+//VGT_HOS_CNTL
+#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
+#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L
+//VGT_HOS_MAX_TESS_LEVEL
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL
+//VGT_HOS_MIN_TESS_LEVEL
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL
+//VGT_HOS_REUSE_DEPTH
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL
+//VGT_GROUP_PRIM_TYPE
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L
+//VGT_GROUP_FIRST_DECR
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL
+//VGT_GROUP_DECR
+#define VGT_GROUP_DECR__DECR__SHIFT 0x0
+#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL
+//VGT_GROUP_VECT_0_CNTL
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L
+#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L
+#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L
+//VGT_GROUP_VECT_1_CNTL
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L
+#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L
+#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L
+//VGT_GROUP_VECT_0_FMT_CNTL
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
+//VGT_GROUP_VECT_1_FMT_CNTL
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
+//VGT_GS_MODE
+#define VGT_GS_MODE__MODE__SHIFT 0x0
+#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
+#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
+#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
+#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
+#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
+#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
+#define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0xe
+#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0xf
+#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x10
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
+#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
+#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
+#define VGT_GS_MODE__MODE_MASK 0x00000007L
+#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L
+#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L
+#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L
+#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L
+#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L
+#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L
+#define VGT_GS_MODE__COMPUTE_MODE_MASK 0x00004000L
+#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x00008000L
+#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x00010000L
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L
+#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L
+#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L
+//VGT_GS_ONCHIP_CNTL
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
+#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L
+#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L
+//PA_SC_MODE_CNTL_0
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
+#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4
+#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5
+#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L
+#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L
+#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L
+#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L
+//PA_SC_MODE_CNTL_1
+#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
+#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L
+//VGT_ENHANCE
+#define VGT_ENHANCE__MISC__SHIFT 0x0
+#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL
+//VGT_GS_PER_ES
+#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
+#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL
+//VGT_ES_PER_GS
+#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
+#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL
+//VGT_GS_PER_VS
+#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
+#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL
+//VGT_GSVS_RING_OFFSET_1
+#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL
+//VGT_GSVS_RING_OFFSET_2
+#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL
+//VGT_GSVS_RING_OFFSET_3
+#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL
+//VGT_GS_OUT_PRIM_TYPE
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L
+//IA_ENHANCE
+#define IA_ENHANCE__MISC__SHIFT 0x0
+#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL
+//VGT_DMA_SIZE
+#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
+#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL
+//VGT_DMA_MAX_SIZE
+#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
+#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL
+//VGT_DMA_INDEX_TYPE
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
+#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8
+#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
+#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
+#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000C0L
+#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x00000100L
+#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L
+#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L
+#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x00003800L
+//WD_ENHANCE
+#define WD_ENHANCE__MISC__SHIFT 0x0
+#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL
+//VGT_PRIMITIVEID_EN
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
+#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L
+#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L
+//VGT_DMA_NUM_INSTANCES
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
+//VGT_PRIMITIVEID_RESET
+#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
+#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL
+//VGT_EVENT_INITIATOR
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
+#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
+#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
+//VGT_MULTI_PRIM_IB_RESET_EN
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L
+#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L
+//VGT_DRAW_PAYLOAD_CNTL
+#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0
+#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1
+#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x2
+#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT 0x3
+#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT 0x4
+#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L
+#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L
+#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000004L
+#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK 0x00000008L
+#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK 0x00000010L
+//VGT_INSTANCE_STEP_RATE_0
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL
+//VGT_INSTANCE_STEP_RATE_1
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL
+//IA_MULTI_VGT_PARAM
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L
+//VGT_ESGS_RING_ITEMSIZE
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GSVS_RING_ITEMSIZE
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
+//VGT_REUSE_OFF
+#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
+#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L
+//VGT_VTX_CNT_EN
+#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
+#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L
+//DB_HTILE_SURFACE
+#define DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT 0x0
+#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
+#define DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT 0x2
+#define DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT 0x3
+#define DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT 0x4
+#define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT 0xa
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
+#define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT 0x11
+#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12
+#define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK 0x00000001L
+#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L
+#define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK 0x00000004L
+#define DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK 0x00000008L
+#define DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK 0x000003F0L
+#define DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK 0x0000FC00L
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L
+#define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK 0x00020000L
+#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L
+//DB_SRESULTS_COMPARE_STATE0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L
+//DB_SRESULTS_COMPARE_STATE1
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L
+//DB_PRELOAD_CONTROL
+#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
+#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
+#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
+#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
+#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL
+#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L
+#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L
+#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L
+//VGT_STRMOUT_BUFFER_SIZE_0
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_0
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_0
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_SIZE_1
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_1
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_1
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_SIZE_2
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_2
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_2
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_SIZE_3
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_VTX_STRIDE_3
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL
+//VGT_STRMOUT_BUFFER_OFFSET_3
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_DRAW_OPAQUE_OFFSET
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL
+//VGT_GS_MAX_VERT_OUT
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL
+//GE_NGG_SUBGRP_CNTL
+#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT 0x0
+#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT 0x9
+#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK 0x000001FFL
+#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK 0x0003FE00L
+//VGT_TESS_DISTRIBUTION
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
+#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L
+#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L
+//VGT_SHADER_STAGES_EN
+#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
+#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
+#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
+#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
+#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
+#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
+#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd
+#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe
+#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf
+#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13
+#define VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT 0x15
+#define VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT 0x16
+#define VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT 0x17
+#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT 0x18
+#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT 0x19
+#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L
+#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L
+#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L
+#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L
+#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L
+#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L
+#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L
+#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L
+#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L
+#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L
+#define VGT_SHADER_STAGES_EN__HS_W32_EN_MASK 0x00200000L
+#define VGT_SHADER_STAGES_EN__GS_W32_EN_MASK 0x00400000L
+#define VGT_SHADER_STAGES_EN__VS_W32_EN_MASK 0x00800000L
+#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK 0x01000000L
+#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK 0x02000000L
+//VGT_LS_HS_CONFIG
+#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
+#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L
+//VGT_GS_VERT_ITEMSIZE
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GS_VERT_ITEMSIZE_1
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GS_VERT_ITEMSIZE_2
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL
+//VGT_GS_VERT_ITEMSIZE_3
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL
+//VGT_TF_PARAM
+#define VGT_TF_PARAM__TYPE__SHIFT 0x0
+#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
+#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
+#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
+#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
+#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
+#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
+#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
+#define VGT_TF_PARAM__DETECT_ONE__SHIFT 0x13
+#define VGT_TF_PARAM__DETECT_ZERO__SHIFT 0x14
+#define VGT_TF_PARAM__MTYPE__SHIFT 0x17
+#define VGT_TF_PARAM__TYPE_MASK 0x00000003L
+#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL
+#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L
+#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L
+#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003C00L
+#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L
+#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00018000L
+#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L
+#define VGT_TF_PARAM__DETECT_ONE_MASK 0x00080000L
+#define VGT_TF_PARAM__DETECT_ZERO_MASK 0x00100000L
+#define VGT_TF_PARAM__MTYPE_MASK 0x03800000L
+//DB_ALPHA_TO_MASK
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L
+//VGT_DISPATCH_DRAW_INDEX
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_DB_FMT_CNTL
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L
+//PA_SU_POLY_OFFSET_CLAMP
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_FRONT_SCALE
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_FRONT_OFFSET
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_BACK_SCALE
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL
+//PA_SU_POLY_OFFSET_BACK_OFFSET
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL
+//VGT_GS_INSTANCE_CNT
+#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
+#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
+#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT 0x1f
+#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L
+#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL
+#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK 0x80000000L
+//VGT_STRMOUT_CONFIG
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
+#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
+#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L
+#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L
+//VGT_STRMOUT_BUFFER_CONFIG
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L
+//VGT_DMA_EVENT_INITIATOR
+#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
+#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
+#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
+#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
+#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
+#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
+//PA_SC_CENTROID_PRIORITY_0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L
+//PA_SC_CENTROID_PRIORITY_1
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L
+//PA_SC_LINE_CNTL
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
+#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT 0xd
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L
+#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK 0x00002000L
+//PA_SC_AA_CONFIG
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
+#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L
+#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L
+//PA_SU_VTX_CNTL
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L
+//PA_CL_GB_VERT_CLIP_ADJ
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_GB_VERT_DISC_ADJ
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_GB_HORZ_CLIP_ADJ
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_CL_GB_HORZ_DISC_ADJ
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L
+//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L
+//PA_SC_AA_MASK_X0Y0_X1Y0
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L
+//PA_SC_AA_MASK_X0Y1_X1Y1
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L
+//PA_SC_SHADER_CONTROL
+#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0
+#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2
+#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3
+#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT 0x5
+#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L
+#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L
+#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L
+#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK 0x00000060L
+//PA_SC_BINNER_CNTL_0
+#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7
+#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
+#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd
+#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12
+#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13
+#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b
+#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c
+#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT 0x1d
+#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L
+#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L
+#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L
+#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L
+#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L
+#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L
+#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L
+#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L
+#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK 0x60000000L
+//PA_SC_BINNER_CNTL_1
+#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0
+#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10
+#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL
+#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L
+//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT 0x19
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT 0x1b
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK 0x06000000L
+#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK 0x18000000L
+//PA_SC_NGG_MODE_CNTL
+#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0
+#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT 0x10
+#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL
+#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L
+//VGT_VERTEX_REUSE_BLOCK_CNTL
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL
+//VGT_OUT_DEALLOC_CNTL
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL
+//CB_COLOR0_BASE
+#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_PITCH
+#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007FFL
+#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L
+//CB_COLOR0_SLICE
+#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR0_VIEW
+#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x1a
+#define CB_COLOR0_VIEW__SLICE_START_MASK 0x00001FFFL
+#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x03FFE000L
+#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x3C000000L
+//CB_COLOR0_INFO
+#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR0_INFO__ALT_TILE_MODE__SHIFT 0x1f
+#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L
+#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+#define CB_COLOR0_INFO__ALT_TILE_MODE_MASK 0x80000000L
+//CB_COLOR0_ATTRIB
+#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12
+#define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13
+#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL
+#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L
+#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L
+#define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L
+//CB_COLOR0_DCC_CONTROL
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L
+//CB_COLOR0_CMASK
+#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_CMASK_SLICE
+#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL
+//CB_COLOR0_FMASK
+#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_FMASK_SLICE
+#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR0_CLEAR_WORD0
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR0_CLEAR_WORD1
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR0_DCC_BASE
+#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_BASE
+#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_PITCH
+#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007FFL
+#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L
+//CB_COLOR1_SLICE
+#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR1_VIEW
+#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x1a
+#define CB_COLOR1_VIEW__SLICE_START_MASK 0x00001FFFL
+#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x03FFE000L
+#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x3C000000L
+//CB_COLOR1_INFO
+#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR1_INFO__ALT_TILE_MODE__SHIFT 0x1f
+#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L
+#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+#define CB_COLOR1_INFO__ALT_TILE_MODE_MASK 0x80000000L
+//CB_COLOR1_ATTRIB
+#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12
+#define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13
+#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL
+#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L
+#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L
+#define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L
+//CB_COLOR1_DCC_CONTROL
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L
+//CB_COLOR1_CMASK
+#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_CMASK_SLICE
+#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL
+//CB_COLOR1_FMASK
+#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR1_FMASK_SLICE
+#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR1_CLEAR_WORD0
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR1_CLEAR_WORD1
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR1_DCC_BASE
+#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_BASE
+#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_PITCH
+#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007FFL
+#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L
+//CB_COLOR2_SLICE
+#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR2_VIEW
+#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x1a
+#define CB_COLOR2_VIEW__SLICE_START_MASK 0x00001FFFL
+#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x03FFE000L
+#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x3C000000L
+//CB_COLOR2_INFO
+#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR2_INFO__ALT_TILE_MODE__SHIFT 0x1f
+#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L
+#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+#define CB_COLOR2_INFO__ALT_TILE_MODE_MASK 0x80000000L
+//CB_COLOR2_ATTRIB
+#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12
+#define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13
+#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL
+#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L
+#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L
+#define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L
+//CB_COLOR2_DCC_CONTROL
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L
+//CB_COLOR2_CMASK
+#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_CMASK_SLICE
+#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL
+//CB_COLOR2_FMASK
+#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR2_FMASK_SLICE
+#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR2_CLEAR_WORD0
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR2_CLEAR_WORD1
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR2_DCC_BASE
+#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_BASE
+#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_PITCH
+#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007FFL
+#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L
+//CB_COLOR3_SLICE
+#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR3_VIEW
+#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x1a
+#define CB_COLOR3_VIEW__SLICE_START_MASK 0x00001FFFL
+#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x03FFE000L
+#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x3C000000L
+//CB_COLOR3_INFO
+#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR3_INFO__ALT_TILE_MODE__SHIFT 0x1f
+#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L
+#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+#define CB_COLOR3_INFO__ALT_TILE_MODE_MASK 0x80000000L
+//CB_COLOR3_ATTRIB
+#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12
+#define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13
+#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL
+#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L
+#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L
+#define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L
+//CB_COLOR3_DCC_CONTROL
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L
+//CB_COLOR3_CMASK
+#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_CMASK_SLICE
+#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL
+//CB_COLOR3_FMASK
+#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR3_FMASK_SLICE
+#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR3_CLEAR_WORD0
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR3_CLEAR_WORD1
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR3_DCC_BASE
+#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_BASE
+#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_PITCH
+#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007FFL
+#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L
+//CB_COLOR4_SLICE
+#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR4_VIEW
+#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x1a
+#define CB_COLOR4_VIEW__SLICE_START_MASK 0x00001FFFL
+#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x03FFE000L
+#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x3C000000L
+//CB_COLOR4_INFO
+#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR4_INFO__ALT_TILE_MODE__SHIFT 0x1f
+#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L
+#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+#define CB_COLOR4_INFO__ALT_TILE_MODE_MASK 0x80000000L
+//CB_COLOR4_ATTRIB
+#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12
+#define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13
+#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL
+#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L
+#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L
+#define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L
+//CB_COLOR4_DCC_CONTROL
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L
+//CB_COLOR4_CMASK
+#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_CMASK_SLICE
+#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL
+//CB_COLOR4_FMASK
+#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR4_FMASK_SLICE
+#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR4_CLEAR_WORD0
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR4_CLEAR_WORD1
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR4_DCC_BASE
+#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_BASE
+#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_PITCH
+#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007FFL
+#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L
+//CB_COLOR5_SLICE
+#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR5_VIEW
+#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x1a
+#define CB_COLOR5_VIEW__SLICE_START_MASK 0x00001FFFL
+#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x03FFE000L
+#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x3C000000L
+//CB_COLOR5_INFO
+#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR5_INFO__ALT_TILE_MODE__SHIFT 0x1f
+#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L
+#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+#define CB_COLOR5_INFO__ALT_TILE_MODE_MASK 0x80000000L
+//CB_COLOR5_ATTRIB
+#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12
+#define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13
+#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL
+#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L
+#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L
+#define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L
+//CB_COLOR5_DCC_CONTROL
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L
+//CB_COLOR5_CMASK
+#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_CMASK_SLICE
+#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL
+//CB_COLOR5_FMASK
+#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR5_FMASK_SLICE
+#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR5_CLEAR_WORD0
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR5_CLEAR_WORD1
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR5_DCC_BASE
+#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_BASE
+#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_PITCH
+#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007FFL
+#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L
+//CB_COLOR6_SLICE
+#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR6_VIEW
+#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x1a
+#define CB_COLOR6_VIEW__SLICE_START_MASK 0x00001FFFL
+#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x03FFE000L
+#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x3C000000L
+//CB_COLOR6_INFO
+#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR6_INFO__ALT_TILE_MODE__SHIFT 0x1f
+#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L
+#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+#define CB_COLOR6_INFO__ALT_TILE_MODE_MASK 0x80000000L
+//CB_COLOR6_ATTRIB
+#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12
+#define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13
+#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL
+#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L
+#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L
+#define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L
+//CB_COLOR6_DCC_CONTROL
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L
+//CB_COLOR6_CMASK
+#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_CMASK_SLICE
+#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL
+//CB_COLOR6_FMASK
+#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR6_FMASK_SLICE
+#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR6_CLEAR_WORD0
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR6_CLEAR_WORD1
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR6_DCC_BASE
+#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_BASE
+#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_PITCH
+#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007FFL
+#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L
+//CB_COLOR7_SLICE
+#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR7_VIEW
+#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x1a
+#define CB_COLOR7_VIEW__SLICE_START_MASK 0x00001FFFL
+#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x03FFE000L
+#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x3C000000L
+//CB_COLOR7_INFO
+#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR7_INFO__ALT_TILE_MODE__SHIFT 0x1f
+#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
+#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL
+#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L
+#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
+#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
+#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
+#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
+#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
+#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
+#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
+#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
+#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
+#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
+#define CB_COLOR7_INFO__ALT_TILE_MODE_MASK 0x80000000L
+//CB_COLOR7_ATTRIB
+#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12
+#define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13
+#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL
+#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L
+#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
+#define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L
+#define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L
+//CB_COLOR7_DCC_CONTROL
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
+#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
+#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
+#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
+#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L
+//CB_COLOR7_CMASK
+#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_CMASK_SLICE
+#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL
+//CB_COLOR7_FMASK
+#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR7_FMASK_SLICE
+#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL
+//CB_COLOR7_CLEAR_WORD0
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
+//CB_COLOR7_CLEAR_WORD1
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
+//CB_COLOR7_DCC_BASE
+#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
+//CB_COLOR0_BASE_EXT
+#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_BASE_EXT
+#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_BASE_EXT
+#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_BASE_EXT
+#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_BASE_EXT
+#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_BASE_EXT
+#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_BASE_EXT
+#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_BASE_EXT
+#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_CMASK_BASE_EXT
+#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_CMASK_BASE_EXT
+#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_CMASK_BASE_EXT
+#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_CMASK_BASE_EXT
+#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_CMASK_BASE_EXT
+#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_CMASK_BASE_EXT
+#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_CMASK_BASE_EXT
+#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_CMASK_BASE_EXT
+#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_FMASK_BASE_EXT
+#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_FMASK_BASE_EXT
+#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_FMASK_BASE_EXT
+#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_FMASK_BASE_EXT
+#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_FMASK_BASE_EXT
+#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_FMASK_BASE_EXT
+#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_FMASK_BASE_EXT
+#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_FMASK_BASE_EXT
+#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_DCC_BASE_EXT
+#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR1_DCC_BASE_EXT
+#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR2_DCC_BASE_EXT
+#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR3_DCC_BASE_EXT
+#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR4_DCC_BASE_EXT
+#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR5_DCC_BASE_EXT
+#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR6_DCC_BASE_EXT
+#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR7_DCC_BASE_EXT
+#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
+//CB_COLOR0_ATTRIB2
+#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR1_ATTRIB2
+#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR2_ATTRIB2
+#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR3_ATTRIB2
+#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR4_ATTRIB2
+#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR5_ATTRIB2
+#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR6_ATTRIB2
+#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR7_ATTRIB2
+#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
+#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
+#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c
+#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
+#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
+#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L
+//CB_COLOR0_ATTRIB3
+#define CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR0_ATTRIB3__META_LINEAR__SHIFT 0xd
+#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe
+#define CB_COLOR0_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13
+#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18
+#define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a
+#define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b
+#define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e
+#define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL
+#define CB_COLOR0_ATTRIB3__META_LINEAR_MASK 0x00002000L
+#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L
+#define CB_COLOR0_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L
+#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L
+#define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L
+#define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L
+#define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L
+//CB_COLOR1_ATTRIB3
+#define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT 0xd
+#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe
+#define CB_COLOR1_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13
+#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18
+#define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a
+#define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b
+#define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e
+#define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL
+#define CB_COLOR1_ATTRIB3__META_LINEAR_MASK 0x00002000L
+#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L
+#define CB_COLOR1_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L
+#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L
+#define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L
+#define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L
+#define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L
+//CB_COLOR2_ATTRIB3
+#define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT 0xd
+#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe
+#define CB_COLOR2_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13
+#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18
+#define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a
+#define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b
+#define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e
+#define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL
+#define CB_COLOR2_ATTRIB3__META_LINEAR_MASK 0x00002000L
+#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L
+#define CB_COLOR2_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L
+#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L
+#define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L
+#define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L
+#define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L
+//CB_COLOR3_ATTRIB3
+#define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT 0xd
+#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe
+#define CB_COLOR3_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13
+#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18
+#define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a
+#define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b
+#define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e
+#define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL
+#define CB_COLOR3_ATTRIB3__META_LINEAR_MASK 0x00002000L
+#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L
+#define CB_COLOR3_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L
+#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L
+#define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L
+#define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L
+#define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L
+//CB_COLOR4_ATTRIB3
+#define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT 0xd
+#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe
+#define CB_COLOR4_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13
+#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18
+#define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a
+#define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b
+#define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e
+#define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL
+#define CB_COLOR4_ATTRIB3__META_LINEAR_MASK 0x00002000L
+#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L
+#define CB_COLOR4_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L
+#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L
+#define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L
+#define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L
+#define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L
+//CB_COLOR5_ATTRIB3
+#define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT 0xd
+#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe
+#define CB_COLOR5_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13
+#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18
+#define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a
+#define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b
+#define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e
+#define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL
+#define CB_COLOR5_ATTRIB3__META_LINEAR_MASK 0x00002000L
+#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L
+#define CB_COLOR5_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L
+#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L
+#define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L
+#define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L
+#define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L
+//CB_COLOR6_ATTRIB3
+#define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT 0xd
+#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe
+#define CB_COLOR6_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13
+#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18
+#define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a
+#define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b
+#define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e
+#define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL
+#define CB_COLOR6_ATTRIB3__META_LINEAR_MASK 0x00002000L
+#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L
+#define CB_COLOR6_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L
+#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L
+#define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L
+#define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L
+#define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L
+//CB_COLOR7_ATTRIB3
+#define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT 0x0
+#define CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT 0xd
+#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe
+#define CB_COLOR7_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13
+#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18
+#define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a
+#define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b
+#define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e
+#define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL
+#define CB_COLOR7_ATTRIB3__META_LINEAR_MASK 0x00002000L
+#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L
+#define CB_COLOR7_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L
+#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L
+#define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L
+#define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L
+#define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L
+
+
+// addressBlock: gc_gfxudec
+//CP_EOP_DONE_ADDR_LO
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
+//CP_EOP_DONE_ADDR_HI
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_EOP_DONE_DATA_LO
+#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
+#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL
+//CP_EOP_DONE_DATA_HI
+#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
+#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL
+//CP_EOP_LAST_FENCE_LO
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL
+//CP_EOP_LAST_FENCE_HI
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL
+//CP_STREAM_OUT_ADDR_LO
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_STREAM_OUT_ADDR_HI
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT0_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT0_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT0_LO
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT0_HI
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT1_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT1_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT1_LO
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT1_HI
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT2_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT2_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT2_LO
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT2_HI
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT3_LO
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_WRITTEN_COUNT3_HI
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT3_LO
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL
+//CP_NUM_PRIM_NEEDED_COUNT3_HI
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL
+//CP_PIPE_STATS_ADDR_LO
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_PIPE_STATS_ADDR_HI
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL
+//CP_VGT_IAVERT_COUNT_LO
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_IAVERT_COUNT_HI
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_IAPRIM_COUNT_LO
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_IAPRIM_COUNT_HI
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_GSPRIM_COUNT_LO
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_GSPRIM_COUNT_HI
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_VSINVOC_COUNT_LO
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_VSINVOC_COUNT_HI
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_GSINVOC_COUNT_LO
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_GSINVOC_COUNT_HI
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_HSINVOC_COUNT_LO
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_HSINVOC_COUNT_HI
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_VGT_DSINVOC_COUNT_LO
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_DSINVOC_COUNT_HI
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_PA_CINVOC_COUNT_LO
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_PA_CINVOC_COUNT_HI
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_PA_CPRIM_COUNT_LO
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_PA_CPRIM_COUNT_HI
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT0_LO
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT0_HI
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT1_LO
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_SC_PSINVOC_COUNT1_HI
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL
+//CP_VGT_CSINVOC_COUNT_LO
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
+//CP_VGT_CSINVOC_COUNT_HI
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
+//CP_EOP_DONE_DOORBELL
+#define CP_EOP_DONE_DOORBELL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_EOP_DONE_DOORBELL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+//CP_STREAM_OUT_DOORBELL
+#define CP_STREAM_OUT_DOORBELL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_STREAM_OUT_DOORBELL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+//CP_SEM_DOORBELL
+#define CP_SEM_DOORBELL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_SEM_DOORBELL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+//CP_PIPE_STATS_CONTROL
+#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19
+#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x06000000L
+//CP_STREAM_OUT_CONTROL
+#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19
+#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x06000000L
+//CP_STRMOUT_CNTL
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L
+//SCRATCH_REG0
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
+//SCRATCH_REG1
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
+//SCRATCH_REG2
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
+//SCRATCH_REG3
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
+//SCRATCH_REG4
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
+//SCRATCH_REG5
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
+//SCRATCH_REG6
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
+//SCRATCH_REG7
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
+//CP_PIPE_STATS_DOORBELL
+#define CP_PIPE_STATS_DOORBELL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_PIPE_STATS_DOORBELL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+//CP_APPEND_DDID_CNT
+#define CP_APPEND_DDID_CNT__DATA__SHIFT 0x0
+#define CP_APPEND_DDID_CNT__DATA_MASK 0x000000FFL
+//CP_APPEND_DATA_HI
+#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0
+#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_CS_FENCE_HI
+#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_PS_FENCE_HI
+#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
+//SCRATCH_UMSK
+#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
+#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
+#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL
+#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L
+//SCRATCH_ADDR
+#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
+#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL
+//CP_PFP_ATOMIC_PREOP_LO
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_PFP_ATOMIC_PREOP_HI
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC0_PREOP_LO
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC0_PREOP_HI
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC1_PREOP_LO
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_PFP_GDS_ATOMIC1_PREOP_HI
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_APPEND_ADDR_LO
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL
+//CP_APPEND_ADDR_HI
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
+#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
+#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
+#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL
+#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L
+#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x06000000L
+#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L
+//CP_APPEND_DATA
+#define CP_APPEND_DATA__DATA__SHIFT 0x0
+#define CP_APPEND_DATA__DATA_MASK 0xFFFFFFFFL
+//CP_APPEND_DATA_LO
+#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0
+#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_CS_FENCE
+#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_CS_FENCE_LO
+#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_PS_FENCE
+#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_APPEND_LAST_PS_FENCE_LO
+#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
+//CP_ATOMIC_PREOP_LO
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ME_ATOMIC_PREOP_LO
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ATOMIC_PREOP_HI
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_ATOMIC_PREOP_HI
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC0_PREOP_LO
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC0_PREOP_LO
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC0_PREOP_HI
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC0_PREOP_HI
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC1_PREOP_LO
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC1_PREOP_LO
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
+//CP_GDS_ATOMIC1_PREOP_HI
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_GDS_ATOMIC1_PREOP_HI
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
+//CP_ME_MC_WADDR_LO
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL
+//CP_ME_MC_WADDR_HI
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00C00000L
+//CP_ME_MC_WDATA_LO
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL
+//CP_ME_MC_WDATA_HI
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL
+//CP_ME_MC_RADDR_LO
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL
+//CP_ME_MC_RADDR_HI
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00C00000L
+//CP_SEM_WAIT_TIMER
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL
+//CP_SIG_SEM_ADDR_LO
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
+//CP_SIG_SEM_ADDR_HI
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
+//CP_WAIT_REG_MEM_TIMEOUT
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL
+//CP_WAIT_SEM_ADDR_LO
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
+//CP_WAIT_SEM_ADDR_HI
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
+//CP_DMA_PFP_CONTROL
+#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_PFP_CONTROL__SRC_VOLATLE__SHIFT 0xf
+#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_PFP_CONTROL__DST_VOLATLE__SHIFT 0x1b
+#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L
+#define CP_DMA_PFP_CONTROL__SRC_VOLATLE_MASK 0x00008000L
+#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L
+#define CP_DMA_PFP_CONTROL__DST_VOLATLE_MASK 0x08000000L
+#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L
+//CP_DMA_ME_CONTROL
+#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_ME_CONTROL__SRC_VOLATLE__SHIFT 0xf
+#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_ME_CONTROL__DST_VOLATLE__SHIFT 0x1b
+#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L
+#define CP_DMA_ME_CONTROL__SRC_VOLATLE_MASK 0x00008000L
+#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L
+#define CP_DMA_ME_CONTROL__DST_VOLATLE_MASK 0x08000000L
+#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L
+//CP_COHER_BASE_HI
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
+//CP_COHER_START_DELAY
+#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
+#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL
+//CP_COHER_CNTL
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
+#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4
+#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
+#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
+#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
+#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
+#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L
+#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L
+#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
+#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
+#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
+#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
+#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L
+//CP_COHER_SIZE
+#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
+#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
+//CP_COHER_BASE
+#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
+#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
+//CP_COHER_STATUS
+#define CP_COHER_STATUS__MEID__SHIFT 0x18
+#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
+#define CP_COHER_STATUS__MEID_MASK 0x03000000L
+#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
+//CP_DMA_ME_SRC_ADDR
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_ME_SRC_ADDR_HI
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_ME_DST_ADDR
+#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_ME_DST_ADDR_HI
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_ME_COMMAND
+#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f
+#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
+#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
+#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
+#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
+#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
+#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
+#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L
+//CP_DMA_PFP_SRC_ADDR
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_PFP_SRC_ADDR_HI
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_PFP_DST_ADDR
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
+//CP_DMA_PFP_DST_ADDR_HI
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
+//CP_DMA_PFP_COMMAND
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
+#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
+#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
+#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
+#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
+#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
+#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L
+//CP_DMA_CNTL
+#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0
+#define CP_DMA_CNTL__WATCH_CONTROL__SHIFT 0x1
+#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
+#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
+#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
+#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
+#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L
+#define CP_DMA_CNTL__WATCH_CONTROL_MASK 0x00000002L
+#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
+#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x01FF0000L
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
+#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
+#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L
+//CP_DMA_READ_TAGS
+#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
+//CP_COHER_SIZE_HI
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
+//CP_PFP_IB_CONTROL
+#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
+#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL
+//CP_PFP_LOAD_CONTROL
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
+//CP_SCRATCH_INDEX
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L
+//CP_SCRATCH_DATA
+#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
+//CP_RB_OFFSET
+#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
+//CP_IB1_OFFSET
+#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
+//CP_IB2_OFFSET
+#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
+//CP_IB1_PREAMBLE_BEGIN
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL
+//CP_IB1_PREAMBLE_END
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL
+//CP_IB2_PREAMBLE_BEGIN
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL
+//CP_IB2_PREAMBLE_END
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL
+//CP_CE_IB1_OFFSET
+#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
+//CP_CE_IB2_OFFSET
+#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
+//CP_CE_COUNTER
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
+//CP_DMA_ME_CMD_ADDR_LO
+#define CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT 0x0
+#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK 0x00000003L
+#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
+//CP_DMA_ME_CMD_ADDR_HI
+#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT 0x10
+#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+#define CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L
+//CP_DMA_PFP_CMD_ADDR_LO
+#define CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT 0x0
+#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK 0x00000003L
+#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
+//CP_DMA_PFP_CMD_ADDR_HI
+#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT 0x10
+#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+#define CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L
+//CP_APPEND_CMD_ADDR_LO
+#define CP_APPEND_CMD_ADDR_LO__RSVD__SHIFT 0x0
+#define CP_APPEND_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_APPEND_CMD_ADDR_LO__RSVD_MASK 0x00000003L
+#define CP_APPEND_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
+//CP_APPEND_CMD_ADDR_HI
+#define CP_APPEND_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_APPEND_CMD_ADDR_HI__RSVD__SHIFT 0x10
+#define CP_APPEND_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+#define CP_APPEND_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L
+//CP_CE_INIT_CMD_BUFSZ
+#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL
+//CP_CE_IB1_CMD_BUFSZ
+#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_CE_IB2_CMD_BUFSZ
+#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_IB1_CMD_BUFSZ
+#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
+#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_IB2_CMD_BUFSZ
+#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
+#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_ST_CMD_BUFSZ
+#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0
+#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_CE_INIT_BASE_LO
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L
+//CP_CE_INIT_BASE_HI
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_INIT_BUFSZ
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL
+//CP_CE_IB1_BASE_LO
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
+//CP_CE_IB1_BASE_HI
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_IB1_BUFSZ
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
+//CP_CE_IB2_BASE_LO
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
+//CP_CE_IB2_BASE_HI
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_IB2_BUFSZ
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
+//CP_IB1_BASE_LO
+#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
+//CP_IB1_BASE_HI
+#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
+//CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
+//CP_IB2_BASE_LO
+#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
+//CP_IB2_BASE_HI
+#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
+//CP_IB2_BUFSZ
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
+//CP_ST_BASE_LO
+#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
+#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL
+//CP_ST_BASE_HI
+#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
+#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL
+//CP_ST_BUFSZ
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL
+//CP_EOP_DONE_EVENT_CNTL
+#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT 0xc
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19
+#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b
+#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c
+#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK 0x00FFF000L
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x06000000L
+#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x08000000L
+#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L
+//CP_EOP_DONE_DATA_CNTL
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L
+//CP_EOP_DONE_CNTX_ID
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
+//CP_DB_BASE_LO
+#define CP_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2
+#define CP_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL
+//CP_DB_BASE_HI
+#define CP_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0
+#define CP_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL
+//CP_DB_BUFSZ
+#define CP_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0
+#define CP_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL
+//CP_DB_CMD_BUFSZ
+#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0
+#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_CE_DB_BASE_LO
+#define CP_CE_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2
+#define CP_CE_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL
+//CP_CE_DB_BASE_HI
+#define CP_CE_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0
+#define CP_CE_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_DB_BUFSZ
+#define CP_CE_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0
+#define CP_CE_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL
+//CP_CE_DB_CMD_BUFSZ
+#define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0
+#define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL
+//CP_PFP_COMPLETION_STATUS
+#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L
+//CP_CE_COMPLETION_STATUS
+#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L
+//CP_PRED_NOT_VISIBLE
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L
+//CP_PFP_METADATA_BASE_ADDR
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_PFP_METADATA_BASE_ADDR_HI
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_CE_METADATA_BASE_ADDR
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_CE_METADATA_BASE_ADDR_HI
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_DRAW_INDX_INDR_ADDR
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_DRAW_INDX_INDR_ADDR_HI
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_DISPATCH_INDR_ADDR
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_DISPATCH_INDR_ADDR_HI
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_INDEX_BASE_ADDR
+#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_INDEX_BASE_ADDR_HI
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_INDEX_TYPE
+#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
+//CP_GDS_BKUP_ADDR
+#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_GDS_BKUP_ADDR_HI
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
+//CP_SAMPLE_STATUS
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L
+//CP_ME_COHER_CNTL
+#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
+#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
+#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
+#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
+#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
+#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
+#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
+#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
+#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
+#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
+#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
+#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
+#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
+#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
+#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
+#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
+#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
+#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
+#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
+#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
+#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
+#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
+#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
+#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
+#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
+#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
+//CP_ME_COHER_SIZE
+#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
+#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
+//CP_ME_COHER_SIZE_HI
+#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
+#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
+//CP_ME_COHER_BASE
+#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
+#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
+//CP_ME_COHER_BASE_HI
+#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
+#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
+//CP_ME_COHER_STATUS
+#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
+#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f
+#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL
+#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L
+//RLC_GPM_PERF_COUNT_0
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L
+#define RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK 0x00000F00L
+#define RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK 0x0000F000L
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L
+#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L
+#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L
+#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L
+//RLC_GPM_PERF_COUNT_1
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L
+#define RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK 0x00000F00L
+#define RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK 0x0000F000L
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L
+#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L
+#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L
+#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L
+//GRBM_GFX_INDEX
+#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX__SA_INDEX__SHIFT 0x8
+#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
+#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL
+#define GRBM_GFX_INDEX__SA_INDEX_MASK 0x0000FF00L
+#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L
+#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L
+//VGT_ESGS_RING_SIZE_UMD
+#define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE__SHIFT 0x0
+#define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE_MASK 0xFFFFFFFFL
+//VGT_GSVS_RING_SIZE_UMD
+#define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE_MASK 0xFFFFFFFFL
+//VGT_PRIMITIVE_TYPE
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
+//VGT_INDEX_TYPE
+#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_1
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_2
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL
+//VGT_STRMOUT_BUFFER_FILLED_SIZE_3
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL
+//GE_MIN_VTX_INDX
+#define GE_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
+#define GE_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL
+//GE_INDX_OFFSET
+#define GE_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
+#define GE_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL
+//GE_MULTI_PRIM_IB_RESET_EN
+#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
+#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1
+#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L
+#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L
+//VGT_NUM_INDICES
+#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
+#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL
+//VGT_NUM_INSTANCES
+#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
+//VGT_TF_RING_SIZE_UMD
+#define VGT_TF_RING_SIZE_UMD__SIZE__SHIFT 0x0
+#define VGT_TF_RING_SIZE_UMD__SIZE_MASK 0x0000FFFFL
+//VGT_HS_OFFCHIP_PARAM_UMD
+#define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING__SHIFT 0x0
+#define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY__SHIFT 0x9
+#define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING_MASK 0x000001FFL
+#define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY_MASK 0x00000600L
+//VGT_TF_MEMORY_BASE_UMD
+#define VGT_TF_MEMORY_BASE_UMD__BASE__SHIFT 0x0
+#define VGT_TF_MEMORY_BASE_UMD__BASE_MASK 0xFFFFFFFFL
+//GE_DMA_FIRST_INDEX
+#define GE_DMA_FIRST_INDEX__FIRST_INDEX__SHIFT 0x0
+#define GE_DMA_FIRST_INDEX__FIRST_INDEX_MASK 0xFFFFFFFFL
+//WD_POS_BUF_BASE
+#define WD_POS_BUF_BASE__BASE__SHIFT 0x0
+#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//WD_POS_BUF_BASE_HI
+#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0
+#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
+//WD_CNTL_SB_BUF_BASE
+#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0
+#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//WD_CNTL_SB_BUF_BASE_HI
+#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0
+#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
+//WD_INDEX_BUF_BASE
+#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0
+#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL
+//WD_INDEX_BUF_BASE_HI
+#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0
+#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
+//IA_MULTI_VGT_PARAM_PIPED
+#define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE__SHIFT 0x0
+#define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON__SHIFT 0x10
+#define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP__SHIFT 0x11
+#define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON__SHIFT 0x12
+#define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI__SHIFT 0x13
+#define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC__SHIFT 0x15
+#define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV__SHIFT 0x16
+#define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY__SHIFT 0x17
+#define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE_MASK 0x0000FFFFL
+#define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON_MASK 0x00010000L
+#define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP_MASK 0x00020000L
+#define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON_MASK 0x00040000L
+#define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI_MASK 0x00080000L
+#define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP_MASK 0x00100000L
+#define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC_MASK 0x00200000L
+#define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV_MASK 0x00400000L
+#define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY_MASK 0x00800000L
+//GE_MAX_VTX_INDX
+#define GE_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
+#define GE_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL
+//VGT_INSTANCE_BASE_ID
+#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0
+#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL
+//GE_CNTL
+#define GE_CNTL__PRIM_GRP_SIZE__SHIFT 0x0
+#define GE_CNTL__VERT_GRP_SIZE__SHIFT 0x9
+#define GE_CNTL__BREAK_WAVE_AT_EOI__SHIFT 0x12
+#define GE_CNTL__PACKET_TO_ONE_PA__SHIFT 0x13
+#define GE_CNTL__PRIM_GRP_SIZE_MASK 0x000001FFL
+#define GE_CNTL__VERT_GRP_SIZE_MASK 0x0003FE00L
+#define GE_CNTL__BREAK_WAVE_AT_EOI_MASK 0x00040000L
+#define GE_CNTL__PACKET_TO_ONE_PA_MASK 0x00080000L
+//GE_USER_VGPR1
+#define GE_USER_VGPR1__DATA__SHIFT 0x0
+#define GE_USER_VGPR1__DATA_MASK 0xFFFFFFFFL
+//GE_USER_VGPR2
+#define GE_USER_VGPR2__DATA__SHIFT 0x0
+#define GE_USER_VGPR2__DATA_MASK 0xFFFFFFFFL
+//GE_USER_VGPR3
+#define GE_USER_VGPR3__DATA__SHIFT 0x0
+#define GE_USER_VGPR3__DATA_MASK 0xFFFFFFFFL
+//GE_STEREO_CNTL
+#define GE_STEREO_CNTL__RT_SLICE__SHIFT 0x0
+#define GE_STEREO_CNTL__VIEWPORT__SHIFT 0x3
+#define GE_STEREO_CNTL__EN_STEREO__SHIFT 0x8
+#define GE_STEREO_CNTL__RT_SLICE_MASK 0x00000007L
+#define GE_STEREO_CNTL__VIEWPORT_MASK 0x00000078L
+#define GE_STEREO_CNTL__EN_STEREO_MASK 0x00000100L
+//GE_PC_ALLOC
+#define GE_PC_ALLOC__OVERSUB_EN__SHIFT 0x0
+#define GE_PC_ALLOC__NUM_PC_LINES__SHIFT 0x1
+#define GE_PC_ALLOC__OVERSUB_EN_MASK 0x00000001L
+#define GE_PC_ALLOC__NUM_PC_LINES_MASK 0x000007FEL
+//VGT_TF_MEMORY_BASE_HI_UMD
+#define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI__SHIFT 0x0
+#define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI_MASK 0x000000FFL
+//GE_USER_VGPR_EN
+#define GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT 0x0
+#define GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT 0x1
+#define GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT 0x2
+#define GE_USER_VGPR_EN__EN_USER_VGPR1_MASK 0x00000001L
+#define GE_USER_VGPR_EN__EN_USER_VGPR2_MASK 0x00000002L
+#define GE_USER_VGPR_EN__EN_USER_VGPR3_MASK 0x00000004L
+//PA_SU_LINE_STIPPLE_VALUE
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL
+//PA_SC_LINE_STIPPLE_STATE
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L
+//PA_SC_SCREEN_EXTENT_MIN_0
+#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_EXTENT_MAX_0
+#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_EXTENT_MIN_1
+#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L
+//PA_SC_SCREEN_EXTENT_MAX_1
+#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L
+//PA_SC_P3D_TRAP_SCREEN_HV_EN
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
+//PA_SC_P3D_TRAP_SCREEN_H
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
+//PA_SC_P3D_TRAP_SCREEN_V
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
+//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
+//PA_SC_P3D_TRAP_SCREEN_COUNT
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
+//PA_SC_HP3D_TRAP_SCREEN_HV_EN
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
+//PA_SC_HP3D_TRAP_SCREEN_H
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
+//PA_SC_HP3D_TRAP_SCREEN_V
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
+//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
+//PA_SC_HP3D_TRAP_SCREEN_COUNT
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
+//PA_SC_TRAP_SCREEN_HV_EN
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
+//PA_SC_TRAP_SCREEN_H
+#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
+//PA_SC_TRAP_SCREEN_V
+#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
+//PA_SC_TRAP_SCREEN_OCCURRENCE
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
+//PA_SC_TRAP_SCREEN_COUNT
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
+//SQ_THREAD_TRACE_USERDATA_0
+#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_1
+#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_2
+#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_3
+#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_4
+#define SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_4__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_5
+#define SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_5__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_6
+#define SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_6__DATA_MASK 0xFFFFFFFFL
+//SQ_THREAD_TRACE_USERDATA_7
+#define SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_7__DATA_MASK 0xFFFFFFFFL
+//SQC_CACHES
+#define SQC_CACHES__TARGET_INST__SHIFT 0x0
+#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
+#define SQC_CACHES__INVALIDATE__SHIFT 0x2
+#define SQC_CACHES__WRITEBACK__SHIFT 0x3
+#define SQC_CACHES__VOL__SHIFT 0x4
+#define SQC_CACHES__COMPLETE__SHIFT 0x10
+#define SQC_CACHES__L2_WB_POLICY__SHIFT 0x11
+#define SQC_CACHES__TARGET_INST_MASK 0x00000001L
+#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L
+#define SQC_CACHES__INVALIDATE_MASK 0x00000004L
+#define SQC_CACHES__WRITEBACK_MASK 0x00000008L
+#define SQC_CACHES__VOL_MASK 0x00000010L
+#define SQC_CACHES__COMPLETE_MASK 0x00010000L
+#define SQC_CACHES__L2_WB_POLICY_MASK 0x00060000L
+//SQC_WRITEBACK
+#define SQC_WRITEBACK__DWB__SHIFT 0x0
+#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
+#define SQC_WRITEBACK__DWB_MASK 0x00000001L
+#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L
+//TA_CS_BC_BASE_ADDR
+#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
+//TA_CS_BC_BASE_ADDR_HI
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
+//DB_OCCLUSION_COUNT0_LOW
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT0_HI
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_OCCLUSION_COUNT1_LOW
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT1_HI
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_OCCLUSION_COUNT2_LOW
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT2_HI
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_OCCLUSION_COUNT3_LOW
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_OCCLUSION_COUNT3_HI
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//DB_ZPASS_COUNT_LOW
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
+//DB_ZPASS_COUNT_HI
+#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
+#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL
+//GDS_RD_ADDR
+#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
+#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL
+//GDS_RD_DATA
+#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
+#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL
+//GDS_RD_BURST_ADDR
+#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
+#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL
+//GDS_RD_BURST_COUNT
+#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
+#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL
+//GDS_RD_BURST_DATA
+#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
+#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL
+//GDS_WR_ADDR
+#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
+//GDS_WR_DATA
+#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
+//GDS_WR_BURST_ADDR
+#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
+//GDS_WR_BURST_DATA
+#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
+//GDS_WRITE_COMPLETE
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL
+//GDS_ATOM_CNTL
+#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
+#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
+#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
+#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
+#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL
+#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L
+#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L
+#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L
+//GDS_ATOM_COMPLETE
+#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
+#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
+#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L
+#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL
+//GDS_ATOM_BASE
+#define GDS_ATOM_BASE__BASE__SHIFT 0x0
+#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL
+#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L
+//GDS_ATOM_SIZE
+#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
+#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL
+#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L
+//GDS_ATOM_OFFSET0
+#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
+#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL
+#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L
+//GDS_ATOM_OFFSET1
+#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
+#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL
+#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L
+//GDS_ATOM_DST
+#define GDS_ATOM_DST__DST__SHIFT 0x0
+#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL
+//GDS_ATOM_OP
+#define GDS_ATOM_OP__OP__SHIFT 0x0
+#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OP__OP_MASK 0x000000FFL
+#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L
+//GDS_ATOM_SRC0
+#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_SRC0_U
+#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_SRC1
+#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_SRC1_U
+#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ0
+#define GDS_ATOM_READ0__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ0_U
+#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ1
+#define GDS_ATOM_READ1__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL
+//GDS_ATOM_READ1_U
+#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL
+//GDS_GWS_RESOURCE_CNTL
+#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
+#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL
+#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L
+//GDS_GWS_RESOURCE
+#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
+#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
+#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
+#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
+#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
+#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
+#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b
+#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c
+#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1d
+#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1e
+#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L
+#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL
+#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L
+#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L
+#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L
+#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x07FF0000L
+#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x08000000L
+#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000L
+#define GDS_GWS_RESOURCE__HALTED_MASK 0x20000000L
+#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xC0000000L
+//GDS_GWS_RESOURCE_CNT
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL
+#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L
+//GDS_OA_CNTL
+#define GDS_OA_CNTL__INDEX__SHIFT 0x0
+#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
+#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL
+#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L
+//GDS_OA_COUNTER
+#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
+#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL
+//GDS_OA_ADDRESS
+#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
+#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10
+#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14
+#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18
+#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
+#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
+#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL
+#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x000F0000L
+#define GDS_OA_ADDRESS__CRAWLER_MASK 0x00F00000L
+#define GDS_OA_ADDRESS__UNUSED_MASK 0x3F000000L
+#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L
+#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L
+//GDS_OA_INCDEC
+#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
+#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
+#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL
+#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L
+//GDS_OA_RING_SIZE
+#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
+#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL
+//SPI_CONFIG_CNTL_REMAP
+#define SPI_CONFIG_CNTL_REMAP__RESERVED__SHIFT 0x0
+#define SPI_CONFIG_CNTL_REMAP__RESERVED_MASK 0xFFFFFFFFL
+//SPI_CONFIG_CNTL_1_REMAP
+#define SPI_CONFIG_CNTL_1_REMAP__RESERVED__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1_REMAP__RESERVED_MASK 0xFFFFFFFFL
+//SPI_CONFIG_CNTL_2_REMAP
+#define SPI_CONFIG_CNTL_2_REMAP__RESERVED__SHIFT 0x0
+#define SPI_CONFIG_CNTL_2_REMAP__RESERVED_MASK 0xFFFFFFFFL
+//SPI_WAVE_LIMIT_CNTL_REMAP
+#define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED__SHIFT 0x0
+#define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_cprs64dec
+//CP_MES_PRGRM_CNTR_START
+#define CP_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MES_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL
+//CP_MES_INTR_ROUTINE_START
+#define CP_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL
+//CP_MES_MTVEC_LO
+#define CP_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0
+#define CP_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_MES_MTVEC_HI
+#define CP_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0
+#define CP_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_MES_CNTL
+#define CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10
+#define CP_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11
+#define CP_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12
+#define CP_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13
+#define CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a
+#define CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b
+#define CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c
+#define CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d
+#define CP_MES_CNTL__MES_HALT__SHIFT 0x1e
+#define CP_MES_CNTL__MES_STEP__SHIFT 0x1f
+#define CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L
+#define CP_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L
+#define CP_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L
+#define CP_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L
+#define CP_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L
+#define CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L
+#define CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L
+#define CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L
+#define CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L
+#define CP_MES_CNTL__MES_HALT_MASK 0x40000000L
+#define CP_MES_CNTL__MES_STEP_MASK 0x80000000L
+//CP_MES_PIPE_PRIORITY_CNTS
+#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
+#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
+#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
+#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
+//CP_MES_PIPE0_PRIORITY
+#define CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_MES_PIPE1_PRIORITY
+#define CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_MES_PIPE2_PRIORITY
+#define CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_MES_PIPE3_PRIORITY
+#define CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
+//CP_MES_HEADER_DUMP
+#define CP_MES_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MES_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
+//CP_MES_MIE_LO
+#define CP_MES_MIE_LO__MES_INT__SHIFT 0x0
+#define CP_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL
+//CP_MES_MIE_HI
+#define CP_MES_MIE_HI__MES_INT__SHIFT 0x0
+#define CP_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL
+//CP_MES_INTERRUPT
+#define CP_MES_INTERRUPT__MES_INT__SHIFT 0x0
+#define CP_MES_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x10
+#define CP_MES_INTERRUPT__MES_INT_MASK 0x0000FFFFL
+#define CP_MES_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFF0000L
+//CP_MES_SCRATCH_INDEX
+#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f
+#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
+#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L
+//CP_MES_SCRATCH_DATA
+#define CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
+//CP_MES_INSTR_PNTR
+#define CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
+#define CP_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL
+//CP_MES_MSCRATCH_HI
+#define CP_MES_MSCRATCH_HI__DATA__SHIFT 0x0
+#define CP_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL
+//CP_MES_MSCRATCH_LO
+#define CP_MES_MSCRATCH_LO__DATA__SHIFT 0x0
+#define CP_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL
+//CP_MES_MSTATUS_LO
+#define CP_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0
+#define CP_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL
+//CP_MES_MSTATUS_HI
+#define CP_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0
+#define CP_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL
+//CP_MES_MEPC_LO
+#define CP_MES_MEPC_LO__MEPC_LO__SHIFT 0x0
+#define CP_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL
+//CP_MES_MEPC_HI
+#define CP_MES_MEPC_HI__MEPC_HI__SHIFT 0x0
+#define CP_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL
+//CP_MES_MCAUSE_LO
+#define CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0
+#define CP_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL
+//CP_MES_MCAUSE_HI
+#define CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0
+#define CP_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL
+//CP_MES_MBADADDR_LO
+#define CP_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0
+#define CP_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//CP_MES_MBADADDR_HI
+#define CP_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL
+//CP_MES_MIP_LO
+#define CP_MES_MIP_LO__MIP_LO__SHIFT 0x0
+#define CP_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL
+//CP_MES_MIP_HI
+#define CP_MES_MIP_HI__MIP_HI__SHIFT 0x0
+#define CP_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL
+//CP_MES_MCYCLE_LO
+#define CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0
+#define CP_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL
+//CP_MES_MCYCLE_HI
+#define CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0
+#define CP_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL
+//CP_MES_MTIME_LO
+#define CP_MES_MTIME_LO__TIME_LO__SHIFT 0x0
+#define CP_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL
+//CP_MES_MTIME_HI
+#define CP_MES_MTIME_HI__TIME_HI__SHIFT 0x0
+#define CP_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL
+//CP_MES_MINSTRET_LO
+#define CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0
+#define CP_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL
+//CP_MES_MINSTRET_HI
+#define CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0
+#define CP_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL
+//CP_MES_MISA_LO
+#define CP_MES_MISA_LO__MISA_LO__SHIFT 0x0
+#define CP_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL
+//CP_MES_MISA_HI
+#define CP_MES_MISA_HI__MISA_HI__SHIFT 0x0
+#define CP_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL
+//CP_MES_MVENDORID_LO
+#define CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0
+#define CP_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL
+//CP_MES_MVENDORID_HI
+#define CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0
+#define CP_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL
+//CP_MES_MARCHID_LO
+#define CP_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0
+#define CP_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL
+//CP_MES_MARCHID_HI
+#define CP_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0
+#define CP_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL
+//CP_MES_MIMPID_LO
+#define CP_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0
+#define CP_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL
+//CP_MES_MIMPID_HI
+#define CP_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0
+#define CP_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL
+//CP_MES_MHARTID_LO
+#define CP_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0
+#define CP_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL
+//CP_MES_MHARTID_HI
+#define CP_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0
+#define CP_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL
+//CP_MES_DC_BASE_CNTL
+#define CP_MES_DC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL
+#define CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L
+//CP_MES_DC_OP_CNTL
+#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0
+#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1
+#define CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2
+#define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED__SHIFT 0x3
+#define CP_MES_DC_OP_CNTL__PRIME_DCACHE__SHIFT 0x4
+#define CP_MES_DC_OP_CNTL__DCACHE_PRIMED__SHIFT 0x5
+#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L
+#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L
+#define CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L
+#define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED_MASK 0x00000008L
+#define CP_MES_DC_OP_CNTL__PRIME_DCACHE_MASK 0x00000010L
+#define CP_MES_DC_OP_CNTL__DCACHE_PRIMED_MASK 0x00000020L
+//CP_MES_MTIMECMP_LO
+#define CP_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0
+#define CP_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL
+//CP_MES_MTIMECMP_HI
+#define CP_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0
+#define CP_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL
+//CP_MES_PROCESS_QUANTUM_PIPE0
+#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT 0x0
+#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT 0x1c
+#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT 0x1d
+#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT 0x1f
+#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK 0x0FFFFFFFL
+#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK 0x10000000L
+#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK 0x60000000L
+#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK 0x80000000L
+//CP_MES_PROCESS_QUANTUM_PIPE1
+#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT 0x0
+#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT 0x1c
+#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT 0x1d
+#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT 0x1f
+#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK 0x0FFFFFFFL
+#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK 0x10000000L
+#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK 0x60000000L
+#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK 0x80000000L
+//CP_MES_DOORBELL_CONTROL1
+#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT 0x1e
+#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT 0x1f
+#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK 0x40000000L
+#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK 0x80000000L
+//CP_MES_DOORBELL_CONTROL2
+#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT 0x1e
+#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT 0x1f
+#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK 0x40000000L
+#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK 0x80000000L
+//CP_MES_DOORBELL_CONTROL3
+#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT 0x1e
+#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT 0x1f
+#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK 0x40000000L
+#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK 0x80000000L
+//CP_MES_DOORBELL_CONTROL4
+#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT 0x1e
+#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT 0x1f
+#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK 0x40000000L
+#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK 0x80000000L
+//CP_MES_DOORBELL_CONTROL5
+#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT 0x1e
+#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT 0x1f
+#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK 0x40000000L
+#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK 0x80000000L
+//CP_MES_DOORBELL_CONTROL6
+#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT 0x1e
+#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT 0x1f
+#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
+#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK 0x40000000L
+#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK 0x80000000L
+//CP_MES_GP0_LO
+#define CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0
+#define CP_MES_GP0_LO__DATA__SHIFT 0x1
+#define CP_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L
+#define CP_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL
+//CP_MES_GP0_HI
+#define CP_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0
+#define CP_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL
+//CP_MES_GP1_LO
+#define CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0
+#define CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL
+//CP_MES_GP1_HI
+#define CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0
+#define CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL
+//CP_MES_GP2_LO
+#define CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0
+#define CP_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL
+//CP_MES_GP2_HI
+#define CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0
+#define CP_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL
+//CP_MES_GP3_LO
+#define CP_MES_GP3_LO__DATA__SHIFT 0x0
+#define CP_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL
+//CP_MES_GP3_HI
+#define CP_MES_GP3_HI__DATA__SHIFT 0x0
+#define CP_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL
+//CP_MES_GP4_LO
+#define CP_MES_GP4_LO__DATA__SHIFT 0x0
+#define CP_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL
+//CP_MES_GP4_HI
+#define CP_MES_GP4_HI__DATA__SHIFT 0x0
+#define CP_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL
+//CP_MES_GP5_LO
+#define CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0
+#define CP_MES_GP5_LO__DATA__SHIFT 0x1
+#define CP_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L
+#define CP_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL
+//CP_MES_GP5_HI
+#define CP_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0
+#define CP_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL
+//CP_MES_GP6_LO
+#define CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0
+#define CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL
+//CP_MES_GP6_HI
+#define CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0
+#define CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL
+//CP_MES_GP7_LO
+#define CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0
+#define CP_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL
+//CP_MES_GP7_HI
+#define CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0
+#define CP_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL
+//CP_MES_GP8_LO
+#define CP_MES_GP8_LO__DATA__SHIFT 0x0
+#define CP_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL
+//CP_MES_GP8_HI
+#define CP_MES_GP8_HI__DATA__SHIFT 0x0
+#define CP_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL
+//CP_MES_GP9_LO
+#define CP_MES_GP9_LO__DATA__SHIFT 0x0
+#define CP_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL
+//CP_MES_GP9_HI
+#define CP_MES_GP9_HI__DATA__SHIFT 0x0
+#define CP_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL
+//CP_MES_DM_INDEX_ADDR
+#define CP_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0
+#define CP_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL
+//CP_MES_DM_INDEX_DATA
+#define CP_MES_DM_INDEX_DATA__DATA__SHIFT 0x0
+#define CP_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL
+//CP_MES_DMCONTROL
+#define CP_MES_DMCONTROL__CONTROL__SHIFT 0x0
+#define CP_MES_DMCONTROL__CONTROL_MASK 0xFFFFFFFFL
+//CP_MES_DMINFO
+#define CP_MES_DMINFO__INFO__SHIFT 0x0
+#define CP_MES_DMINFO__INFO_MASK 0xFFFFFFFFL
+//CP_MES_SETHALTNOTIFICATION
+#define CP_MES_SETHALTNOTIFICATION__SETHALT__SHIFT 0x0
+#define CP_MES_SETHALTNOTIFICATION__SETHALT_MASK 0xFFFFFFFFL
+//CP_MES_TSELCT_LOW
+#define CP_MES_TSELCT_LOW__TSELECT__SHIFT 0x0
+#define CP_MES_TSELCT_LOW__TSELECT_MASK 0xFFFFFFFFL
+//CP_MES_TSELCT_HIGH
+#define CP_MES_TSELCT_HIGH__TSELECT__SHIFT 0x0
+#define CP_MES_TSELCT_HIGH__TSELECT_MASK 0xFFFFFFFFL
+//CP_MES_TDATA1_LOW
+#define CP_MES_TDATA1_LOW__DATA__SHIFT 0x0
+#define CP_MES_TDATA1_LOW__DATA_MASK 0xFFFFFFFFL
+//CP_MES_TDATA1_HIGH
+#define CP_MES_TDATA1_HIGH__DATA__SHIFT 0x0
+#define CP_MES_TDATA1_HIGH__DATA_MASK 0xFFFFFFFFL
+//CP_MES_TDATA2_LOW
+#define CP_MES_TDATA2_LOW__DATA__SHIFT 0x0
+#define CP_MES_TDATA2_LOW__DATA_MASK 0xFFFFFFFFL
+//CP_MES_TDATA2_HIGH
+#define CP_MES_TDATA2_HIGH__DATA__SHIFT 0x0
+#define CP_MES_TDATA2_HIGH__DATA_MASK 0xFFFFFFFFL
+//CP_MES_TDATA3_LOW
+#define CP_MES_TDATA3_LOW__DATA__SHIFT 0x0
+#define CP_MES_TDATA3_LOW__DATA_MASK 0xFFFFFFFFL
+//CP_MES_TDATA3_HIH
+#define CP_MES_TDATA3_HIH__DATA__SHIFT 0x0
+#define CP_MES_TDATA3_HIH__DATA_MASK 0xFFFFFFFFL
+//CP_MES_DCSR
+#define CP_MES_DCSR__CSR__SHIFT 0x0
+#define CP_MES_DCSR__CSR_MASK 0xFFFFFFFFL
+//CP_MES_DPC_LOW
+#define CP_MES_DPC_LOW__INSTR_PNTR__SHIFT 0x0
+#define CP_MES_DPC_LOW__INSTR_PNTR_MASK 0xFFFFFFFFL
+//CP_MES_DPC_HIGH
+#define CP_MES_DPC_HIGH__INSTR_PNTR__SHIFT 0x0
+#define CP_MES_DPC_HIGH__INSTR_PNTR_MASK 0xFFFFFFFFL
+//CP_MES_DSCRATCH_LOW
+#define CP_MES_DSCRATCH_LOW__DATA__SHIFT 0x0
+#define CP_MES_DSCRATCH_LOW__DATA_MASK 0xFFFFFFFFL
+//CP_MES_DSCRATCH_HIGH
+#define CP_MES_DSCRATCH_HIGH__DATA__SHIFT 0x0
+#define CP_MES_DSCRATCH_HIGH__DATA_MASK 0xFFFFFFFFL
+//CP_MES_PERFCOUNT_CNTL
+#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0
+#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x00000007L
+
+
+// addressBlock: gc_gusdec
+//GUS_IO_RD_COMBINE_FLUSH
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L
+#define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L
+//GUS_IO_WR_COMBINE_FLUSH
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L
+#define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L
+//GUS_IO_RD_PRI_AGE_RATE
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L
+#define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L
+//GUS_IO_WR_PRI_AGE_RATE
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L
+#define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L
+//GUS_IO_RD_PRI_AGE_COEFF
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L
+#define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L
+//GUS_IO_WR_PRI_AGE_COEFF
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L
+#define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L
+//GUS_IO_RD_PRI_QUEUING
+#define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc
+#define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf
+#define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+#define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L
+#define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L
+//GUS_IO_WR_PRI_QUEUING
+#define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc
+#define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf
+#define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+#define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L
+#define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L
+//GUS_IO_RD_PRI_FIXED
+#define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc
+#define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf
+#define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+#define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L
+#define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L
+//GUS_IO_WR_PRI_FIXED
+#define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc
+#define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf
+#define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+#define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L
+#define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L
+//GUS_IO_RD_PRI_URGENCY_COEFF
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L
+#define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L
+//GUS_IO_WR_PRI_URGENCY_COEFF
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L
+#define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L
+//GUS_IO_RD_PRI_URGENCY_MODE
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L
+#define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L
+//GUS_IO_WR_PRI_URGENCY_MODE
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L
+#define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L
+//GUS_IO_RD_PRI_QUANT_PRI1
+#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_IO_RD_PRI_QUANT_PRI2
+#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_IO_RD_PRI_QUANT_PRI3
+#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_IO_RD_PRI_QUANT_PRI4
+#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_IO_WR_PRI_QUANT_PRI1
+#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_IO_WR_PRI_QUANT_PRI2
+#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_IO_WR_PRI_QUANT_PRI3
+#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_IO_WR_PRI_QUANT_PRI4
+#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_IO_RD_PRI_QUANT1_PRI1
+#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_IO_RD_PRI_QUANT1_PRI2
+#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_IO_RD_PRI_QUANT1_PRI3
+#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_IO_RD_PRI_QUANT1_PRI4
+#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_IO_WR_PRI_QUANT1_PRI1
+#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_IO_WR_PRI_QUANT1_PRI2
+#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_IO_WR_PRI_QUANT1_PRI3
+#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_IO_WR_PRI_QUANT1_PRI4
+#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_DRAM_COMBINE_FLUSH
+#define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10
+#define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14
+#define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+#define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L
+#define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L
+//GUS_DRAM_COMBINE_RD_WR_EN
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT 0x0
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT 0x2
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT 0x4
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT 0x6
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT 0x8
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT 0xa
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK 0x00000003L
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK 0x0000000CL
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK 0x00000030L
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK 0x000000C0L
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK 0x00000300L
+#define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK 0x00000C00L
+//GUS_DRAM_PRI_AGE_RATE
+#define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0
+#define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3
+#define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6
+#define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9
+#define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc
+#define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf
+#define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L
+#define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L
+//GUS_DRAM_PRI_AGE_COEFF
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L
+#define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L
+//GUS_DRAM_PRI_QUEUING
+#define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc
+#define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf
+#define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+#define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L
+#define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L
+//GUS_DRAM_PRI_FIXED
+#define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc
+#define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf
+#define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+#define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L
+#define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L
+//GUS_DRAM_PRI_URGENCY_COEFF
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L
+#define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L
+//GUS_DRAM_PRI_URGENCY_MODE
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L
+#define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L
+//GUS_DRAM_PRI_QUANT_PRI1
+#define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_DRAM_PRI_QUANT_PRI2
+#define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_DRAM_PRI_QUANT_PRI3
+#define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_DRAM_PRI_QUANT_PRI4
+#define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_DRAM_PRI_QUANT_PRI5
+#define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT 0x10
+#define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT 0x18
+#define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK 0xFF000000L
+//GUS_DRAM_PRI_QUANT1_PRI1
+#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_DRAM_PRI_QUANT1_PRI2
+#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_DRAM_PRI_QUANT1_PRI3
+#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_DRAM_PRI_QUANT1_PRI4
+#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_DRAM_PRI_QUANT1_PRI5
+#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT 0x0
+#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT 0x8
+#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK 0x000000FFL
+#define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK 0x0000FF00L
+//GUS_IO_GROUP_BURST
+#define GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//GUS_DRAM_GROUP_BURST
+#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT 0x0
+#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT 0x8
+#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK 0x000000FFL
+#define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK 0x0000FF00L
+//GUS_SDP_ARB_FINAL
+#define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT 0x0
+#define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x5
+#define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x11
+#define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x12
+#define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x000003E0L
+#define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x00020000L
+#define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x00040000L
+//GUS_SDP_QOS_VC_PRIORITY
+#define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT 0x0
+#define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT 0x4
+#define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT 0x8
+#define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT 0xc
+#define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK 0x0000000FL
+#define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK 0x000000F0L
+#define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK 0x00000F00L
+#define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK 0x0000F000L
+//GUS_SDP_CREDITS
+#define GUS_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define GUS_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//GUS_SDP_TAG_RESERVE0
+#define GUS_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define GUS_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define GUS_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define GUS_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define GUS_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define GUS_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define GUS_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define GUS_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//GUS_SDP_TAG_RESERVE1
+#define GUS_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define GUS_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define GUS_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define GUS_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define GUS_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define GUS_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define GUS_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define GUS_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//GUS_SDP_VCC_RESERVE0
+#define GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//GUS_SDP_VCC_RESERVE1
+#define GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//GUS_SDP_VCD_RESERVE0
+#define GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//GUS_SDP_VCD_RESERVE1
+#define GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//GUS_SDP_REQ_CNTL
+#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
+#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
+//GUS_MISC
+#define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT 0x0
+#define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x1
+#define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x2
+#define GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x3
+#define GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x4
+#define GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x6
+#define GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x8
+#define GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xa
+#define GUS_MISC__SEND0_IOWR_ONLY__SHIFT 0xf
+#define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK 0x00000001L
+#define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000002L
+#define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000004L
+#define GUS_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000008L
+#define GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000030L
+#define GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x000000C0L
+#define GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00000300L
+#define GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x00007C00L
+#define GUS_MISC__SEND0_IOWR_ONLY_MASK 0x00008000L
+//GUS_LATENCY_SAMPLING
+#define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x2
+#define GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x3
+#define GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x4
+#define GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x5
+#define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x6
+#define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x7
+#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0x8
+#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0x9
+#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xa
+#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xb
+#define GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xc
+#define GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x14
+#define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000004L
+#define GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000008L
+#define GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000010L
+#define GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000020L
+#define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000040L
+#define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000080L
+#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000100L
+#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000200L
+#define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00000400L
+#define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00000800L
+#define GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x000FF000L
+#define GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x0FF00000L
+//GUS_PERFCOUNTER_LO
+#define GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define GUS_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//GUS_PERFCOUNTER_HI
+#define GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define GUS_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//GUS_PERFCOUNTER0_CFG
+#define GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define GUS_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define GUS_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//GUS_PERFCOUNTER1_CFG
+#define GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define GUS_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define GUS_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//GUS_PERFCOUNTER_RSLT_CNTL
+#define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//GUS_ERR_STATUS
+#define GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define GUS_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define GUS_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define GUS_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+//GUS_MISC2
+#define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0x0
+#define GUS_MISC2__CH_L1_RO_MASK__SHIFT 0x1
+#define GUS_MISC2__SA0_L1_RO_MASK__SHIFT 0x2
+#define GUS_MISC2__SA1_L1_RO_MASK__SHIFT 0x3
+#define GUS_MISC2__SA2_L1_RO_MASK__SHIFT 0x4
+#define GUS_MISC2__SA3_L1_RO_MASK__SHIFT 0x5
+#define GUS_MISC2__CH_L1_PERF_MASK__SHIFT 0x6
+#define GUS_MISC2__SA0_L1_PERF_MASK__SHIFT 0x7
+#define GUS_MISC2__SA1_L1_PERF_MASK__SHIFT 0x8
+#define GUS_MISC2__SA2_L1_PERF_MASK__SHIFT 0x9
+#define GUS_MISC2__SA3_L1_PERF_MASK__SHIFT 0xa
+#define GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT 0xb
+#define GUS_MISC2__L1_RET_CLKEN__SHIFT 0xc
+#define GUS_MISC2__FGCLKEN_HIGH__SHIFT 0xd
+#define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00000001L
+#define GUS_MISC2__CH_L1_RO_MASK_MASK 0x00000002L
+#define GUS_MISC2__SA0_L1_RO_MASK_MASK 0x00000004L
+#define GUS_MISC2__SA1_L1_RO_MASK_MASK 0x00000008L
+#define GUS_MISC2__SA2_L1_RO_MASK_MASK 0x00000010L
+#define GUS_MISC2__SA3_L1_RO_MASK_MASK 0x00000020L
+#define GUS_MISC2__CH_L1_PERF_MASK_MASK 0x00000040L
+#define GUS_MISC2__SA0_L1_PERF_MASK_MASK 0x00000080L
+#define GUS_MISC2__SA1_L1_PERF_MASK_MASK 0x00000100L
+#define GUS_MISC2__SA2_L1_PERF_MASK_MASK 0x00000200L
+#define GUS_MISC2__SA3_L1_PERF_MASK_MASK 0x00000400L
+#define GUS_MISC2__FP_ATOMICS_ENABLE_MASK 0x00000800L
+#define GUS_MISC2__L1_RET_CLKEN_MASK 0x00001000L
+#define GUS_MISC2__FGCLKEN_HIGH_MASK 0x00002000L
+//GUS_SDP_BACKDOOR_CMDCREDITS0
+#define GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x0
+#define GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL
+//GUS_SDP_BACKDOOR_CMDCREDITS1
+#define GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x0
+#define GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL
+//GUS_SDP_BACKDOOR_DATACREDITS0
+#define GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x0
+#define GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL
+//GUS_SDP_BACKDOOR_DATACREDITS1
+#define GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x0
+#define GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL
+//GUS_SDP_BACKDOOR_MISCCREDITS
+#define GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0
+#define GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8
+#define GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL
+#define GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L
+//GUS_SDP_ENABLE
+#define GUS_SDP_ENABLE__ENABLE__SHIFT 0x0
+#define GUS_SDP_ENABLE__ENABLE_MASK 0x00000001L
+//GUS_L1_CH0_CMD_IN
+#define GUS_L1_CH0_CMD_IN__COUNT__SHIFT 0x0
+#define GUS_L1_CH0_CMD_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_CH0_CMD_OUT
+#define GUS_L1_CH0_CMD_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_CH0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_CH0_DATA_IN
+#define GUS_L1_CH0_DATA_IN__COUNT__SHIFT 0x0
+#define GUS_L1_CH0_DATA_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_CH0_DATA_OUT
+#define GUS_L1_CH0_DATA_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_CH0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_CH1_CMD_IN
+#define GUS_L1_CH1_CMD_IN__COUNT__SHIFT 0x0
+#define GUS_L1_CH1_CMD_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_CH1_CMD_OUT
+#define GUS_L1_CH1_CMD_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_CH1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_CH1_DATA_IN
+#define GUS_L1_CH1_DATA_IN__COUNT__SHIFT 0x0
+#define GUS_L1_CH1_DATA_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_CH1_DATA_OUT
+#define GUS_L1_CH1_DATA_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_CH1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA0_CMD_IN
+#define GUS_L1_SA0_CMD_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA0_CMD_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA0_CMD_OUT
+#define GUS_L1_SA0_CMD_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA0_DATA_IN
+#define GUS_L1_SA0_DATA_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA0_DATA_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA0_DATA_OUT
+#define GUS_L1_SA0_DATA_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA0_DATA_U_IN
+#define GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA0_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA0_DATA_U_OUT
+#define GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA0_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA1_CMD_IN
+#define GUS_L1_SA1_CMD_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA1_CMD_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA1_CMD_OUT
+#define GUS_L1_SA1_CMD_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA1_DATA_IN
+#define GUS_L1_SA1_DATA_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA1_DATA_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA1_DATA_OUT
+#define GUS_L1_SA1_DATA_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA1_DATA_U_IN
+#define GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA1_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA1_DATA_U_OUT
+#define GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA1_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA2_CMD_IN
+#define GUS_L1_SA2_CMD_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA2_CMD_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA2_CMD_OUT
+#define GUS_L1_SA2_CMD_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA2_CMD_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA2_DATA_IN
+#define GUS_L1_SA2_DATA_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA2_DATA_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA2_DATA_OUT
+#define GUS_L1_SA2_DATA_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA2_DATA_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA2_DATA_U_IN
+#define GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA2_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA2_DATA_U_OUT
+#define GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA2_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA3_CMD_IN
+#define GUS_L1_SA3_CMD_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA3_CMD_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA3_CMD_OUT
+#define GUS_L1_SA3_CMD_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA3_CMD_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA3_DATA_IN
+#define GUS_L1_SA3_DATA_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA3_DATA_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA3_DATA_OUT
+#define GUS_L1_SA3_DATA_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA3_DATA_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA3_DATA_U_IN
+#define GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT 0x0
+#define GUS_L1_SA3_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL
+//GUS_L1_SA3_DATA_U_OUT
+#define GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT 0x0
+#define GUS_L1_SA3_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL
+//GUS_MISC3
+//GUS_WRRSP_FIFO_CNTL
+#define GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT 0x0
+#define GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK 0x0000003FL
+
+
+// addressBlock: gc_gl1dec
+//GL1_ARB_CTRL
+#define GL1_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0
+#define GL1_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000007L
+//GL1_DRAM_BURST_MASK
+#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0
+#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL
+//GL1_ARB_STATUS
+#define GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0
+#define GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1
+#define GL1_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L
+#define GL1_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L
+//GL1_DRAM_BURST_CTRL
+#define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0
+#define GL1_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3
+#define GL1_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT 0x4
+#define GL1_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT 0x5
+#define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L
+#define GL1_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L
+#define GL1_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK 0x00000010L
+#define GL1_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK 0x00000020L
+//GL1_PIPE_STEER
+#define GL1_PIPE_STEER__PIPE0__SHIFT 0x0
+#define GL1_PIPE_STEER__PIPE1__SHIFT 0x2
+#define GL1_PIPE_STEER__PIPE2__SHIFT 0x4
+#define GL1_PIPE_STEER__PIPE3__SHIFT 0x6
+#define GL1_PIPE_STEER__PIPE4__SHIFT 0x8
+#define GL1_PIPE_STEER__PIPE5__SHIFT 0xa
+#define GL1_PIPE_STEER__PIPE6__SHIFT 0xc
+#define GL1_PIPE_STEER__PIPE7__SHIFT 0xe
+#define GL1_PIPE_STEER__PIPE8__SHIFT 0x10
+#define GL1_PIPE_STEER__PIPE9__SHIFT 0x12
+#define GL1_PIPE_STEER__PIPE10__SHIFT 0x14
+#define GL1_PIPE_STEER__PIPE11__SHIFT 0x16
+#define GL1_PIPE_STEER__PIPE12__SHIFT 0x18
+#define GL1_PIPE_STEER__PIPE13__SHIFT 0x1a
+#define GL1_PIPE_STEER__PIPE14__SHIFT 0x1c
+#define GL1_PIPE_STEER__PIPE15__SHIFT 0x1e
+#define GL1_PIPE_STEER__PIPE0_MASK 0x00000003L
+#define GL1_PIPE_STEER__PIPE1_MASK 0x0000000CL
+#define GL1_PIPE_STEER__PIPE2_MASK 0x00000030L
+#define GL1_PIPE_STEER__PIPE3_MASK 0x000000C0L
+#define GL1_PIPE_STEER__PIPE4_MASK 0x00000300L
+#define GL1_PIPE_STEER__PIPE5_MASK 0x00000C00L
+#define GL1_PIPE_STEER__PIPE6_MASK 0x00003000L
+#define GL1_PIPE_STEER__PIPE7_MASK 0x0000C000L
+#define GL1_PIPE_STEER__PIPE8_MASK 0x00030000L
+#define GL1_PIPE_STEER__PIPE9_MASK 0x000C0000L
+#define GL1_PIPE_STEER__PIPE10_MASK 0x00300000L
+#define GL1_PIPE_STEER__PIPE11_MASK 0x00C00000L
+#define GL1_PIPE_STEER__PIPE12_MASK 0x03000000L
+#define GL1_PIPE_STEER__PIPE13_MASK 0x0C000000L
+#define GL1_PIPE_STEER__PIPE14_MASK 0x30000000L
+#define GL1_PIPE_STEER__PIPE15_MASK 0xC0000000L
+//GL1C_CTRL
+#define GL1C_CTRL__FORCE_MISS__SHIFT 0x0
+#define GL1C_CTRL__FORCE_HIT__SHIFT 0x1
+#define GL1C_CTRL__NOFILL_32B__SHIFT 0x2
+#define GL1C_CTRL__NOFILL_64B__SHIFT 0x3
+#define GL1C_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x4
+#define GL1C_CTRL__ACK_QUEUE_DISABLE__SHIFT 0x8
+#define GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE__SHIFT 0x9
+#define GL1C_CTRL__HIT_QUEUE_DISABLE__SHIFT 0xa
+#define GL1C_CTRL__FORCE_MISS_MASK 0x00000001L
+#define GL1C_CTRL__FORCE_HIT_MASK 0x00000002L
+#define GL1C_CTRL__NOFILL_32B_MASK 0x00000004L
+#define GL1C_CTRL__NOFILL_64B_MASK 0x00000008L
+#define GL1C_CTRL__LATENCY_FIFO_SIZE_MASK 0x000000F0L
+#define GL1C_CTRL__ACK_QUEUE_DISABLE_MASK 0x00000100L
+#define GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE_MASK 0x00000200L
+#define GL1C_CTRL__HIT_QUEUE_DISABLE_MASK 0x00000400L
+//GL1C_STATUS
+#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0
+#define GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1
+#define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2
+#define GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3
+#define GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4
+#define GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5
+#define GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6
+#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7
+#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8
+#define GL1C_STATUS__GL2_RH_BUSY__SHIFT 0x9
+#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa
+#define GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT 0x14
+#define GL1C_STATUS__TAG_STALL__SHIFT 0x15
+#define GL1C_STATUS__TAG_BUSY__SHIFT 0x16
+#define GL1C_STATUS__TAG_ACK_STALL__SHIFT 0x17
+#define GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT 0x18
+#define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT 0x19
+#define GL1C_STATUS__TAG_EVICT__SHIFT 0x1a
+#define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT 0x1b
+#define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT 0x1f
+#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L
+#define GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L
+#define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L
+#define GL1C_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L
+#define GL1C_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L
+#define GL1C_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L
+#define GL1C_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L
+#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L
+#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L
+#define GL1C_STATUS__GL2_RH_BUSY_MASK 0x00000200L
+#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L
+#define GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK 0x00100000L
+#define GL1C_STATUS__TAG_STALL_MASK 0x00200000L
+#define GL1C_STATUS__TAG_BUSY_MASK 0x00400000L
+#define GL1C_STATUS__TAG_ACK_STALL_MASK 0x00800000L
+#define GL1C_STATUS__TAG_GCR_INV_STALL_MASK 0x01000000L
+#define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK 0x02000000L
+#define GL1C_STATUS__TAG_EVICT_MASK 0x04000000L
+#define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK 0x78000000L
+#define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK 0x80000000L
+
+
+// addressBlock: gc_chdec
+//CH_ARB_CTRL
+#define CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0
+#define CH_ARB_CTRL__UC_IO_WR_PATH__SHIFT 0x3
+#define CH_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000007L
+#define CH_ARB_CTRL__UC_IO_WR_PATH_MASK 0x00000008L
+//CH_DRAM_BURST_MASK
+#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0
+#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL
+//CH_ARB_STATUS
+#define CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0
+#define CH_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1
+#define CH_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L
+#define CH_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L
+//CH_DRAM_BURST_CTRL
+#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0
+#define CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3
+#define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT 0x4
+#define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT 0x5
+#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L
+#define CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L
+#define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK 0x00000010L
+#define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK 0x00000020L
+//CH_PIPE_STEER
+#define CH_PIPE_STEER__PIPE0__SHIFT 0x0
+#define CH_PIPE_STEER__PIPE1__SHIFT 0x2
+#define CH_PIPE_STEER__PIPE2__SHIFT 0x4
+#define CH_PIPE_STEER__PIPE3__SHIFT 0x6
+#define CH_PIPE_STEER__PIPE4__SHIFT 0x8
+#define CH_PIPE_STEER__PIPE5__SHIFT 0xa
+#define CH_PIPE_STEER__PIPE6__SHIFT 0xc
+#define CH_PIPE_STEER__PIPE7__SHIFT 0xe
+#define CH_PIPE_STEER__PIPE8__SHIFT 0x10
+#define CH_PIPE_STEER__PIPE9__SHIFT 0x12
+#define CH_PIPE_STEER__PIPE10__SHIFT 0x14
+#define CH_PIPE_STEER__PIPE11__SHIFT 0x16
+#define CH_PIPE_STEER__PIPE12__SHIFT 0x18
+#define CH_PIPE_STEER__PIPE13__SHIFT 0x1a
+#define CH_PIPE_STEER__PIPE14__SHIFT 0x1c
+#define CH_PIPE_STEER__PIPE15__SHIFT 0x1e
+#define CH_PIPE_STEER__PIPE0_MASK 0x00000003L
+#define CH_PIPE_STEER__PIPE1_MASK 0x0000000CL
+#define CH_PIPE_STEER__PIPE2_MASK 0x00000030L
+#define CH_PIPE_STEER__PIPE3_MASK 0x000000C0L
+#define CH_PIPE_STEER__PIPE4_MASK 0x00000300L
+#define CH_PIPE_STEER__PIPE5_MASK 0x00000C00L
+#define CH_PIPE_STEER__PIPE6_MASK 0x00003000L
+#define CH_PIPE_STEER__PIPE7_MASK 0x0000C000L
+#define CH_PIPE_STEER__PIPE8_MASK 0x00030000L
+#define CH_PIPE_STEER__PIPE9_MASK 0x000C0000L
+#define CH_PIPE_STEER__PIPE10_MASK 0x00300000L
+#define CH_PIPE_STEER__PIPE11_MASK 0x00C00000L
+#define CH_PIPE_STEER__PIPE12_MASK 0x03000000L
+#define CH_PIPE_STEER__PIPE13_MASK 0x0C000000L
+#define CH_PIPE_STEER__PIPE14_MASK 0x30000000L
+#define CH_PIPE_STEER__PIPE15_MASK 0xC0000000L
+//CH_VC5_ENABLE
+#define CH_VC5_ENABLE__UTCL2_VC5_ENABLE__SHIFT 0x1
+#define CH_VC5_ENABLE__UTCL2_VC5_ENABLE_MASK 0x00000002L
+//CHC_CTRL
+#define CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0
+#define CHC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL
+//CHC_STATUS
+#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0
+#define CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1
+#define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2
+#define CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3
+#define CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4
+#define CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5
+#define CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6
+#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7
+#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8
+#define CHC_STATUS__GL2_RH_BUSY__SHIFT 0x9
+#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa
+#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14
+#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15
+#define CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16
+#define CHC_STATUS__BUFFER_FULL__SHIFT 0x17
+#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L
+#define CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L
+#define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L
+#define CHC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L
+#define CHC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L
+#define CHC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L
+#define CHC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L
+#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L
+#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L
+#define CHC_STATUS__GL2_RH_BUSY_MASK 0x00000200L
+#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L
+#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L
+#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L
+#define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L
+#define CHC_STATUS__BUFFER_FULL_MASK 0x00800000L
+//CHCG_CTRL
+#define CHCG_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0
+#define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX__SHIFT 0x4
+#define CHCG_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL
+#define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX_MASK 0x000000F0L
+//CHCG_STATUS
+#define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0
+#define CHCG_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1
+#define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2
+#define CHCG_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3
+#define CHCG_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4
+#define CHCG_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5
+#define CHCG_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6
+#define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7
+#define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8
+#define CHCG_STATUS__GL2_RH_BUSY__SHIFT 0x9
+#define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa
+#define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14
+#define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15
+#define CHCG_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16
+#define CHCG_STATUS__BUFFER_FULL__SHIFT 0x17
+#define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY__SHIFT 0x18
+#define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY__SHIFT 0x19
+#define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL__SHIFT 0x1a
+#define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL__SHIFT 0x1b
+#define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L
+#define CHCG_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L
+#define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L
+#define CHCG_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L
+#define CHCG_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L
+#define CHCG_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L
+#define CHCG_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L
+#define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L
+#define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L
+#define CHCG_STATUS__GL2_RH_BUSY_MASK 0x00000200L
+#define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L
+#define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L
+#define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L
+#define CHCG_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L
+#define CHCG_STATUS__BUFFER_FULL_MASK 0x00800000L
+#define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY_MASK 0x01000000L
+#define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY_MASK 0x02000000L
+#define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL_MASK 0x04000000L
+#define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL_MASK 0x08000000L
+
+
+// addressBlock: gc_gl2dec
+//GL2C_CTRL
+#define GL2C_CTRL__CACHE_SIZE__SHIFT 0x0
+#define GL2C_CTRL__RATE__SHIFT 0x2
+#define GL2C_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
+#define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
+#define GL2C_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
+#define GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
+#define GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT 0x14
+#define GL2C_CTRL__LINEAR_SET_HASH__SHIFT 0x15
+#define GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT 0x16
+#define GL2C_CTRL__MDC_SIZE__SHIFT 0x18
+#define GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT 0x1a
+#define GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT 0x1b
+#define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
+#define GL2C_CTRL__CACHE_SIZE_MASK 0x00000003L
+#define GL2C_CTRL__RATE_MASK 0x0000000CL
+#define GL2C_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L
+#define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L
+#define GL2C_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L
+#define GL2C_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L
+#define GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK 0x00100000L
+#define GL2C_CTRL__LINEAR_SET_HASH_MASK 0x00200000L
+#define GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK 0x00C00000L
+#define GL2C_CTRL__MDC_SIZE_MASK 0x03000000L
+#define GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK 0x04000000L
+#define GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK 0x08000000L
+#define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L
+//GL2C_CTRL2
+#define GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0
+#define GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT 0x4
+#define GL2C_CTRL2__FILL_SIZE_32__SHIFT 0x5
+#define GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT 0x6
+#define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT 0x7
+#define GL2C_CTRL2__RO_DISABLE__SHIFT 0x8
+#define GL2C_CTRL2__FORCE_MDC_INV__SHIFT 0x9
+#define GL2C_CTRL2__GCR_ARB_CTRL__SHIFT 0xa
+#define GL2C_CTRL2__GCR_ALL_SET__SHIFT 0xd
+#define GL2C_CTRL2__MDC_PF_BLOCK__SHIFT 0xe
+#define GL2C_CTRL2__MDC_PF_MAX_SIZE__SHIFT 0x10
+#define GL2C_CTRL2__FILL_SIZE_64__SHIFT 0x11
+#define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT 0x12
+#define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT 0x13
+#define GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT 0x14
+#define GL2C_CTRL2__RB_VOLATILE_EN__SHIFT 0x15
+#define GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT 0x16
+#define GL2C_CTRL2__MAX_MIN_CTRL__SHIFT 0x17
+#define GL2C_CTRL2__MDC_PF_LINEAR_METADATA__SHIFT 0x19
+#define GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT 0x1a
+#define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE__SHIFT 0x1b
+#define GL2C_CTRL2__MDC_PF_DISABLE__SHIFT 0x1d
+#define GL2C_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL
+#define GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK 0x00000010L
+#define GL2C_CTRL2__FILL_SIZE_32_MASK 0x00000020L
+#define GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK 0x00000040L
+#define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK 0x00000080L
+#define GL2C_CTRL2__RO_DISABLE_MASK 0x00000100L
+#define GL2C_CTRL2__FORCE_MDC_INV_MASK 0x00000200L
+#define GL2C_CTRL2__GCR_ARB_CTRL_MASK 0x00001C00L
+#define GL2C_CTRL2__GCR_ALL_SET_MASK 0x00002000L
+#define GL2C_CTRL2__MDC_PF_BLOCK_MASK 0x0000C000L
+#define GL2C_CTRL2__MDC_PF_MAX_SIZE_MASK 0x00010000L
+#define GL2C_CTRL2__FILL_SIZE_64_MASK 0x00020000L
+#define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK 0x00040000L
+#define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK 0x00080000L
+#define GL2C_CTRL2__METADATA_VOLATILE_EN_MASK 0x00100000L
+#define GL2C_CTRL2__RB_VOLATILE_EN_MASK 0x00200000L
+#define GL2C_CTRL2__PROBE_UNSHARED_EN_MASK 0x00400000L
+#define GL2C_CTRL2__MAX_MIN_CTRL_MASK 0x01800000L
+#define GL2C_CTRL2__MDC_PF_LINEAR_METADATA_MASK 0x02000000L
+#define GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK 0x04000000L
+#define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE_MASK 0x18000000L
+#define GL2C_CTRL2__MDC_PF_DISABLE_MASK 0xE0000000L
+//GL2C_STATUS
+#define GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC__SHIFT 0x0
+#define GL2C_STATUS__BC_COMPRESSED_WRITE_ATOMIC__SHIFT 0x1
+#define GL2C_STATUS__COMPRESSED_GEN1_INVALID_SIZE__SHIFT 0x2
+#define GL2C_STATUS__COMPRESSED_GEN0__SHIFT 0x3
+#define GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC_MASK 0x00000001L
+#define GL2C_STATUS__BC_COMPRESSED_WRITE_ATOMIC_MASK 0x00000002L
+#define GL2C_STATUS__COMPRESSED_GEN1_INVALID_SIZE_MASK 0x00000004L
+#define GL2C_STATUS__COMPRESSED_GEN0_MASK 0x00000008L
+//GL2C_ADDR_MATCH_MASK
+#define GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0
+#define GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL
+//GL2C_ADDR_MATCH_SIZE
+#define GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0
+#define GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L
+//GL2C_WBINVL2
+#define GL2C_WBINVL2__DONE__SHIFT 0x4
+#define GL2C_WBINVL2__DONE_MASK 0x00000010L
+//GL2C_SOFT_RESET
+#define GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0
+#define GL2C_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L
+//GL2C_CM_CTRL0
+#define GL2C_CM_CTRL0__HASH_MASK__SHIFT 0x0
+#define GL2C_CM_CTRL0__HASH_MASK_MASK 0xFFFFFFFFL
+//GL2C_CM_CTRL1
+#define GL2C_CM_CTRL1__HASH_MASK__SHIFT 0x0
+#define GL2C_CM_CTRL1__BURST_TIMER__SHIFT 0x8
+#define GL2C_CM_CTRL1__RVF_SIZE__SHIFT 0x10
+#define GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT 0x17
+#define GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT 0x19
+#define GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT 0x1a
+#define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT 0x1b
+#define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT 0x1c
+#define GL2C_CM_CTRL1__BURST_MODE__SHIFT 0x1d
+#define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT 0x1e
+#define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT 0x1f
+#define GL2C_CM_CTRL1__HASH_MASK_MASK 0x0000000FL
+#define GL2C_CM_CTRL1__BURST_TIMER_MASK 0x0000FF00L
+#define GL2C_CM_CTRL1__RVF_SIZE_MASK 0x000F0000L
+#define GL2C_CM_CTRL1__WRITE_COH_MODE_MASK 0x01800000L
+#define GL2C_CM_CTRL1__MDC_ARB_MODE_MASK 0x02000000L
+#define GL2C_CM_CTRL1__READ_REQ_ONLY_MASK 0x04000000L
+#define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK 0x08000000L
+#define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK 0x10000000L
+#define GL2C_CM_CTRL1__BURST_MODE_MASK 0x20000000L
+#define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK 0x40000000L
+#define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK 0x80000000L
+//GL2C_CM_STALL
+#define GL2C_CM_STALL__QUEUE__SHIFT 0x0
+#define GL2C_CM_STALL__QUEUE_MASK 0xFFFFFFFFL
+//GL2C_MDC_PF_FLAG_CTRL
+#define GL2C_MDC_PF_FLAG_CTRL__TIMER__SHIFT 0x0
+#define GL2C_MDC_PF_FLAG_CTRL__TIMER_MASK 0xFFFFFFFFL
+//GL2C_CM_CTRL2
+#define GL2C_CM_CTRL2__READ_BURST_TIMER__SHIFT 0x0
+#define GL2C_CM_CTRL2__READ_BURST_TIMER_MASK 0x000000FFL
+//GL2C_CTRL3
+#define GL2C_CTRL3__METADATA_MTYPE_COHERENCY__SHIFT 0x0
+#define GL2C_CTRL3__MDC_PF_COLOR_USE_REQ_METADATA__SHIFT 0x2
+#define GL2C_CTRL3__METADATA_NOFILL__SHIFT 0x3
+#define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH__SHIFT 0x4
+#define GL2C_CTRL3__COMPRESSED_ATOMICS_AVOID_EA_READ__SHIFT 0x5
+#define GL2C_CTRL3__HTILE_TO_HI_PRIORITY__SHIFT 0x6
+#define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE__SHIFT 0x7
+#define GL2C_CTRL3__IO_CHANNEL_ENABLE__SHIFT 0x8
+#define GL2C_CTRL3__FMASK_TO_HI_PRIORITY__SHIFT 0x9
+#define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT 0xa
+#define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE__SHIFT 0xb
+#define GL2C_CTRL3__COMP_TO_CONST_CAM_CHECK_ENABLE__SHIFT 0xc
+#define GL2C_CTRL3__FGCG_OVERRIDE__SHIFT 0xf
+#define GL2C_CTRL3__SCRATCH__SHIFT 0x10
+#define GL2C_CTRL3__METADATA_MTYPE_COHERENCY_MASK 0x00000003L
+#define GL2C_CTRL3__MDC_PF_COLOR_USE_REQ_METADATA_MASK 0x00000004L
+#define GL2C_CTRL3__METADATA_NOFILL_MASK 0x00000008L
+#define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH_MASK 0x00000010L
+#define GL2C_CTRL3__COMPRESSED_ATOMICS_AVOID_EA_READ_MASK 0x00000020L
+#define GL2C_CTRL3__HTILE_TO_HI_PRIORITY_MASK 0x00000040L
+#define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE_MASK 0x00000080L
+#define GL2C_CTRL3__IO_CHANNEL_ENABLE_MASK 0x00000100L
+#define GL2C_CTRL3__FMASK_TO_HI_PRIORITY_MASK 0x00000200L
+#define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY_MASK 0x00000400L
+#define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE_MASK 0x00000800L
+#define GL2C_CTRL3__COMP_TO_CONST_CAM_CHECK_ENABLE_MASK 0x00001000L
+#define GL2C_CTRL3__FGCG_OVERRIDE_MASK 0x00008000L
+#define GL2C_CTRL3__SCRATCH_MASK 0xFFFF0000L
+//GL2C_LB_CTR_CTRL
+#define GL2C_LB_CTR_CTRL__START__SHIFT 0x0
+#define GL2C_LB_CTR_CTRL__LOAD__SHIFT 0x1
+#define GL2C_LB_CTR_CTRL__CLEAR__SHIFT 0x2
+#define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x1f
+#define GL2C_LB_CTR_CTRL__START_MASK 0x00000001L
+#define GL2C_LB_CTR_CTRL__LOAD_MASK 0x00000002L
+#define GL2C_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
+#define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x80000000L
+//GL2C_LB_DATA0
+#define GL2C_LB_DATA0__DATA__SHIFT 0x0
+#define GL2C_LB_DATA0__DATA_MASK 0xFFFFFFFFL
+//GL2C_LB_DATA1
+#define GL2C_LB_DATA1__DATA__SHIFT 0x0
+#define GL2C_LB_DATA1__DATA_MASK 0xFFFFFFFFL
+//GL2C_LB_DATA2
+#define GL2C_LB_DATA2__DATA__SHIFT 0x0
+#define GL2C_LB_DATA2__DATA_MASK 0xFFFFFFFFL
+//GL2C_LB_DATA3
+#define GL2C_LB_DATA3__DATA__SHIFT 0x0
+#define GL2C_LB_DATA3__DATA_MASK 0xFFFFFFFFL
+//GL2C_LB_CTR_SEL0
+#define GL2C_LB_CTR_SEL0__SEL0__SHIFT 0x0
+#define GL2C_LB_CTR_SEL0__DIV0__SHIFT 0xf
+#define GL2C_LB_CTR_SEL0__SEL1__SHIFT 0x10
+#define GL2C_LB_CTR_SEL0__DIV1__SHIFT 0x1f
+#define GL2C_LB_CTR_SEL0__SEL0_MASK 0x000000FFL
+#define GL2C_LB_CTR_SEL0__DIV0_MASK 0x00008000L
+#define GL2C_LB_CTR_SEL0__SEL1_MASK 0x00FF0000L
+#define GL2C_LB_CTR_SEL0__DIV1_MASK 0x80000000L
+//GL2C_LB_CTR_SEL1
+#define GL2C_LB_CTR_SEL1__SEL2__SHIFT 0x0
+#define GL2C_LB_CTR_SEL1__DIV2__SHIFT 0xf
+#define GL2C_LB_CTR_SEL1__SEL3__SHIFT 0x10
+#define GL2C_LB_CTR_SEL1__DIV3__SHIFT 0x1f
+#define GL2C_LB_CTR_SEL1__SEL2_MASK 0x000000FFL
+#define GL2C_LB_CTR_SEL1__DIV2_MASK 0x00008000L
+#define GL2C_LB_CTR_SEL1__SEL3_MASK 0x00FF0000L
+#define GL2C_LB_CTR_SEL1__DIV3_MASK 0x80000000L
+//GL2A_ADDR_MATCH_CTRL
+#define GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT 0x0
+#define GL2A_ADDR_MATCH_CTRL__DISABLE_MASK 0xFFFFFFFFL
+//GL2A_ADDR_MATCH_MASK
+#define GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0
+#define GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL
+//GL2A_ADDR_MATCH_SIZE
+#define GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0
+#define GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L
+//GL2A_PRIORITY_CTRL
+#define GL2A_PRIORITY_CTRL__DISABLE__SHIFT 0x0
+#define GL2A_PRIORITY_CTRL__DISABLE_MASK 0xFFFFFFFFL
+//GL2A_CTRL
+#define GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE__SHIFT 0x0
+#define GL2A_CTRL__STAY_ON_BURST__SHIFT 0x1
+#define GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE_MASK 0x00000001L
+#define GL2A_CTRL__STAY_ON_BURST_MASK 0x00000002L
+//GL2_PIPE_STEER_0
+#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT 0x0
+#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT 0x4
+#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT 0x8
+#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT 0xc
+#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT 0x10
+#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT 0x14
+#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT 0x18
+#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT 0x1c
+#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK 0x00000007L
+#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK 0x00000070L
+#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK 0x00000700L
+#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK 0x00007000L
+#define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK 0x00070000L
+#define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK 0x00700000L
+#define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK 0x07000000L
+#define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK 0x70000000L
+//GL2_PIPE_STEER_1
+#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT 0x0
+#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT 0x4
+#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT 0x8
+#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT 0xc
+#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT 0x10
+#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT 0x14
+#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT 0x18
+#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT 0x1c
+#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK 0x00000007L
+#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK 0x00000070L
+#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK 0x00000700L
+#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK 0x00007000L
+#define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK 0x00070000L
+#define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK 0x00700000L
+#define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK 0x07000000L
+#define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK 0x70000000L
+
+
+// addressBlock: gc_perfddec
+//CPG_PERFCOUNTER1_LO
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPG_PERFCOUNTER1_HI
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPG_PERFCOUNTER0_LO
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPG_PERFCOUNTER0_HI
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER1_LO
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER1_HI
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER0_LO
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPC_PERFCOUNTER0_HI
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER1_LO
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER1_HI
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER0_LO
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CPF_PERFCOUNTER0_HI
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CPF_LATENCY_STATS_DATA
+#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0
+#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
+//CPG_LATENCY_STATS_DATA
+#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0
+#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
+//CPC_LATENCY_STATS_DATA
+#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0
+#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER0_LO
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER0_HI
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER1_LO
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_PERFCOUNTER1_HI
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE0_PERFCOUNTER_LO
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE0_PERFCOUNTER_HI
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE1_PERFCOUNTER_LO
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE1_PERFCOUNTER_HI
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE2_PERFCOUNTER_LO
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE2_PERFCOUNTER_HI
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GRBM_SE3_PERFCOUNTER_LO
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GRBM_SE3_PERFCOUNTER_HI
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER0_LO
+#define GE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER0_HI
+#define GE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER1_LO
+#define GE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER1_HI
+#define GE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER2_LO
+#define GE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER2_HI
+#define GE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER3_LO
+#define GE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER3_HI
+#define GE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER4_LO
+#define GE_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER4_HI
+#define GE_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER5_LO
+#define GE_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER5_HI
+#define GE_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER6_LO
+#define GE_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER6_HI
+#define GE_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER7_LO
+#define GE_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER7_HI
+#define GE_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER8_LO
+#define GE_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER8_HI
+#define GE_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER9_LO
+#define GE_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER9_HI
+#define GE_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER10_LO
+#define GE_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER10_HI
+#define GE_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER11_LO
+#define GE_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GE_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GE_PERFCOUNTER11_HI
+#define GE_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GE_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER0_LO
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER0_HI
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SU_PERFCOUNTER1_LO
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER1_HI
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SU_PERFCOUNTER2_LO
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER2_HI
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SU_PERFCOUNTER3_LO
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SU_PERFCOUNTER3_HI
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
+//PA_SC_PERFCOUNTER0_LO
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER0_HI
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER1_LO
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER1_HI
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER2_LO
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER2_HI
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER3_LO
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER3_HI
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER4_LO
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER4_HI
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER5_LO
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER5_HI
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER6_LO
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER6_HI
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER7_LO
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_SC_PERFCOUNTER7_HI
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER0_HI
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER0_LO
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER1_HI
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER1_LO
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER2_HI
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER2_LO
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER3_HI
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER3_LO
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER4_HI
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER4_LO
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER5_HI
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SPI_PERFCOUNTER5_LO
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER0_LO
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER0_HI
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER1_LO
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER1_HI
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER2_LO
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER2_HI
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER3_LO
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER3_HI
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER4_LO
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER4_HI
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER5_LO
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER5_HI
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER6_LO
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER6_HI
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER7_LO
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER7_HI
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER8_LO
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER8_HI
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER9_LO
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER9_HI
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER10_LO
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER10_HI
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER11_LO
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER11_HI
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER12_LO
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER12_HI
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER13_LO
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER13_HI
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER14_LO
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER14_HI
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER15_LO
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SQ_PERFCOUNTER15_HI
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER0_LO
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER0_HI
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER1_LO
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER1_HI
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER2_LO
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER2_HI
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER3_LO
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//SX_PERFCOUNTER3_HI
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GCEA_PERFCOUNTER2_LO
+#define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GCEA_PERFCOUNTER2_HI
+#define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER0_LO
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER0_HI
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER1_LO
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER1_HI
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER2_LO
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER2_HI
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER3_LO
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GDS_PERFCOUNTER3_HI
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER0_LO
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER0_HI
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER1_LO
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TA_PERFCOUNTER1_HI
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER0_LO
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER0_HI
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER1_LO
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TD_PERFCOUNTER1_HI
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER0_LO
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER0_HI
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER1_LO
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER1_HI
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER2_LO
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER2_HI
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER3_LO
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//TCP_PERFCOUNTER3_HI
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL2C_PERFCOUNTER0_LO
+#define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL2C_PERFCOUNTER0_HI
+#define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL2C_PERFCOUNTER1_LO
+#define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL2C_PERFCOUNTER1_HI
+#define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL2C_PERFCOUNTER2_LO
+#define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL2C_PERFCOUNTER2_HI
+#define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL2C_PERFCOUNTER3_LO
+#define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL2C_PERFCOUNTER3_HI
+#define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL2A_PERFCOUNTER0_LO
+#define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL2A_PERFCOUNTER0_HI
+#define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL2A_PERFCOUNTER1_LO
+#define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL2A_PERFCOUNTER1_HI
+#define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL2A_PERFCOUNTER2_LO
+#define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL2A_PERFCOUNTER2_HI
+#define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL2A_PERFCOUNTER3_LO
+#define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL2A_PERFCOUNTER3_HI
+#define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL1C_PERFCOUNTER0_LO
+#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL1C_PERFCOUNTER0_HI
+#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL1C_PERFCOUNTER1_LO
+#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL1C_PERFCOUNTER1_HI
+#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL1C_PERFCOUNTER2_LO
+#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL1C_PERFCOUNTER2_HI
+#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL1C_PERFCOUNTER3_LO
+#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL1C_PERFCOUNTER3_HI
+#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHC_PERFCOUNTER0_LO
+#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHC_PERFCOUNTER0_HI
+#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHC_PERFCOUNTER1_LO
+#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHC_PERFCOUNTER1_HI
+#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHC_PERFCOUNTER2_LO
+#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHC_PERFCOUNTER2_HI
+#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHC_PERFCOUNTER3_LO
+#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHC_PERFCOUNTER3_HI
+#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHCG_PERFCOUNTER0_LO
+#define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHCG_PERFCOUNTER0_HI
+#define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHCG_PERFCOUNTER1_LO
+#define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHCG_PERFCOUNTER1_HI
+#define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHCG_PERFCOUNTER2_LO
+#define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHCG_PERFCOUNTER2_HI
+#define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHCG_PERFCOUNTER3_LO
+#define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHCG_PERFCOUNTER3_HI
+#define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER0_LO
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER0_HI
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER1_LO
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER1_HI
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER2_LO
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER2_HI
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER3_LO
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CB_PERFCOUNTER3_HI
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER0_LO
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER0_HI
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER1_LO
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER1_HI
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER2_LO
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER2_HI
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER3_LO
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//DB_PERFCOUNTER3_HI
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER0_LO
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER0_HI
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER1_LO
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RLC_PERFCOUNTER1_HI
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER0_LO
+#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER0_HI
+#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER1_LO
+#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER1_HI
+#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER2_LO
+#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER2_HI
+#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER3_LO
+#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//RMI_PERFCOUNTER3_HI
+#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//UTCL1_PERFCOUNTER0_LO
+#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//UTCL1_PERFCOUNTER0_HI
+#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//UTCL1_PERFCOUNTER1_LO
+#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//UTCL1_PERFCOUNTER1_HI
+#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GCR_PERFCOUNTER0_LO
+#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GCR_PERFCOUNTER0_HI
+#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GCR_PERFCOUNTER1_LO
+#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GCR_PERFCOUNTER1_HI
+#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER0_LO
+#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER0_HI
+#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER1_LO
+#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER1_HI
+#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER2_LO
+#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER2_HI
+#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER3_LO
+#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER3_HI
+#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER4_LO
+#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER4_HI
+#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER5_LO
+#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER5_HI
+#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER6_LO
+#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER6_HI
+#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER7_LO
+#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//PA_PH_PERFCOUNTER7_HI
+#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL1A_PERFCOUNTER0_LO
+#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL1A_PERFCOUNTER0_HI
+#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL1A_PERFCOUNTER1_LO
+#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL1A_PERFCOUNTER1_HI
+#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL1A_PERFCOUNTER2_LO
+#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL1A_PERFCOUNTER2_HI
+#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GL1A_PERFCOUNTER3_LO
+#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GL1A_PERFCOUNTER3_HI
+#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHA_PERFCOUNTER0_LO
+#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHA_PERFCOUNTER0_HI
+#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHA_PERFCOUNTER1_LO
+#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHA_PERFCOUNTER1_HI
+#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHA_PERFCOUNTER2_LO
+#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHA_PERFCOUNTER2_HI
+#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//CHA_PERFCOUNTER3_LO
+#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//CHA_PERFCOUNTER3_HI
+#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GUS_PERFCOUNTER2_LO
+#define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GUS_PERFCOUNTER2_HI
+#define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_gcatcl2pfcntrdec
+//GC_ATC_L2_PERFCOUNTER_LO
+#define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//GC_ATC_L2_PERFCOUNTER_HI
+#define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_gcvml2prdec
+//GCMC_VM_L2_PERFCOUNTER_LO
+#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//GCMC_VM_L2_PERFCOUNTER_HI
+#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: gc_gcvml2perfddec
+//GCVML2_PERFCOUNTER2_0_LO
+#define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GCVML2_PERFCOUNTER2_1_LO
+#define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GCVML2_PERFCOUNTER2_0_HI
+#define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+//GCVML2_PERFCOUNTER2_1_HI
+#define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_gcatcl2perfddec
+//GC_ATC_L2_PERFCOUNTER2_LO
+#define GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
+//GC_ATC_L2_PERFCOUNTER2_HI
+#define GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_perfsdec
+//CPG_PERFCOUNTER1_SELECT
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPG_PERFCOUNTER0_SELECT1
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
+#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
+//CPG_PERFCOUNTER0_SELECT
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPC_PERFCOUNTER1_SELECT
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPC_PERFCOUNTER0_SELECT1
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
+#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
+//CPF_PERFCOUNTER1_SELECT
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPF_PERFCOUNTER0_SELECT1
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
+#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
+//CPF_PERFCOUNTER0_SELECT
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CP_PERFMON_CNTL
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
+//CPC_PERFCOUNTER0_SELECT
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
+//CPF_TC_PERF_COUNTER_WINDOW_SELECT
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
+#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
+//CPG_TC_PERF_COUNTER_WINDOW_SELECT
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
+#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
+//CPF_LATENCY_STATS_SELECT
+#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
+#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
+#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
+#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL
+#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
+#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
+//CPG_LATENCY_STATS_SELECT
+#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
+#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
+#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
+#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL
+#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
+#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
+//CPC_LATENCY_STATS_SELECT
+#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
+#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
+#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
+#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL
+#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
+#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
+//CP_DRAW_OBJECT
+#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
+#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL
+//CP_DRAW_OBJECT_COUNTER
+#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
+#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL
+//CP_DRAW_WINDOW_MASK_HI
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL
+//CP_DRAW_WINDOW_HI
+#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL
+//CP_DRAW_WINDOW_LO
+#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
+#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
+#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL
+#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L
+//CP_DRAW_WINDOW_CNTL
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
+#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L
+#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L
+//GRBM_PERFCOUNTER0_SELECT
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
+#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
+#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
+#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
+#define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
+#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
+#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
+#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
+//GRBM_PERFCOUNTER1_SELECT
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
+#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
+#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
+#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
+#define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
+#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
+#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
+#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
+//GRBM_SE0_PERFCOUNTER_SELECT
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+//GRBM_SE1_PERFCOUNTER_SELECT
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+//GRBM_SE2_PERFCOUNTER_SELECT
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+//GRBM_SE3_PERFCOUNTER_SELECT
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
+#define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
+//GRBM_PERFCOUNTER0_SELECT_HI
+#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1
+#define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2
+#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3
+#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4
+#define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5
+#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6
+#define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7
+#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8
+#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L
+#define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L
+#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L
+#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L
+#define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L
+#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L
+#define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L
+#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L
+//GRBM_PERFCOUNTER1_SELECT_HI
+#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1
+#define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2
+#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3
+#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4
+#define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5
+#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6
+#define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7
+#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8
+#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L
+#define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L
+#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L
+#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L
+#define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L
+#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L
+#define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L
+#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L
+//GE_PERFCOUNTER0_SELECT
+#define GE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define GE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x18
+#define GE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x1c
+#define GE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0x0F000000L
+#define GE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xF0000000L
+//GE_PERFCOUNTER0_SELECT1
+#define GE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GE_PERFCOUNTER1_SELECT
+#define GE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define GE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x18
+#define GE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x1c
+#define GE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0x0F000000L
+#define GE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xF0000000L
+//GE_PERFCOUNTER1_SELECT1
+#define GE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GE_PERFCOUNTER2_SELECT
+#define GE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define GE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x18
+#define GE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x1c
+#define GE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0x0F000000L
+#define GE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xF0000000L
+//GE_PERFCOUNTER2_SELECT1
+#define GE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GE_PERFCOUNTER3_SELECT
+#define GE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define GE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x18
+#define GE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x1c
+#define GE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0x0F000000L
+#define GE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xF0000000L
+//GE_PERFCOUNTER3_SELECT1
+#define GE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GE_PERFCOUNTER4_SELECT
+#define GE_PERFCOUNTER4_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
+#define GE_PERFCOUNTER4_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L
+//GE_PERFCOUNTER5_SELECT
+#define GE_PERFCOUNTER5_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
+#define GE_PERFCOUNTER5_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L
+//GE_PERFCOUNTER6_SELECT
+#define GE_PERFCOUNTER6_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
+#define GE_PERFCOUNTER6_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L
+//GE_PERFCOUNTER7_SELECT
+#define GE_PERFCOUNTER7_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
+#define GE_PERFCOUNTER7_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L
+//GE_PERFCOUNTER8_SELECT
+#define GE_PERFCOUNTER8_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
+#define GE_PERFCOUNTER8_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L
+//GE_PERFCOUNTER9_SELECT
+#define GE_PERFCOUNTER9_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
+#define GE_PERFCOUNTER9_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L
+//GE_PERFCOUNTER10_SELECT
+#define GE_PERFCOUNTER10_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
+#define GE_PERFCOUNTER10_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L
+//GE_PERFCOUNTER11_SELECT
+#define GE_PERFCOUNTER11_SELECT__PERF_SEL0__SHIFT 0x0
+#define GE_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
+#define GE_PERFCOUNTER11_SELECT__PERF_SEL0_MASK 0x000003FFL
+#define GE_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER0_SELECT
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER0_SELECT1
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER1_SELECT
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER1_SELECT1
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER2_SELECT
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER2_SELECT1
+#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER3_SELECT
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SU_PERFCOUNTER3_SELECT1
+#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_SC_PERFCOUNTER0_SELECT
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_SC_PERFCOUNTER0_SELECT1
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_SC_PERFCOUNTER1_SELECT
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER2_SELECT
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER3_SELECT
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER4_SELECT
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER5_SELECT
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER6_SELECT
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_SC_PERFCOUNTER7_SELECT
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL
+//SPI_PERFCOUNTER0_SELECT
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER1_SELECT
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER2_SELECT
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER3_SELECT
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//SPI_PERFCOUNTER0_SELECT1
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER1_SELECT1
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER2_SELECT1
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER3_SELECT1
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//SPI_PERFCOUNTER4_SELECT
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL
+//SPI_PERFCOUNTER5_SELECT
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL
+//SPI_PERFCOUNTER_BINS
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L
+//SQ_PERFCOUNTER0_SELECT
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER1_SELECT
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER2_SELECT
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER3_SELECT
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER4_SELECT
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER5_SELECT
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER6_SELECT
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER7_SELECT
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER8_SELECT
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER9_SELECT
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER10_SELECT
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER11_SELECT
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER12_SELECT
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER13_SELECT
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER14_SELECT
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER15_SELECT
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L
+//SQ_PERFCOUNTER_CTRL
+#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
+#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
+#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
+#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
+#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
+#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
+#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L
+#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L
+#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L
+#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L
+#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L
+#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L
+#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00000300L
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L
+//SQ_PERFCOUNTER_CTRL2
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L
+//GCEA_PERFCOUNTER2_SELECT
+#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//GCEA_PERFCOUNTER2_SELECT1
+#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//GCEA_PERFCOUNTER2_MODE
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L
+#define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L
+//SX_PERFCOUNTER0_SELECT
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+//SX_PERFCOUNTER1_SELECT
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+//SX_PERFCOUNTER2_SELECT
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+//SX_PERFCOUNTER3_SELECT
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+//SX_PERFCOUNTER0_SELECT1
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
+//SX_PERFCOUNTER1_SELECT1
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
+//GDS_PERFCOUNTER0_SELECT
+#define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//GDS_PERFCOUNTER1_SELECT
+#define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//GDS_PERFCOUNTER2_SELECT
+#define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//GDS_PERFCOUNTER3_SELECT
+#define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//GDS_PERFCOUNTER0_SELECT1
+#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TA_PERFCOUNTER0_SELECT
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TA_PERFCOUNTER0_SELECT1
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TA_PERFCOUNTER1_SELECT
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TD_PERFCOUNTER0_SELECT
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TD_PERFCOUNTER0_SELECT1
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TD_PERFCOUNTER1_SELECT
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER0_SELECT
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER0_SELECT1
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TCP_PERFCOUNTER1_SELECT
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER1_SELECT1
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//TCP_PERFCOUNTER2_SELECT
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//TCP_PERFCOUNTER3_SELECT
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL2C_PERFCOUNTER0_SELECT
+#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL2C_PERFCOUNTER0_SELECT1
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GL2C_PERFCOUNTER1_SELECT
+#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL2C_PERFCOUNTER1_SELECT1
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GL2C_PERFCOUNTER2_SELECT
+#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL2C_PERFCOUNTER3_SELECT
+#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL2A_PERFCOUNTER0_SELECT
+#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL2A_PERFCOUNTER0_SELECT1
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GL2A_PERFCOUNTER1_SELECT
+#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL2A_PERFCOUNTER1_SELECT1
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GL2A_PERFCOUNTER2_SELECT
+#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL2A_PERFCOUNTER3_SELECT
+#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL1C_PERFCOUNTER0_SELECT
+#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL1C_PERFCOUNTER0_SELECT1
+#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GL1C_PERFCOUNTER1_SELECT
+#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL1C_PERFCOUNTER2_SELECT
+#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL1C_PERFCOUNTER3_SELECT
+#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHC_PERFCOUNTER0_SELECT
+#define CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHC_PERFCOUNTER0_SELECT1
+#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//CHC_PERFCOUNTER1_SELECT
+#define CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHC_PERFCOUNTER2_SELECT
+#define CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHC_PERFCOUNTER3_SELECT
+#define CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHCG_PERFCOUNTER0_SELECT
+#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define CHCG_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHCG_PERFCOUNTER0_SELECT1
+#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//CHCG_PERFCOUNTER1_SELECT
+#define CHCG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHCG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHCG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHCG_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHCG_PERFCOUNTER2_SELECT
+#define CHCG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHCG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHCG_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHCG_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHCG_PERFCOUNTER3_SELECT
+#define CHCG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHCG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHCG_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHCG_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER_FILTER
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L
+//CB_PERFCOUNTER0_SELECT
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER0_SELECT1
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//CB_PERFCOUNTER1_SELECT
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER2_SELECT
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//CB_PERFCOUNTER3_SELECT
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER0_SELECT
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER0_SELECT1
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//DB_PERFCOUNTER1_SELECT
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER1_SELECT1
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//DB_PERFCOUNTER2_SELECT
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//DB_PERFCOUNTER3_SELECT
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//RLC_SPM_PERFMON_CNTL
+#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
+#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L
+#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L
+//RLC_SPM_PERFMON_RING_BASE_LO
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL
+//RLC_SPM_PERFMON_RING_BASE_HI
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L
+//RLC_SPM_PERFMON_RING_SIZE
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL
+//RLC_SPM_PERFMON_SEGMENT_SIZE
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L
+//RLC_SPM_RING_RDPTR
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL
+//RLC_SPM_SEGMENT_THRESHOLD
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
+#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT 0x8
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0x000000FFL
+#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_SE_MUXSEL_ADDR
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT 0x9
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0x000001FFL
+#define RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK 0xFFFFFE00L
+//RLC_SPM_SE_MUXSEL_DATA
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
+//RLC_SPM_GLOBAL_MUXSEL_ADDR
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT 0x8
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0x000000FFL
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_GLOBAL_MUXSEL_DATA
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
+//RLC_SPM_DESER_START_SKEW
+#define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW__SHIFT 0x0
+#define RLC_SPM_DESER_START_SKEW__RESERVED__SHIFT 0x7
+#define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW_MASK 0x0000007FL
+#define RLC_SPM_DESER_START_SKEW__RESERVED_MASK 0xFFFFFF80L
+//RLC_SPM_GLOBALS_SAMPLE_SKEW
+#define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW__SHIFT 0x0
+#define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED__SHIFT 0x7
+#define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW_MASK 0x0000007FL
+#define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED_MASK 0xFFFFFF80L
+//RLC_SPM_GLOBALS_MUXSEL_SKEW
+#define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW__SHIFT 0x0
+#define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED__SHIFT 0x7
+#define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW_MASK 0x0000007FL
+#define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED_MASK 0xFFFFFF80L
+//RLC_SPM_SE_SAMPLE_SKEW
+#define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW__SHIFT 0x0
+#define RLC_SPM_SE_SAMPLE_SKEW__RESERVED__SHIFT 0x7
+#define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW_MASK 0x0000007FL
+#define RLC_SPM_SE_SAMPLE_SKEW__RESERVED_MASK 0xFFFFFF80L
+//RLC_SPM_SE_MUXSEL_SKEW
+#define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_SKEW__RESERVED__SHIFT 0x7
+#define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW_MASK 0x0000007FL
+#define RLC_SPM_SE_MUXSEL_SKEW__RESERVED_MASK 0xFFFFFF80L
+//RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR
+#define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX__SHIFT 0x0
+#define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX_MASK 0xFFFFFFFFL
+//RLC_SPM_GLB_SAMPLEDELAY_IND_DATA
+#define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data__SHIFT 0x0
+#define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT 0x7
+#define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data_MASK 0x0000007FL
+#define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED_MASK 0xFFFFFF80L
+//RLC_SPM_SE_SAMPLEDELAY_IND_ADDR
+#define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX__SHIFT 0x0
+#define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX_MASK 0xFFFFFFFFL
+//RLC_SPM_SE_SAMPLEDELAY_IND_DATA
+#define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data__SHIFT 0x0
+#define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT 0x7
+#define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data_MASK 0x0000007FL
+#define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED_MASK 0xFFFFFF80L
+//RLC_SPM_RING_WRPTR
+#define RLC_SPM_RING_WRPTR__RESERVED__SHIFT 0x0
+#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT 0x5
+#define RLC_SPM_RING_WRPTR__RESERVED_MASK 0x0000001FL
+#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK 0xFFFFFFE0L
+//RLC_SPM_ACCUM_DATARAM_ADDR
+#define RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT 0x0
+#define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT 0x7
+#define RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK 0x0000007FL
+#define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK 0xFFFFFF80L
+//RLC_SPM_ACCUM_DATARAM_DATA
+#define RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT 0x0
+#define RLC_SPM_ACCUM_DATARAM_DATA__data_MASK 0xFFFFFFFFL
+//RLC_SPM_ACCUM_CTRLRAM_ADDR
+#define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT 0x0
+#define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT 0x9
+#define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK 0x000001FFL
+#define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK 0xFFFFFE00L
+//RLC_SPM_ACCUM_CTRLRAM_DATA
+#define RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT 0x0
+#define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT 0x8
+#define RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK 0x000000FFL
+#define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_ACCUM_STATUS
+#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT 0x0
+#define RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT 0x8
+#define RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT 0x9
+#define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT 0xa
+#define RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT 0xb
+#define RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT 0xc
+#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT 0xd
+#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT 0xe
+#define RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT 0xf
+#define RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT 0x10
+#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK 0x000000FFL
+#define RLC_SPM_ACCUM_STATUS__AccumDone_MASK 0x00000100L
+#define RLC_SPM_ACCUM_STATUS__SpmDone_MASK 0x00000200L
+#define RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK 0x00000400L
+#define RLC_SPM_ACCUM_STATUS__AccumArmed_MASK 0x00000800L
+#define RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK 0x00001000L
+#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK 0x00002000L
+#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK 0x00004000L
+#define RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK 0x00008000L
+#define RLC_SPM_ACCUM_STATUS__RESERVED_MASK 0xFFFF0000L
+//RLC_SPM_ACCUM_CTRL
+#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT 0x0
+#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT 0x1
+#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT 0x2
+#define RLC_SPM_ACCUM_CTRL__StrobeSpmDoneInt__SHIFT 0x3
+#define RLC_SPM_ACCUM_CTRL__StrobeAccumDoneInt__SHIFT 0x4
+#define RLC_SPM_ACCUM_CTRL__StrobeResetAccum__SHIFT 0x5
+#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT 0x6
+#define RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT 0xa
+#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK 0x00000001L
+#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK 0x00000002L
+#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK 0x00000004L
+#define RLC_SPM_ACCUM_CTRL__StrobeSpmDoneInt_MASK 0x00000008L
+#define RLC_SPM_ACCUM_CTRL__StrobeAccumDoneInt_MASK 0x00000010L
+#define RLC_SPM_ACCUM_CTRL__StrobeResetAccum_MASK 0x00000020L
+#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK 0x000003C0L
+#define RLC_SPM_ACCUM_CTRL__RESERVED_MASK 0xFFFFFC00L
+//RLC_SPM_ACCUM_MODE
+#define RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT 0x0
+#define RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT 0x1
+#define RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT 0x2
+#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT 0x3
+#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT 0x4
+#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT 0x5
+#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT 0x6
+#define RLC_SPM_ACCUM_MODE__RESERVED__SHIFT 0x7
+#define RLC_SPM_ACCUM_MODE__EnableAccum_MASK 0x00000001L
+#define RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK 0x00000002L
+#define RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK 0x00000004L
+#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK 0x00000008L
+#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK 0x00000010L
+#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK 0x00000020L
+#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK 0x00000040L
+#define RLC_SPM_ACCUM_MODE__RESERVED_MASK 0xFFFFFF80L
+//RLC_SPM_ACCUM_THRESHOLD
+#define RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT 0x0
+#define RLC_SPM_ACCUM_THRESHOLD__RESERVED__SHIFT 0x10
+#define RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK 0x0000FFFFL
+#define RLC_SPM_ACCUM_THRESHOLD__RESERVED_MASK 0xFFFF0000L
+//RLC_SPM_ACCUM_SAMPLES_REQUESTED
+#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT 0x0
+#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__RESERVED__SHIFT 0x8
+#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK 0x000000FFL
+#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__RESERVED_MASK 0xFFFFFF00L
+//RLC_SPM_ACCUM_DATARAM_WRCOUNT
+#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT 0x0
+#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT 0x13
+#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK 0x0007FFFFL
+#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK 0xFFF80000L
+//RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE
+#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x8
+#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x10
+#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE__SHIFT 0x18
+#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x000000FFL
+#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x0000FF00L
+#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x00FF0000L
+#define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE_MASK 0xFF000000L
+//RLC_SPM_PERFMON_GLB_SEGMENT_SIZE
+#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0x8
+#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED__SHIFT 0x10
+#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL
+#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000FF00L
+#define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED_MASK 0xFFFF0000L
+//RLC_SPM_VIRT_CTRL
+#define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest__SHIFT 0x0
+#define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest_MASK 0x00000001L
+//RLC_SPM_VIRT_STATUS
+#define RLC_SPM_VIRT_STATUS__SpmSamplingPaused__SHIFT 0x0
+#define RLC_SPM_VIRT_STATUS__SpmSamplingPaused_MASK 0x00000001L
+//RLC_PERFMON_CNTL
+#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
+//RLC_PERFCOUNTER0_SELECT
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL
+//RLC_PERFCOUNTER1_SELECT
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL
+//RLC_GPU_IOV_PERF_CNT_CNTL
+#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3
+#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L
+#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L
+#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L
+//RLC_GPU_IOV_PERF_CNT_WR_ADDR
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L
+#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L
+//RLC_GPU_IOV_PERF_CNT_WR_DATA
+#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_PERF_CNT_RD_ADDR
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L
+#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L
+//RLC_GPU_IOV_PERF_CNT_RD_DATA
+#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_PERFMON_CLK_CNTL
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L
+//RLC_PERFMON_CLK_CNTL_UCODE
+#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0
+#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L
+//RMI_PERFCOUNTER0_SELECT
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERFCOUNTER0_SELECT1
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//RMI_PERFCOUNTER1_SELECT
+#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERFCOUNTER2_SELECT
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERFCOUNTER2_SELECT1
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//RMI_PERFCOUNTER3_SELECT
+#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
+#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//RMI_PERF_COUNTER_CNTL
+#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0
+#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2
+#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13
+#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19
+#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a
+#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L
+#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL
+#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L
+#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L
+#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L
+#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L
+#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L
+//GCR_PERFCOUNTER0_SELECT
+#define GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
+#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
+#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//GCR_PERFCOUNTER0_SELECT1
+#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
+#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
+#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//GCR_PERFCOUNTER1_SELECT
+#define GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x18
+#define GCR_PERFCOUNTER1_SELECT__CNTL_MODE__SHIFT 0x1c
+#define GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
+#define GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0x0F000000L
+#define GCR_PERFCOUNTER1_SELECT__CNTL_MODE_MASK 0xF0000000L
+//UTCL1_PERFCOUNTER0_SELECT
+#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT 0x1c
+#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK 0xF0000000L
+//UTCL1_PERFCOUNTER1_SELECT
+#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c
+#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L
+//PA_PH_PERFCOUNTER0_SELECT
+#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_PH_PERFCOUNTER0_SELECT1
+#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_PH_PERFCOUNTER1_SELECT
+#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_PH_PERFCOUNTER2_SELECT
+#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_PH_PERFCOUNTER3_SELECT
+#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//PA_PH_PERFCOUNTER4_SELECT
+#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_PH_PERFCOUNTER5_SELECT
+#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_PH_PERFCOUNTER6_SELECT
+#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_PH_PERFCOUNTER7_SELECT
+#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL
+//PA_PH_PERFCOUNTER1_SELECT1
+#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_PH_PERFCOUNTER2_SELECT1
+#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//PA_PH_PERFCOUNTER3_SELECT1
+#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
+#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//GL1A_PERFCOUNTER0_SELECT
+#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL1A_PERFCOUNTER0_SELECT1
+#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//GL1A_PERFCOUNTER1_SELECT
+#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL1A_PERFCOUNTER2_SELECT
+#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//GL1A_PERFCOUNTER3_SELECT
+#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHA_PERFCOUNTER0_SELECT
+#define CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHA_PERFCOUNTER0_SELECT1
+#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
+#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
+//CHA_PERFCOUNTER1_SELECT
+#define CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHA_PERFCOUNTER2_SELECT
+#define CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//CHA_PERFCOUNTER3_SELECT
+#define CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
+#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
+//GUS_PERFCOUNTER2_SELECT
+#define GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//GUS_PERFCOUNTER2_SELECT1
+#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//GUS_PERFCOUNTER2_MODE
+#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0
+#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2
+#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4
+#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6
+#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8
+#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc
+#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10
+#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14
+#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L
+#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL
+#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L
+#define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L
+#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L
+#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L
+#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L
+#define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L
+
+
+// addressBlock: gc_gcatcl2pfcntldec
+//GC_ATC_L2_PERFCOUNTER0_CFG
+#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//GC_ATC_L2_PERFCOUNTER1_CFG
+#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//GC_ATC_L2_PERFCOUNTER_RSLT_CNTL
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: gc_gcvml2pldec
+//GCMC_VM_L2_PERFCOUNTER0_CFG
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//GCMC_VM_L2_PERFCOUNTER1_CFG
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//GCMC_VM_L2_PERFCOUNTER2_CFG
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//GCMC_VM_L2_PERFCOUNTER3_CFG
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//GCMC_VM_L2_PERFCOUNTER4_CFG
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
+#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
+//GCMC_VM_L2_PERFCOUNTER5_CFG
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
+#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
+//GCMC_VM_L2_PERFCOUNTER6_CFG
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
+#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
+//GCMC_VM_L2_PERFCOUNTER7_CFG
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
+#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
+//GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: gc_gcvml2perfsdec
+//GCVML2_PERFCOUNTER2_0_SELECT
+#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT 0xa
+#define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT 0x18
+#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT 0x1c
+#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK 0xF0000000L
+//GCVML2_PERFCOUNTER2_1_SELECT
+#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT 0xa
+#define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT 0x18
+#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT 0x1c
+#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK 0xF0000000L
+//GCVML2_PERFCOUNTER2_0_SELECT1
+#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//GCVML2_PERFCOUNTER2_1_SELECT1
+#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//GCVML2_PERFCOUNTER2_0_MODE
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT 0x2
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT 0x4
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT 0x6
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT 0x8
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT 0xc
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT 0x10
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT 0x14
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK 0x00000003L
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK 0x0000000CL
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK 0x00000030L
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK 0x000000C0L
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK 0x00000F00L
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK 0x0000F000L
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK 0x000F0000L
+#define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK 0x00F00000L
+//GCVML2_PERFCOUNTER2_1_MODE
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT 0x0
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT 0x2
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT 0x4
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT 0x6
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT 0x8
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT 0xc
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT 0x10
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT 0x14
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK 0x00000003L
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK 0x0000000CL
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK 0x00000030L
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK 0x000000C0L
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK 0x00000F00L
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK 0x0000F000L
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK 0x000F0000L
+#define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK 0x00F00000L
+
+
+// addressBlock: gc_gcatcl2perfsdec
+//GC_ATC_L2_PERFCOUNTER2_SELECT
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
+#define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
+//GC_ATC_L2_PERFCOUNTER2_SELECT1
+#define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
+#define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
+#define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
+#define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
+#define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
+//GC_ATC_L2_PERFCOUNTER2_MODE
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L
+#define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L
+
+
+// addressBlock: gc_rlcdec
+//RLC_CNTL
+#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
+#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
+#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
+#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
+#define RLC_CNTL__RESERVED__SHIFT 0x4
+#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L
+#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L
+#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L
+#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L
+#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L
+//RLC_F32_UCODE_VERSION
+#define RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT 0x0
+#define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT 0xa
+#define RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT 0x14
+#define RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK 0x000003FFL
+#define RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK 0x000FFC00L
+#define RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK 0x3FF00000L
+//RLC_STAT
+#define RLC_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1
+#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2
+#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3
+#define RLC_STAT__MC_BUSY__SHIFT 0x4
+#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5
+#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6
+#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7
+#define RLC_STAT__RESERVED__SHIFT 0x8
+#define RLC_STAT__RLC_BUSY_MASK 0x00000001L
+#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L
+#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L
+#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L
+#define RLC_STAT__MC_BUSY_MASK 0x00000010L
+#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L
+#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L
+#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L
+#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L
+//RLC_SAFE_MODE
+#define RLC_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_SAFE_MODE__CMD_MASK 0x00000001L
+#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL
+#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L
+#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L
+#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
+//RLC_MEM_SLP_CNTL
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
+#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L
+#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
+#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
+//SMU_RLC_RESPONSE
+#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
+#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
+//RLC_RLCV_SAFE_MODE
+#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L
+#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL
+#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L
+#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L
+#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
+//RLC_SMU_SAFE_MODE
+#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L
+#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL
+#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L
+#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L
+#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
+//RLC_RLCV_COMMAND
+#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
+#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
+#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL
+#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L
+//RLC_REFCLOCK_TIMESTAMP_LSB
+#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0
+#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL
+//RLC_REFCLOCK_TIMESTAMP_MSB
+#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0
+#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_INT_0
+#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_INT_1
+#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_INT_2
+#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_CTRL
+#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
+#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
+#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2
+#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3
+#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x4
+#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x5
+#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT 0x6
+#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT 0x7
+#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x8
+#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x9
+#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT 0xa
+#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT 0xb
+#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0xc
+#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
+#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
+#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L
+#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L
+#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000010L
+#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000020L
+#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK 0x00000040L
+#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK 0x00000080L
+#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000100L
+#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000200L
+#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK 0x00000400L
+#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK 0x00000800L
+#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFF000L
+//RLC_LB_CNTR_MAX_1
+#define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX__SHIFT 0x0
+#define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX_MASK 0xFFFFFFFFL
+//RLC_GPM_TIMER_STAT
+#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
+#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
+#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2
+#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3
+#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8
+#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9
+#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa
+#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb
+#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xc
+#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xd
+#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT 0xe
+#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT 0xf
+#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x10
+#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
+#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
+#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L
+#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L
+#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L
+#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L
+#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L
+#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L
+#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00001000L
+#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00002000L
+#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK 0x00004000L
+#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK 0x00008000L
+#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFF0000L
+//RLC_GPM_TIMER_INT_3
+#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0
+#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL
+//RLC_INT_STAT
+#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0
+#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8
+#define RLC_INT_STAT__RESERVED__SHIFT 0x9
+#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL
+#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L
+#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L
+//RLC_LB_CNTL
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
+#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
+#define RLC_LB_CNTL__RESERVED__SHIFT 0x4
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L
+#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L
+#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFFFF0L
+//RLC_MGCG_CTRL
+#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
+#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
+#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
+#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
+#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf
+#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10
+#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11
+#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L
+#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L
+#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L
+#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L
+#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L
+#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L
+#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
+//RLC_LB_CNTR_INIT_1
+#define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT__SHIFT 0x0
+#define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT_MASK 0xFFFFFFFFL
+//RLC_LB_CNTR_1
+#define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
+#define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL
+//RLC_JUMP_TABLE_RESTORE
+#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
+#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL
+//RLC_PG_DELAY_2
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT 0x10
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L
+#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK 0xFFFF0000L
+//RLC_GPU_CLOCK_COUNT_LSB
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
+//RLC_GPU_CLOCK_COUNT_MSB
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
+//RLC_CAPTURE_GPU_CLOCK_COUNT
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_UCODE_CNTL
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL
+//RLC_GPM_THREAD_RESET
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
+#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L
+#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L
+//RLC_GPM_CP_DMA_COMPLETE_T0
+#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0
+#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1
+#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L
+#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPM_CP_DMA_COMPLETE_T1
+#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0
+#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1
+#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L
+#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_LB_CNTR_INIT_2
+#define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT__SHIFT 0x0
+#define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT_MASK 0xFFFFFFFFL
+//RLC_LB_CNTR_MAX_2
+#define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX__SHIFT 0x0
+#define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX_MASK 0xFFFFFFFFL
+//RLC_LB_CONFIG_5
+#define RLC_LB_CONFIG_5__DATA__SHIFT 0x0
+#define RLC_LB_CONFIG_5__DATA_MASK 0xFFFFFFFFL
+//RLC_CLK_COUNT_GFXCLK_LSB
+#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0
+#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL
+//RLC_CLK_COUNT_GFXCLK_MSB
+#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0
+#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL
+//RLC_CLK_COUNT_REFCLK_LSB
+#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0
+#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL
+//RLC_CLK_COUNT_REFCLK_MSB
+#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0
+#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL
+//RLC_CLK_COUNT_CTRL
+#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0
+#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1
+#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2
+#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3
+#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4
+#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5
+#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L
+#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L
+#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L
+#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L
+#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L
+#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L
+//RLC_CLK_COUNT_STAT
+#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0
+#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1
+#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2
+#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3
+#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4
+#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5
+#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L
+#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L
+#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L
+#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L
+#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L
+#define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L
+//RLC_GPU_CLOCK_32_RES_SEL
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L
+//RLC_GPU_CLOCK_32
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL
+//RLC_PG_CNTL
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
+#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT 0x2
+#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT 0x3
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
+#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
+#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
+#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
+#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
+#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
+#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15
+#define RLC_PG_CNTL__RESERVED2__SHIFT 0x16
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L
+#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK 0x00000004L
+#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK 0x00000008L
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L
+#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L
+#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L
+#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L
+#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L
+#define RLC_PG_CNTL__RESERVED1_MASK 0x00100000L
+#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L
+#define RLC_PG_CNTL__RESERVED2_MASK 0x00C00000L
+//RLC_GPM_THREAD_PRIORITY
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L
+//RLC_GPM_THREAD_ENABLE
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
+#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L
+#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L
+//RLC_CGTT_MGCG_OVERRIDE
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT 0x0
+#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4
+#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9__SHIFT 0x9
+#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT 0x10
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT 0x11
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK 0x00000001L
+#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L
+#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L
+#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9_MASK 0x0000FE00L
+#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK 0x00010000L
+#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK 0xFFFE0000L
+//RLC_CGCG_CGLS_CTRL
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L
+//RLC_CGCG_RAMP_CTRL
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L
+//RLC_DYN_PG_STATUS
+#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0
+#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL
+//RLC_DYN_PG_REQUEST
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT 0x0
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK 0xFFFFFFFFL
+//RLC_PG_DELAY
+#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
+#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
+#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL
+#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L
+//RLC_WGP_STATUS
+#define RLC_WGP_STATUS__WORK_PENDING__SHIFT 0x0
+#define RLC_WGP_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL
+//RLC_LB_INIT_WGP_MASK
+#define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK__SHIFT 0x0
+#define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK_MASK 0xFFFFFFFFL
+//RLC_LB_ALWAYS_ACTIVE_WGP_MASK
+#define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK__SHIFT 0x0
+#define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK_MASK 0xFFFFFFFFL
+//RLC_LB_PARAMS
+#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
+#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L
+#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L
+//RLC_LB_DELAY
+#define RLC_LB_DELAY__WGP_IDLE_DELAY__SHIFT 0x0
+#define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
+#define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
+#define RLC_LB_DELAY__SPARE__SHIFT 0x18
+#define RLC_LB_DELAY__WGP_IDLE_DELAY_MASK 0x000000FFL
+#define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L
+#define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L
+#define RLC_LB_DELAY__SPARE_MASK 0xFF000000L
+//RLC_PG_ALWAYS_ON_WGP_MASK
+#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT 0x0
+#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK 0xFFFFFFFFL
+//RLC_MAX_PG_WGP
+#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT 0x0
+#define RLC_MAX_PG_WGP__SPARE__SHIFT 0x8
+#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK 0x000000FFL
+#define RLC_MAX_PG_WGP__SPARE_MASK 0xFFFFFF00L
+//RLC_AUTO_PG_CTRL
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L
+//RLC_SMU_GRBM_REG_SAVE_CTRL
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL
+//RLC_SERDES_RD_INDEX
+#define RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT 0x0
+#define RLC_SERDES_RD_INDEX__SPARE__SHIFT 0x2
+#define RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK 0x00000003L
+#define RLC_SERDES_RD_INDEX__SPARE_MASK 0xFFFFFFFCL
+//RLC_SERDES_RD_DATA_0
+#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_RD_DATA_1
+#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_RD_DATA_2
+#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_RD_DATA_3
+#define RLC_SERDES_RD_DATA_3__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_3__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_MASK
+#define RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT 0x0
+#define RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT 0x1
+#define RLC_SERDES_MASK__RESERVED__SHIFT 0x2
+#define RLC_SERDES_MASK__GC_SE_0__SHIFT 0x10
+#define RLC_SERDES_MASK__GC_SE_1__SHIFT 0x11
+#define RLC_SERDES_MASK__GC_SE_2__SHIFT 0x12
+#define RLC_SERDES_MASK__GC_SE_3__SHIFT 0x13
+#define RLC_SERDES_MASK__RESERVED_1__SHIFT 0x14
+#define RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK 0x00000001L
+#define RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK 0x00000002L
+#define RLC_SERDES_MASK__RESERVED_MASK 0x0000FFFCL
+#define RLC_SERDES_MASK__GC_SE_0_MASK 0x00010000L
+#define RLC_SERDES_MASK__GC_SE_1_MASK 0x00020000L
+#define RLC_SERDES_MASK__GC_SE_2_MASK 0x00040000L
+#define RLC_SERDES_MASK__GC_SE_3_MASK 0x00080000L
+#define RLC_SERDES_MASK__RESERVED_1_MASK 0xFFF00000L
+//RLC_SERDES_CTRL
+#define RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT 0x0
+#define RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT 0x1
+#define RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT 0x2
+#define RLC_SERDES_CTRL__BPM_ADDR__SHIFT 0x3
+#define RLC_SERDES_CTRL__REG_ADDR__SHIFT 0x10
+#define RLC_SERDES_CTRL__BPM_BROADCAST_MASK 0x000001L
+#define RLC_SERDES_CTRL__BPM_REG_WRITE_MASK 0x000002L
+#define RLC_SERDES_CTRL__BPM_LONG_CMD_MASK 0x000004L
+#define RLC_SERDES_CTRL__BPM_ADDR_MASK 0x00FFF8L
+#define RLC_SERDES_CTRL__REG_ADDR_MASK 0xFF0000L
+//RLC_SERDES_DATA
+#define RLC_SERDES_DATA__DATA__SHIFT 0x0
+#define RLC_SERDES_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SERDES_BUSY
+#define RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT 0x0
+#define RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT 0x1
+#define RLC_SERDES_BUSY__RESERVED__SHIFT 0x2
+#define RLC_SERDES_BUSY__GC_SE_0__SHIFT 0x10
+#define RLC_SERDES_BUSY__GC_SE_1__SHIFT 0x11
+#define RLC_SERDES_BUSY__GC_SE_2__SHIFT 0x12
+#define RLC_SERDES_BUSY__GC_SE_3__SHIFT 0x13
+#define RLC_SERDES_BUSY__RESERVED_29_20__SHIFT 0x14
+#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT 0x1e
+#define RLC_SERDES_BUSY__RD_PENDING__SHIFT 0x1f
+#define RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK 0x00000001L
+#define RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK 0x00000002L
+#define RLC_SERDES_BUSY__RESERVED_MASK 0x0000FFFCL
+#define RLC_SERDES_BUSY__GC_SE_0_MASK 0x00010000L
+#define RLC_SERDES_BUSY__GC_SE_1_MASK 0x00020000L
+#define RLC_SERDES_BUSY__GC_SE_2_MASK 0x00040000L
+#define RLC_SERDES_BUSY__GC_SE_3_MASK 0x00080000L
+#define RLC_SERDES_BUSY__RESERVED_29_20_MASK 0x3FF00000L
+#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK 0x40000000L
+#define RLC_SERDES_BUSY__RD_PENDING_MASK 0x80000000L
+//RLC_GPM_GENERAL_0
+#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_1
+#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_2
+#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_3
+#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_4
+#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_5
+#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_6
+#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_7
+#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL
+//RLC_STATIC_PG_STATUS
+#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0
+#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL
+//RLC_SPM_INT_INFO_1
+#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0
+#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL
+//RLC_SPM_INT_INFO_2
+#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0
+#define RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10
+#define RLC_SPM_INT_INFO_2__RESERVED__SHIFT 0x18
+#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL
+#define RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x00FF0000L
+#define RLC_SPM_INT_INFO_2__RESERVED_MASK 0xFF000000L
+//RLC_SPM_MC_CNTL
+#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0
+#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4
+#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x6
+#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x7
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x8
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x9
+#define RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT 0xc
+#define RLC_SPM_MC_CNTL__RESERVED_2__SHIFT 0xd
+#define RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT 0xe
+#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT 0xf
+#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0x10
+#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL
+#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000030L
+#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000040L
+#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000080L
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000100L
+#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000E00L
+#define RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK 0x00001000L
+#define RLC_SPM_MC_CNTL__RESERVED_2_MASK 0x00002000L
+#define RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK 0x00004000L
+#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK 0x00008000L
+#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFF0000L
+//RLC_SPM_INT_CNTL
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
+#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L
+#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RLC_SPM_INT_STATUS
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
+#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L
+#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL
+//RLC_SMU_MESSAGE
+#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
+#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL
+//RLC_GPM_LOG_SIZE
+#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
+#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL
+//RLC_PG_DELAY_3
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
+#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL
+#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L
+//RLC_GPR_REG1
+#define RLC_GPR_REG1__DATA__SHIFT 0x0
+#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPR_REG2
+#define RLC_GPR_REG2__DATA__SHIFT 0x0
+#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_LOG_CONT
+#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
+#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL
+//RLC_GPM_INT_DISABLE_TH0
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL
+//RLC_GPM_INT_FORCE_TH0
+#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
+#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL
+//RLC_SRM_CNTL
+#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
+#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
+#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L
+#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_GPM_COMMAND
+#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
+#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
+#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
+#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL
+#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L
+#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L
+#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L
+//RLC_SRM_GPM_COMMAND_STATUS
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_RLCV_COMMAND
+#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
+#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L
+#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL
+#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L
+#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L
+//RLC_SRM_RLCV_COMMAND_STATUS
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_INDEX_CNTL_ADDR_0
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_1
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_2
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_3
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_4
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_5
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_6
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_ADDR_7
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L
+//RLC_SRM_INDEX_CNTL_DATA_0
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_1
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_2
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_3
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_4
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_5
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_6
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_INDEX_CNTL_DATA_7
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_STAT
+#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0
+#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1
+#define RLC_SRM_STAT__RESERVED__SHIFT 0x2
+#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L
+#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L
+#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL
+//RLC_SRM_GPM_ABORT
+#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
+#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
+#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L
+#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_CSIB_ADDR_LO
+#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL
+//RLC_CSIB_ADDR_HI
+#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL
+//RLC_CSIB_LENGTH
+#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
+#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL
+//RLC_PACE_INT_STAT
+#define RLC_PACE_INT_STAT__STATUS__SHIFT 0x0
+#define RLC_PACE_INT_STAT__STATUS_MASK 0xFFFFFFFFL
+//RLC_SMU_COMMAND
+#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
+#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL
+//RLC_CP_SCHEDULERS
+#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
+#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
+#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
+#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
+#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL
+#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L
+#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L
+#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L
+//RLC_SMU_ARGUMENT_1
+#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0
+#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL
+//RLC_SMU_ARGUMENT_2
+#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0
+#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_8
+#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_9
+#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_10
+#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_11
+#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_12
+#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_CNTL_0
+#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18
+#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19
+#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a
+#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e
+#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L
+#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L
+#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L
+#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L
+//RLC_GPM_UTCL1_CNTL_1
+#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18
+#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19
+#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a
+#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e
+#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L
+#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L
+#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L
+#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L
+//RLC_GPM_UTCL1_CNTL_2
+#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18
+#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19
+#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a
+#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e
+#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L
+#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L
+#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L
+#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L
+//RLC_SPM_UTCL1_CNTL
+#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e
+#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
+//RLC_UTCL1_STATUS_2
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9
+#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L
+#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L
+#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L
+#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L
+#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L
+#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L
+#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L
+//RLC_LB_CONFIG_2
+#define RLC_LB_CONFIG_2__DATA__SHIFT 0x0
+#define RLC_LB_CONFIG_2__DATA_MASK 0xFFFFFFFFL
+//RLC_LB_CONFIG_3
+#define RLC_LB_CONFIG_3__DATA__SHIFT 0x0
+#define RLC_LB_CONFIG_3__DATA_MASK 0xFFFFFFFFL
+//RLC_LB_CONFIG_4
+#define RLC_LB_CONFIG_4__DATA__SHIFT 0x0
+#define RLC_LB_CONFIG_4__DATA_MASK 0xFFFFFFFFL
+//RLC_SPM_UTCL1_ERROR_1
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_SPM_UTCL1_ERROR_2
+#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH0_ERROR_1
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_LB_CONFIG_1
+#define RLC_LB_CONFIG_1__DATA__SHIFT 0x0
+#define RLC_LB_CONFIG_1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH0_ERROR_2
+#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH1_ERROR_1
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_GPM_UTCL1_TH1_ERROR_2
+#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_GPM_UTCL1_TH2_ERROR_1
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
+#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
+//RLC_GPM_UTCL1_TH2_ERROR_2
+#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
+#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
+//RLC_CGCG_CGLS_CTRL_3D
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1
+#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c
+#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d
+#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L
+#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L
+#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L
+#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L
+#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L
+#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L
+//RLC_CGCG_RAMP_CTRL_3D
+#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0
+#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4
+#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8
+#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc
+#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10
+#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c
+#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL
+#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
+#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L
+#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L
+#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L
+#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L
+//RLC_SEMAPHORE_0
+#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
+//RLC_SEMAPHORE_1
+#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
+//RLC_CP_EOF_INT
+#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0
+#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1
+#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_CP_EOF_INT_CNT
+#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0
+#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL
+//RLC_SPARE_INT
+#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0
+#define RLC_SPARE_INT__RESERVED__SHIFT 0x1
+#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_PREWALKER_UTCL1_CNTL
+#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
+#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19
+#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
+#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
+#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e
+#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
+#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
+#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L
+#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
+#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
+#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
+#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
+//RLC_PREWALKER_UTCL1_TRIG
+#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1
+#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5
+#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6
+#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7
+#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8
+#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9
+#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f
+#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L
+#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL
+#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L
+#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L
+#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L
+#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L
+#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L
+#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L
+//RLC_PREWALKER_UTCL1_ADDR_LSB
+#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL
+//RLC_PREWALKER_UTCL1_ADDR_MSB
+#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL
+//RLC_PREWALKER_UTCL1_SIZE_LSB
+#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL
+//RLC_PREWALKER_UTCL1_SIZE_MSB
+#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0
+#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L
+//RLC_UTCL1_STATUS
+#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
+#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
+#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
+#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3
+#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
+#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe
+#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
+#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16
+#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
+#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e
+#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
+#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
+#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
+#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L
+#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
+#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L
+#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
+#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L
+#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
+#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L
+//RLC_R2I_CNTL_0
+#define RLC_R2I_CNTL_0__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL
+//RLC_R2I_CNTL_1
+#define RLC_R2I_CNTL_1__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL
+//RLC_R2I_CNTL_2
+#define RLC_R2I_CNTL_2__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL
+//RLC_R2I_CNTL_3
+#define RLC_R2I_CNTL_3__Data__SHIFT 0x0
+#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL
+//RLC_LB_WGP_STAT
+#define RLC_LB_WGP_STAT__MAX_WGP__SHIFT 0x0
+#define RLC_LB_WGP_STAT__ON_WGP__SHIFT 0x10
+#define RLC_LB_WGP_STAT__MAX_WGP_MASK 0x0000FFFFL
+#define RLC_LB_WGP_STAT__ON_WGP_MASK 0xFFFF0000L
+//RLC_GPM_INT_STAT_TH0
+#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0
+#define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_13
+#define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_14
+#define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_GENERAL_15
+#define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL
+//RLC_SPARE_INT_1
+#define RLC_SPARE_INT_1__INTERRUPT__SHIFT 0x0
+#define RLC_SPARE_INT_1__RESERVED__SHIFT 0x1
+#define RLC_SPARE_INT_1__INTERRUPT_MASK 0x00000001L
+#define RLC_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_RLCV_SPARE_INT_1
+#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0
+#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1
+#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L
+#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_PACE_SPARE_INT_1
+#define RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT 0x0
+#define RLC_PACE_SPARE_INT_1__RESERVED__SHIFT 0x1
+#define RLC_PACE_SPARE_INT_1__INTERRUPT_MASK 0x00000001L
+#define RLC_PACE_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_SEMAPHORE_2
+#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
+//RLC_SEMAPHORE_3
+#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
+#define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5
+#define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
+#define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
+//RLC_SMU_ARGUMENT_3
+#define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0
+#define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL
+//RLC_SMU_ARGUMENT_4
+#define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0
+#define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL
+//RLC_GPU_CLOCK_COUNT_LSB_1
+#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
+//RLC_GPU_CLOCK_COUNT_MSB_1
+#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
+//RLC_CAPTURE_GPU_CLOCK_COUNT_1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_GPU_CLOCK_COUNT_LSB_2
+#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
+//RLC_GPU_CLOCK_COUNT_MSB_2
+#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
+//RLC_PACE_INT_DISABLE
+#define RLC_PACE_INT_DISABLE__DISABLE__SHIFT 0x0
+#define RLC_PACE_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL
+//RLC_CAPTURE_GPU_CLOCK_COUNT_2
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L
+#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL
+//RLC_RLCV_SPARE_INT
+#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0
+#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1
+#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_PACE_TIMER_INT_0
+#define RLC_PACE_TIMER_INT_0__TIMER__SHIFT 0x0
+#define RLC_PACE_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
+//RLC_PACE_TIMER_CTRL
+#define RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
+#define RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
+#define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2
+#define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3
+#define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4
+#define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5
+#define RLC_PACE_TIMER_CTRL__RESERVED__SHIFT 0x6
+#define RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
+#define RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
+#define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L
+#define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L
+#define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L
+#define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L
+#define RLC_PACE_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L
+//RLC_PACE_TIMER_INT_1
+#define RLC_PACE_TIMER_INT_1__TIMER__SHIFT 0x0
+#define RLC_PACE_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
+//RLC_PACE_SPARE_INT
+#define RLC_PACE_SPARE_INT__INTERRUPT__SHIFT 0x0
+#define RLC_PACE_SPARE_INT__RESERVED__SHIFT 0x1
+#define RLC_PACE_SPARE_INT__INTERRUPT_MASK 0x00000001L
+#define RLC_PACE_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
+//RLC_SMU_CLK_REQ
+#define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0
+#define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L
+//RLC_CP_STAT_INVAL_STAT
+#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT 0x0
+#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT 0x1
+#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT 0x2
+#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT 0x3
+#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT 0x4
+#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT 0x5
+#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK 0x00000001L
+#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK 0x00000002L
+#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK 0x00000004L
+#define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK 0x00000008L
+#define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK 0x00000010L
+#define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK 0x00000020L
+//RLC_CP_STAT_INVAL_CTRL
+#define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT 0x0
+#define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT 0x1
+#define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT 0x2
+#define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK 0x00000001L
+#define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK 0x00000002L
+#define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK 0x00000004L
+//RLC_SPP_CTRL
+#define RLC_SPP_CTRL__ENABLE__SHIFT 0x0
+#define RLC_SPP_CTRL__ENABLE_PPROF__SHIFT 0x1
+#define RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT 0x2
+#define RLC_SPP_CTRL__PAUSE__SHIFT 0x3
+#define RLC_SPP_CTRL__ENABLE_MASK 0x00000001L
+#define RLC_SPP_CTRL__ENABLE_PPROF_MASK 0x00000002L
+#define RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK 0x00000004L
+#define RLC_SPP_CTRL__PAUSE_MASK 0x00000008L
+//RLC_SPP_SHADER_PROFILE_EN
+#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT 0x0
+#define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE__SHIFT 0x1
+#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT 0x2
+#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT 0x3
+#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT 0x4
+#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT 0x5
+#define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT 0x6
+#define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION__SHIFT 0x7
+#define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT 0x8
+#define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT 0x9
+#define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT 0xa
+#define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT 0xb
+#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT 0xc
+#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT 0xd
+#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT 0xe
+#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT 0xf
+#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT 0x10
+#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK 0x00000001L
+#define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE_MASK 0x00000002L
+#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK 0x00000004L
+#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK 0x00000008L
+#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK 0x00000010L
+#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK 0x00000020L
+#define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK 0x00000040L
+#define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION_MASK 0x00000080L
+#define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK 0x00000100L
+#define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK 0x00000200L
+#define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK 0x00000400L
+#define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK 0x00000800L
+#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK 0x00001000L
+#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK 0x00002000L
+#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK 0x00004000L
+#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK 0x00008000L
+#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK 0x00010000L
+//RLC_SPP_SSF_CAPTURE_EN
+#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT 0x0
+#define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE__SHIFT 0x1
+#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT 0x2
+#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT 0x3
+#define RLC_SPP_SSF_CAPTURE_EN__CGS_ENABLE__SHIFT 0x4
+#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT 0x5
+#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK 0x00000001L
+#define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE_MASK 0x00000002L
+#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK 0x00000004L
+#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK 0x00000008L
+#define RLC_SPP_SSF_CAPTURE_EN__CGS_ENABLE_MASK 0x00000010L
+#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK 0x00000020L
+//RLC_SPP_SSF_THRESHOLD_0
+#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT 0x0
+#define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD__SHIFT 0x10
+#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK 0x0000FFFFL
+#define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD_MASK 0xFFFF0000L
+//RLC_SPP_SSF_THRESHOLD_1
+#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT 0x0
+#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT 0x10
+#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK 0x0000FFFFL
+#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK 0xFFFF0000L
+//RLC_SPP_SSF_THRESHOLD_2
+#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT 0x0
+#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT 0x10
+#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK 0x0000FFFFL
+#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK 0xFFFF0000L
+//RLC_SPP_INFLIGHT_RD_ADDR
+#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT 0x0
+#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK 0x0000001FL
+//RLC_SPP_INFLIGHT_RD_DATA
+#define RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT 0x0
+#define RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SPP_PROF_INFO_1
+#define RLC_SPP_PROF_INFO_1__SH_ID__SHIFT 0x0
+#define RLC_SPP_PROF_INFO_1__SH_ID_MASK 0xFFFFFFFFL
+//RLC_SPP_PROF_INFO_2
+#define RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT 0x0
+#define RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT 0x4
+#define RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT 0x5
+#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT 0x6
+#define RLC_SPP_PROF_INFO_2__SH_TYPE_MASK 0x0000000FL
+#define RLC_SPP_PROF_INFO_2__CAM_HIT_MASK 0x00000010L
+#define RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK 0x00000020L
+#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK 0x00000040L
+//RLC_SPP_GLOBAL_SH_ID
+#define RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT 0x0
+#define RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK 0xFFFFFFFFL
+//RLC_SPP_GLOBAL_SH_ID_VALID
+#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT 0x0
+#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK 0x00000001L
+//RLC_SPP_STATUS
+#define RLC_SPP_STATUS__RESERVED_0__SHIFT 0x0
+#define RLC_SPP_STATUS__SSF_BUSY__SHIFT 0x1
+#define RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT 0x2
+#define RLC_SPP_STATUS__SPP_BUSY__SHIFT 0x1f
+#define RLC_SPP_STATUS__RESERVED_0_MASK 0x00000001L
+#define RLC_SPP_STATUS__SSF_BUSY_MASK 0x00000002L
+#define RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK 0x00000004L
+#define RLC_SPP_STATUS__SPP_BUSY_MASK 0x80000000L
+//RLC_SPP_PVT_STAT_0
+#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT 0x0
+#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT 0x6
+#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT 0xc
+#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT 0x12
+#define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER__SHIFT 0x18
+#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK 0x0000003FL
+#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK 0x00000FC0L
+#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK 0x0003F000L
+#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK 0x00FC0000L
+#define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER_MASK 0x7F000000L
+//RLC_SPP_PVT_STAT_1
+#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT 0x0
+#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT 0x6
+#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT 0xc
+#define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER__SHIFT 0x12
+#define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER__SHIFT 0x18
+#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK 0x0000003FL
+#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK 0x00000FC0L
+#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK 0x0003F000L
+#define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER_MASK 0x00FC0000L
+#define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER_MASK 0x7F000000L
+//RLC_SPP_PVT_STAT_2
+#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT 0x0
+#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT 0x6
+#define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER__SHIFT 0xc
+#define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER__SHIFT 0x12
+#define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER__SHIFT 0x18
+#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK 0x0000003FL
+#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK 0x00000FC0L
+#define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER_MASK 0x0003F000L
+#define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER_MASK 0x00FC0000L
+#define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER_MASK 0x7F000000L
+//RLC_SPP_PVT_STAT_3
+#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT 0x0
+#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK 0x0000003FL
+//RLC_SPP_PVT_LEVEL_MAX
+#define RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT 0x0
+#define RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK 0x0000000FL
+//RLC_SPP_STALL_STATE_UPDATE
+#define RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT 0x0
+#define RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT 0x1
+#define RLC_SPP_STALL_STATE_UPDATE__STALL_MASK 0x00000001L
+#define RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK 0x00000002L
+//RLC_SPP_PBB_INFO
+#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT 0x0
+#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT 0x1
+#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT 0x2
+#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT 0x3
+#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK 0x00000001L
+#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK 0x00000002L
+#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK 0x00000004L
+#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK 0x00000008L
+//RLC_SPP_RESET
+#define RLC_SPP_RESET__SSF_RESET__SHIFT 0x0
+#define RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT 0x1
+#define RLC_SPP_RESET__CAM_RESET__SHIFT 0x2
+#define RLC_SPP_RESET__PVT_RESET__SHIFT 0x3
+#define RLC_SPP_RESET__SSF_RESET_MASK 0x00000001L
+#define RLC_SPP_RESET__EVENT_ARB_RESET_MASK 0x00000002L
+#define RLC_SPP_RESET__CAM_RESET_MASK 0x00000004L
+#define RLC_SPP_RESET__PVT_RESET_MASK 0x00000008L
+//RLC_SPM_SAMPLE_CNT
+#define RLC_SPM_SAMPLE_CNT__COUNT__SHIFT 0x0
+#define RLC_SPM_SAMPLE_CNT__COUNT_MASK 0xFFFFFFFFL
+//RLC_PCC_STRETCH_HYSTERESIS_CNTL
+#define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0
+#define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT__SHIFT 0x8
+#define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL
+#define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT_MASK 0x0000FF00L
+//RLC_GPU_CLOCK_COUNT_SPM_LSB
+#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
+//RLC_GPU_CLOCK_COUNT_SPM_MSB
+#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
+//RLC_SPM_THREAD_TRACE_CTRL
+#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT 0x0
+#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK 0x00000001L
+//RLC_LB_CNTR_2
+#define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
+#define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL
+//RLC_CPAXI_DOORBELL_MON_CTRL
+#define RLC_CPAXI_DOORBELL_MON_CTRL__EN__SHIFT 0x0
+#define RLC_CPAXI_DOORBELL_MON_CTRL__ID__SHIFT 0x1
+#define RLC_CPAXI_DOORBELL_MON_CTRL__EN_MASK 0x00000001L
+#define RLC_CPAXI_DOORBELL_MON_CTRL__ID_MASK 0x0000003EL
+//RLC_CPAXI_DOORBELL_MON_STAT
+#define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH__SHIFT 0x0
+#define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR__SHIFT 0x1
+#define RLC_CPAXI_DOORBELL_MON_STAT__ADDR__SHIFT 0x2
+#define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH_MASK 0x00000001L
+#define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR_MASK 0x00000002L
+#define RLC_CPAXI_DOORBELL_MON_STAT__ADDR_MASK 0x0FFFFFFCL
+//RLC_CPAXI_DOORBELL_MON_DATA_LSB
+#define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA__SHIFT 0x0
+#define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA_MASK 0xFFFFFFFFL
+//RLC_CPAXI_DOORBELL_MON_DATA_MSB
+#define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA__SHIFT 0x0
+#define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_rlcrdec
+//RLC_SPP_CAM_ADDR
+#define RLC_SPP_CAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SPP_CAM_ADDR__ADDR_MASK 0x000000FFL
+//RLC_SPP_CAM_DATA
+#define RLC_SPP_CAM_DATA__DATA__SHIFT 0x0
+#define RLC_SPP_CAM_DATA__TAG__SHIFT 0x8
+#define RLC_SPP_CAM_DATA__DATA_MASK 0x000000FFL
+#define RLC_SPP_CAM_DATA__TAG_MASK 0xFFFFFF00L
+//RLC_SPP_CAM_EXT_ADDR
+#define RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT 0x0
+#define RLC_SPP_CAM_EXT_ADDR__ADDR_MASK 0x000000FFL
+//RLC_SPP_CAM_EXT_DATA
+#define RLC_SPP_CAM_EXT_DATA__VALID__SHIFT 0x0
+#define RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT 0x1
+#define RLC_SPP_CAM_EXT_DATA__VALID_MASK 0x00000001L
+#define RLC_SPP_CAM_EXT_DATA__LOCK_MASK 0x00000002L
+//RLC_PACE_SCRATCH_ADDR
+#define RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_PACE_SCRATCH_ADDR__ADDR_MASK 0xFFFFFFFFL
+//RLC_PACE_SCRATCH_DATA
+#define RLC_PACE_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_PACE_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_rlcsdec
+//RLC_RLCS_DEC_START
+//RLC_RLCS_DEC_DUMP_ADDR
+//RLC_RLCS_EXCEPTION_REG_1
+#define RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT 0x0
+#define RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT 0x12
+#define RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK 0x0003FFFFL
+#define RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_EXCEPTION_REG_2
+#define RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT 0x0
+#define RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT 0x12
+#define RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK 0x0003FFFFL
+#define RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_EXCEPTION_REG_3
+#define RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT 0x0
+#define RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT 0x12
+#define RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK 0x0003FFFFL
+#define RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_EXCEPTION_REG_4
+#define RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT 0x0
+#define RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT 0x12
+#define RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK 0x0003FFFFL
+#define RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_GENERAL_6
+#define RLC_RLCS_GENERAL_6__DATA__SHIFT 0x0
+#define RLC_RLCS_GENERAL_6__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_GENERAL_7
+#define RLC_RLCS_GENERAL_7__DATA__SHIFT 0x0
+#define RLC_RLCS_GENERAL_7__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_CGCG_REQUEST
+#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT 0x0
+#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT 0x1
+#define RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT 0x2
+#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK 0x00000001L
+#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK 0x00000002L
+#define RLC_RLCS_CGCG_REQUEST__RESERVED_MASK 0xFFFFFFFCL
+//RLC_RLCS_CGCG_STATUS
+#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT 0x0
+#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT 0x2
+#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT 0x3
+#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT 0x5
+#define RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT 0x6
+#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK 0x00000003L
+#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK 0x00000004L
+#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK 0x00000018L
+#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK 0x00000020L
+#define RLC_RLCS_CGCG_STATUS__RESERVED_MASK 0xFFFFFFC0L
+//RLC_RLCS_SMU_GFXCLK_STATUS
+#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG__SHIFT 0x0
+#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE__SHIFT 0x1
+#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC__SHIFT 0x2
+#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL__SHIFT 0x3
+#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG_MASK 0x00000001L
+#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE_MASK 0x00000002L
+#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC_MASK 0x00000004L
+#define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL_MASK 0x00000008L
+//RLC_RLCS_SMU_GFXCLK_CONTROL
+#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG__SHIFT 0x0
+#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER__SHIFT 0x1
+#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL__SHIFT 0x8
+#define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED__SHIFT 0x9
+#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG_MASK 0x00000001L
+#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER_MASK 0x000000FEL
+#define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL_MASK 0x00000100L
+#define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED_MASK 0xFFFFFE00L
+//RLC_RLCS_SOC_DS_CNTL
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT 0x0
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x2
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x3
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x4
+#define RLC_RLCS_SOC_DS_CNTL__RESERVED_5__SHIFT 0x5
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7
+#define RLC_RLCS_SOC_DS_CNTL__RESERVED__SHIFT 0x8
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK 0x00000001L
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00000008L
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00000010L
+#define RLC_RLCS_SOC_DS_CNTL__RESERVED_5_MASK 0x00000020L
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L
+#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L
+#define RLC_RLCS_SOC_DS_CNTL__RESERVED_MASK 0xFFFFFF00L
+//RLC_RLCS_GFX_DS_CNTL
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT 0x0
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x2
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x3
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x4
+#define RLC_RLCS_GFX_DS_CNTL__RESERVED_5__SHIFT 0x5
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7
+#define RLC_RLCS_GFX_DS_CNTL__RESERVED__SHIFT 0x8
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK 0x00000001L
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00000008L
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00000010L
+#define RLC_RLCS_GFX_DS_CNTL__RESERVED_5_MASK 0x00000020L
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L
+#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L
+#define RLC_RLCS_GFX_DS_CNTL__RESERVED_MASK 0xFFFFFF00L
+//RLC_GPM_STAT
+#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
+#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
+#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
+#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
+#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd
+#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe
+#define RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf
+#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
+#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12
+#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14
+#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15
+#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16
+#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17
+#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
+#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L
+#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L
+#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L
+#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L
+#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L
+#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L
+#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L
+#define RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L
+#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L
+#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L
+#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L
+#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L
+#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L
+#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L
+#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L
+//RLC_RLCS_GPM_STAT
+#define RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
+#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
+#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
+#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
+#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
+#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
+#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
+#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
+#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
+#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
+#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
+#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
+#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd
+#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe
+#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf
+#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10
+#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
+#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT 0x12
+#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13
+#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14
+#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15
+#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16
+#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17
+#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
+#define RLC_RLCS_GPM_STAT__RLC_BUSY_MASK 0x00000001L
+#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L
+#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L
+#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L
+#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L
+#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L
+#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L
+#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L
+#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L
+#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L
+#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L
+#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L
+#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L
+#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L
+#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L
+#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L
+#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L
+#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L
+#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK 0x00040000L
+#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L
+#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L
+#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L
+#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L
+#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L
+#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L
+//RLC_RLCS_ABORTED_PD_SEQUENCE
+#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT 0x0
+#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT 0x10
+#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK 0x0000FFFFL
+#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK 0xFFFF0000L
+//RLC_RLCS_DIDT_FORCE_STALL
+#define RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT 0x0
+#define RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT 0x3
+#define RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK 0x00000007L
+#define RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK 0xFFFFFFF8L
+//RLC_RLCS_IOV_CMD_STATUS
+#define RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT 0x0
+#define RLC_RLCS_IOV_CMD_STATUS__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_IOV_CNTX_LOC_SIZE
+#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT 0x0
+#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT 0x8
+#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK 0x000000FFL
+#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK 0xFFFFFF00L
+//RLC_RLCS_IOV_SCH_BLOCK
+#define RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT 0x0
+#define RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_IOV_VM_BUSY_STATUS
+#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT 0x0
+#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_GPM_STAT_2
+#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT 0x0
+#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT 0x1
+#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT 0x2
+#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT 0x3
+#define RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT 0x4
+#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK 0x00000001L
+#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK 0x00000002L
+#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK 0x00000004L
+#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK 0x00000008L
+#define RLC_RLCS_GPM_STAT_2__RESERVED_MASK 0xFFFFFFF0L
+//RLC_RLCS_GRBM_SOFT_RESET
+#define RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT 0x0
+#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT 0x1
+#define RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK 0x00000001L
+#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL
+//RLC_RLCS_PG_CHANGE_STATUS
+#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT 0x0
+#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT 0x1
+#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT 0x2
+#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT 0x3
+#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT 0x4
+#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK 0x00000001L
+#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK 0x00000002L
+#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK 0x00000004L
+#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK 0x00000008L
+#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK 0xFFFFFFF0L
+//RLC_RLCS_PG_CHANGE_READ
+#define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED__SHIFT 0x0
+#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT 0x1
+#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT 0x2
+#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT 0x3
+#define RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT 0x4
+#define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED_MASK 0x00000001L
+#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK 0x00000002L
+#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK 0x00000004L
+#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK 0x00000008L
+#define RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK 0xFFFFFFF0L
+//RLC_RLCS_LB_STATUS
+#define RLC_RLCS_LB_STATUS__LB_CNTR_START__SHIFT 0x0
+#define RLC_RLCS_LB_STATUS__LB_CNTR_STOP__SHIFT 0x1
+#define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG__SHIFT 0x2
+#define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG__SHIFT 0x3
+#define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG__SHIFT 0x4
+#define RLC_RLCS_LB_STATUS__RESERVED__SHIFT 0x5
+#define RLC_RLCS_LB_STATUS__LB_CNTR_START_MASK 0x00000001L
+#define RLC_RLCS_LB_STATUS__LB_CNTR_STOP_MASK 0x00000002L
+#define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG_MASK 0x00000004L
+#define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG_MASK 0x00000008L
+#define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG_MASK 0x00000010L
+#define RLC_RLCS_LB_STATUS__RESERVED_MASK 0xFFFFFFE0L
+//RLC_RLCS_LB_READ
+#define RLC_RLCS_LB_READ__LB_CNTR_START__SHIFT 0x0
+#define RLC_RLCS_LB_READ__LB_CNTR_STOP__SHIFT 0x1
+#define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG__SHIFT 0x2
+#define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG__SHIFT 0x3
+#define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG__SHIFT 0x4
+#define RLC_RLCS_LB_READ__RESERVED__SHIFT 0x5
+#define RLC_RLCS_LB_READ__LB_CNTR_START_MASK 0x00000001L
+#define RLC_RLCS_LB_READ__LB_CNTR_STOP_MASK 0x00000002L
+#define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG_MASK 0x00000004L
+#define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG_MASK 0x00000008L
+#define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG_MASK 0x00000010L
+#define RLC_RLCS_LB_READ__RESERVED_MASK 0xFFFFFFE0L
+//RLC_RLCS_LB_CONTROL
+#define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ__SHIFT 0x0
+#define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY__SHIFT 0x1
+#define RLC_RLCS_LB_CONTROL__RESERVED__SHIFT 0x2
+#define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ_MASK 0x00000001L
+#define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY_MASK 0x00000002L
+#define RLC_RLCS_LB_CONTROL__RESERVED_MASK 0xFFFFFFFCL
+//RLC_RLCS_IH_SEMAPHORE
+#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT 0x0
+#define RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT 0x5
+#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL
+#define RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L
+//RLC_RLCS_IH_COOKIE_SEMAPHORE
+#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT 0x0
+#define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT 0x5
+#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL
+#define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L
+//RLC_RLCS_IH_CTRL_1
+#define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1__SHIFT 0x0
+#define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1_MASK 0xFFFFFFFFL
+//RLC_RLCS_IH_CTRL_2
+#define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2__SHIFT 0x0
+#define RLC_RLCS_IH_CTRL_2__IH_RING_ID__SHIFT 0x8
+#define RLC_RLCS_IH_CTRL_2__IH_VM_ID__SHIFT 0x10
+#define RLC_RLCS_IH_CTRL_2__RESERVED__SHIFT 0x14
+#define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2_MASK 0x000000FFL
+#define RLC_RLCS_IH_CTRL_2__IH_RING_ID_MASK 0x0000FF00L
+#define RLC_RLCS_IH_CTRL_2__IH_VM_ID_MASK 0x000F0000L
+#define RLC_RLCS_IH_CTRL_2__RESERVED_MASK 0xFFF00000L
+//RLC_RLCS_IH_CTRL_3
+#define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID__SHIFT 0x0
+#define RLC_RLCS_IH_CTRL_3__IH_VF_ID__SHIFT 0x8
+#define RLC_RLCS_IH_CTRL_3__IH_VF__SHIFT 0xd
+#define RLC_RLCS_IH_CTRL_3__RESERVED__SHIFT 0xe
+#define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID_MASK 0x000000FFL
+#define RLC_RLCS_IH_CTRL_3__IH_VF_ID_MASK 0x00001F00L
+#define RLC_RLCS_IH_CTRL_3__IH_VF_MASK 0x00002000L
+#define RLC_RLCS_IH_CTRL_3__RESERVED_MASK 0xFFFFC000L
+//RLC_RLCS_IH_STATUS
+#define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT__SHIFT 0x0
+#define RLC_RLCS_IH_STATUS__IH_BUSY__SHIFT 0x6
+#define RLC_RLCS_IH_STATUS__RESERVED__SHIFT 0x7
+#define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT_MASK 0x0000003FL
+#define RLC_RLCS_IH_STATUS__IH_BUSY_MASK 0x00000040L
+#define RLC_RLCS_IH_STATUS__RESERVED_MASK 0xFFFFFF80L
+//RLC_RLCS_WGP_STATUS
+#define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT 0x0
+#define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1
+#define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2
+#define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT 0x3
+#define RLC_RLCS_WGP_STATUS__RESERVED__SHIFT 0x4
+#define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK 0x00000001L
+#define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L
+#define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L
+#define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK 0x00000008L
+#define RLC_RLCS_WGP_STATUS__RESERVED_MASK 0xFFFFFFF0L
+//RLC_RLCS_WGP_READ
+#define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT 0x0
+#define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1
+#define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2
+#define RLC_RLCS_WGP_READ__RESERVED__SHIFT 0x3
+#define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK 0x00000001L
+#define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L
+#define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L
+#define RLC_RLCS_WGP_READ__RESERVED_MASK 0xFFFFFFF8L
+//RLC_RLCS_CP_INT_CTRL_1
+#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT 0x0
+#define RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT 0x1
+#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK 0x00000001L
+#define RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK 0xFFFFFFFEL
+//RLC_RLCS_CP_INT_CTRL_2
+#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT 0x0
+#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT 0x1
+#define RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT 0x2
+#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK 0x00000001L
+#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK 0x00000002L
+#define RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK 0xFFFFFFFCL
+//RLC_RLCS_CP_INT_INFO_1
+#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0
+#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL
+//RLC_RLCS_CP_INT_INFO_2
+#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0
+#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10
+#define RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT 0x19
+#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL
+#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L
+#define RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK 0xFE000000L
+//RLC_RLCS_SPM_INT_CTRL
+#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT 0x0
+#define RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT 0x1
+#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK 0x00000001L
+#define RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK 0xFFFFFFFEL
+//RLC_RLCS_SPM_INT_INFO_1
+#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0
+#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL
+//RLC_RLCS_SPM_INT_INFO_2
+#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0
+#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10
+#define RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT 0x19
+#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL
+#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L
+#define RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK 0xFE000000L
+//RLC_RLCS_DSM_TRIG
+#define RLC_RLCS_DSM_TRIG__START__SHIFT 0x0
+#define RLC_RLCS_DSM_TRIG__RESERVED__SHIFT 0x1
+#define RLC_RLCS_DSM_TRIG__START_MASK 0x00000001L
+#define RLC_RLCS_DSM_TRIG__RESERVED_MASK 0xFFFFFFFEL
+//RLC_RLCS_GE_FAST_CLOCK
+#define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_CHANGED__SHIFT 0x0
+#define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS__SHIFT 0x1
+#define RLC_RLCS_GE_FAST_CLOCK__INT_CLEAR__SHIFT 0x2
+#define RLC_RLCS_GE_FAST_CLOCK__RESERVED__SHIFT 0x3
+#define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_CHANGED_MASK 0x00000001L
+#define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_MASK 0x00000002L
+#define RLC_RLCS_GE_FAST_CLOCK__INT_CLEAR_MASK 0x00000004L
+#define RLC_RLCS_GE_FAST_CLOCK__RESERVED_MASK 0xFFFFFFF8L
+//RLC_RLCS_BOOTLOAD_STATUS
+#define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED__SHIFT 0x0
+#define RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT 0x1
+#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT 0x1f
+#define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED_MASK 0x00000001L
+#define RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK 0x7FFFFFFEL
+#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK 0x80000000L
+//RLC_RLCS_POWER_BRAKE_CNTL
+#define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT 0x0
+#define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT 0x1
+#define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT 0x2
+#define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT 0xa
+#define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT 0x12
+#define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK 0x00000001L
+#define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK 0x00000002L
+#define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK 0x000003FCL
+#define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK 0x0003FC00L
+#define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_GENERAL_0
+#define RLC_RLCS_GENERAL_0__DATA__SHIFT 0x0
+#define RLC_RLCS_GENERAL_0__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_GENERAL_1
+#define RLC_RLCS_GENERAL_1__DATA__SHIFT 0x0
+#define RLC_RLCS_GENERAL_1__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_GENERAL_2
+#define RLC_RLCS_GENERAL_2__DATA__SHIFT 0x0
+#define RLC_RLCS_GENERAL_2__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_GENERAL_3
+#define RLC_RLCS_GENERAL_3__DATA__SHIFT 0x0
+#define RLC_RLCS_GENERAL_3__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_GENERAL_4
+#define RLC_RLCS_GENERAL_4__DATA__SHIFT 0x0
+#define RLC_RLCS_GENERAL_4__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_GENERAL_5
+#define RLC_RLCS_GENERAL_5__DATA__SHIFT 0x0
+#define RLC_RLCS_GENERAL_5__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCS_GRBM_IDLE_BUSY_STAT
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_gc_stat_idle__SHIFT 0x0
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT 0x2
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT 0x3
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_4__SHIFT 0x4
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT 0x5
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT 0x6
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_7__SHIFT 0x7
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED__SHIFT 0x8
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_gc_stat_idle_MASK 0x00000003L
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK 0x00000004L
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK 0x00000008L
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_4_MASK 0x00000010L
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK 0x00000020L
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK 0x00000040L
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_7_MASK 0x00000080L
+#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_MASK 0xFFFFFF00L
+//RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL
+#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT 0x0
+#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT 0x1
+#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__RESERVED_2__SHIFT 0x2
+#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK 0x00000001L
+#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK 0x00000002L
+#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__RESERVED_2_MASK 0x00000004L
+//RLC_RLCS_CMP_IDLE_CNTL
+#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT 0x0
+#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT 0x1
+#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT 0x2
+#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT 0x3
+#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT 0xb
+#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT 0x13
+#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK 0x00000001L
+#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK 0x00000002L
+#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK 0x00000004L
+#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK 0x000007F8L
+#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK 0x0007F800L
+#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK 0xFFF80000L
+//RLC_RLCS_POWER_BRAKE_CNTL_TH1
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT 0x0
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT 0x1
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT 0x2
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT 0xa
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT 0x12
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK 0x00000001L
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK 0x00000002L
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK 0x000003FCL
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK 0x0003FC00L
+#define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_AUXILIARY_REG_1
+#define RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT 0x0
+#define RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT 0x12
+#define RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK 0x0003FFFFL
+#define RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_AUXILIARY_REG_2
+#define RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT 0x0
+#define RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT 0x12
+#define RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK 0x0003FFFFL
+#define RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_AUXILIARY_REG_3
+#define RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT 0x0
+#define RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT 0x12
+#define RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK 0x0003FFFFL
+#define RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_AUXILIARY_REG_4
+#define RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT 0x0
+#define RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT 0x12
+#define RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK 0x0003FFFFL
+#define RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK 0xFFFC0000L
+//RLC_RLCS_SPM_SQTT_MODE
+#define RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT 0x0
+#define RLC_RLCS_SPM_SQTT_MODE__MODE_MASK 0x00000001L
+//RLC_RLCS_CP_DMA_SRCID_OVER
+#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT 0x0
+#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK 0x00000001L
+//RLC_RLCS_UTCL2_CNTL
+#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0
+#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT 0x1
+#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT 0x2
+#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT 0x3
+#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT 0x5
+#define RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT 0x6
+#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L
+#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK 0x00000002L
+#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK 0x00000004L
+#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK 0x00000018L
+#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK 0x00000020L
+#define RLC_RLCS_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFC0L
+//RLC_RLCS_MP1_RLC_DOORBELL_CTRL
+#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR__SHIFT 0x0
+#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL__SHIFT 0x1
+#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED__SHIFT 0x2
+#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR_MASK 0x00000001L
+#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL_MASK 0x00000002L
+#define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED_MASK 0xFFFFFFFCL
+//RLC_RLCS_BOOTLOAD_ID_STATUS1
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT 0x0
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT 0x1
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT 0x2
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT 0x3
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT 0x4
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT 0x5
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT 0x6
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT 0x7
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT 0x8
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT 0x9
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT 0xa
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT 0xb
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT 0xc
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT 0xd
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT 0xe
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT 0xf
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT 0x10
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT 0x11
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT 0x12
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT 0x13
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT 0x14
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT 0x15
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT 0x16
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT 0x17
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT 0x18
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT 0x19
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT 0x1a
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT 0x1b
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT 0x1c
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT 0x1d
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT 0x1e
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT 0x1f
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK 0x00000001L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK 0x00000002L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK 0x00000004L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK 0x00000008L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK 0x00000010L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK 0x00000020L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK 0x00000040L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK 0x00000080L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK 0x00000100L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK 0x00000200L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK 0x00000400L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK 0x00000800L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK 0x00001000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK 0x00002000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK 0x00004000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK 0x00008000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK 0x00010000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK 0x00020000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK 0x00040000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK 0x00080000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK 0x00100000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK 0x00200000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK 0x00400000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK 0x00800000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK 0x01000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK 0x02000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK 0x04000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK 0x08000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK 0x10000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK 0x20000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK 0x40000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK 0x80000000L
+//RLC_RLCS_BOOTLOAD_ID_STATUS2
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT 0x0
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT 0x1
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT 0x2
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT 0x3
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT 0x4
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT 0x5
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT 0x6
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT 0x7
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT 0x8
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT 0x9
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT 0xa
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT 0xb
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT 0xc
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT 0xd
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT 0xe
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT 0xf
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT 0x10
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT 0x11
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT 0x12
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT 0x13
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT 0x14
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT 0x15
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT 0x16
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT 0x17
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT 0x18
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT 0x19
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT 0x1a
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT 0x1b
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT 0x1c
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT 0x1d
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT 0x1e
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT 0x1f
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK 0x00000001L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK 0x00000002L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK 0x00000004L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK 0x00000008L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK 0x00000010L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK 0x00000020L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK 0x00000040L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK 0x00000080L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK 0x00000100L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK 0x00000200L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK 0x00000400L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK 0x00000800L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK 0x00001000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK 0x00002000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK 0x00004000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK 0x00008000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK 0x00010000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK 0x00020000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK 0x00040000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK 0x00080000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK 0x00100000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK 0x00200000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK 0x00400000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK 0x00800000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK 0x01000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK 0x02000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK 0x04000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK 0x08000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK 0x10000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK 0x20000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK 0x40000000L
+#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK 0x80000000L
+//RLC_RLCS_EDC_INT_CNTL
+#define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT 0x0
+#define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK 0x00000001L
+//RLC_RLCS_DEC_END
+
+
+// addressBlock: gc_pwrdec
+//CGTS_SA0_QUAD0_SM_CTRL_REG
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__MASK_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT 0x11
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT 0x17
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT 0x18
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT 0x19
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT 0x1a
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__MASK_OVERRIDE_MASK 0x00008000L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN_MASK 0x00800000L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK 0x01000000L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN_MASK 0x02000000L
+#define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK 0xFC000000L
+//CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG
+#define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT 0x0
+#define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa
+#define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK 0x000003FFL
+#define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK 0x0007FC00L
+//CGTS_SA0_QUAD1_SM_CTRL_REG
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__MASK_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE__SHIFT 0x11
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT 0x17
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT 0x18
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT 0x19
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT 0x1a
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__MASK_OVERRIDE_MASK 0x00008000L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN_MASK 0x00800000L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK 0x01000000L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN_MASK 0x02000000L
+#define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK 0xFC000000L
+//CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG
+#define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT 0x0
+#define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa
+#define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK 0x000003FFL
+#define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK 0x0007FC00L
+//CGTS_SA1_QUAD0_SM_CTRL_REG
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__MASK_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT 0x11
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT 0x17
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT 0x18
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT 0x19
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT 0x1a
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__MASK_OVERRIDE_MASK 0x00008000L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN_MASK 0x00800000L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK 0x01000000L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN_MASK 0x02000000L
+#define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK 0xFC000000L
+//CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG
+#define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT 0x0
+#define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa
+#define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK 0x000003FFL
+#define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK 0x0007FC00L
+//CGTS_SA1_QUAD1_SM_CTRL_REG
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__MASK_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE__SHIFT 0x11
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT 0x17
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT 0x18
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT 0x19
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT 0x1a
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__MASK_OVERRIDE_MASK 0x00008000L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN_MASK 0x00800000L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK 0x01000000L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN_MASK 0x02000000L
+#define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK 0xFC000000L
+//CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG
+#define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT 0x0
+#define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa
+#define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK 0x000003FFL
+#define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK 0x0007FC00L
+//CGTS_RD_CTRL_REG
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x4
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000000FL
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x000000F0L
+//CGTS_RD_REG
+#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
+#define CGTS_RD_REG__READ_DATA_MASK 0xFFFFFFFFL
+//CGTS_TCC_DISABLE
+#define CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8
+#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L
+#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
+//CGTS_USER_TCC_DISABLE
+#define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
+//CGTS_STATUS_REG
+#define CGTS_STATUS_REG__SA0_QUAD0_MGCG_ENABLED__SHIFT 0x0
+#define CGTS_STATUS_REG__SA0_QUAD0_CG_STATUS__SHIFT 0x1
+#define CGTS_STATUS_REG__SA0_QUAD1_MGCG_ENABLED__SHIFT 0x4
+#define CGTS_STATUS_REG__SA0_QUAD1_CG_STATUS__SHIFT 0x5
+#define CGTS_STATUS_REG__SA1_QUAD0_MGCG_ENABLED__SHIFT 0x8
+#define CGTS_STATUS_REG__SA1_QUAD0_CG_STATUS__SHIFT 0x9
+#define CGTS_STATUS_REG__SA1_QUAD1_MGCG_ENABLED__SHIFT 0xc
+#define CGTS_STATUS_REG__SA1_QUAD1_CG_STATUS__SHIFT 0xd
+#define CGTS_STATUS_REG__SA0_QUAD0_MGCG_ENABLED_MASK 0x00000001L
+#define CGTS_STATUS_REG__SA0_QUAD0_CG_STATUS_MASK 0x00000006L
+#define CGTS_STATUS_REG__SA0_QUAD1_MGCG_ENABLED_MASK 0x00000010L
+#define CGTS_STATUS_REG__SA0_QUAD1_CG_STATUS_MASK 0x00000060L
+#define CGTS_STATUS_REG__SA1_QUAD0_MGCG_ENABLED_MASK 0x00000100L
+#define CGTS_STATUS_REG__SA1_QUAD0_CG_STATUS_MASK 0x00000600L
+#define CGTS_STATUS_REG__SA1_QUAD1_MGCG_ENABLED_MASK 0x00001000L
+#define CGTS_STATUS_REG__SA1_QUAD1_CG_STATUS_MASK 0x00006000L
+//CGTT_SPI_CGTSSM_CLK_CTRL
+#define CGTT_SPI_CGTSSM_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_CGTSSM_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPI_CGTSSM_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPI_CGTSSM_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPI_CGTSSM_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
+#define CGTT_SPI_CGTSSM_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
+#define CGTT_SPI_CGTSSM_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
+#define CGTT_SPI_CGTSSM_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
+//CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP00_CU0_TATD_CTRL_REG
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP00_CU0_TCP_CTRL_REG
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP00_CU1_TATD_CTRL_REG
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP00_CU1_TCP_CTRL_REG
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP01_CU0_TATD_CTRL_REG
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP01_CU0_TCP_CTRL_REG
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP01_CU1_TATD_CTRL_REG
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP01_CU1_TCP_CTRL_REG
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP02_CU0_TATD_CTRL_REG
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP02_CU0_TCP_CTRL_REG
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP02_CU1_TATD_CTRL_REG
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP02_CU1_TCP_CTRL_REG
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP10_CU0_TATD_CTRL_REG
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP10_CU0_TCP_CTRL_REG
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP10_CU1_TATD_CTRL_REG
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP10_CU1_TCP_CTRL_REG
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP11_CU0_TATD_CTRL_REG
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP11_CU0_TCP_CTRL_REG
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP11_CU1_TATD_CTRL_REG
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP11_CU1_TCP_CTRL_REG
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP00_CU0_TATD_CTRL_REG
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP00_CU0_TCP_CTRL_REG
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP00_CU1_TATD_CTRL_REG
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP00_CU1_TCP_CTRL_REG
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP01_CU0_TATD_CTRL_REG
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP01_CU0_TCP_CTRL_REG
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP01_CU1_TATD_CTRL_REG
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP01_CU1_TCP_CTRL_REG
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP02_CU0_TATD_CTRL_REG
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP02_CU0_TCP_CTRL_REG
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP02_CU1_TATD_CTRL_REG
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP02_CU1_TCP_CTRL_REG
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP10_CU0_TATD_CTRL_REG
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP10_CU0_TCP_CTRL_REG
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP10_CU1_TATD_CTRL_REG
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP10_CU1_TCP_CTRL_REG
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP11_CU0_TATD_CTRL_REG
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP11_CU0_TCP_CTRL_REG
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP11_CU1_TATD_CTRL_REG
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP11_CU1_TCP_CTRL_REG
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA0_WGP12_CU0_TATD_CTRL_REG
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP12_CU0_TCP_CTRL_REG
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP12_CU1_TATD_CTRL_REG
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA0_WGP12_CU1_TCP_CTRL_REG
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L
+#define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L
+//CGTS_SA1_WGP12_CU0_TATD_CTRL_REG
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP12_CU0_TCP_CTRL_REG
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP12_CU1_TATD_CTRL_REG
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD__SHIFT 0xa
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTS_SA1_WGP12_CU1_TCP_CTRL_REG
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L
+#define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L
+//CGTT_SPI_PS_CLK_CTRL
+#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16
+#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18
+#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19
+#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a
+#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
+#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
+#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
+#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_SPIS_CLK_CTRL
+#define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16
+#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18
+#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19
+#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a
+#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
+#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
+#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L
+#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L
+#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L
+#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
+#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
+#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
+#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
+#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_SPI_CLK_CTRL
+#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16
+#define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18
+#define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19
+#define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
+#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
+#define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L
+#define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L
+#define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_PC_CLK_CTRL
+#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT 0x11
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19
+#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK 0x00020000L
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
+#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L
+#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_BCI_CLK_CTRL
+#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_VGT_CLK_CTRL
+#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
+#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
+#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
+#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
+#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_IA_CLK_CTRL
+#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_WD_CLK_CTRL
+#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
+#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
+#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
+#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
+#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_PA_CLK_CTRL
+#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
+//CGTT_SC_CLK_CTRL0
+#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16
+#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
+#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
+#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L
+#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L
+#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L
+#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L
+//CGTT_SC_CLK_CTRL1
+#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0__SHIFT 0x10
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16
+#define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE__SHIFT 0x17
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0__SHIFT 0x18
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0_MASK 0x00010000L
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L
+#define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE_MASK 0x00800000L
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0_MASK 0x01000000L
+#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L
+#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L
+#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L
+#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L
+#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L
+#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L
+#define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE_MASK 0x80000000L
+//CGTT_SC_CLK_CTRL2
+#define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL2__DBR_CLK_OVERRIDE__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SC_CLK_CTRL2__DBR_CLK_OVERRIDE_MASK 0x04000000L
+#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L
+#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L
+#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L
+#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L
+//CGTT_SQ_CLK_CTRL
+#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SQ_CLK_CTRL__WCLK2DCLK_OVERRIDE__SHIFT 0x1b
+#define CGTT_SQ_CLK_CTRL__WCLK_OVERRIDE__SHIFT 0x1c
+#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SQ_CLK_CTRL__WCLK2DCLK_OVERRIDE_MASK 0x08000000L
+#define CGTT_SQ_CLK_CTRL__WCLK_OVERRIDE_MASK 0x10000000L
+#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//CGTT_SQG_CLK_CTRL
+#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
+//SQ_ALU_CLK_CTRL
+#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0
+#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10
+#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL
+#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L
+//SQ_TEX_CLK_CTRL
+#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0
+#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10
+#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL
+#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L
+//SQ_LDS_CLK_CTRL
+#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0
+#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10
+#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL
+#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L
+//CGTT_SX_CLK_CTRL0
+#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL1
+#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL2
+#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL3
+#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_SX_CLK_CTRL4
+#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
+//TD_CGTT_CTRL
+#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
+#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//TA_CGTT_CTRL
+#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
+#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_TCPI_CLK_CTRL
+#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_TCI_CLK_CTRL
+#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_GDS_CLK_CTRL
+#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_GDS_CLK_CTRL__UNUSED__SHIFT 0xc
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_GDS_CLK_CTRL__UNUSED_MASK 0x0000F000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//DB_CGTT_CLK_CTRL_0
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
+#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L
+//CB_CGTT_SCLK_CTRL
+#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//GL2C_CGTT_SCLK_CTRL
+#define GL2C_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define GL2C_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//GL2A_CGTT_SCLK_CTRL
+#define GL2A_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define GL2A_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//GL2A_CGTT_SCLK_CTRL_1
+#define GL2A_CGTT_SCLK_CTRL_1__ON_DELAY__SHIFT 0x0
+#define GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS__SHIFT 0x4
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7__SHIFT 0x18
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6__SHIFT 0x19
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5__SHIFT 0x1a
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4__SHIFT 0x1b
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3__SHIFT 0x1c
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2__SHIFT 0x1d
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1__SHIFT 0x1e
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0__SHIFT 0x1f
+#define GL2A_CGTT_SCLK_CTRL_1__ON_DELAY_MASK 0x0000000FL
+#define GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7_MASK 0x01000000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6_MASK 0x02000000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5_MASK 0x04000000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4_MASK 0x08000000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3_MASK 0x10000000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2_MASK 0x20000000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1_MASK 0x40000000L
+#define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_CP_CLK_CTRL
+#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//CGTT_CPF_CLK_CTRL
+#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1a
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT 0x1b
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT 0x1c
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT 0x1d
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x04000000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK 0x08000000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK 0x10000000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK 0x20000000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//CGTT_CPC_CLK_CTRL
+#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//CGTT_RLC_CLK_CTRL
+#define CGTT_RLC_CLK_CTRL__RESERVED__SHIFT 0x0
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_RLC_CLK_CTRL__RESERVED_MASK 0x0000000FL
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//RLC_GFX_RM_CNTL
+#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0
+#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1
+#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L
+#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL
+//RMI_CGTT_SCLK_CTRL
+#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_TCPF_CLK_CTRL
+#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//GCR_CGTT_SCLK_CTRL
+#define GCR_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define GCR_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//UTCL1_CGTT_CLK_CTRL
+#define UTCL1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define UTCL1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//GCEA_CGTT_CLK_CTRL
+#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GCEA_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define GCEA_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GCEA_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define GCEA_CGTT_CLK_CTRL__SPARE1_MASK 0x0F800000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//SE_CAC_CGTT_CLK_CTRL
+#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//GC_CAC_CGTT_CLK_CTRL
+#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
+//GRBM_CGTT_CLK_CNTL
+#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
+#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL
+#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
+//CGTT_GL1C_CLK_CTRL
+#define CGTT_GL1C_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_GL1C_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_GL1C_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_GL1C_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_GL1C_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_GL1C_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_GL1C_CLK_CTRL__RESERVED_MASK 0x00007000L
+#define CGTT_GL1C_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_CHC_CLK_CTRL
+#define CGTT_CHC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CHC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CHC_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_CHC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_CHC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CHC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CHC_CLK_CTRL__RESERVED_MASK 0x00007000L
+#define CGTT_CHC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_CHCG_CLK_CTRL
+#define CGTT_CHCG_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CHCG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CHCG_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_CHCG_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_CHCG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CHCG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CHCG_CLK_CTRL__RESERVED_MASK 0x00007000L
+#define CGTT_CHCG_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_GL1A_CLK_CTRL
+#define CGTT_GL1A_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_GL1A_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_GL1A_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_GL1A_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_GL1A_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_GL1A_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_GL1A_CLK_CTRL__RESERVED_MASK 0x00007000L
+#define CGTT_GL1A_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//CGTT_CHA_CLK_CTRL
+#define CGTT_CHA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CHA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CHA_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_CHA_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_CHA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define CGTT_CHA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_CHA_CLK_CTRL__RESERVED_MASK 0x00007000L
+#define CGTT_CHA_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
+//GUS_CGTT_CLK_CTRL
+#define GUS_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GUS_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM__SHIFT 0x13
+#define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define GUS_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM__SHIFT 0x1b
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define GUS_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GUS_CGTT_CLK_CTRL__SPARE0_MASK 0x0007F000L
+#define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM_MASK 0x00080000L
+#define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define GUS_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM_MASK 0x08000000L
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//CGTT_PH_CLK_CTRL0
+#define CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_PH_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
+#define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK 0x40000000L
+#define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L
+//CGTT_PH_CLK_CTRL1
+#define CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_PH_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
+//CGTT_PH_CLK_CTRL2
+#define CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT 0x0
+#define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_PH_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
+//CGTT_PH_CLK_CTRL3
+#define CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT 0x0
+#define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_PH_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL
+#define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
+#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
+
+
+// addressBlock: gc_hypdec
+//CP_PFP_UCODE_ADDR
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL
+//CP_PFP_UCODE_DATA
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_ME_RAM_RADDR
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000FFFFFL
+//CP_ME_RAM_WADDR
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x001FFFFFL
+//CP_ME_RAM_DATA
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL
+//CP_CE_UCODE_ADDR
+#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL
+//CP_CE_UCODE_DATA
+#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_MEC_ME1_UCODE_ADDR
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL
+//CP_MEC_ME1_UCODE_DATA
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_MEC_ME2_UCODE_ADDR
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL
+//CP_MEC_ME2_UCODE_DATA
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//CP_PFP_IC_BASE_LO
+#define CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
+//CP_PFP_IC_BASE_HI
+#define CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
+//CP_PFP_IC_BASE_CNTL
+#define CP_PFP_IC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4
+#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17
+#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_PFP_IC_BASE_CNTL__VMID_MASK 0x0000000FL
+#define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L
+#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L
+#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L
+//CP_PFP_IC_OP_CNTL
+#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
+#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1
+#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
+#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
+#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
+#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L
+#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
+#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
+//CP_ME_IC_BASE_LO
+#define CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_ME_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
+//CP_ME_IC_BASE_HI
+#define CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_ME_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
+//CP_ME_IC_BASE_CNTL
+#define CP_ME_IC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4
+#define CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17
+#define CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_ME_IC_BASE_CNTL__VMID_MASK 0x0000000FL
+#define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L
+#define CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L
+#define CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L
+//CP_ME_IC_OP_CNTL
+#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
+#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1
+#define CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
+#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
+#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
+#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L
+#define CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
+#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
+//CP_CE_IC_BASE_LO
+#define CP_CE_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_CE_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
+//CP_CE_IC_BASE_HI
+#define CP_CE_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_CE_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
+//CP_CE_IC_BASE_CNTL
+#define CP_CE_IC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4
+#define CP_CE_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17
+#define CP_CE_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_CE_IC_BASE_CNTL__VMID_MASK 0x0000000FL
+#define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L
+#define CP_CE_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L
+#define CP_CE_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L
+//CP_CE_IC_OP_CNTL
+#define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
+#define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1
+#define CP_CE_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
+#define CP_CE_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
+#define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
+#define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L
+#define CP_CE_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
+#define CP_CE_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
+//CP_CPC_IC_BASE_LO
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
+//CP_CPC_IC_BASE_HI
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
+//CP_CPC_IC_BASE_CNTL
+#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4
+#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL
+#define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L
+#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L
+//CP_CPC_IC_OP_CNTL
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
+//CP_MES_IC_BASE_LO
+#define CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
+//CP_MES_MIBASE_LO
+#define CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
+//CP_MES_IC_BASE_HI
+#define CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
+//CP_MES_MIBASE_HI
+#define CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
+//CP_MES_IC_BASE_CNTL
+#define CP_MES_IC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17
+#define CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL
+#define CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L
+#define CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L
+//CP_MES_IC_OP_CNTL
+#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
+#define CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
+#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
+#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
+#define CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
+#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
+//CP_MES_DC_BASE_LO
+#define CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10
+#define CP_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L
+//CP_MES_MDBASE_LO
+#define CP_MES_MDBASE_LO__BASE_LO__SHIFT 0x10
+#define CP_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L
+//CP_MES_DC_BASE_HI
+#define CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0
+#define CP_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL
+//CP_MES_MDBASE_HI
+#define CP_MES_MDBASE_HI__BASE_HI__SHIFT 0x0
+#define CP_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL
+//CP_MES_LOCAL_BASE0_LO
+#define CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10
+#define CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L
+//CP_MES_LOCAL_BASE0_HI
+#define CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0
+#define CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL
+//CP_MES_LOCAL_MASK0_LO
+#define CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10
+#define CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L
+//CP_MES_LOCAL_MASK0_HI
+#define CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0
+#define CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL
+//CP_MES_LOCAL_APERTURE
+#define CP_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0
+#define CP_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000003L
+//CP_MES_MIBOUND_LO
+#define CP_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0
+#define CP_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL
+//CP_MES_MIBOUND_HI
+#define CP_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0
+#define CP_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL
+//CP_MES_MDBOUND_LO
+#define CP_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0
+#define CP_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL
+//CP_MES_MDBOUND_HI
+#define CP_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0
+#define CP_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL
+//GFX_PIPE_PRIORITY
+#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0
+#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x00000001L
+//GRBM_GFX_INDEX_SR_SELECT
+#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L
+//GRBM_GFX_INDEX_SR_DATA
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT 0x8
+#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10
+#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT 0x1d
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL
+#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK 0x0000FF00L
+#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L
+#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK 0x20000000L
+#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
+#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L
+//GRBM_GFX_CNTL_SR_SELECT
+#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0
+#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L
+//GRBM_GFX_CNTL_SR_DATA
+#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0
+#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2
+#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4
+#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8
+#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L
+#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL
+#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L
+#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L
+//GRBM_CAM_INDEX
+#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL
+//GRBM_HYP_CAM_INDEX
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL
+//GRBM_CAM_DATA
+#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
+#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
+//GRBM_HYP_CAM_DATA
+#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
+//GRBM_CAM_DATA_UPPER
+#define GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0
+#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L
+#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L
+//GRBM_HYP_CAM_DATA_UPPER
+#define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0
+#define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L
+#define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L
+//GC_IH_COOKIE_0_PTR
+#define GC_IH_COOKIE_0_PTR__ADDR__SHIFT 0x0
+#define GC_IH_COOKIE_0_PTR__ADDR_MASK 0x000FFFFFL
+//RLC_GPU_IOV_VF_ENABLE
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L
+//RLC_GPU_IOV_CFG_REG6
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
+#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L
+#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L
+//RLC_GPU_IOV_CFG_REG8
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_RLCV_TIMER_INT_0
+#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0
+#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
+//RLC_RLCV_TIMER_CTRL
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
+#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2
+#define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4
+#define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5
+#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x6
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
+#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L
+#define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L
+#define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L
+#define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L
+#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L
+//RLC_RLCV_TIMER_STAT
+#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
+#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
+#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2
+#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8
+#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9
+#define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa
+#define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb
+#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
+#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
+#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL
+#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L
+#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L
+#define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L
+#define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L
+//RLC_GPU_IOV_VF_DOORBELL_STATUS
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x7FFFFFFFL
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L
+//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x7FFFFFFFL
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L
+//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x7FFFFFFFL
+#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L
+//RLC_GPU_IOV_VF_MASK
+#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0
+#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x7FFFFFFFL
+//RLC_HYP_SEMAPHORE_0
+#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
+//RLC_HYP_SEMAPHORE_1
+#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
+//RLC_BUSY_CLK_CNTL
+#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT 0x0
+#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK 0x0000003FL
+//RLC_CLK_CNTL
+#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0
+#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x2
+#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT 0x4
+#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT 0x5
+#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT 0x6
+#define RLC_CLK_CNTL__RESERVED_7__SHIFT 0x7
+#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8
+#define RLC_CLK_CNTL__RESERVED_9__SHIFT 0x9
+#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0xa
+#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc
+#define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL__SHIFT 0xd
+#define RLC_CLK_CNTL__RESERVED_15__SHIFT 0xf
+#define RLC_CLK_CNTL__RESERVED__SHIFT 0x12
+#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000003L
+#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x0000000CL
+#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK 0x00000010L
+#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK 0x00000020L
+#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK 0x00000040L
+#define RLC_CLK_CNTL__RESERVED_7_MASK 0x00000080L
+#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L
+#define RLC_CLK_CNTL__RESERVED_9_MASK 0x00000200L
+#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK 0x00000C00L
+#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L
+#define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL_MASK 0x00002000L
+#define RLC_CLK_CNTL__RESERVED_15_MASK 0x00008000L
+#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFC0000L
+//RLC_PACE_TIMER_STAT
+#define RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
+#define RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
+#define RLC_PACE_TIMER_STAT__RESERVED__SHIFT 0x2
+#define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8
+#define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9
+#define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa
+#define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb
+#define RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
+#define RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
+#define RLC_PACE_TIMER_STAT__RESERVED_MASK 0x000000FCL
+#define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L
+#define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L
+#define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L
+#define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L
+//RLC_GPU_IOV_SCH_BLOCK
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8
+#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L
+#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L
+#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L
+//RLC_GPU_IOV_CFG_REG1
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
+#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L
+//RLC_GPU_IOV_CFG_REG2
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL
+#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L
+//RLC_GPU_IOV_VM_BUSY_STATUS
+#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCH_0
+#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_ACTIVE_FCN_ID
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000001FL
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
+//RLC_GPU_IOV_SCH_3
+#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCH_1
+#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCH_2
+#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL
+//RLC_PACE_INT_FORCE
+#define RLC_PACE_INT_FORCE__FORCE__SHIFT 0x0
+#define RLC_PACE_INT_FORCE__FORCE_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_INT_STAT
+#define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL
+//RLC_RLCV_TIMER_INT_1
+#define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0
+#define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
+//RLC_IH_COOKIE
+#define RLC_IH_COOKIE__DATA__SHIFT 0x0
+#define RLC_IH_COOKIE__DATA_MASK 0xFFFFFFFFL
+//RLC_IH_COOKIE_CNTL
+#define RLC_IH_COOKIE_CNTL__CREDIT__SHIFT 0x0
+#define RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT 0x2
+#define RLC_IH_COOKIE_CNTL__CREDIT_MASK 0x00000003L
+#define RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK 0x00000004L
+//RLC_HYP_RLCG_UCODE_CHKSUM
+#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0
+#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL
+//RLC_HYP_RLCP_UCODE_CHKSUM
+#define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0
+#define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL
+//RLC_HYP_RLCV_UCODE_CHKSUM
+#define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0
+#define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_F32_CNTL
+#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L
+//RLC_GPU_IOV_F32_RESET
+#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
+#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L
+//RLC_GPU_IOV_SDMA0_STATUS
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_7_1__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_11_9__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_31_13__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_7_1_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_11_9_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_31_13_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SDMA1_STATUS
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_7_1__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_11_9__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_31_13__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_7_1_MASK 0x000000FEL
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_11_9_MASK 0x00000E00L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_31_13_MASK 0xFFFFE000L
+//RLC_GPU_IOV_SMU_RESPONSE
+#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
+#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_VIRT_RESET_REQ
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L
+//RLC_GPU_IOV_RLC_RESPONSE
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_INT_DISABLE
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_INT_FORCE
+#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
+#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA0_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SDMA1_BUSY_STATUS
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
+//RLC_HYP_SEMAPHORE_2
+#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
+//RLC_HYP_SEMAPHORE_3
+#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
+#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5
+#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
+#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
+//RLC_HYP_RESET_VECTOR
+#define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT 0x0
+#define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT__SHIFT 0x1
+#define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT__SHIFT 0x2
+#define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT__SHIFT 0x3
+#define RLC_HYP_RESET_VECTOR__RESERVED_4__SHIFT 0x4
+#define RLC_HYP_RESET_VECTOR__RESERVED_5__SHIFT 0x5
+#define RLC_HYP_RESET_VECTOR__RESERVED_6__SHIFT 0x6
+#define RLC_HYP_RESET_VECTOR__RESERVED_7__SHIFT 0x7
+#define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK 0x00000001L
+#define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK 0x00000002L
+#define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT_MASK 0x00000004L
+#define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT_MASK 0x00000008L
+#define RLC_HYP_RESET_VECTOR__RESERVED_4_MASK 0x00000010L
+#define RLC_HYP_RESET_VECTOR__RESERVED_5_MASK 0x00000020L
+#define RLC_HYP_RESET_VECTOR__RESERVED_6_MASK 0x00000040L
+#define RLC_HYP_RESET_VECTOR__RESERVED_7_MASK 0x00000080L
+//RLC_HYP_BOOTLOAD_SIZE
+#define RLC_HYP_BOOTLOAD_SIZE__SIZE__SHIFT 0x0
+#define RLC_HYP_BOOTLOAD_SIZE__SIZE_MASK 0x03FFFFFFL
+//RLC_HYP_BOOTLOAD_ADDR_LO
+#define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT 0x0
+#define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL
+//RLC_HYP_BOOTLOAD_ADDR_HI
+#define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL
+//RLC_GPM_IRAM_ADDR
+#define RLC_GPM_IRAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPM_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL
+//RLC_GPM_IRAM_DATA
+#define RLC_GPM_IRAM_DATA__DATA__SHIFT 0x0
+#define RLC_GPM_IRAM_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_UCODE_ADDR
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
+#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L
+//RLC_GPM_UCODE_DATA
+#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//RLC_PACE_UCODE_ADDR
+#define RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_PACE_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
+#define RLC_PACE_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_PACE_UCODE_DATA
+#define RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_PACE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_UCODE_ADDR
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_GPU_IOV_UCODE_DATA
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCRATCH_ADDR
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0xFFFFFFFFL
+//RLC_GPU_IOV_SCRATCH_DATA
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCV_IRAM_ADDR
+#define RLC_RLCV_IRAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_RLCV_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL
+//RLC_RLCV_IRAM_DATA
+#define RLC_RLCV_IRAM_DATA__DATA__SHIFT 0x0
+#define RLC_RLCV_IRAM_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_RLCP_IRAM_ADDR
+#define RLC_RLCP_IRAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_RLCP_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL
+//RLC_RLCP_IRAM_DATA
+#define RLC_RLCP_IRAM_DATA__DATA__SHIFT 0x0
+#define RLC_RLCP_IRAM_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_DRAM_ADDR
+#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc
+#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL
+#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_SRM_DRAM_DATA
+#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_SRM_ARAM_ADDR
+#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc
+#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL
+#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L
+//RLC_SRM_ARAM_DATA
+#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_GPM_SCRATCH_ADDR
+#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0xFFFFFFFFL
+//RLC_GPM_SCRATCH_DATA
+#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
+//RLC_GTS_OFFSET_LSB
+#define RLC_GTS_OFFSET_LSB__DATA__SHIFT 0x0
+#define RLC_GTS_OFFSET_LSB__DATA_MASK 0xFFFFFFFFL
+//RLC_GTS_OFFSET_MSB
+#define RLC_GTS_OFFSET_MSB__DATA__SHIFT 0x0
+#define RLC_GTS_OFFSET_MSB__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: gc_sdma0_sdma0hypdec
+//SDMA0_UCODE_ADDR
+#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00003FFFL
+//SDMA0_UCODE_DATA
+#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA0_VM_CTX_LO
+#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA0_VM_CTX_HI
+#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA0_ACTIVE_FCN_ID
+#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5
+#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
+#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L
+#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//SDMA0_VM_CTX_CNTL
+#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L
+#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L
+//SDMA0_VIRT_RESET_REQ
+#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
+#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//SDMA0_VF_ENABLE
+#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+//SDMA0_CONTEXT_REG_TYPE0
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L
+//SDMA0_CONTEXT_REG_TYPE1
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x18
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF000000L
+//SDMA0_CONTEXT_REG_TYPE2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
+//SDMA0_CONTEXT_REG_TYPE3
+#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
+//SDMA0_VM_CNTL
+#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL
+
+
+// addressBlock: gc_sdma1_sdma1hypdec
+//SDMA1_UCODE_ADDR
+#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00003FFFL
+//SDMA1_UCODE_DATA
+#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
+//SDMA1_VM_CTX_LO
+#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
+//SDMA1_VM_CTX_HI
+#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
+//SDMA1_ACTIVE_FCN_ID
+#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5
+#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
+#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L
+#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//SDMA1_VM_CTX_CNTL
+#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L
+#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L
+//SDMA1_VIRT_RESET_REQ
+#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
+#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//SDMA1_VF_ENABLE
+#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
+//SDMA1_CONTEXT_REG_TYPE0
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L
+//SDMA1_CONTEXT_REG_TYPE1
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x18
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF000000L
+//SDMA1_CONTEXT_REG_TYPE2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
+//SDMA1_CONTEXT_REG_TYPE3
+#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
+//SDMA1_VM_CNTL
+#define SDMA1_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL
+
+
+// addressBlock: gc_gcvmsharedhvdec
+//GCMC_VM_FB_SIZE_OFFSET_VF0
+#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF1
+#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF2
+#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF3
+#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF4
+#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF5
+#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF6
+#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF7
+#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF8
+#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF9
+#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF10
+#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF11
+#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF12
+#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF13
+#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF14
+#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF15
+#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF16
+#define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF17
+#define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF18
+#define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF19
+#define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF20
+#define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF21
+#define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF22
+#define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF23
+#define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF24
+#define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF25
+#define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF26
+#define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF27
+#define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF28
+#define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF29
+#define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF30
+#define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCMC_VM_FB_SIZE_OFFSET_VF31
+#define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT 0x0
+#define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT 0x10
+#define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK 0x0000FFFFL
+#define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK 0xFFFF0000L
+//GCVM_IOMMU_MMIO_CNTRL_1
+#define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8
+#define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L
+//GCMC_VM_MARC_BASE_LO_0
+#define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
+#define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
+//GCMC_VM_MARC_BASE_LO_1
+#define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
+#define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
+//GCMC_VM_MARC_BASE_LO_2
+#define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
+#define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
+//GCMC_VM_MARC_BASE_LO_3
+#define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
+#define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
+//GCMC_VM_MARC_BASE_HI_0
+#define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
+#define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
+//GCMC_VM_MARC_BASE_HI_1
+#define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
+#define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
+//GCMC_VM_MARC_BASE_HI_2
+#define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
+#define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
+//GCMC_VM_MARC_BASE_HI_3
+#define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
+#define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
+//GCMC_VM_MARC_RELOC_LO_0
+#define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
+#define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
+#define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
+#define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
+#define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
+#define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
+//GCMC_VM_MARC_RELOC_LO_1
+#define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
+#define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
+#define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
+#define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
+#define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
+#define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
+//GCMC_VM_MARC_RELOC_LO_2
+#define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
+#define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
+#define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
+#define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
+#define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
+#define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
+//GCMC_VM_MARC_RELOC_LO_3
+#define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
+#define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
+#define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
+#define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
+#define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
+#define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
+//GCMC_VM_MARC_RELOC_HI_0
+#define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
+#define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
+//GCMC_VM_MARC_RELOC_HI_1
+#define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
+#define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
+//GCMC_VM_MARC_RELOC_HI_2
+#define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
+#define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
+//GCMC_VM_MARC_RELOC_HI_3
+#define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
+#define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
+//GCMC_VM_MARC_LEN_LO_0
+#define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
+#define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
+//GCMC_VM_MARC_LEN_LO_1
+#define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
+#define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
+//GCMC_VM_MARC_LEN_LO_2
+#define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
+#define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
+//GCMC_VM_MARC_LEN_LO_3
+#define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
+#define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
+//GCMC_VM_MARC_LEN_HI_0
+#define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
+#define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
+//GCMC_VM_MARC_LEN_HI_1
+#define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
+#define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
+//GCMC_VM_MARC_LEN_HI_2
+#define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
+#define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
+//GCMC_VM_MARC_LEN_HI_3
+#define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
+#define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
+//GCVM_IOMMU_CONTROL_REGISTER
+#define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
+#define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
+//GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
+#define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
+#define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
+//GCVM_PCIE_ATS_CNTL
+#define GCVM_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define GCVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define GCVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_0
+#define GCVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_1
+#define GCVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_2
+#define GCVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_3
+#define GCVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_4
+#define GCVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_5
+#define GCVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_6
+#define GCVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_7
+#define GCVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_8
+#define GCVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_9
+#define GCVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_10
+#define GCVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_11
+#define GCVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_12
+#define GCVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_13
+#define GCVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_14
+#define GCVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_15
+#define GCVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_16
+#define GCVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_17
+#define GCVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_18
+#define GCVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_19
+#define GCVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_20
+#define GCVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_21
+#define GCVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_22
+#define GCVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_23
+#define GCVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_24
+#define GCVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_25
+#define GCVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_26
+#define GCVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_27
+#define GCVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_28
+#define GCVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_29
+#define GCVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_30
+#define GCVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L
+//GCVM_PCIE_ATS_CNTL_VF_31
+#define GCVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT 0x1f
+#define GCVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK 0x80000000L
+//GCUTCL2_CGTT_CLK_CTRL
+#define GCUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define GCUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
+#define GCUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define GCUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define GCUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define GCUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
+#define GCUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define GCUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//GCMC_SHARED_ACTIVE_FCN_ID
+#define GCMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define GCMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define GCMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
+#define GCMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+
+
+// addressBlock: gccacind
+//PCC_STALL_PATTERN_CTRL
+#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT 0x0
+#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT 0xa
+#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT 0xf
+#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14
+#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT 0x18
+#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT 0x19
+#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT 0x1a
+#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK 0x000003FFL
+#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK 0x00007C00L
+#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK 0x000F8000L
+#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L
+#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK 0x01000000L
+#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK 0x02000000L
+#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK 0x04000000L
+//PWRBRK_STALL_PATTERN_CTRL
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L
+#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L
+//PCC_STALL_PATTERN_1_2
+#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0
+#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10
+#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//PCC_STALL_PATTERN_3_4
+#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0
+#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10
+#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//PCC_STALL_PATTERN_5_6
+#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0
+#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10
+#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//PCC_STALL_PATTERN_7
+#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0
+#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL
+//PWRBRK_STALL_PATTERN_1_2
+#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10
+#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL
+#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L
+//PWRBRK_STALL_PATTERN_3_4
+#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10
+#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL
+#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L
+//PWRBRK_STALL_PATTERN_5_6
+#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10
+#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL
+#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L
+//PWRBRK_STALL_PATTERN_7
+#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0
+#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL
+//GC_CAC_ID
+#define GC_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0
+#define GC_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6
+#define GC_CAC_ID__UNUSED_0__SHIFT 0xe
+#define GC_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL
+#define GC_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L
+#define GC_CAC_ID__UNUSED_0_MASK 0xFFFFC000L
+//GC_CAC_CNTL
+#define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0
+#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
+#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x11
+#define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L
+#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
+#define GC_CAC_CNTL__UNUSED_0_MASK 0xFFFE0000L
+//GC_CAC_OVR_SEL
+#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
+#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
+//GC_CAC_OVR_VAL
+#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
+#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
+//GC_CAC_WEIGHT_BCI_0
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CB_0
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CB_1
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CBR_0
+#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CBR_1
+#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CP_0
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CP_1
+#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_DB_0
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_DB_1
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_DBR_0
+#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_DBR_1
+#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_GDS_0
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_GDS_1
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_LDS_0
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_LDS_1
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_PA_0
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_PC_0
+#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SC_0
+#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SPI_0
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SPI_1
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SPI_2
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_0
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_1
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SQ_2
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SX_0
+#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_SXRB_0
+#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_SXRB_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_SXRB_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TA_0
+#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCP_0
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCP_1
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TCP_2
+#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_0
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_1
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_2
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_3
+#define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_TD_4
+#define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT 0x0
+#define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT 0x10
+#define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_RMI_0
+#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_RMI_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_RMI_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_EA_0
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_EA_1
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_EA_2
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ATCL2_0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ATCL2_1
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ATCL2_2
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_1
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_2
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_3
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_ROUTER_4
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_VML2_0
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_VML2_1
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_VML2_2
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_WALKER_0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_WALKER_1
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL2_WALKER_2
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_CU_0
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_0__UNUSED_0__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_CU_0__UNUSED_0_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_UTCL1_0
+#define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_GE_0
+#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_PMM_0
+#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_GL2C_0
+#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_GL2C_1
+#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_GL2C_2
+#define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_GUS_0
+#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK 0x0000FFFFL
+#define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK 0xFFFF0000L
+//GC_CAC_WEIGHT_GUS_1
+#define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK 0x0000FFFFL
+//GC_CAC_WEIGHT_PH_0
+#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK 0x0000FFFFL
+//GC_CAC_ACC_BCI0
+#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_BCI1
+#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB0
+#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB1
+#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB2
+#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CB3
+#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CBR0
+#define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CBR1
+#define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CBR2
+#define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CBR3
+#define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CP0
+#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CP1
+#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CP2
+#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB0
+#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB1
+#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB2
+#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DB3
+#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DBR0
+#define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DBR1
+#define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DBR2
+#define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_DBR3
+#define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS0
+#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS1
+#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS2
+#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GDS3
+#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS0
+#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS1
+#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS2
+#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_LDS3
+#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PA0
+#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PA1
+#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PC0
+#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SC0
+#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI0
+#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI1
+#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI2
+#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI3
+#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI4
+#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SPI5
+#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ0_LOWER
+#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ0_UPPER
+#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ1_LOWER
+#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ1_UPPER
+#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ2_LOWER
+#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ2_UPPER
+#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ3_LOWER
+#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ3_UPPER
+#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ4_LOWER
+#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ4_UPPER
+#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ5_LOWER
+#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ5_UPPER
+#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ6_LOWER
+#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ6_UPPER
+#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ7_LOWER
+#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ7_UPPER
+#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SQ8_LOWER
+#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SQ8_UPPER
+#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
+#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8
+#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
+#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L
+//GC_CAC_ACC_SX0
+#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_SXRB0
+#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TA0
+#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP0
+#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP1
+#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP2
+#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP3
+#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TCP4
+#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD0
+#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD1
+#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD2
+#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD3
+#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD4
+#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD5
+#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD6
+#define GC_CAC_ACC_TD6__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD7
+#define GC_CAC_ACC_TD7__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD8
+#define GC_CAC_ACC_TD8__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_TD9
+#define GC_CAC_ACC_TD9__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_TD9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_RMI0
+#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA0
+#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA1
+#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA2
+#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA3
+#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA4
+#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_EA5
+#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL20
+#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL21
+#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL22
+#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL23
+#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ATCL24
+#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER0
+#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER1
+#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER2
+#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER3
+#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER4
+#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER5
+#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER6
+#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER7
+#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER8
+#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_ROUTER9
+#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML20
+#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML21
+#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML22
+#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML23
+#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_VML24
+#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER0
+#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER1
+#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER2
+#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER3
+#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL2_WALKER4
+#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CU0
+#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_UTCL10
+#define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_CH0
+#define GC_CAC_ACC_CH0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CH0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GE0
+#define GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PMM0
+#define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GL2C0
+#define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GL2C1
+#define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GL2C2
+#define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GL2C3
+#define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GL2C4
+#define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GUS0
+#define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GUS1
+#define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_GUS2
+#define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_ACC_PH0
+#define GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
+//GC_CAC_OVRD_BCI
+#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2
+#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L
+#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL
+//GC_CAC_OVRD_CB
+#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_CBR
+#define GC_CAC_OVRD_CBR__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CBR__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_CBR__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_CBR__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_CP
+#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3
+#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L
+#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L
+//GC_CAC_OVRD_DB
+#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_DBR
+#define GC_CAC_OVRD_DBR__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_DBR__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_DBR__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_DBR__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_GDS
+#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_LDS
+#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4
+#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL
+#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L
+//GC_CAC_OVRD_PA
+#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2
+#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L
+#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL
+//GC_CAC_OVRD_PC
+#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SC
+#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SPI
+#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6
+#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL
+#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L
+//GC_CAC_OVRD_CU
+#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SQ
+#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x6
+#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x0000003FL
+#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x00000FC0L
+//GC_CAC_OVRD_SX
+#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_SXRB
+#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_TA
+#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_TCP
+#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_OVRD_TD
+#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0xa
+#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x000003FFL
+#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x000FFC00L
+//GC_CAC_OVRD_RMI
+#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_EA
+#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6
+#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL
+#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L
+//GC_CAC_OVRD_UTCL2_ATCL2
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_OVRD_UTCL2_ROUTER
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL
+#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L
+//GC_CAC_OVRD_UTCL2_VML2
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_OVRD_UTCL2_WALKER
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_OVRD_UTCL1
+#define GC_CAC_OVRD_UTCL1__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_UTCL1__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_UTCL1__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_UTCL1__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_GE
+#define GC_CAC_OVRD_GE__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_GE__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_GE__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_GE__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_PMM
+#define GC_CAC_OVRD_PMM__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_PMM__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_PMM__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_PMM__OVRRD_VALUE_MASK 0x00000002L
+//GC_CAC_OVRD_GL2C
+#define GC_CAC_OVRD_GL2C__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_GL2C__OVRRD_VALUE__SHIFT 0x5
+#define GC_CAC_OVRD_GL2C__OVRRD_SELECT_MASK 0x0000001FL
+#define GC_CAC_OVRD_GL2C__OVRRD_VALUE_MASK 0x000003E0L
+//GC_CAC_OVRD_GUS
+#define GC_CAC_OVRD_GUS__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_GUS__OVRRD_VALUE__SHIFT 0x3
+#define GC_CAC_OVRD_GUS__OVRRD_SELECT_MASK 0x00000007L
+#define GC_CAC_OVRD_GUS__OVRRD_VALUE_MASK 0x00000038L
+//GC_CAC_OVRD_PH
+#define GC_CAC_OVRD_PH__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_PH__OVRRD_VALUE__SHIFT 0x1
+#define GC_CAC_OVRD_PH__OVRRD_SELECT_MASK 0x00000001L
+#define GC_CAC_OVRD_PH__OVRRD_VALUE_MASK 0x00000002L
+//RELEASE_TO_STALL_LUT_1_8
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L
+#define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L
+//RELEASE_TO_STALL_LUT_9_16
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L
+#define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L
+//RELEASE_TO_STALL_LUT_17_20
+#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0
+#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4
+#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8
+#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc
+#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L
+#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L
+#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L
+#define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L
+//STALL_TO_RELEASE_LUT_1_4
+#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0
+#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8
+#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10
+#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18
+#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL
+#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L
+#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L
+#define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L
+//STALL_TO_RELEASE_LUT_5_7
+#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0
+#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8
+#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10
+#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL
+#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L
+#define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L
+//STALL_TO_PWRBRK_LUT_1_4
+#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0
+#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8
+#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10
+#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18
+#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1_MASK 0x00000007L
+#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2_MASK 0x00000700L
+#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3_MASK 0x00070000L
+#define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4_MASK 0x07000000L
+//STALL_TO_PWRBRK_LUT_5_7
+#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0
+#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8
+#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10
+#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5_MASK 0x00000007L
+#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6_MASK 0x00000700L
+#define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7_MASK 0x00070000L
+//PWRBRK_STALL_TO_RELEASE_LUT_1_4
+#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0
+#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8
+#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10
+#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18
+#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL
+#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L
+#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L
+#define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L
+//PWRBRK_STALL_TO_RELEASE_LUT_5_7
+#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0
+#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8
+#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10
+#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL
+#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L
+#define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L
+//PWRBRK_RELEASE_TO_STALL_LUT_1_8
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L
+#define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L
+//PWRBRK_RELEASE_TO_STALL_LUT_9_16
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L
+#define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L
+//PWRBRK_RELEASE_TO_STALL_LUT_17_20
+#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0
+#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4
+#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8
+#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc
+#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L
+#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L
+#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L
+#define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L
+//FIXED_PATTERN_PERF_COUNTER_1
+#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_2
+#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_3
+#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_4
+#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_5
+#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_6
+#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_7
+#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_8
+#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_9
+#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK 0x0001FFFFL
+//FIXED_PATTERN_PERF_COUNTER_10
+#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT 0x0
+#define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK 0x0001FFFFL
+//HW_LUT_UPDATE_STATUS
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT 0x0
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT 0x1
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT 0x2
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT 0x5
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT 0x6
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT 0x7
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT 0xa
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT 0xb
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT 0xc
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT 0x11
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT 0x12
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT 0x13
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT 0x16
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT 0x17
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT 0x18
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK 0x00000001L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK 0x00000002L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK 0x0000001CL
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK 0x00000020L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK 0x00000040L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK 0x00000380L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK 0x00000400L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK 0x00000800L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK 0x0001F000L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK 0x00020000L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK 0x00040000L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK 0x00380000L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK 0x00400000L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK 0x00800000L
+#define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK 0x1F000000L
+
+
+// addressBlock: secacind
+//SE_CAC_ID
+#define SE_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0
+#define SE_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6
+#define SE_CAC_ID__UNUSED_0__SHIFT 0xe
+#define SE_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL
+#define SE_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L
+#define SE_CAC_ID__UNUSED_0_MASK 0xFFFFC000L
+//SE_CAC_CNTL
+#define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0
+#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
+#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x11
+#define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L
+#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
+#define SE_CAC_CNTL__UNUSED_0_MASK 0xFFFE0000L
+//SE_CAC_OVR_SEL
+#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
+#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
+//SE_CAC_OVR_VAL
+#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
+#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: spmglbind
+//GLB_CPG_SAMPLEDELAY
+#define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_CPG_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_CPG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_CPC_SAMPLEDELAY
+#define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_CPC_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_CPC_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_CPF_SAMPLEDELAY
+#define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_CPF_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_CPF_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GDS_SAMPLEDELAY
+#define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GDS_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GDS_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GCR_SAMPLEDELAY
+#define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GCR_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GCR_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_PH_SAMPLEDELAY
+#define GLB_PH_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_PH_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_PH_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_PH_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GE_SAMPLEDELAY
+#define GLB_GE_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GE_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GE_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GE_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GUS_SAMPLEDELAY
+#define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GUS_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GUS_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_CHA_SAMPLEDELAY
+#define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_CHA_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_CHA_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_CHCG_SAMPLEDELAY
+#define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_CHCG_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_CHCG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_ATCL2_SAMPLEDELAY
+#define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_ATCL2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_ATCL2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_VML2_SAMPLEDELAY
+#define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_VML2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_VML2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_SDMA0_SAMPLEDELAY
+#define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_SDMA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_SDMA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_SDMA1_SAMPLEDELAY
+#define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_SDMA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_SDMA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2A0_SAMPLEDELAY
+#define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2A0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2A0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2A1_SAMPLEDELAY
+#define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2A1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2A1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2A2_SAMPLEDELAY
+#define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2A2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2A2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2A3_SAMPLEDELAY
+#define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2A3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2A3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C0_SAMPLEDELAY
+#define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C1_SAMPLEDELAY
+#define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C2_SAMPLEDELAY
+#define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C3_SAMPLEDELAY
+#define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C4_SAMPLEDELAY
+#define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C4_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C4_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C5_SAMPLEDELAY
+#define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C5_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C5_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C6_SAMPLEDELAY
+#define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C6_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C6_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C7_SAMPLEDELAY
+#define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C7_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C7_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C8_SAMPLEDELAY
+#define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C8_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C8_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C9_SAMPLEDELAY
+#define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C9_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C9_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C10_SAMPLEDELAY
+#define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C10_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C10_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C11_SAMPLEDELAY
+#define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C11_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C11_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C12_SAMPLEDELAY
+#define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C12_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C12_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C13_SAMPLEDELAY
+#define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C13_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C13_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C14_SAMPLEDELAY
+#define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C14_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C14_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_GL2C15_SAMPLEDELAY
+#define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_GL2C15_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_GL2C15_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA0_SAMPLEDELAY
+#define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA1_SAMPLEDELAY
+#define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA2_SAMPLEDELAY
+#define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA3_SAMPLEDELAY
+#define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA4_SAMPLEDELAY
+#define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA4_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA4_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA5_SAMPLEDELAY
+#define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA5_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA5_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA6_SAMPLEDELAY
+#define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA6_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA6_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA7_SAMPLEDELAY
+#define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA7_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA7_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA8_SAMPLEDELAY
+#define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA8_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA8_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA9_SAMPLEDELAY
+#define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA9_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA9_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA10_SAMPLEDELAY
+#define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA10_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA10_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA11_SAMPLEDELAY
+#define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA11_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA11_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA12_SAMPLEDELAY
+#define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA12_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA12_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA13_SAMPLEDELAY
+#define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA13_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA13_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA14_SAMPLEDELAY
+#define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA14_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA14_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_EA15_SAMPLEDELAY
+#define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_EA15_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_EA15_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_CHC0_SAMPLEDELAY
+#define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_CHC0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_CHC0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_CHC1_SAMPLEDELAY
+#define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_CHC1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_CHC1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_CHC2_SAMPLEDELAY
+#define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_CHC2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_CHC2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//GLB_CHC3_SAMPLEDELAY
+#define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define GLB_CHC3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define GLB_CHC3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+
+
+// addressBlock: spmind
+//SE_SPI_SAMPLEDELAY
+#define SE_SPI_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SPI_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SPI_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SPI_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SQG_SAMPLEDELAY
+#define SE_SQG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SQG_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SQG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SQG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_CBR_SAMPLEDELAY
+#define SE_CBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_CBR_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_CBR_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_CBR_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_DBR_SAMPLEDELAY
+#define SE_DBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_DBR_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_DBR_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_DBR_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0SX_SAMPLEDELAY
+#define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0SX_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0SX_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0PA_SAMPLEDELAY
+#define SE_SA0PA_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0PA_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0PA_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0PA_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0GL1A_SAMPLEDELAY
+#define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0GL1A_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0GL1A_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0GL1CG_SAMPLEDELAY
+#define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0GL1CG_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0GL1CG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0CB0_SAMPLEDELAY
+#define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0CB0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0CB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0CB1_SAMPLEDELAY
+#define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0CB1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0CB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0CB2_SAMPLEDELAY
+#define SE_SA0CB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0CB2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0CB2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0CB2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0CB3_SAMPLEDELAY
+#define SE_SA0CB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0CB3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0CB3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0CB3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0DB0_SAMPLEDELAY
+#define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0DB0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0DB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0DB1_SAMPLEDELAY
+#define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0DB1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0DB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0DB2_SAMPLEDELAY
+#define SE_SA0DB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0DB2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0DB2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0DB2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0DB3_SAMPLEDELAY
+#define SE_SA0DB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0DB3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0DB3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0DB3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0SC0_SAMPLEDELAY
+#define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0SC0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0SC0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0SC1_SAMPLEDELAY
+#define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0SC1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0SC1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0RMI0_SAMPLEDELAY
+#define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0RMI0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0RMI0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0RMI1_SAMPLEDELAY
+#define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0RMI1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0RMI1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0GL1C0_SAMPLEDELAY
+#define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0GL1C0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0GL1C0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0GL1C1_SAMPLEDELAY
+#define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0GL1C1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0GL1C1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0GL1C2_SAMPLEDELAY
+#define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0GL1C2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0GL1C2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0GL1C3_SAMPLEDELAY
+#define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0GL1C3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0GL1C3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP00TA0_SAMPLEDELAY
+#define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP00TA1_SAMPLEDELAY
+#define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP00TD0_SAMPLEDELAY
+#define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP00TD1_SAMPLEDELAY
+#define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP00TCP0_SAMPLEDELAY
+#define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP00TCP1_SAMPLEDELAY
+#define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP01TA0_SAMPLEDELAY
+#define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP01TA1_SAMPLEDELAY
+#define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP01TD0_SAMPLEDELAY
+#define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP01TD1_SAMPLEDELAY
+#define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP01TCP0_SAMPLEDELAY
+#define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP01TCP1_SAMPLEDELAY
+#define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP02TA0_SAMPLEDELAY
+#define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP02TA1_SAMPLEDELAY
+#define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP02TD0_SAMPLEDELAY
+#define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP02TD1_SAMPLEDELAY
+#define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP02TCP0_SAMPLEDELAY
+#define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP02TCP1_SAMPLEDELAY
+#define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP10TA0_SAMPLEDELAY
+#define SE_SA0WGP10TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP10TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP10TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP10TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP10TA1_SAMPLEDELAY
+#define SE_SA0WGP10TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP10TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP10TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP10TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP10TD0_SAMPLEDELAY
+#define SE_SA0WGP10TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP10TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP10TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP10TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP10TD1_SAMPLEDELAY
+#define SE_SA0WGP10TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP10TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP10TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP10TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP10TCP0_SAMPLEDELAY
+#define SE_SA0WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP10TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP10TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP10TCP1_SAMPLEDELAY
+#define SE_SA0WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP10TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP10TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP11TA0_SAMPLEDELAY
+#define SE_SA0WGP11TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP11TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP11TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP11TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP11TA1_SAMPLEDELAY
+#define SE_SA0WGP11TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP11TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP11TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP11TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP11TD0_SAMPLEDELAY
+#define SE_SA0WGP11TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP11TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP11TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP11TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP11TD1_SAMPLEDELAY
+#define SE_SA0WGP11TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP11TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP11TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP11TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP11TCP0_SAMPLEDELAY
+#define SE_SA0WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP11TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP11TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA0WGP11TCP1_SAMPLEDELAY
+#define SE_SA0WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA0WGP11TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA0WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA0WGP11TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1SX_SAMPLEDELAY
+#define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1SX_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1SX_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1PA_SAMPLEDELAY
+#define SE_SA1PA_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1PA_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1PA_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1PA_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1GL1A_SAMPLEDELAY
+#define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1GL1A_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1GL1A_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1GL1CG_SAMPLEDELAY
+#define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1GL1CG_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1GL1CG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1CB0_SAMPLEDELAY
+#define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1CB0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1CB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1CB1_SAMPLEDELAY
+#define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1CB1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1CB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1CB2_SAMPLEDELAY
+#define SE_SA1CB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1CB2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1CB2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1CB2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1CB3_SAMPLEDELAY
+#define SE_SA1CB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1CB3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1CB3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1CB3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1DB0_SAMPLEDELAY
+#define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1DB0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1DB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1DB1_SAMPLEDELAY
+#define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1DB1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1DB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1DB2_SAMPLEDELAY
+#define SE_SA1DB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1DB2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1DB2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1DB2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1DB3_SAMPLEDELAY
+#define SE_SA1DB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1DB3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1DB3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1DB3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1SC0_SAMPLEDELAY
+#define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1SC0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1SC0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1SC1_SAMPLEDELAY
+#define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1SC1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1SC1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1RMI0_SAMPLEDELAY
+#define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1RMI0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1RMI0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1RMI1_SAMPLEDELAY
+#define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1RMI1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1RMI1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1GL1C0_SAMPLEDELAY
+#define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1GL1C0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1GL1C0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1GL1C1_SAMPLEDELAY
+#define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1GL1C1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1GL1C1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1GL1C2_SAMPLEDELAY
+#define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1GL1C2_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1GL1C2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1GL1C3_SAMPLEDELAY
+#define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1GL1C3_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1GL1C3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP00TA0_SAMPLEDELAY
+#define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP00TA1_SAMPLEDELAY
+#define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP00TD0_SAMPLEDELAY
+#define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP00TD1_SAMPLEDELAY
+#define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP00TCP0_SAMPLEDELAY
+#define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP00TCP1_SAMPLEDELAY
+#define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP01TA0_SAMPLEDELAY
+#define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP01TA1_SAMPLEDELAY
+#define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP01TD0_SAMPLEDELAY
+#define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP01TD1_SAMPLEDELAY
+#define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP01TCP0_SAMPLEDELAY
+#define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP01TCP1_SAMPLEDELAY
+#define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP02TA0_SAMPLEDELAY
+#define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP02TA1_SAMPLEDELAY
+#define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP02TD0_SAMPLEDELAY
+#define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP02TD1_SAMPLEDELAY
+#define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP02TCP0_SAMPLEDELAY
+#define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP02TCP1_SAMPLEDELAY
+#define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP10TA0_SAMPLEDELAY
+#define SE_SA1WGP10TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP10TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP10TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP10TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP10TA1_SAMPLEDELAY
+#define SE_SA1WGP10TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP10TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP10TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP10TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP10TD0_SAMPLEDELAY
+#define SE_SA1WGP10TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP10TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP10TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP10TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP10TD1_SAMPLEDELAY
+#define SE_SA1WGP10TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP10TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP10TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP10TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP10TCP0_SAMPLEDELAY
+#define SE_SA1WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP10TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP10TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP10TCP1_SAMPLEDELAY
+#define SE_SA1WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP10TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP10TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP11TA0_SAMPLEDELAY
+#define SE_SA1WGP11TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP11TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP11TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP11TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP11TA1_SAMPLEDELAY
+#define SE_SA1WGP11TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP11TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP11TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP11TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP11TD0_SAMPLEDELAY
+#define SE_SA1WGP11TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP11TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP11TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP11TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP11TD1_SAMPLEDELAY
+#define SE_SA1WGP11TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP11TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP11TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP11TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP11TCP0_SAMPLEDELAY
+#define SE_SA1WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP11TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP11TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+//SE_SA1WGP11TCP1_SAMPLEDELAY
+#define SE_SA1WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0
+#define SE_SA1WGP11TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6
+#define SE_SA1WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL
+#define SE_SA1WGP11TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L
+
+
+// addressBlock: sqind
+//SQ_WAVE_MODE
+#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
+#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
+#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
+#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
+#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
+#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
+#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17
+#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1b
+#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
+#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
+#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL
+#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L
+#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L
+#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L
+#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L
+#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L
+#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L
+#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x08000000L
+#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L
+#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L
+//SQ_WAVE_STATUS
+#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
+#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
+#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
+#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
+#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
+#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
+#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
+#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
+#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
+#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
+#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
+#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
+#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
+#define SQ_WAVE_STATUS__TTRACE_SIMD_EN__SHIFT 0xf
+#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
+#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
+#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
+#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
+#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17
+#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
+#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L
+#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L
+#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L
+#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L
+#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L
+#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L
+#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L
+#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L
+#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L
+#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L
+#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L
+#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L
+#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L
+#define SQ_WAVE_STATUS__TTRACE_SIMD_EN_MASK 0x00008000L
+#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L
+#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L
+#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L
+#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L
+#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L
+#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L
+//SQ_WAVE_TRAPSTS
+#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
+#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
+#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb
+#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc
+#define SQ_WAVE_TRAPSTS__BUFFER_OOB__SHIFT 0xf
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
+#define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK__SHIFT 0x14
+#define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI__SHIFT 0x18
+#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c
+#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
+#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL
+#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L
+#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L
+#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L
+#define SQ_WAVE_TRAPSTS__BUFFER_OOB_MASK 0x00008000L
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x000F0000L
+#define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK_MASK 0x00F00000L
+#define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI_MASK 0x01000000L
+#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L
+#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L
+//SQ_WAVE_HW_ID_LEGACY
+#define SQ_WAVE_HW_ID_LEGACY__WAVE_ID__SHIFT 0x0
+#define SQ_WAVE_HW_ID_LEGACY__SIMD_ID__SHIFT 0x4
+#define SQ_WAVE_HW_ID_LEGACY__PIPE_ID__SHIFT 0x6
+#define SQ_WAVE_HW_ID_LEGACY__CU_ID__SHIFT 0x8
+#define SQ_WAVE_HW_ID_LEGACY__SH_ID__SHIFT 0xc
+#define SQ_WAVE_HW_ID_LEGACY__SE_ID__SHIFT 0xd
+#define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB__SHIFT 0xf
+#define SQ_WAVE_HW_ID_LEGACY__TG_ID__SHIFT 0x10
+#define SQ_WAVE_HW_ID_LEGACY__VM_ID__SHIFT 0x14
+#define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID__SHIFT 0x18
+#define SQ_WAVE_HW_ID_LEGACY__STATE_ID__SHIFT 0x1b
+#define SQ_WAVE_HW_ID_LEGACY__ME_ID__SHIFT 0x1e
+#define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MASK 0x0000000FL
+#define SQ_WAVE_HW_ID_LEGACY__SIMD_ID_MASK 0x00000030L
+#define SQ_WAVE_HW_ID_LEGACY__PIPE_ID_MASK 0x000000C0L
+#define SQ_WAVE_HW_ID_LEGACY__CU_ID_MASK 0x00000F00L
+#define SQ_WAVE_HW_ID_LEGACY__SH_ID_MASK 0x00001000L
+#define SQ_WAVE_HW_ID_LEGACY__SE_ID_MASK 0x00006000L
+#define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB_MASK 0x00008000L
+#define SQ_WAVE_HW_ID_LEGACY__TG_ID_MASK 0x000F0000L
+#define SQ_WAVE_HW_ID_LEGACY__VM_ID_MASK 0x00F00000L
+#define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID_MASK 0x07000000L
+#define SQ_WAVE_HW_ID_LEGACY__STATE_ID_MASK 0x38000000L
+#define SQ_WAVE_HW_ID_LEGACY__ME_ID_MASK 0xC0000000L
+//SQ_WAVE_GPR_ALLOC
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x000000FFL
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x0000FF00L
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x00FF0000L
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L
+//SQ_WAVE_LDS_ALLOC
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
+#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT 0x18
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000001FFL
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L
+#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK 0x0F000000L
+//SQ_WAVE_IB_STS
+#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
+#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
+#define SQ_WAVE_IB_STS__LGKM_CNT_BIT4__SHIFT 0x7
+#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
+#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
+#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
+#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
+#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16
+#define SQ_WAVE_IB_STS__LGKM_CNT_BIT5__SHIFT 0x18
+#define SQ_WAVE_IB_STS__REPLAY_W64H__SHIFT 0x19
+#define SQ_WAVE_IB_STS__VS_CNT__SHIFT 0x1a
+#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL
+#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L
+#define SQ_WAVE_IB_STS__LGKM_CNT_BIT4_MASK 0x00000080L
+#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L
+#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L
+#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L
+#define SQ_WAVE_IB_STS__RCNT_MASK 0x003F0000L
+#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L
+#define SQ_WAVE_IB_STS__LGKM_CNT_BIT5_MASK 0x01000000L
+#define SQ_WAVE_IB_STS__REPLAY_W64H_MASK 0x02000000L
+#define SQ_WAVE_IB_STS__VS_CNT_MASK 0xFC000000L
+//SQ_WAVE_PC_LO
+#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
+#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL
+//SQ_WAVE_PC_HI
+#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
+#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL
+//SQ_WAVE_INST_DW0
+#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
+#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL
+//SQ_WAVE_IB_DBG1
+#define SQ_WAVE_IB_DBG1__XNACK_ERROR__SHIFT 0x0
+#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
+#define SQ_WAVE_IB_DBG1__XNACK_OVERRIDE__SHIFT 0x3
+#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
+#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb
+#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12
+#define SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT 0x18
+#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19
+#define SQ_WAVE_IB_DBG1__XNACK_ERROR_MASK 0x00000001L
+#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L
+#define SQ_WAVE_IB_DBG1__XNACK_OVERRIDE_MASK 0x00000008L
+#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000003F0L
+#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0001F800L
+#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x00FC0000L
+#define SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK 0x01000000L
+#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L
+//SQ_WAVE_FLUSH_IB
+#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0
+#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL
+//SQ_WAVE_HW_ID1
+#define SQ_WAVE_HW_ID1__WAVE_ID__SHIFT 0x0
+#define SQ_WAVE_HW_ID1__SIMD_ID__SHIFT 0x8
+#define SQ_WAVE_HW_ID1__WGP_ID__SHIFT 0xa
+#define SQ_WAVE_HW_ID1__SA_ID__SHIFT 0x10
+#define SQ_WAVE_HW_ID1__SE_ID__SHIFT 0x12
+#define SQ_WAVE_HW_ID1__WAVE_ID_MASK 0x0000001FL
+#define SQ_WAVE_HW_ID1__SIMD_ID_MASK 0x00000300L
+#define SQ_WAVE_HW_ID1__WGP_ID_MASK 0x00003C00L
+#define SQ_WAVE_HW_ID1__SA_ID_MASK 0x00010000L
+#define SQ_WAVE_HW_ID1__SE_ID_MASK 0x000C0000L
+//SQ_WAVE_HW_ID2
+#define SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT 0x0
+#define SQ_WAVE_HW_ID2__PIPE_ID__SHIFT 0x4
+#define SQ_WAVE_HW_ID2__ME_ID__SHIFT 0x8
+#define SQ_WAVE_HW_ID2__STATE_ID__SHIFT 0xc
+#define SQ_WAVE_HW_ID2__WG_ID__SHIFT 0x10
+#define SQ_WAVE_HW_ID2__VM_ID__SHIFT 0x18
+#define SQ_WAVE_HW_ID2__COMPAT_LEVEL__SHIFT 0x1d
+#define SQ_WAVE_HW_ID2__QUEUE_ID_MASK 0x0000000FL
+#define SQ_WAVE_HW_ID2__PIPE_ID_MASK 0x00000030L
+#define SQ_WAVE_HW_ID2__ME_ID_MASK 0x00000300L
+#define SQ_WAVE_HW_ID2__STATE_ID_MASK 0x00007000L
+#define SQ_WAVE_HW_ID2__WG_ID_MASK 0x001F0000L
+#define SQ_WAVE_HW_ID2__VM_ID_MASK 0x0F000000L
+#define SQ_WAVE_HW_ID2__COMPAT_LEVEL_MASK 0x60000000L
+//SQ_WAVE_POPS_PACKER
+#define SQ_WAVE_POPS_PACKER__POPS_EN__SHIFT 0x0
+#define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID__SHIFT 0x1
+#define SQ_WAVE_POPS_PACKER__POPS_EN_MASK 0x00000001L
+#define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID_MASK 0x00000006L
+//SQ_WAVE_SCHED_MODE
+#define SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT 0x0
+#define SQ_WAVE_SCHED_MODE__DEP_MODE_MASK 0x00000003L
+//SQ_WAVE_VGPR_OFFSET
+#define SQ_WAVE_VGPR_OFFSET__SRC0__SHIFT 0x0
+#define SQ_WAVE_VGPR_OFFSET__SRC1__SHIFT 0x6
+#define SQ_WAVE_VGPR_OFFSET__SRC2__SHIFT 0xc
+#define SQ_WAVE_VGPR_OFFSET__DST__SHIFT 0x12
+#define SQ_WAVE_VGPR_OFFSET__SRC0_MASK 0x0000003FL
+#define SQ_WAVE_VGPR_OFFSET__SRC1_MASK 0x00000FC0L
+#define SQ_WAVE_VGPR_OFFSET__SRC2_MASK 0x0003F000L
+#define SQ_WAVE_VGPR_OFFSET__DST_MASK 0x00FC0000L
+//SQ_WAVE_IB_STS2
+#define SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT 0x0
+#define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE__SHIFT 0x7
+#define SQ_WAVE_IB_STS2__MEM_ORDER__SHIFT 0x8
+#define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT 0xa
+#define SQ_WAVE_IB_STS2__WAVE64__SHIFT 0xb
+#define SQ_WAVE_IB_STS2__WAVE64HI__SHIFT 0xc
+#define SQ_WAVE_IB_STS2__SUBV_LOOP__SHIFT 0xd
+#define SQ_WAVE_IB_STS2__INST_PREFETCH_MASK 0x00000003L
+#define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE_MASK 0x00000080L
+#define SQ_WAVE_IB_STS2__MEM_ORDER_MASK 0x00000300L
+#define SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK 0x00000400L
+#define SQ_WAVE_IB_STS2__WAVE64_MASK 0x00000800L
+#define SQ_WAVE_IB_STS2__WAVE64HI_MASK 0x00001000L
+#define SQ_WAVE_IB_STS2__SUBV_LOOP_MASK 0x00002000L
+//SQ_WAVE_TTMP0
+#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP1
+#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP2
+#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP3
+#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP4
+#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP5
+#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP6
+#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP7
+#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP8
+#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP9
+#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP10
+#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP11
+#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP12
+#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP13
+#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP14
+#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_TTMP15
+#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_M0
+#define SQ_WAVE_M0__M0__SHIFT 0x0
+#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL
+//SQ_WAVE_EXEC_LO
+#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
+#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL
+//SQ_WAVE_EXEC_HI
+#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
+#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL
+//SQ_WAVE_FLAT_SCRATCH_LO
+#define SQ_WAVE_FLAT_SCRATCH_LO__DATA__SHIFT 0x0
+#define SQ_WAVE_FLAT_SCRATCH_LO__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_FLAT_SCRATCH_HI
+#define SQ_WAVE_FLAT_SCRATCH_HI__DATA__SHIFT 0x0
+#define SQ_WAVE_FLAT_SCRATCH_HI__DATA_MASK 0xFFFFFFFFL
+//SQ_WAVE_FLAT_XNACK_MASK
+#define SQ_WAVE_FLAT_XNACK_MASK__MASK__SHIFT 0x0
+#define SQ_WAVE_FLAT_XNACK_MASK__MASK_MASK 0xFFFFFFFFL
+//SQ_INTERRUPT_WORD_AUTO
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL__SHIFT 0x2
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL__SHIFT 0x3
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x24
+#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x26
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x0000000001L
+#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x0000000002L
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL_MASK 0x0000000004L
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL_MASK 0x0000000008L
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR_MASK 0x0000000100L
+#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000000L
+#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xC000000000L
+//SQ_INTERRUPT_WORD_ERROR
+#define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE__SHIFT 0x13
+#define SQ_INTERRUPT_WORD_ERROR__SA_ID__SHIFT 0x17
+#define SQ_INTERRUPT_WORD_ERROR__PRIV__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_ERROR__WAVE_ID__SHIFT 0x19
+#define SQ_INTERRUPT_WORD_ERROR__SIMD_ID__SHIFT 0x1e
+#define SQ_INTERRUPT_WORD_ERROR__WGP_ID__SHIFT 0x20
+#define SQ_INTERRUPT_WORD_ERROR__SE_ID__SHIFT 0x24
+#define SQ_INTERRUPT_WORD_ERROR__ENCODING__SHIFT 0x26
+#define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL_MASK 0x000007FFFFL
+#define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE_MASK 0x0000780000L
+#define SQ_INTERRUPT_WORD_ERROR__SA_ID_MASK 0x0000800000L
+#define SQ_INTERRUPT_WORD_ERROR__PRIV_MASK 0x0001000000L
+#define SQ_INTERRUPT_WORD_ERROR__WAVE_ID_MASK 0x003E000000L
+#define SQ_INTERRUPT_WORD_ERROR__SIMD_ID_MASK 0x00C0000000L
+#define SQ_INTERRUPT_WORD_ERROR__WGP_ID_MASK 0x0F00000000L
+#define SQ_INTERRUPT_WORD_ERROR__SE_ID_MASK 0x3000000000L
+#define SQ_INTERRUPT_WORD_ERROR__ENCODING_MASK 0xC000000000L
+//SQ_INTERRUPT_WORD_WAVE
+#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE__SA_ID__SHIFT 0x17
+#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0x19
+#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x1e
+#define SQ_INTERRUPT_WORD_WAVE__WGP_ID__SHIFT 0x20
+#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x24
+#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x26
+#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0x00007FFFFFL
+#define SQ_INTERRUPT_WORD_WAVE__SA_ID_MASK 0x0000800000L
+#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x0001000000L
+#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x003E000000L
+#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0x00C0000000L
+#define SQ_INTERRUPT_WORD_WAVE__WGP_ID_MASK 0x0F00000000L
+#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000000L
+#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xC000000000L
+
+
+
+
+
+
+// addressBlock: didtind
+//DIDT_SQ_CTRL0
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
+#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
+#define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
+#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
+#define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L
+//DIDT_SQ_CTRL1
+#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_SQ_CTRL2
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+//DIDT_SQ_CTRL_OCP
+#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0
+#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL
+//DIDT_SQ_STALL_CTRL
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+//DIDT_SQ_TUNING_CTRL
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_SQ_STALL_AUTO_RELEASE_CTRL
+#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_SQ_CTRL3
+#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_SQ_STALL_PATTERN_1_2
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_SQ_STALL_PATTERN_3_4
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_SQ_STALL_PATTERN_5_6
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_SQ_STALL_PATTERN_7
+#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_SQ_MPD_SCALE_FACTOR
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
+#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
+//DIDT_SQ_STALL_RELEASE_CNTL0
+#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0
+#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
+#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
+#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
+#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L
+#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
+#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
+#define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
+//DIDT_SQ_STALL_RELEASE_CNTL1
+#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
+#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
+#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
+#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
+#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
+#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
+#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
+#define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
+//DIDT_SQ_STALL_RELEASE_CNTL_STATUS
+#define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0
+#define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L
+//DIDT_SQ_WEIGHT0_3
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_SQ_WEIGHT4_7
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_SQ_WEIGHT8_11
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_SQ_EDC_CTRL
+#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
+#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18
+#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
+#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L
+//DIDT_SQ_EDC_THRESHOLD
+#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_SQ_EDC_STALL_PATTERN_1_2
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_SQ_EDC_STALL_PATTERN_3_4
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_SQ_EDC_STALL_PATTERN_5_6
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_SQ_EDC_STALL_PATTERN_7
+#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_SQ_EDC_TIMER_PERIOD
+#define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0
+#define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL
+//DIDT_SQ_THROTTLE_CTRL
+#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0
+#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
+#define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2
+#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3
+#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L
+#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
+#define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L
+#define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L
+//DIDT_SQ_EDC_STALL_DELAY_1
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x6
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xc
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x12
+#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000003FL
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00000FC0L
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x0003F000L
+#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x00FC0000L
+#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
+//DIDT_SQ_EDC_STALL_DELAY_2
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x6
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0xc
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x12
+#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000003FL
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x00000FC0L
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x0003F000L
+#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0x00FC0000L
+#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L
+//DIDT_SQ_EDC_STALL_DELAY_3
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x6
+#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT 0xc
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x0000003FL
+#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x00000FC0L
+#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFFF000L
+//DIDT_SQ_EDC_STATUS
+#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_SQ_EDC_OVERFLOW
+#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_SQ_EDC_ROLLING_POWER_DELTA
+#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_SQ_EDC_PCC_PERF_COUNTER
+#define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0
+#define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_DB_CTRL0
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
+#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
+#define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
+#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
+#define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L
+//DIDT_DB_CTRL1
+#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_DB_CTRL2
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+//DIDT_DB_CTRL_OCP
+#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0
+#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL
+//DIDT_DB_STALL_CTRL
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+//DIDT_DB_TUNING_CTRL
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_DB_STALL_AUTO_RELEASE_CTRL
+#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_DB_CTRL3
+#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_DB_STALL_PATTERN_1_2
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_DB_STALL_PATTERN_3_4
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_DB_STALL_PATTERN_5_6
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_DB_STALL_PATTERN_7
+#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_DB_MPD_SCALE_FACTOR
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
+#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
+//DIDT_DB_STALL_RELEASE_CNTL0
+#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0
+#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
+#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
+#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
+#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L
+#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
+#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
+#define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
+//DIDT_DB_STALL_RELEASE_CNTL1
+#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
+#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
+#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
+#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
+#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
+#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
+#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
+#define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
+//DIDT_DB_STALL_RELEASE_CNTL_STATUS
+#define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0
+#define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L
+//DIDT_DB_WEIGHT0_3
+#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_DB_WEIGHT4_7
+#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_DB_WEIGHT8_11
+#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_DB_EDC_CTRL
+#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
+#define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18
+#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
+#define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L
+//DIDT_DB_EDC_THRESHOLD
+#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_DB_EDC_STALL_PATTERN_1_2
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_DB_EDC_STALL_PATTERN_3_4
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_DB_EDC_STALL_PATTERN_5_6
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_DB_EDC_STALL_PATTERN_7
+#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_DB_EDC_TIMER_PERIOD
+#define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0
+#define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL
+//DIDT_DB_THROTTLE_CTRL
+#define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0
+#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
+#define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2
+#define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3
+#define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L
+#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
+#define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L
+#define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L
+//DIDT_DB_EDC_STALL_DELAY_1
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x5
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT 0xa
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT 0xf
+#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x14
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000001FL
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x000003E0L
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK 0x00007C00L
+#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK 0x000F8000L
+#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFF00000L
+//DIDT_DB_EDC_STATUS
+#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_DB_EDC_OVERFLOW
+#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_DB_EDC_ROLLING_POWER_DELTA
+#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_DB_EDC_PCC_PERF_COUNTER
+#define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0
+#define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TD_CTRL0
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
+#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
+#define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
+#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
+#define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L
+//DIDT_TD_CTRL1
+#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_TD_CTRL2
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+//DIDT_TD_CTRL_OCP
+#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0
+#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL
+//DIDT_TD_STALL_CTRL
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+//DIDT_TD_TUNING_CTRL
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_TD_STALL_AUTO_RELEASE_CTRL
+#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_TD_CTRL3
+#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_TD_STALL_PATTERN_1_2
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_TD_STALL_PATTERN_3_4
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_TD_STALL_PATTERN_5_6
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_TD_STALL_PATTERN_7
+#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_TD_MPD_SCALE_FACTOR
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
+#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
+//DIDT_TD_STALL_RELEASE_CNTL0
+#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0
+#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
+#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
+#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
+#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L
+#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
+#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
+#define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
+//DIDT_TD_STALL_RELEASE_CNTL1
+#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
+#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
+#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
+#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
+#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
+#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
+#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
+#define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
+//DIDT_TD_STALL_RELEASE_CNTL_STATUS
+#define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0
+#define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L
+//DIDT_TD_WEIGHT0_3
+#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_TD_WEIGHT4_7
+#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_TD_WEIGHT8_11
+#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_TD_EDC_CTRL
+#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
+#define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18
+#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
+#define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L
+//DIDT_TD_EDC_THRESHOLD
+#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_TD_EDC_STALL_PATTERN_1_2
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_TD_EDC_STALL_PATTERN_3_4
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_TD_EDC_STALL_PATTERN_5_6
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_TD_EDC_STALL_PATTERN_7
+#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_TD_EDC_TIMER_PERIOD
+#define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0
+#define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL
+//DIDT_TD_THROTTLE_CTRL
+#define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0
+#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
+#define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2
+#define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3
+#define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L
+#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
+#define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L
+#define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L
+//DIDT_TD_EDC_STALL_DELAY_1
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x6
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xc
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x12
+#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000003FL
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00000FC0L
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x0003F000L
+#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x00FC0000L
+#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
+//DIDT_TD_EDC_STALL_DELAY_2
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x6
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0xc
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x12
+#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000003FL
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x00000FC0L
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x0003F000L
+#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0x00FC0000L
+#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L
+//DIDT_TD_EDC_STALL_DELAY_3
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x6
+#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT 0xc
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x0000003FL
+#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x00000FC0L
+#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFFF000L
+//DIDT_TD_EDC_STATUS
+#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_TD_EDC_OVERFLOW
+#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_TD_EDC_ROLLING_POWER_DELTA
+#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_TD_EDC_PCC_PERF_COUNTER
+#define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0
+#define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TCP_CTRL0
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
+#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
+#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
+#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
+#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
+#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
+#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
+#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
+#define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
+#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
+#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
+#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
+#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
+#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
+#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
+#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
+#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
+#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
+#define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L
+//DIDT_TCP_CTRL1
+#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL
+#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L
+//DIDT_TCP_CTRL2
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
+//DIDT_TCP_CTRL_OCP
+#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0
+#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL
+//DIDT_TCP_STALL_CTRL
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
+#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
+#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
+//DIDT_TCP_TUNING_CTRL
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
+#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
+//DIDT_TCP_STALL_AUTO_RELEASE_CTRL
+#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
+#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
+//DIDT_TCP_CTRL3
+#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
+#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
+#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2
+#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
+#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
+#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
+#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
+#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
+#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
+#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
+#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
+#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
+#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
+#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
+#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
+#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
+#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
+#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
+#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
+#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
+//DIDT_TCP_STALL_PATTERN_1_2
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_TCP_STALL_PATTERN_3_4
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_TCP_STALL_PATTERN_5_6
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_TCP_STALL_PATTERN_7
+#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_TCP_MPD_SCALE_FACTOR
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
+#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
+//DIDT_TCP_STALL_RELEASE_CNTL0
+#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0
+#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
+#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
+#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
+#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L
+#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
+#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
+#define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
+//DIDT_TCP_STALL_RELEASE_CNTL1
+#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
+#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
+#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
+#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
+#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
+#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
+#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
+#define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
+//DIDT_TCP_STALL_RELEASE_CNTL_STATUS
+#define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0
+#define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L
+//DIDT_TCP_WEIGHT0_3
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
+//DIDT_TCP_WEIGHT4_7
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
+//DIDT_TCP_WEIGHT8_11
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
+//DIDT_TCP_EDC_CTRL
+#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0
+#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
+#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
+#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
+#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
+#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
+#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
+#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
+#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
+#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
+#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
+#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
+#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18
+#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L
+#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
+#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
+#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
+#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
+#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
+#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
+#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
+#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
+#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
+#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
+#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
+#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L
+//DIDT_TCP_EDC_THRESHOLD
+#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
+#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
+//DIDT_TCP_EDC_STALL_PATTERN_1_2
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
+//DIDT_TCP_EDC_STALL_PATTERN_3_4
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
+//DIDT_TCP_EDC_STALL_PATTERN_5_6
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
+#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
+//DIDT_TCP_EDC_STALL_PATTERN_7
+#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
+//DIDT_TCP_EDC_TIMER_PERIOD
+#define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0
+#define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL
+//DIDT_TCP_THROTTLE_CTRL
+#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0
+#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
+#define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2
+#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3
+#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L
+#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
+#define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L
+#define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L
+//DIDT_TCP_EDC_STALL_DELAY_1
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x6
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xc
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x12
+#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000003FL
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00000FC0L
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x0003F000L
+#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x00FC0000L
+#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
+//DIDT_TCP_EDC_STALL_DELAY_2
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x6
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0xc
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x12
+#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000003FL
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x00000FC0L
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x0003F000L
+#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0x00FC0000L
+#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L
+//DIDT_TCP_EDC_STALL_DELAY_3
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x6
+#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT 0xc
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x0000003FL
+#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x00000FC0L
+#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFFF000L
+//DIDT_TCP_EDC_STATUS
+#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
+#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
+#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
+#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
+//DIDT_TCP_EDC_OVERFLOW
+#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
+#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
+#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
+#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
+//DIDT_TCP_EDC_ROLLING_POWER_DELTA
+#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
+#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
+//DIDT_TCP_EDC_PCC_PERF_COUNTER
+#define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0
+#define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_SQ_STALL_EVENT_COUNTER
+#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_DB_STALL_EVENT_COUNTER
+#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TD_STALL_EVENT_COUNTER
+#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+//DIDT_TCP_STALL_EVENT_COUNTER
+#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
+#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
+
+
+
+
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
index 529b37db274c..f1d048e0ed2c 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
@@ -829,6 +829,8 @@
#define mmTD_CNTL_BASE_IDX 0
#define mmTD_STATUS 0x0526
#define mmTD_STATUS_BASE_IDX 0
+#define mmTD_EDC_CNT 0x052e
+#define mmTD_EDC_CNT_BASE_IDX 0
#define mmTD_DSM_CNTL 0x052f
#define mmTD_DSM_CNTL_BASE_IDX 0
#define mmTD_DSM_CNTL2 0x0530
@@ -845,6 +847,8 @@
#define mmTA_STATUS_BASE_IDX 0
#define mmTA_SCRATCH 0x0564
#define mmTA_SCRATCH_BASE_IDX 0
+#define mmTA_EDC_CNT 0x0586
+#define mmTA_EDC_CNT_BASE_IDX 0
// addressBlock: gc_gdsdec
@@ -1051,6 +1055,13 @@
#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0
+// addressBlock: gc_ea_gceadec2
+// base address: 0x9c00
+#define mmGCEA_EDC_CNT 0x0706
+#define mmGCEA_EDC_CNT_BASE_IDX 0
+#define mmGCEA_EDC_CNT2 0x0707
+#define mmGCEA_EDC_CNT2_BASE_IDX 0
+
// addressBlock: gc_rmi_rmidec
// base address: 0x9e00
#define mmRMI_GENERAL_CNTL 0x0780
@@ -1709,6 +1720,8 @@
#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0
#define mmTC_CFG_L2_VOLATILE 0x0b23
#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0
+#define mmTCI_EDC_CNT 0x0b60
+#define mmTCI_EDC_CNT_BASE_IDX 0
#define mmTCI_STATUS 0x0b61
#define mmTCI_STATUS_BASE_IDX 0
#define mmTCI_CNTL_1 0x0b62
@@ -2594,6 +2607,24 @@
#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0
#define mmCP_RB_DOORBELL_CLEAR 0x1188
#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0
+#define mmCPF_EDC_TAG_CNT 0x1189
+#define mmCPF_EDC_TAG_CNT_BASE_IDX 0
+#define mmCPF_EDC_ROQ_CNT 0x118a
+#define mmCPF_EDC_ROQ_CNT_BASE_IDX 0
+#define mmCPG_EDC_TAG_CNT 0x118b
+#define mmCPG_EDC_TAG_CNT_BASE_IDX 0
+#define mmCPG_EDC_DMA_CNT 0x118d
+#define mmCPG_EDC_DMA_CNT_BASE_IDX 0
+#define mmCPC_EDC_SCRATCH_CNT 0x118e
+#define mmCPC_EDC_SCRATCH_CNT_BASE_IDX 0
+#define mmCPC_EDC_UCODE_CNT 0x118f
+#define mmCPC_EDC_UCODE_CNT_BASE_IDX 0
+#define mmDC_EDC_STATE_CNT 0x1191
+#define mmDC_EDC_STATE_CNT_BASE_IDX 0
+#define mmDC_EDC_CSINVOC_CNT 0x1192
+#define mmDC_EDC_CSINVOC_CNT_BASE_IDX 0
+#define mmDC_EDC_RESTORE_CNT 0x1193
+#define mmDC_EDC_RESTORE_CNT_BASE_IDX 0
#define mmCP_GFX_MQD_CONTROL 0x11a0
#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0
#define mmCP_GFX_MQD_BASE_ADDR 0x11a1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_offset.h
new file mode 100644
index 000000000000..64da122d0047
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_offset.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _hdp_5_0_0_OFFSET_HEADER
+#define _hdp_5_0_0_OFFSET_HEADER
+
+
+
+// addressBlock: hdp_hdpdec
+// base address: 0x3c80
+#define mmHDP_MMHUB_TLVL 0x0000
+#define mmHDP_MMHUB_TLVL_BASE_IDX 0
+#define mmHDP_MMHUB_UNITID 0x0001
+#define mmHDP_MMHUB_UNITID_BASE_IDX 0
+#define mmHDP_NONSURFACE_BASE 0x0040
+#define mmHDP_NONSURFACE_BASE_BASE_IDX 0
+#define mmHDP_NONSURFACE_INFO 0x0041
+#define mmHDP_NONSURFACE_INFO_BASE_IDX 0
+#define mmHDP_NONSURFACE_BASE_HI 0x0042
+#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0
+#define mmHDP_SURFACE_WRITE_FLAGS 0x00c4
+#define mmHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0
+#define mmHDP_SURFACE_READ_FLAGS 0x00c5
+#define mmHDP_SURFACE_READ_FLAGS_BASE_IDX 0
+#define mmHDP_SURFACE_WRITE_FLAGS_CLR 0x00c6
+#define mmHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX 0
+#define mmHDP_SURFACE_READ_FLAGS_CLR 0x00c7
+#define mmHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX 0
+#define mmHDP_NONSURF_FLAGS 0x00c8
+#define mmHDP_NONSURF_FLAGS_BASE_IDX 0
+#define mmHDP_NONSURF_FLAGS_CLR 0x00c9
+#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0
+#define mmHDP_HOST_PATH_CNTL 0x00cc
+#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0
+#define mmHDP_SW_SEMAPHORE 0x00cd
+#define mmHDP_SW_SEMAPHORE_BASE_IDX 0
+#define mmHDP_LAST_SURFACE_HIT 0x00d0
+#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0
+#define mmHDP_READ_CACHE_INVALIDATE 0x00d1
+#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0
+#define mmHDP_OUTSTANDING_REQ 0x00d2
+#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0
+#define mmHDP_MISC_CNTL 0x00d3
+#define mmHDP_MISC_CNTL_BASE_IDX 0
+#define mmHDP_MEM_POWER_CTRL 0x00d4
+#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
+#define mmHDP_MMHUB_CNTL 0x00d5
+#define mmHDP_MMHUB_CNTL_BASE_IDX 0
+#define mmHDP_EDC_CNT 0x00d6
+#define mmHDP_EDC_CNT_BASE_IDX 0
+#define mmHDP_VERSION 0x00d7
+#define mmHDP_VERSION_BASE_IDX 0
+#define mmHDP_CLK_CNTL 0x00d8
+#define mmHDP_CLK_CNTL_BASE_IDX 0
+#define mmHDP_MEMIO_CNTL 0x00f6
+#define mmHDP_MEMIO_CNTL_BASE_IDX 0
+#define mmHDP_MEMIO_ADDR 0x00f7
+#define mmHDP_MEMIO_ADDR_BASE_IDX 0
+#define mmHDP_MEMIO_STATUS 0x00f8
+#define mmHDP_MEMIO_STATUS_BASE_IDX 0
+#define mmHDP_MEMIO_WR_DATA 0x00f9
+#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0
+#define mmHDP_MEMIO_RD_DATA 0x00fa
+#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0
+#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100
+#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0
+#define mmHDP_XDP_D2H_FLUSH 0x0101
+#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0
+#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102
+#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_3 0x0103
+#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_4 0x0104
+#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_5 0x0105
+#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_6 0x0106
+#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_7 0x0107
+#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_8 0x0108
+#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_9 0x0109
+#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_10 0x010a
+#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_11 0x010b
+#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_12 0x010c
+#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_13 0x010d
+#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_14 0x010e
+#define mmHDP_XDP_D2H_RSVD_14_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_15 0x010f
+#define mmHDP_XDP_D2H_RSVD_15_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_16 0x0110
+#define mmHDP_XDP_D2H_RSVD_16_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_17 0x0111
+#define mmHDP_XDP_D2H_RSVD_17_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_18 0x0112
+#define mmHDP_XDP_D2H_RSVD_18_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_19 0x0113
+#define mmHDP_XDP_D2H_RSVD_19_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_20 0x0114
+#define mmHDP_XDP_D2H_RSVD_20_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_21 0x0115
+#define mmHDP_XDP_D2H_RSVD_21_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_22 0x0116
+#define mmHDP_XDP_D2H_RSVD_22_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_23 0x0117
+#define mmHDP_XDP_D2H_RSVD_23_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_24 0x0118
+#define mmHDP_XDP_D2H_RSVD_24_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_25 0x0119
+#define mmHDP_XDP_D2H_RSVD_25_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_26 0x011a
+#define mmHDP_XDP_D2H_RSVD_26_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_27 0x011b
+#define mmHDP_XDP_D2H_RSVD_27_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_28 0x011c
+#define mmHDP_XDP_D2H_RSVD_28_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_29 0x011d
+#define mmHDP_XDP_D2H_RSVD_29_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_30 0x011e
+#define mmHDP_XDP_D2H_RSVD_30_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_31 0x011f
+#define mmHDP_XDP_D2H_RSVD_31_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_32 0x0120
+#define mmHDP_XDP_D2H_RSVD_32_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_33 0x0121
+#define mmHDP_XDP_D2H_RSVD_33_BASE_IDX 0
+#define mmHDP_XDP_D2H_RSVD_34 0x0122
+#define mmHDP_XDP_D2H_RSVD_34_BASE_IDX 0
+#define mmHDP_XDP_DIRECT2HDP_LAST 0x0123
+#define mmHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR_CFG 0x0124
+#define mmHDP_XDP_P2P_BAR_CFG_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_OFFSET 0x0125
+#define mmHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR0 0x0126
+#define mmHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR1 0x0127
+#define mmHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR2 0x0128
+#define mmHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR3 0x0129
+#define mmHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR4 0x012a
+#define mmHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR5 0x012b
+#define mmHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0
+#define mmHDP_XDP_P2P_MBX_ADDR6 0x012c
+#define mmHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0
+#define mmHDP_XDP_HDP_MBX_MC_CFG 0x012d
+#define mmHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0
+#define mmHDP_XDP_HDP_MC_CFG 0x012e
+#define mmHDP_XDP_HDP_MC_CFG_BASE_IDX 0
+#define mmHDP_XDP_HST_CFG 0x012f
+#define mmHDP_XDP_HST_CFG_BASE_IDX 0
+#define mmHDP_XDP_HDP_IPH_CFG 0x0131
+#define mmHDP_XDP_HDP_IPH_CFG_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR0 0x0134
+#define mmHDP_XDP_P2P_BAR0_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR1 0x0135
+#define mmHDP_XDP_P2P_BAR1_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR2 0x0136
+#define mmHDP_XDP_P2P_BAR2_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR3 0x0137
+#define mmHDP_XDP_P2P_BAR3_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR4 0x0138
+#define mmHDP_XDP_P2P_BAR4_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR5 0x0139
+#define mmHDP_XDP_P2P_BAR5_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR6 0x013a
+#define mmHDP_XDP_P2P_BAR6_BASE_IDX 0
+#define mmHDP_XDP_P2P_BAR7 0x013b
+#define mmHDP_XDP_P2P_BAR7_BASE_IDX 0
+#define mmHDP_XDP_FLUSH_ARMED_STS 0x013c
+#define mmHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0
+#define mmHDP_XDP_FLUSH_CNTR0_STS 0x013d
+#define mmHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0
+#define mmHDP_XDP_BUSY_STS 0x013e
+#define mmHDP_XDP_BUSY_STS_BASE_IDX 0
+#define mmHDP_XDP_STICKY 0x013f
+#define mmHDP_XDP_STICKY_BASE_IDX 0
+#define mmHDP_XDP_CHKN 0x0140
+#define mmHDP_XDP_CHKN_BASE_IDX 0
+#define mmHDP_XDP_BARS_ADDR_39_36 0x0144
+#define mmHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0
+#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145
+#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0
+#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148
+#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG2 0x0149
+#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0
+#define mmHDP_XDP_MMHUB_ERROR 0x014a
+#define mmHDP_XDP_MMHUB_ERROR_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h
new file mode 100644
index 000000000000..87b942cebf62
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h
@@ -0,0 +1,659 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _hdp_5_0_0_SH_MASK_HEADER
+#define _hdp_5_0_0_SH_MASK_HEADER
+
+
+// addressBlock: hdp_hdpdec
+//HDP_MMHUB_TLVL
+#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
+#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
+#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
+#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
+#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
+#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L
+#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L
+#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L
+#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L
+#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L
+//HDP_MMHUB_UNITID
+#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0
+#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8
+#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10
+#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL
+#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L
+#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L
+//HDP_NONSURFACE_BASE
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL
+//HDP_NONSURFACE_INFO
+#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4
+#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8
+#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L
+#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L
+//HDP_NONSURFACE_BASE_HI
+#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0
+#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL
+//HDP_SURFACE_WRITE_FLAGS
+#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0
+#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1
+#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L
+#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L
+//HDP_SURFACE_READ_FLAGS
+#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0
+#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1
+#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L
+#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L
+//HDP_SURFACE_WRITE_FLAGS_CLR
+#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0
+#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1
+#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L
+#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L
+//HDP_SURFACE_READ_FLAGS_CLR
+#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0
+#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1
+#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L
+#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L
+//HDP_NONSURF_FLAGS
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L
+//HDP_NONSURF_FLAGS_CLR
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L
+//HDP_HOST_PATH_CNTL
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16
+#define HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN__SHIFT 0x17
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L
+#define HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN_MASK 0x00800000L
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L
+//HDP_SW_SEMAPHORE
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL
+//HDP_LAST_SURFACE_HIT
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L
+//HDP_READ_CACHE_INVALIDATE
+#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0
+#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L
+//HDP_OUTSTANDING_REQ
+#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
+#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
+#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL
+#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L
+//HDP_MISC_CNTL
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
+#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
+#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
+#define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE__SHIFT 0x7
+#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
+#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
+#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16
+#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17
+#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18
+#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19
+#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a
+#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b
+#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c
+#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d
+#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L
+#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
+#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L
+#define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE_MASK 0x00000080L
+#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
+#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
+#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L
+#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L
+#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L
+#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L
+#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L
+#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L
+#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L
+#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L
+#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L
+//HDP_MEM_POWER_CTRL
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN__SHIFT 0x0
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN__SHIFT 0x1
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN__SHIFT 0x2
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN__SHIFT 0x3
+#define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS__SHIFT 0x4
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13
+#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0x1e
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK 0x00000004L
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK 0x00000008L
+#define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS_MASK 0x00000070L
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L
+#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L
+#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L
+#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0xC0000000L
+//HDP_MMHUB_CNTL
+#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0
+#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1
+#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2
+#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L
+#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L
+#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L
+//HDP_EDC_CNT
+#define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0
+#define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2
+#define HDP_EDC_CNT__MEM2_SED_COUNT__SHIFT 0x4
+#define HDP_EDC_CNT__MEM3_SED_COUNT__SHIFT 0x6
+#define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L
+#define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL
+#define HDP_EDC_CNT__MEM2_SED_COUNT_MASK 0x00000030L
+#define HDP_EDC_CNT__MEM3_SED_COUNT_MASK 0x000000C0L
+//HDP_VERSION
+#define HDP_VERSION__MINVER__SHIFT 0x0
+#define HDP_VERSION__MAJVER__SHIFT 0x8
+#define HDP_VERSION__REV__SHIFT 0x10
+#define HDP_VERSION__MINVER_MASK 0x000000FFL
+#define HDP_VERSION__MAJVER_MASK 0x0000FF00L
+#define HDP_VERSION__REV_MASK 0x00FF0000L
+//HDP_CLK_CNTL
+#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0
+#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4
+#define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a
+#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b
+#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c
+#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
+#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e
+#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
+#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL
+#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L
+#define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L
+#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L
+#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L
+#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
+#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L
+#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
+//HDP_MEMIO_CNTL
+#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
+#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
+#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
+#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
+#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
+#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L
+#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L
+#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L
+#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L
+#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L
+//HDP_MEMIO_ADDR
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL
+//HDP_MEMIO_STATUS
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L
+//HDP_MEMIO_WR_DATA
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL
+//HDP_MEMIO_RD_DATA
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL
+//HDP_XDP_DIRECT2HDP_FIRST
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_FLUSH
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L
+//HDP_XDP_D2H_BAR_UPDATE
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L
+//HDP_XDP_D2H_RSVD_3
+#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_4
+#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_5
+#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_6
+#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_7
+#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_8
+#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_9
+#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_10
+#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_11
+#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_12
+#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_13
+#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_14
+#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_15
+#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_16
+#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_17
+#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_18
+#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_19
+#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_20
+#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_21
+#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_22
+#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_23
+#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_24
+#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_25
+#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_26
+#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_27
+#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_28
+#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_29
+#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_30
+#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_31
+#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_32
+#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_33
+#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_D2H_RSVD_34
+#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_DIRECT2HDP_LAST
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL
+//HDP_XDP_P2P_BAR_CFG
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L
+//HDP_XDP_P2P_MBX_OFFSET
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL
+//HDP_XDP_P2P_MBX_ADDR0
+#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR1
+#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR2
+#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR3
+#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR4
+#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR5
+#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_P2P_MBX_ADDR6
+#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18
+#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L
+//HDP_XDP_HDP_MBX_MC_CFG
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L
+//HDP_XDP_HDP_MC_CFG
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L
+//HDP_XDP_HST_CFG
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L
+//HDP_XDP_HDP_IPH_CFG
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L
+//HDP_XDP_P2P_BAR0
+#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR1
+#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR2
+#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR3
+#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR4
+#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR5
+#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR6
+#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L
+//HDP_XDP_P2P_BAR7
+#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL
+#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L
+#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L
+//HDP_XDP_FLUSH_ARMED_STS
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL
+//HDP_XDP_FLUSH_CNTR0_STS
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL
+//HDP_XDP_BUSY_STS
+#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
+#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x00FFFFFFL
+//HDP_XDP_STICKY
+#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
+#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL
+#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L
+//HDP_XDP_CHKN
+#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
+#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
+#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
+#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL
+#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L
+#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L
+#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L
+//HDP_XDP_BARS_ADDR_39_36
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L
+//HDP_XDP_MC_VM_FB_LOCATION_BASE
+#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL
+//HDP_XDP_GPU_IOV_VIOLATION_LOG
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x01F00000L
+//HDP_XDP_GPU_IOV_VIOLATION_LOG2
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
+#define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
+//HDP_XDP_MMHUB_ERROR
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L
+#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L
+#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L
+#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L
+#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L
+#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h
new file mode 100644
index 000000000000..5fca506ffede
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h
@@ -0,0 +1,927 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mmhub_2_0_0_DEFAULT_HEADER
+#define _mmhub_2_0_0_DEFAULT_HEADER
+
+
+// addressBlock: mmhub_dagbdec
+#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI16_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI17_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RDCLI18_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8
+#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x00003046
+#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039
+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
+#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111
+#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a0e408
+#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7
+#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI16_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI17_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WRCLI18_DEFAULT 0xfe5fe0f9
+#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8
+#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x00003046
+#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039
+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
+#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111
+#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_DEFAULT 0x11111111
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_DEFAULT 0x00000000
+#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082
+#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a0e408
+#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7
+#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x60606070
+#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88
+#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_DEFAULT 0x00000000
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_DEFAULT 0x00000000
+#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000
+#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa
+#define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000
+#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff
+#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000
+#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff
+#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff
+#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmDAGB0_RESERVE0_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE1_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE2_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE3_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE4_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE5_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE6_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE7_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE8_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE9_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE10_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE11_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE12_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE13_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE14_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE15_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE16_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE17_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE18_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE19_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE20_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE21_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE22_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE23_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE24_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE25_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE26_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE27_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE28_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE29_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE30_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE31_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE32_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE33_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE34_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE35_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE36_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE37_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE38_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE39_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE40_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE41_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE42_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE43_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE44_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE45_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE46_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE47_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE48_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE49_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE50_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE51_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE52_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE53_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE54_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE55_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE56_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE57_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE58_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE59_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE60_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE61_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE62_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE63_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE64_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE65_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE66_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE67_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE68_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE69_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE70_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE71_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE72_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE73_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE74_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE75_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE76_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE77_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE78_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE79_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE80_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE81_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE82_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE83_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE84_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE85_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE86_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE87_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE88_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE89_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE90_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE91_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE92_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE93_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE94_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE95_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE96_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE97_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE98_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE99_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE100_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE101_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE102_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE103_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE104_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE105_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE106_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE107_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE108_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE109_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE110_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE111_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE112_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE113_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE114_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE115_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE116_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE117_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE118_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE119_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE120_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE121_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE122_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE123_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE124_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE125_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE126_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE127_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE128_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE129_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE130_DEFAULT 0xffffffff
+#define mmDAGB0_RESERVE131_DEFAULT 0xffffffff
+
+
+// addressBlock: mmhub_mmea_mmeadec
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555
+#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25
+#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25
+#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x78000924
+#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x78000924
+#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444
+#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444
+#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000
+#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6
+#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000
+#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef
+#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000
+#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
+#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
+#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4
+#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4
+#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777
+#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777
+#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03
+#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249
+#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6
+#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924
+#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492
+#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492
+#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff
+#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff
+#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00101e40
+#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff
+#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000
+#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000
+#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000101bf
+#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000
+#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000
+#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000
+#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000
+#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000
+#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000
+#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f
+#define mmMMEA0_MISC_DEFAULT 0x0c00a070
+#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000
+#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000
+#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000
+#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100
+#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000
+#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000300
+#define mmMMEA0_MISC2_DEFAULT 0x00000000
+#define mmMMEA0_ADDRDEC_SELECT_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_pctldec
+#define mmPCTL_MISC_DEFAULT 0x00000889
+#define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000
+#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000
+#define mmPCTL_PG_DAGB_DEFAULT 0x00000000
+#define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000
+#define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000
+#define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000
+#define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000
+#define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000
+#define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000
+#define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000
+#define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000
+#define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff
+#define mmPCTL0_MISC_DEFAULT 0x00011000
+#define mmPCTL1_MISC_DEFAULT 0x00000800
+#define mmPCTL2_MISC_DEFAULT 0x00000800
+#define mmPCTL_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmPCTL_PERFCOUNTER_HI_DEFAULT 0x00000000
+#define mmPCTL_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmPCTL_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmPCTL_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+
+// addressBlock: mmhub_l1tlb_mmvml1pfdec
+#define mmMMMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_l1tlb_mmvml1pldec
+#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+
+// addressBlock: mmhub_l1tlb_mmvml1prdec
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+#define mmMM_ATC_L2_CNTL_DEFAULT 0x000001c0
+#define mmMM_ATC_L2_CNTL2_DEFAULT 0x00000100
+#define mmMM_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000
+#define mmMM_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000
+#define mmMM_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000
+#define mmMM_ATC_L2_CNTL3_DEFAULT 0x000001f8
+#define mmMM_ATC_L2_STATUS_DEFAULT 0x00000000
+#define mmMM_ATC_L2_STATUS2_DEFAULT 0x00000000
+#define mmMM_ATC_L2_MISC_CG_DEFAULT 0x00000200
+#define mmMM_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmMM_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+#define mmMM_ATC_L2_SDPPORT_CTRL_DEFAULT 0x000003ff
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+#define mmMMVM_L2_CNTL_DEFAULT 0x00080602
+#define mmMMVM_L2_CNTL2_DEFAULT 0x00000000
+#define mmMMVM_L2_CNTL3_DEFAULT 0x80100007
+#define mmMMVM_L2_STATUS_DEFAULT 0x00000000
+#define mmMMVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_CNTL_DEFAULT 0x0000010f
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff
+#define mmMMVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000
+#define mmMMVM_L2_CNTL4_DEFAULT 0x000000c1
+#define mmMMVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000
+#define mmMMVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000
+#define mmMMVM_L2_IH_LOG_CNTL_DEFAULT 0x00000002
+#define mmMMVM_L2_IH_LOG_BUSY_DEFAULT 0x00000000
+#define mmMMVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+#define mmMMVM_L2_CNTL5_DEFAULT 0x00003fe0
+#define mmMMVM_L2_GCR_CNTL_DEFAULT 0x00000000
+#define mmMMVML2_WALKER_MACRO_THROTTLE_TIME_DEFAULT 0x00000000
+#define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000
+#define mmMMVML2_WALKER_MICRO_THROTTLE_TIME_DEFAULT 0x00000000
+#define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+#define mmMMVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80
+#define mmMMVM_CONTEXTS_DISABLE_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG0_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG1_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG2_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG3_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG4_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG5_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG6_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG7_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG8_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG9_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG10_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG11_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG12_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG13_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG14_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG15_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG16_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG17_REQ_DEFAULT 0x02f80000
+#define mmMMVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+#define mmMMMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+#define mmMMMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF16_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF17_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF18_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF19_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF20_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF21_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF22_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF23_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF24_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF25_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF26_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF27_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF28_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF29_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF30_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF31_DEFAULT 0x00000000
+#define mmMMVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100
+#define mmMMMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000
+#define mmMMMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000
+#define mmMMVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000
+#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_16_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_17_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_18_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_19_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_20_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_21_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_22_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_23_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_24_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_25_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_26_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_27_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_28_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_29_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_30_DEFAULT 0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_31_DEFAULT 0x00000000
+#define mmMMUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080
+#define mmMMMC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+#define mmMMMC_VM_NB_MMIOBASE_DEFAULT 0x00000000
+#define mmMMMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000
+#define mmMMMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000
+#define mmMMMC_VM_NB_PCI_ARB_DEFAULT 0x00000008
+#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000
+#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000
+#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_OFFSET_DEFAULT 0x00000000
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000
+#define mmMMMC_VM_STEERING_DEFAULT 0x00000001
+#define mmMMMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000
+#define mmMMMC_MEM_POWER_LS_DEFAULT 0x00000208
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000
+#define mmMMMC_VM_APT_CNTL_DEFAULT 0x00000000
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff
+#define mmMMMC_SHARED_VIRT_RESET_REQ2_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+#define mmMMMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000
+#define mmMMMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000
+#define mmMMMC_VM_AGP_TOP_DEFAULT 0x00000000
+#define mmMMMC_VM_AGP_BOT_DEFAULT 0x00000000
+#define mmMMMC_VM_AGP_BASE_DEFAULT 0x00000000
+#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000
+#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000
+#define mmMMMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000501
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+#define mmMM_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000
+#define mmMM_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+#define mmMM_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000
+#define mmMM_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000
+#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h
new file mode 100644
index 000000000000..7883a0140aa3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h
@@ -0,0 +1,1799 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mmhub_2_0_0_OFFSET_HEADER
+#define _mmhub_2_0_0_OFFSET_HEADER
+
+
+
+// addressBlock: mmhub_dagbdec
+// base address: 0x68000
+#define mmDAGB0_RDCLI0 0x0000
+#define mmDAGB0_RDCLI0_BASE_IDX 0
+#define mmDAGB0_RDCLI1 0x0001
+#define mmDAGB0_RDCLI1_BASE_IDX 0
+#define mmDAGB0_RDCLI2 0x0002
+#define mmDAGB0_RDCLI2_BASE_IDX 0
+#define mmDAGB0_RDCLI3 0x0003
+#define mmDAGB0_RDCLI3_BASE_IDX 0
+#define mmDAGB0_RDCLI4 0x0004
+#define mmDAGB0_RDCLI4_BASE_IDX 0
+#define mmDAGB0_RDCLI5 0x0005
+#define mmDAGB0_RDCLI5_BASE_IDX 0
+#define mmDAGB0_RDCLI6 0x0006
+#define mmDAGB0_RDCLI6_BASE_IDX 0
+#define mmDAGB0_RDCLI7 0x0007
+#define mmDAGB0_RDCLI7_BASE_IDX 0
+#define mmDAGB0_RDCLI8 0x0008
+#define mmDAGB0_RDCLI8_BASE_IDX 0
+#define mmDAGB0_RDCLI9 0x0009
+#define mmDAGB0_RDCLI9_BASE_IDX 0
+#define mmDAGB0_RDCLI10 0x000a
+#define mmDAGB0_RDCLI10_BASE_IDX 0
+#define mmDAGB0_RDCLI11 0x000b
+#define mmDAGB0_RDCLI11_BASE_IDX 0
+#define mmDAGB0_RDCLI12 0x000c
+#define mmDAGB0_RDCLI12_BASE_IDX 0
+#define mmDAGB0_RDCLI13 0x000d
+#define mmDAGB0_RDCLI13_BASE_IDX 0
+#define mmDAGB0_RDCLI14 0x000e
+#define mmDAGB0_RDCLI14_BASE_IDX 0
+#define mmDAGB0_RDCLI15 0x000f
+#define mmDAGB0_RDCLI15_BASE_IDX 0
+#define mmDAGB0_RDCLI16 0x0010
+#define mmDAGB0_RDCLI16_BASE_IDX 0
+#define mmDAGB0_RDCLI17 0x0011
+#define mmDAGB0_RDCLI17_BASE_IDX 0
+#define mmDAGB0_RDCLI18 0x0012
+#define mmDAGB0_RDCLI18_BASE_IDX 0
+#define mmDAGB0_RD_CNTL 0x0013
+#define mmDAGB0_RD_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_GMI_CNTL 0x0014
+#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB 0x0015
+#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0
+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0016
+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0017
+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0018
+#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0019
+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x001a
+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x001b
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x001c
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001d
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001e
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x001f
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0020
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0
+#define mmDAGB0_RD_VC0_CNTL 0x0021
+#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC1_CNTL 0x0022
+#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC2_CNTL 0x0023
+#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC3_CNTL 0x0024
+#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC4_CNTL 0x0025
+#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC5_CNTL 0x0026
+#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC6_CNTL 0x0027
+#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_VC7_CNTL 0x0028
+#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0
+#define mmDAGB0_RD_CNTL_MISC 0x0029
+#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0
+#define mmDAGB0_RD_TLB_CREDIT 0x002a
+#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0
+#define mmDAGB0_RDCLI_ASK_PENDING 0x002b
+#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_GO_PENDING 0x002c
+#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x002d
+#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_TLB_PENDING 0x002e
+#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_OARB_PENDING 0x002f
+#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0
+#define mmDAGB0_RDCLI_OSD_PENDING 0x0030
+#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI0 0x0031
+#define mmDAGB0_WRCLI0_BASE_IDX 0
+#define mmDAGB0_WRCLI1 0x0032
+#define mmDAGB0_WRCLI1_BASE_IDX 0
+#define mmDAGB0_WRCLI2 0x0033
+#define mmDAGB0_WRCLI2_BASE_IDX 0
+#define mmDAGB0_WRCLI3 0x0034
+#define mmDAGB0_WRCLI3_BASE_IDX 0
+#define mmDAGB0_WRCLI4 0x0035
+#define mmDAGB0_WRCLI4_BASE_IDX 0
+#define mmDAGB0_WRCLI5 0x0036
+#define mmDAGB0_WRCLI5_BASE_IDX 0
+#define mmDAGB0_WRCLI6 0x0037
+#define mmDAGB0_WRCLI6_BASE_IDX 0
+#define mmDAGB0_WRCLI7 0x0038
+#define mmDAGB0_WRCLI7_BASE_IDX 0
+#define mmDAGB0_WRCLI8 0x0039
+#define mmDAGB0_WRCLI8_BASE_IDX 0
+#define mmDAGB0_WRCLI9 0x003a
+#define mmDAGB0_WRCLI9_BASE_IDX 0
+#define mmDAGB0_WRCLI10 0x003b
+#define mmDAGB0_WRCLI10_BASE_IDX 0
+#define mmDAGB0_WRCLI11 0x003c
+#define mmDAGB0_WRCLI11_BASE_IDX 0
+#define mmDAGB0_WRCLI12 0x003d
+#define mmDAGB0_WRCLI12_BASE_IDX 0
+#define mmDAGB0_WRCLI13 0x003e
+#define mmDAGB0_WRCLI13_BASE_IDX 0
+#define mmDAGB0_WRCLI14 0x003f
+#define mmDAGB0_WRCLI14_BASE_IDX 0
+#define mmDAGB0_WRCLI15 0x0040
+#define mmDAGB0_WRCLI15_BASE_IDX 0
+#define mmDAGB0_WRCLI16 0x0041
+#define mmDAGB0_WRCLI16_BASE_IDX 0
+#define mmDAGB0_WRCLI17 0x0042
+#define mmDAGB0_WRCLI17_BASE_IDX 0
+#define mmDAGB0_WRCLI18 0x0043
+#define mmDAGB0_WRCLI18_BASE_IDX 0
+#define mmDAGB0_WR_CNTL 0x0044
+#define mmDAGB0_WR_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_GMI_CNTL 0x0045
+#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB 0x0046
+#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0
+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0047
+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0048
+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0049
+#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x004a
+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x004b
+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x004c
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x004d
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x004e
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x004f
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x0050
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x0051
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB 0x0052
+#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0053
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0054
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0055
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0056
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0057
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0058
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0
+#define mmDAGB0_WR_VC0_CNTL 0x0059
+#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC1_CNTL 0x005a
+#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC2_CNTL 0x005b
+#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC3_CNTL 0x005c
+#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC4_CNTL 0x005d
+#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC5_CNTL 0x005e
+#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC6_CNTL 0x005f
+#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_VC7_CNTL 0x0060
+#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0
+#define mmDAGB0_WR_CNTL_MISC 0x0061
+#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0
+#define mmDAGB0_WR_TLB_CREDIT 0x0062
+#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0
+#define mmDAGB0_WR_DATA_CREDIT 0x0063
+#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0
+#define mmDAGB0_WR_MISC_CREDIT 0x0064
+#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0
+#define mmDAGB0_WRCLI_ASK_PENDING 0x0065
+#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_GO_PENDING 0x0066
+#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x0067
+#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_TLB_PENDING 0x0068
+#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_OARB_PENDING 0x0069
+#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_OSD_PENDING 0x006a
+#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x006b
+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x006c
+#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x006d
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x006e
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
+#define mmDAGB0_DAGB_DLY 0x006f
+#define mmDAGB0_DAGB_DLY_BASE_IDX 0
+#define mmDAGB0_CNTL_MISC 0x0070
+#define mmDAGB0_CNTL_MISC_BASE_IDX 0
+#define mmDAGB0_CNTL_MISC2 0x0071
+#define mmDAGB0_CNTL_MISC2_BASE_IDX 0
+#define mmDAGB0_FIFO_EMPTY 0x0072
+#define mmDAGB0_FIFO_EMPTY_BASE_IDX 0
+#define mmDAGB0_FIFO_FULL 0x0073
+#define mmDAGB0_FIFO_FULL_BASE_IDX 0
+#define mmDAGB0_WR_CREDITS_FULL 0x0074
+#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0
+#define mmDAGB0_RD_CREDITS_FULL 0x0075
+#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER_LO 0x0076
+#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER_HI 0x0077
+#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER0_CFG 0x0078
+#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER1_CFG 0x0079
+#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER2_CFG 0x007a
+#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x007b
+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmDAGB0_RESERVE0 0x007c
+#define mmDAGB0_RESERVE0_BASE_IDX 0
+#define mmDAGB0_RESERVE1 0x007d
+#define mmDAGB0_RESERVE1_BASE_IDX 0
+#define mmDAGB0_RESERVE2 0x007e
+#define mmDAGB0_RESERVE2_BASE_IDX 0
+#define mmDAGB0_RESERVE3 0x007f
+#define mmDAGB0_RESERVE3_BASE_IDX 0
+#define mmDAGB0_RESERVE4 0x0080
+#define mmDAGB0_RESERVE4_BASE_IDX 0
+#define mmDAGB0_RESERVE5 0x0081
+#define mmDAGB0_RESERVE5_BASE_IDX 0
+#define mmDAGB0_RESERVE6 0x0082
+#define mmDAGB0_RESERVE6_BASE_IDX 0
+#define mmDAGB0_RESERVE7 0x0083
+#define mmDAGB0_RESERVE7_BASE_IDX 0
+#define mmDAGB0_RESERVE8 0x0084
+#define mmDAGB0_RESERVE8_BASE_IDX 0
+#define mmDAGB0_RESERVE9 0x0085
+#define mmDAGB0_RESERVE9_BASE_IDX 0
+#define mmDAGB0_RESERVE10 0x0086
+#define mmDAGB0_RESERVE10_BASE_IDX 0
+#define mmDAGB0_RESERVE11 0x0087
+#define mmDAGB0_RESERVE11_BASE_IDX 0
+#define mmDAGB0_RESERVE12 0x0088
+#define mmDAGB0_RESERVE12_BASE_IDX 0
+#define mmDAGB0_RESERVE13 0x0089
+#define mmDAGB0_RESERVE13_BASE_IDX 0
+#define mmDAGB0_RESERVE14 0x008a
+#define mmDAGB0_RESERVE14_BASE_IDX 0
+#define mmDAGB0_RESERVE15 0x008b
+#define mmDAGB0_RESERVE15_BASE_IDX 0
+#define mmDAGB0_RESERVE16 0x008c
+#define mmDAGB0_RESERVE16_BASE_IDX 0
+#define mmDAGB0_RESERVE17 0x008d
+#define mmDAGB0_RESERVE17_BASE_IDX 0
+#define mmDAGB0_RESERVE18 0x008e
+#define mmDAGB0_RESERVE18_BASE_IDX 0
+#define mmDAGB0_RESERVE19 0x008f
+#define mmDAGB0_RESERVE19_BASE_IDX 0
+#define mmDAGB0_RESERVE20 0x0090
+#define mmDAGB0_RESERVE20_BASE_IDX 0
+#define mmDAGB0_RESERVE21 0x0091
+#define mmDAGB0_RESERVE21_BASE_IDX 0
+#define mmDAGB0_RESERVE22 0x0092
+#define mmDAGB0_RESERVE22_BASE_IDX 0
+#define mmDAGB0_RESERVE23 0x0093
+#define mmDAGB0_RESERVE23_BASE_IDX 0
+#define mmDAGB0_RESERVE24 0x0094
+#define mmDAGB0_RESERVE24_BASE_IDX 0
+#define mmDAGB0_RESERVE25 0x0095
+#define mmDAGB0_RESERVE25_BASE_IDX 0
+#define mmDAGB0_RESERVE26 0x0096
+#define mmDAGB0_RESERVE26_BASE_IDX 0
+#define mmDAGB0_RESERVE27 0x0097
+#define mmDAGB0_RESERVE27_BASE_IDX 0
+#define mmDAGB0_RESERVE28 0x0098
+#define mmDAGB0_RESERVE28_BASE_IDX 0
+#define mmDAGB0_RESERVE29 0x0099
+#define mmDAGB0_RESERVE29_BASE_IDX 0
+#define mmDAGB0_RESERVE30 0x009a
+#define mmDAGB0_RESERVE30_BASE_IDX 0
+#define mmDAGB0_RESERVE31 0x009b
+#define mmDAGB0_RESERVE31_BASE_IDX 0
+#define mmDAGB0_RESERVE32 0x009c
+#define mmDAGB0_RESERVE32_BASE_IDX 0
+#define mmDAGB0_RESERVE33 0x009d
+#define mmDAGB0_RESERVE33_BASE_IDX 0
+#define mmDAGB0_RESERVE34 0x009e
+#define mmDAGB0_RESERVE34_BASE_IDX 0
+#define mmDAGB0_RESERVE35 0x009f
+#define mmDAGB0_RESERVE35_BASE_IDX 0
+#define mmDAGB0_RESERVE36 0x00a0
+#define mmDAGB0_RESERVE36_BASE_IDX 0
+#define mmDAGB0_RESERVE37 0x00a1
+#define mmDAGB0_RESERVE37_BASE_IDX 0
+#define mmDAGB0_RESERVE38 0x00a2
+#define mmDAGB0_RESERVE38_BASE_IDX 0
+#define mmDAGB0_RESERVE39 0x00a3
+#define mmDAGB0_RESERVE39_BASE_IDX 0
+#define mmDAGB0_RESERVE40 0x00a4
+#define mmDAGB0_RESERVE40_BASE_IDX 0
+#define mmDAGB0_RESERVE41 0x00a5
+#define mmDAGB0_RESERVE41_BASE_IDX 0
+#define mmDAGB0_RESERVE42 0x00a6
+#define mmDAGB0_RESERVE42_BASE_IDX 0
+#define mmDAGB0_RESERVE43 0x00a7
+#define mmDAGB0_RESERVE43_BASE_IDX 0
+#define mmDAGB0_RESERVE44 0x00a8
+#define mmDAGB0_RESERVE44_BASE_IDX 0
+#define mmDAGB0_RESERVE45 0x00a9
+#define mmDAGB0_RESERVE45_BASE_IDX 0
+#define mmDAGB0_RESERVE46 0x00aa
+#define mmDAGB0_RESERVE46_BASE_IDX 0
+#define mmDAGB0_RESERVE47 0x00ab
+#define mmDAGB0_RESERVE47_BASE_IDX 0
+#define mmDAGB0_RESERVE48 0x00ac
+#define mmDAGB0_RESERVE48_BASE_IDX 0
+#define mmDAGB0_RESERVE49 0x00ad
+#define mmDAGB0_RESERVE49_BASE_IDX 0
+#define mmDAGB0_RESERVE50 0x00ae
+#define mmDAGB0_RESERVE50_BASE_IDX 0
+#define mmDAGB0_RESERVE51 0x00af
+#define mmDAGB0_RESERVE51_BASE_IDX 0
+#define mmDAGB0_RESERVE52 0x00b0
+#define mmDAGB0_RESERVE52_BASE_IDX 0
+#define mmDAGB0_RESERVE53 0x00b1
+#define mmDAGB0_RESERVE53_BASE_IDX 0
+#define mmDAGB0_RESERVE54 0x00b2
+#define mmDAGB0_RESERVE54_BASE_IDX 0
+#define mmDAGB0_RESERVE55 0x00b3
+#define mmDAGB0_RESERVE55_BASE_IDX 0
+#define mmDAGB0_RESERVE56 0x00b4
+#define mmDAGB0_RESERVE56_BASE_IDX 0
+#define mmDAGB0_RESERVE57 0x00b5
+#define mmDAGB0_RESERVE57_BASE_IDX 0
+#define mmDAGB0_RESERVE58 0x00b6
+#define mmDAGB0_RESERVE58_BASE_IDX 0
+#define mmDAGB0_RESERVE59 0x00b7
+#define mmDAGB0_RESERVE59_BASE_IDX 0
+#define mmDAGB0_RESERVE60 0x00b8
+#define mmDAGB0_RESERVE60_BASE_IDX 0
+#define mmDAGB0_RESERVE61 0x00b9
+#define mmDAGB0_RESERVE61_BASE_IDX 0
+#define mmDAGB0_RESERVE62 0x00ba
+#define mmDAGB0_RESERVE62_BASE_IDX 0
+#define mmDAGB0_RESERVE63 0x00bb
+#define mmDAGB0_RESERVE63_BASE_IDX 0
+#define mmDAGB0_RESERVE64 0x00bc
+#define mmDAGB0_RESERVE64_BASE_IDX 0
+#define mmDAGB0_RESERVE65 0x00bd
+#define mmDAGB0_RESERVE65_BASE_IDX 0
+#define mmDAGB0_RESERVE66 0x00be
+#define mmDAGB0_RESERVE66_BASE_IDX 0
+#define mmDAGB0_RESERVE67 0x00bf
+#define mmDAGB0_RESERVE67_BASE_IDX 0
+#define mmDAGB0_RESERVE68 0x00c0
+#define mmDAGB0_RESERVE68_BASE_IDX 0
+#define mmDAGB0_RESERVE69 0x00c1
+#define mmDAGB0_RESERVE69_BASE_IDX 0
+#define mmDAGB0_RESERVE70 0x00c2
+#define mmDAGB0_RESERVE70_BASE_IDX 0
+#define mmDAGB0_RESERVE71 0x00c3
+#define mmDAGB0_RESERVE71_BASE_IDX 0
+#define mmDAGB0_RESERVE72 0x00c4
+#define mmDAGB0_RESERVE72_BASE_IDX 0
+#define mmDAGB0_RESERVE73 0x00c5
+#define mmDAGB0_RESERVE73_BASE_IDX 0
+#define mmDAGB0_RESERVE74 0x00c6
+#define mmDAGB0_RESERVE74_BASE_IDX 0
+#define mmDAGB0_RESERVE75 0x00c7
+#define mmDAGB0_RESERVE75_BASE_IDX 0
+#define mmDAGB0_RESERVE76 0x00c8
+#define mmDAGB0_RESERVE76_BASE_IDX 0
+#define mmDAGB0_RESERVE77 0x00c9
+#define mmDAGB0_RESERVE77_BASE_IDX 0
+#define mmDAGB0_RESERVE78 0x00ca
+#define mmDAGB0_RESERVE78_BASE_IDX 0
+#define mmDAGB0_RESERVE79 0x00cb
+#define mmDAGB0_RESERVE79_BASE_IDX 0
+#define mmDAGB0_RESERVE80 0x00cc
+#define mmDAGB0_RESERVE80_BASE_IDX 0
+#define mmDAGB0_RESERVE81 0x00cd
+#define mmDAGB0_RESERVE81_BASE_IDX 0
+#define mmDAGB0_RESERVE82 0x00ce
+#define mmDAGB0_RESERVE82_BASE_IDX 0
+#define mmDAGB0_RESERVE83 0x00cf
+#define mmDAGB0_RESERVE83_BASE_IDX 0
+#define mmDAGB0_RESERVE84 0x00d0
+#define mmDAGB0_RESERVE84_BASE_IDX 0
+#define mmDAGB0_RESERVE85 0x00d1
+#define mmDAGB0_RESERVE85_BASE_IDX 0
+#define mmDAGB0_RESERVE86 0x00d2
+#define mmDAGB0_RESERVE86_BASE_IDX 0
+#define mmDAGB0_RESERVE87 0x00d3
+#define mmDAGB0_RESERVE87_BASE_IDX 0
+#define mmDAGB0_RESERVE88 0x00d4
+#define mmDAGB0_RESERVE88_BASE_IDX 0
+#define mmDAGB0_RESERVE89 0x00d5
+#define mmDAGB0_RESERVE89_BASE_IDX 0
+#define mmDAGB0_RESERVE90 0x00d6
+#define mmDAGB0_RESERVE90_BASE_IDX 0
+#define mmDAGB0_RESERVE91 0x00d7
+#define mmDAGB0_RESERVE91_BASE_IDX 0
+#define mmDAGB0_RESERVE92 0x00d8
+#define mmDAGB0_RESERVE92_BASE_IDX 0
+#define mmDAGB0_RESERVE93 0x00d9
+#define mmDAGB0_RESERVE93_BASE_IDX 0
+#define mmDAGB0_RESERVE94 0x00da
+#define mmDAGB0_RESERVE94_BASE_IDX 0
+#define mmDAGB0_RESERVE95 0x00db
+#define mmDAGB0_RESERVE95_BASE_IDX 0
+#define mmDAGB0_RESERVE96 0x00dc
+#define mmDAGB0_RESERVE96_BASE_IDX 0
+#define mmDAGB0_RESERVE97 0x00dd
+#define mmDAGB0_RESERVE97_BASE_IDX 0
+#define mmDAGB0_RESERVE98 0x00de
+#define mmDAGB0_RESERVE98_BASE_IDX 0
+#define mmDAGB0_RESERVE99 0x00df
+#define mmDAGB0_RESERVE99_BASE_IDX 0
+#define mmDAGB0_RESERVE100 0x00e0
+#define mmDAGB0_RESERVE100_BASE_IDX 0
+#define mmDAGB0_RESERVE101 0x00e1
+#define mmDAGB0_RESERVE101_BASE_IDX 0
+#define mmDAGB0_RESERVE102 0x00e2
+#define mmDAGB0_RESERVE102_BASE_IDX 0
+#define mmDAGB0_RESERVE103 0x00e3
+#define mmDAGB0_RESERVE103_BASE_IDX 0
+#define mmDAGB0_RESERVE104 0x00e4
+#define mmDAGB0_RESERVE104_BASE_IDX 0
+#define mmDAGB0_RESERVE105 0x00e5
+#define mmDAGB0_RESERVE105_BASE_IDX 0
+#define mmDAGB0_RESERVE106 0x00e6
+#define mmDAGB0_RESERVE106_BASE_IDX 0
+#define mmDAGB0_RESERVE107 0x00e7
+#define mmDAGB0_RESERVE107_BASE_IDX 0
+#define mmDAGB0_RESERVE108 0x00e8
+#define mmDAGB0_RESERVE108_BASE_IDX 0
+#define mmDAGB0_RESERVE109 0x00e9
+#define mmDAGB0_RESERVE109_BASE_IDX 0
+#define mmDAGB0_RESERVE110 0x00ea
+#define mmDAGB0_RESERVE110_BASE_IDX 0
+#define mmDAGB0_RESERVE111 0x00eb
+#define mmDAGB0_RESERVE111_BASE_IDX 0
+#define mmDAGB0_RESERVE112 0x00ec
+#define mmDAGB0_RESERVE112_BASE_IDX 0
+#define mmDAGB0_RESERVE113 0x00ed
+#define mmDAGB0_RESERVE113_BASE_IDX 0
+#define mmDAGB0_RESERVE114 0x00ee
+#define mmDAGB0_RESERVE114_BASE_IDX 0
+#define mmDAGB0_RESERVE115 0x00ef
+#define mmDAGB0_RESERVE115_BASE_IDX 0
+#define mmDAGB0_RESERVE116 0x00f0
+#define mmDAGB0_RESERVE116_BASE_IDX 0
+#define mmDAGB0_RESERVE117 0x00f1
+#define mmDAGB0_RESERVE117_BASE_IDX 0
+#define mmDAGB0_RESERVE118 0x00f2
+#define mmDAGB0_RESERVE118_BASE_IDX 0
+#define mmDAGB0_RESERVE119 0x00f3
+#define mmDAGB0_RESERVE119_BASE_IDX 0
+#define mmDAGB0_RESERVE120 0x00f4
+#define mmDAGB0_RESERVE120_BASE_IDX 0
+#define mmDAGB0_RESERVE121 0x00f5
+#define mmDAGB0_RESERVE121_BASE_IDX 0
+#define mmDAGB0_RESERVE122 0x00f6
+#define mmDAGB0_RESERVE122_BASE_IDX 0
+#define mmDAGB0_RESERVE123 0x00f7
+#define mmDAGB0_RESERVE123_BASE_IDX 0
+#define mmDAGB0_RESERVE124 0x00f8
+#define mmDAGB0_RESERVE124_BASE_IDX 0
+#define mmDAGB0_RESERVE125 0x00f9
+#define mmDAGB0_RESERVE125_BASE_IDX 0
+#define mmDAGB0_RESERVE126 0x00fa
+#define mmDAGB0_RESERVE126_BASE_IDX 0
+#define mmDAGB0_RESERVE127 0x00fb
+#define mmDAGB0_RESERVE127_BASE_IDX 0
+#define mmDAGB0_RESERVE128 0x00fc
+#define mmDAGB0_RESERVE128_BASE_IDX 0
+#define mmDAGB0_RESERVE129 0x00fd
+#define mmDAGB0_RESERVE129_BASE_IDX 0
+#define mmDAGB0_RESERVE130 0x00fe
+#define mmDAGB0_RESERVE130_BASE_IDX 0
+#define mmDAGB0_RESERVE131 0x00ff
+#define mmDAGB0_RESERVE131_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmea_mmeadec
+// base address: 0x68400
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104
+#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105
+#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_LAZY 0x0106
+#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_LAZY 0x0107
+#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108
+#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109
+#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0
+#define mmMMEA0_DRAM_PAGE_BURST 0x010a
+#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_AGE 0x010b
+#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_AGE 0x010c
+#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d
+#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e
+#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f
+#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110
+#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111
+#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112
+#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0134
+#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0135
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0136
+#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0137
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0138
+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
+#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0143
+#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
+#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0145
+#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
+#define mmMMEA0_ADDRDEC_BANK_CFG 0x0147
+#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0
+#define mmMMEA0_ADDRDEC_MISC_CFG 0x0148
+#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0149
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x014a
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x014b
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x014c
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x014d
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x014e
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014f
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x0150
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x0151
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0152
+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 0x0153
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 0x0154
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 0x0155
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX 0
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 0x0156
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0165
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0166
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0167
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0168
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0169
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x016a
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x016b
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x016c
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x016d
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x016e
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x016f
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0170
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0171
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0172
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0173
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0174
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0175
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0176
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x0177
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0178
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x0179
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x017a
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x017b
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x017c
+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x017d
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x017e
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x017f
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0180
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0181
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0182
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0183
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0184
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0185
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0186
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0187
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0188
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0189
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x018a
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x018b
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x018c
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x018d
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x018e
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x018f
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0190
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0191
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0192
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0193
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0194
+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
+#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01dd
+#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01de
+#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01df
+#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
+#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01e0
+#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
+#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01e1
+#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0
+#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01e2
+#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0
+#define mmMMEA0_IO_GROUP_BURST 0x01e3
+#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_AGE 0x01e4
+#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_AGE 0x01e5
+#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_QUEUING 0x01e6
+#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_QUEUING 0x01e7
+#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_FIXED 0x01e8
+#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_FIXED 0x01e9
+#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_URGENCY 0x01ea
+#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_URGENCY 0x01eb
+#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x01ec
+#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x01ed
+#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01ee
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01ef
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01f0
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01f1
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01f2
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01f3
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
+#define mmMMEA0_SDP_ARB_DRAM 0x01f4
+#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0
+#define mmMMEA0_SDP_ARB_FINAL 0x01f6
+#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0
+#define mmMMEA0_SDP_DRAM_PRIORITY 0x01f7
+#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0
+#define mmMMEA0_SDP_IO_PRIORITY 0x01f9
+#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0
+#define mmMMEA0_SDP_CREDITS 0x01fa
+#define mmMMEA0_SDP_CREDITS_BASE_IDX 0
+#define mmMMEA0_SDP_TAG_RESERVE0 0x01fb
+#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0
+#define mmMMEA0_SDP_TAG_RESERVE1 0x01fc
+#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0
+#define mmMMEA0_SDP_VCC_RESERVE0 0x01fd
+#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0
+#define mmMMEA0_SDP_VCC_RESERVE1 0x01fe
+#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0
+#define mmMMEA0_SDP_VCD_RESERVE0 0x01ff
+#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0
+#define mmMMEA0_SDP_VCD_RESERVE1 0x0200
+#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0
+#define mmMMEA0_SDP_REQ_CNTL 0x0201
+#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0
+#define mmMMEA0_MISC 0x0202
+#define mmMMEA0_MISC_BASE_IDX 0
+#define mmMMEA0_LATENCY_SAMPLING 0x0203
+#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER_LO 0x0204
+#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER_HI 0x0205
+#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER0_CFG 0x0206
+#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER1_CFG 0x0207
+#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0208
+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define mmMMEA0_EDC_CNT 0x020f
+#define mmMMEA0_EDC_CNT_BASE_IDX 0
+#define mmMMEA0_EDC_CNT2 0x0210
+#define mmMMEA0_EDC_CNT2_BASE_IDX 0
+#define mmMMEA0_DSM_CNTL 0x0211
+#define mmMMEA0_DSM_CNTL_BASE_IDX 0
+#define mmMMEA0_DSM_CNTLA 0x0212
+#define mmMMEA0_DSM_CNTLA_BASE_IDX 0
+#define mmMMEA0_DSM_CNTLB 0x0213
+#define mmMMEA0_DSM_CNTLB_BASE_IDX 0
+#define mmMMEA0_DSM_CNTL2 0x0214
+#define mmMMEA0_DSM_CNTL2_BASE_IDX 0
+#define mmMMEA0_DSM_CNTL2A 0x0215
+#define mmMMEA0_DSM_CNTL2A_BASE_IDX 0
+#define mmMMEA0_DSM_CNTL2B 0x0216
+#define mmMMEA0_DSM_CNTL2B_BASE_IDX 0
+#define mmMMEA0_CGTT_CLK_CTRL 0x0218
+#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmMMEA0_EDC_MODE 0x0219
+#define mmMMEA0_EDC_MODE_BASE_IDX 0
+#define mmMMEA0_ERR_STATUS 0x021a
+#define mmMMEA0_ERR_STATUS_BASE_IDX 0
+#define mmMMEA0_MISC2 0x021b
+#define mmMMEA0_MISC2_BASE_IDX 0
+#define mmMMEA0_ADDRDEC_SELECT 0x021c
+#define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 0
+
+
+// addressBlock: mmhub_pctldec
+// base address: 0x68e00
+#define mmPCTL_MISC 0x0380
+#define mmPCTL_MISC_BASE_IDX 0
+#define mmPCTL_MMHUB_DEEPSLEEP 0x0381
+#define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0
+#define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383
+#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0
+#define mmPCTL_PG_DAGB 0x0384
+#define mmPCTL_PG_DAGB_BASE_IDX 0
+#define mmPCTL0_RENG_RAM_INDEX 0x0385
+#define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0
+#define mmPCTL0_RENG_RAM_DATA 0x0386
+#define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0
+#define mmPCTL0_RENG_EXECUTE 0x0387
+#define mmPCTL0_RENG_EXECUTE_BASE_IDX 0
+#define mmPCTL1_RENG_RAM_INDEX 0x0388
+#define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0
+#define mmPCTL1_RENG_RAM_DATA 0x0389
+#define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0
+#define mmPCTL1_RENG_EXECUTE 0x038a
+#define mmPCTL1_RENG_EXECUTE_BASE_IDX 0
+#define mmPCTL2_RENG_RAM_INDEX 0x038b
+#define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0
+#define mmPCTL2_RENG_RAM_DATA 0x038c
+#define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0
+#define mmPCTL2_RENG_EXECUTE 0x038d
+#define mmPCTL2_RENG_EXECUTE_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x038e
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038f
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x0390
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3 0x0391
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4 0x0392
+#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x0393
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0394
+#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0395
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0396
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0397
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3 0x0398
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4 0x0399
+#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x039a
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039b
+#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039c
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x039d
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x039e
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3 0x039f
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4 0x03a0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x03a1
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a2
+#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
+#define mmPCTL0_MISC 0x03a3
+#define mmPCTL0_MISC_BASE_IDX 0
+#define mmPCTL1_MISC 0x03a4
+#define mmPCTL1_MISC_BASE_IDX 0
+#define mmPCTL2_MISC 0x03a5
+#define mmPCTL2_MISC_BASE_IDX 0
+#define mmPCTL_PERFCOUNTER_LO 0x03a6
+#define mmPCTL_PERFCOUNTER_LO_BASE_IDX 0
+#define mmPCTL_PERFCOUNTER_HI 0x03a7
+#define mmPCTL_PERFCOUNTER_HI_BASE_IDX 0
+#define mmPCTL_PERFCOUNTER0_CFG 0x03a8
+#define mmPCTL_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmPCTL_PERFCOUNTER1_CFG 0x03a9
+#define mmPCTL_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmPCTL_PERFCOUNTER_RSLT_CNTL 0x03aa
+#define mmPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_l1tlb_mmvml1pfdec
+// base address: 0x69600
+#define mmMMMC_VM_MX_L1_TLB0_STATUS 0x0588
+#define mmMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_TLB1_STATUS 0x0589
+#define mmMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_TLB2_STATUS 0x058a
+#define mmMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_TLB3_STATUS 0x058b
+#define mmMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_TLB4_STATUS 0x058c
+#define mmMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_TLB5_STATUS 0x058d
+#define mmMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_TLB6_STATUS 0x058e
+#define mmMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_TLB7_STATUS 0x058f
+#define mmMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0
+
+
+// addressBlock: mmhub_l1tlb_mmvml1pldec
+// base address: 0x69650
+#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594
+#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595
+#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596
+#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597
+#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_l1tlb_mmvml1prdec
+// base address: 0x69670
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO 0x059c
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI 0x059d
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+// base address: 0x69900
+#define mmMM_ATC_L2_CNTL 0x0640
+#define mmMM_ATC_L2_CNTL_BASE_IDX 0
+#define mmMM_ATC_L2_CNTL2 0x0641
+#define mmMM_ATC_L2_CNTL2_BASE_IDX 0
+#define mmMM_ATC_L2_CACHE_DATA0 0x0644
+#define mmMM_ATC_L2_CACHE_DATA0_BASE_IDX 0
+#define mmMM_ATC_L2_CACHE_DATA1 0x0645
+#define mmMM_ATC_L2_CACHE_DATA1_BASE_IDX 0
+#define mmMM_ATC_L2_CACHE_DATA2 0x0646
+#define mmMM_ATC_L2_CACHE_DATA2_BASE_IDX 0
+#define mmMM_ATC_L2_CNTL3 0x0647
+#define mmMM_ATC_L2_CNTL3_BASE_IDX 0
+#define mmMM_ATC_L2_STATUS 0x0648
+#define mmMM_ATC_L2_STATUS_BASE_IDX 0
+#define mmMM_ATC_L2_STATUS2 0x0649
+#define mmMM_ATC_L2_STATUS2_BASE_IDX 0
+#define mmMM_ATC_L2_MISC_CG 0x064a
+#define mmMM_ATC_L2_MISC_CG_BASE_IDX 0
+#define mmMM_ATC_L2_MEM_POWER_LS 0x064b
+#define mmMM_ATC_L2_MEM_POWER_LS_BASE_IDX 0
+#define mmMM_ATC_L2_CGTT_CLK_CTRL 0x064c
+#define mmMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmMM_ATC_L2_SDPPORT_CTRL 0x064d
+#define mmMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+// base address: 0x69a00
+#define mmMMVM_L2_CNTL 0x0680
+#define mmMMVM_L2_CNTL_BASE_IDX 0
+#define mmMMVM_L2_CNTL2 0x0681
+#define mmMMVM_L2_CNTL2_BASE_IDX 0
+#define mmMMVM_L2_CNTL3 0x0682
+#define mmMMVM_L2_CNTL3_BASE_IDX 0
+#define mmMMVM_L2_STATUS 0x0683
+#define mmMMVM_L2_STATUS_BASE_IDX 0
+#define mmMMVM_DUMMY_PAGE_FAULT_CNTL 0x0684
+#define mmMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_CNTL 0x0687
+#define mmMMVM_INVALIDATE_CNTL_BASE_IDX 0
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL 0x0688
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL2 0x0689
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x068a
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068b
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
+#define mmMMVM_L2_PROTECTION_FAULT_STATUS 0x068c
+#define mmMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068d
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068e
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068f
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0690
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0692
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0693
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0694
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0695
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0696
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0697
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
+#define mmMMVM_L2_CNTL4 0x0698
+#define mmMMVM_L2_CNTL4_BASE_IDX 0
+#define mmMMVM_L2_MM_GROUP_RT_CLASSES 0x0699
+#define mmMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID 0x069a
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2 0x069b
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
+#define mmMMVM_L2_CACHE_PARITY_CNTL 0x069c
+#define mmMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
+#define mmMMVM_L2_IH_LOG_CNTL 0x069d
+#define mmMMVM_L2_IH_LOG_CNTL_BASE_IDX 0
+#define mmMMVM_L2_IH_LOG_BUSY 0x069e
+#define mmMMVM_L2_IH_LOG_BUSY_BASE_IDX 0
+#define mmMMVM_L2_CGTT_CLK_CTRL 0x069f
+#define mmMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmMMVM_L2_CNTL5 0x06a1
+#define mmMMVM_L2_CNTL5_BASE_IDX 0
+#define mmMMVM_L2_GCR_CNTL 0x06a2
+#define mmMMVM_L2_GCR_CNTL_BASE_IDX 0
+#define mmMMVML2_WALKER_MACRO_THROTTLE_TIME 0x06a3
+#define mmMMVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0
+#define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x06a4
+#define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0
+#define mmMMVML2_WALKER_MICRO_THROTTLE_TIME 0x06a5
+#define mmMMVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0
+#define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x06a6
+#define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+// base address: 0x69b00
+#define mmMMVM_CONTEXT0_CNTL 0x06c0
+#define mmMMVM_CONTEXT0_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT1_CNTL 0x06c1
+#define mmMMVM_CONTEXT1_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT2_CNTL 0x06c2
+#define mmMMVM_CONTEXT2_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT3_CNTL 0x06c3
+#define mmMMVM_CONTEXT3_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT4_CNTL 0x06c4
+#define mmMMVM_CONTEXT4_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT5_CNTL 0x06c5
+#define mmMMVM_CONTEXT5_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT6_CNTL 0x06c6
+#define mmMMVM_CONTEXT6_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT7_CNTL 0x06c7
+#define mmMMVM_CONTEXT7_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT8_CNTL 0x06c8
+#define mmMMVM_CONTEXT8_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT9_CNTL 0x06c9
+#define mmMMVM_CONTEXT9_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT10_CNTL 0x06ca
+#define mmMMVM_CONTEXT10_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT11_CNTL 0x06cb
+#define mmMMVM_CONTEXT11_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT12_CNTL 0x06cc
+#define mmMMVM_CONTEXT12_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT13_CNTL 0x06cd
+#define mmMMVM_CONTEXT13_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT14_CNTL 0x06ce
+#define mmMMVM_CONTEXT14_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXT15_CNTL 0x06cf
+#define mmMMVM_CONTEXT15_CNTL_BASE_IDX 0
+#define mmMMVM_CONTEXTS_DISABLE 0x06d0
+#define mmMMVM_CONTEXTS_DISABLE_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG0_SEM 0x06d1
+#define mmMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG1_SEM 0x06d2
+#define mmMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG2_SEM 0x06d3
+#define mmMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG3_SEM 0x06d4
+#define mmMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG4_SEM 0x06d5
+#define mmMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG5_SEM 0x06d6
+#define mmMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG6_SEM 0x06d7
+#define mmMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG7_SEM 0x06d8
+#define mmMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG8_SEM 0x06d9
+#define mmMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG9_SEM 0x06da
+#define mmMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG10_SEM 0x06db
+#define mmMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG11_SEM 0x06dc
+#define mmMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG12_SEM 0x06dd
+#define mmMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG13_SEM 0x06de
+#define mmMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG14_SEM 0x06df
+#define mmMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG15_SEM 0x06e0
+#define mmMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG16_SEM 0x06e1
+#define mmMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG17_SEM 0x06e2
+#define mmMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG0_REQ 0x06e3
+#define mmMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG1_REQ 0x06e4
+#define mmMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG2_REQ 0x06e5
+#define mmMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG3_REQ 0x06e6
+#define mmMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG4_REQ 0x06e7
+#define mmMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG5_REQ 0x06e8
+#define mmMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG6_REQ 0x06e9
+#define mmMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG7_REQ 0x06ea
+#define mmMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG8_REQ 0x06eb
+#define mmMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG9_REQ 0x06ec
+#define mmMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG10_REQ 0x06ed
+#define mmMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG11_REQ 0x06ee
+#define mmMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG12_REQ 0x06ef
+#define mmMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG13_REQ 0x06f0
+#define mmMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG14_REQ 0x06f1
+#define mmMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG15_REQ 0x06f2
+#define mmMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG16_REQ 0x06f3
+#define mmMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG17_REQ 0x06f4
+#define mmMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG0_ACK 0x06f5
+#define mmMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG1_ACK 0x06f6
+#define mmMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG2_ACK 0x06f7
+#define mmMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG3_ACK 0x06f8
+#define mmMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG4_ACK 0x06f9
+#define mmMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG5_ACK 0x06fa
+#define mmMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG6_ACK 0x06fb
+#define mmMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG7_ACK 0x06fc
+#define mmMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG8_ACK 0x06fd
+#define mmMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG9_ACK 0x06fe
+#define mmMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG10_ACK 0x06ff
+#define mmMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG11_ACK 0x0700
+#define mmMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG12_ACK 0x0701
+#define mmMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG13_ACK 0x0702
+#define mmMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG14_ACK 0x0703
+#define mmMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG15_ACK 0x0704
+#define mmMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG16_ACK 0x0705
+#define mmMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG17_ACK 0x0706
+#define mmMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+// base address: 0x69e90
+#define mmMMMC_VM_L2_PERFCOUNTER0_CFG 0x07a4
+#define mmMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmMMMC_VM_L2_PERFCOUNTER1_CFG 0x07a5
+#define mmMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmMMMC_VM_L2_PERFCOUNTER2_CFG 0x07a6
+#define mmMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0
+#define mmMMMC_VM_L2_PERFCOUNTER3_CFG 0x07a7
+#define mmMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0
+#define mmMMMC_VM_L2_PERFCOUNTER4_CFG 0x07a8
+#define mmMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0
+#define mmMMMC_VM_L2_PERFCOUNTER5_CFG 0x07a9
+#define mmMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0
+#define mmMMMC_VM_L2_PERFCOUNTER6_CFG 0x07aa
+#define mmMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0
+#define mmMMMC_VM_L2_PERFCOUNTER7_CFG 0x07ab
+#define mmMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0
+#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac
+#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+// base address: 0x69ee0
+#define mmMMMC_VM_L2_PERFCOUNTER_LO 0x07b8
+#define mmMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0
+#define mmMMMC_VM_L2_PERFCOUNTER_HI 0x07b9
+#define mmMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+// base address: 0x69f30
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF0 0x07cc
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF1 0x07cd
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF2 0x07ce
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF3 0x07cf
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF4 0x07d0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF5 0x07d1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF6 0x07d2
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF7 0x07d3
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF8 0x07d4
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF9 0x07d5
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF10 0x07d6
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF11 0x07d7
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF12 0x07d8
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF13 0x07d9
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF14 0x07da
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF15 0x07db
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF16 0x07dc
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF17 0x07dd
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF18 0x07de
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF19 0x07df
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF20 0x07e0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF21 0x07e1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF22 0x07e2
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF23 0x07e3
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF24 0x07e4
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF25 0x07e5
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF26 0x07e6
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF27 0x07e7
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF28 0x07e8
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF29 0x07e9
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF30 0x07ea
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX 0
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF31 0x07eb
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX 0
+#define mmMMVM_IOMMU_MMIO_CNTRL_1 0x07ec
+#define mmMMVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0
+#define mmMMMC_VM_MARC_BASE_LO_0 0x07ed
+#define mmMMMC_VM_MARC_BASE_LO_0_BASE_IDX 0
+#define mmMMMC_VM_MARC_BASE_LO_1 0x07ee
+#define mmMMMC_VM_MARC_BASE_LO_1_BASE_IDX 0
+#define mmMMMC_VM_MARC_BASE_LO_2 0x07ef
+#define mmMMMC_VM_MARC_BASE_LO_2_BASE_IDX 0
+#define mmMMMC_VM_MARC_BASE_LO_3 0x07f0
+#define mmMMMC_VM_MARC_BASE_LO_3_BASE_IDX 0
+#define mmMMMC_VM_MARC_BASE_HI_0 0x07f1
+#define mmMMMC_VM_MARC_BASE_HI_0_BASE_IDX 0
+#define mmMMMC_VM_MARC_BASE_HI_1 0x07f2
+#define mmMMMC_VM_MARC_BASE_HI_1_BASE_IDX 0
+#define mmMMMC_VM_MARC_BASE_HI_2 0x07f3
+#define mmMMMC_VM_MARC_BASE_HI_2_BASE_IDX 0
+#define mmMMMC_VM_MARC_BASE_HI_3 0x07f4
+#define mmMMMC_VM_MARC_BASE_HI_3_BASE_IDX 0
+#define mmMMMC_VM_MARC_RELOC_LO_0 0x07f5
+#define mmMMMC_VM_MARC_RELOC_LO_0_BASE_IDX 0
+#define mmMMMC_VM_MARC_RELOC_LO_1 0x07f6
+#define mmMMMC_VM_MARC_RELOC_LO_1_BASE_IDX 0
+#define mmMMMC_VM_MARC_RELOC_LO_2 0x07f7
+#define mmMMMC_VM_MARC_RELOC_LO_2_BASE_IDX 0
+#define mmMMMC_VM_MARC_RELOC_LO_3 0x07f8
+#define mmMMMC_VM_MARC_RELOC_LO_3_BASE_IDX 0
+#define mmMMMC_VM_MARC_RELOC_HI_0 0x07f9
+#define mmMMMC_VM_MARC_RELOC_HI_0_BASE_IDX 0
+#define mmMMMC_VM_MARC_RELOC_HI_1 0x07fa
+#define mmMMMC_VM_MARC_RELOC_HI_1_BASE_IDX 0
+#define mmMMMC_VM_MARC_RELOC_HI_2 0x07fb
+#define mmMMMC_VM_MARC_RELOC_HI_2_BASE_IDX 0
+#define mmMMMC_VM_MARC_RELOC_HI_3 0x07fc
+#define mmMMMC_VM_MARC_RELOC_HI_3_BASE_IDX 0
+#define mmMMMC_VM_MARC_LEN_LO_0 0x07fd
+#define mmMMMC_VM_MARC_LEN_LO_0_BASE_IDX 0
+#define mmMMMC_VM_MARC_LEN_LO_1 0x07fe
+#define mmMMMC_VM_MARC_LEN_LO_1_BASE_IDX 0
+#define mmMMMC_VM_MARC_LEN_LO_2 0x07ff
+#define mmMMMC_VM_MARC_LEN_LO_2_BASE_IDX 0
+#define mmMMMC_VM_MARC_LEN_LO_3 0x0800
+#define mmMMMC_VM_MARC_LEN_LO_3_BASE_IDX 0
+#define mmMMMC_VM_MARC_LEN_HI_0 0x0801
+#define mmMMMC_VM_MARC_LEN_HI_0_BASE_IDX 0
+#define mmMMMC_VM_MARC_LEN_HI_1 0x0802
+#define mmMMMC_VM_MARC_LEN_HI_1_BASE_IDX 0
+#define mmMMMC_VM_MARC_LEN_HI_2 0x0803
+#define mmMMMC_VM_MARC_LEN_HI_2_BASE_IDX 0
+#define mmMMMC_VM_MARC_LEN_HI_3 0x0804
+#define mmMMMC_VM_MARC_LEN_HI_3_BASE_IDX 0
+#define mmMMVM_IOMMU_CONTROL_REGISTER 0x0805
+#define mmMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0
+#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0806
+#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL 0x0807
+#define mmMMVM_PCIE_ATS_CNTL_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_0 0x0808
+#define mmMMVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_1 0x0809
+#define mmMMVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_2 0x080a
+#define mmMMVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_3 0x080b
+#define mmMMVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_4 0x080c
+#define mmMMVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_5 0x080d
+#define mmMMVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_6 0x080e
+#define mmMMVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_7 0x080f
+#define mmMMVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_8 0x0810
+#define mmMMVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_9 0x0811
+#define mmMMVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_10 0x0812
+#define mmMMVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_11 0x0813
+#define mmMMVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_12 0x0814
+#define mmMMVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_13 0x0815
+#define mmMMVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_14 0x0816
+#define mmMMVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_15 0x0817
+#define mmMMVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_16 0x0818
+#define mmMMVM_PCIE_ATS_CNTL_VF_16_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_17 0x0819
+#define mmMMVM_PCIE_ATS_CNTL_VF_17_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_18 0x081a
+#define mmMMVM_PCIE_ATS_CNTL_VF_18_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_19 0x081b
+#define mmMMVM_PCIE_ATS_CNTL_VF_19_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_20 0x081c
+#define mmMMVM_PCIE_ATS_CNTL_VF_20_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_21 0x081d
+#define mmMMVM_PCIE_ATS_CNTL_VF_21_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_22 0x081e
+#define mmMMVM_PCIE_ATS_CNTL_VF_22_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_23 0x081f
+#define mmMMVM_PCIE_ATS_CNTL_VF_23_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_24 0x0820
+#define mmMMVM_PCIE_ATS_CNTL_VF_24_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_25 0x0821
+#define mmMMVM_PCIE_ATS_CNTL_VF_25_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_26 0x0822
+#define mmMMVM_PCIE_ATS_CNTL_VF_26_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_27 0x0823
+#define mmMMVM_PCIE_ATS_CNTL_VF_27_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_28 0x0824
+#define mmMMVM_PCIE_ATS_CNTL_VF_28_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_29 0x0825
+#define mmMMVM_PCIE_ATS_CNTL_VF_29_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_30 0x0826
+#define mmMMVM_PCIE_ATS_CNTL_VF_30_BASE_IDX 0
+#define mmMMVM_PCIE_ATS_CNTL_VF_31 0x0827
+#define mmMMVM_PCIE_ATS_CNTL_VF_31_BASE_IDX 0
+#define mmMMUTCL2_CGTT_CLK_CTRL 0x0828
+#define mmMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 0
+#define mmMMMC_SHARED_ACTIVE_FCN_ID 0x0829
+#define mmMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+// base address: 0x6a140
+#define mmMMMC_VM_NB_MMIOBASE 0x0850
+#define mmMMMC_VM_NB_MMIOBASE_BASE_IDX 0
+#define mmMMMC_VM_NB_MMIOLIMIT 0x0851
+#define mmMMMC_VM_NB_MMIOLIMIT_BASE_IDX 0
+#define mmMMMC_VM_NB_PCI_CTRL 0x0852
+#define mmMMMC_VM_NB_PCI_CTRL_BASE_IDX 0
+#define mmMMMC_VM_NB_PCI_ARB 0x0853
+#define mmMMMC_VM_NB_PCI_ARB_BASE_IDX 0
+#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0854
+#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0
+#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0855
+#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0
+#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0856
+#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0
+#define mmMMMC_VM_FB_OFFSET 0x0857
+#define mmMMMC_VM_FB_OFFSET_BASE_IDX 0
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0858
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0859
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
+#define mmMMMC_VM_STEERING 0x085a
+#define mmMMMC_VM_STEERING_BASE_IDX 0
+#define mmMMMC_SHARED_VIRT_RESET_REQ 0x085b
+#define mmMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
+#define mmMMMC_MEM_POWER_LS 0x085c
+#define mmMMMC_MEM_POWER_LS_BASE_IDX 0
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x085d
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x085e
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
+#define mmMMMC_VM_APT_CNTL 0x085f
+#define mmMMMC_VM_APT_CNTL_BASE_IDX 0
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0860
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START 0x0861
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END 0x0862
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
+#define mmMMMC_SHARED_VIRT_RESET_REQ2 0x0863
+#define mmMMMC_SHARED_VIRT_RESET_REQ2_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+// base address: 0x6a1b0
+#define mmMMMC_VM_FB_LOCATION_BASE 0x086c
+#define mmMMMC_VM_FB_LOCATION_BASE_BASE_IDX 0
+#define mmMMMC_VM_FB_LOCATION_TOP 0x086d
+#define mmMMMC_VM_FB_LOCATION_TOP_BASE_IDX 0
+#define mmMMMC_VM_AGP_TOP 0x086e
+#define mmMMMC_VM_AGP_TOP_BASE_IDX 0
+#define mmMMMC_VM_AGP_BOT 0x086f
+#define mmMMMC_VM_AGP_BOT_BASE_IDX 0
+#define mmMMMC_VM_AGP_BASE 0x0870
+#define mmMMMC_VM_AGP_BASE_BASE_IDX 0
+#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0871
+#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
+#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0872
+#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
+#define mmMMMC_VM_MX_L1_TLB_CNTL 0x0873
+#define mmMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+// base address: 0x6a200
+#define mmMM_ATC_L2_PERFCOUNTER_LO 0x0880
+#define mmMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 0
+#define mmMM_ATC_L2_PERFCOUNTER_HI 0x0881
+#define mmMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 0
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+// base address: 0x6a220
+#define mmMM_ATC_L2_PERFCOUNTER0_CFG 0x0888
+#define mmMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0
+#define mmMM_ATC_L2_PERFCOUNTER1_CFG 0x0889
+#define mmMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0
+#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x088a
+#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h
new file mode 100644
index 000000000000..0a0a889cc405
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h
@@ -0,0 +1,7567 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mmhub_2_0_0_SH_MASK_HEADER
+#define _mmhub_2_0_0_SH_MASK_HEADER
+
+
+// addressBlock: mmhub_dagbdec
+//DAGB0_RDCLI0
+#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI1
+#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI2
+#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI3
+#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI4
+#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI5
+#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI6
+#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI7
+#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI8
+#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI9
+#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI10
+#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI11
+#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI12
+#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI13
+#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI14
+#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI15
+#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI16
+#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI17
+#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RDCLI18
+#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4
+#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8
+#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd
+#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16
+#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a
+#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L
+#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L
+#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L
+#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L
+//DAGB0_RD_CNTL
+#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+//DAGB0_RD_GMI_CNTL
+#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB0_RD_ADDR_DAGB
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB0_RD_CGTT_CLK_CTRL
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST2
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
+//DAGB0_RD_VC0_CNTL
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC1_CNTL
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC2_CNTL
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC3_CNTL
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC4_CNTL
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC5_CNTL
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC6_CNTL
+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_VC7_CNTL
+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_RD_CNTL_MISC
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB0_RD_CNTL_MISC__HDP_CID__SHIFT 0x1a
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB0_RD_CNTL_MISC__HDP_CID_MASK 0x7C000000L
+//DAGB0_RD_TLB_CREDIT
+#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB0_RDCLI_ASK_PENDING
+#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_GO_PENDING
+#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_GBLSEND_PENDING
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_TLB_PENDING
+#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_OARB_PENDING
+#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_RDCLI_OSD_PENDING
+#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI0
+#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI1
+#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI2
+#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI3
+#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI4
+#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI5
+#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI6
+#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI7
+#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI8
+#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI9
+#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI10
+#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI11
+#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI12
+#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI13
+#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI14
+#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI15
+#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI16
+#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI17
+#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WRCLI18
+#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0
+#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3
+#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4
+#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8
+#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc
+#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd
+#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15
+#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16
+#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19
+#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a
+#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L
+#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L
+#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L
+#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L
+#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L
+#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L
+#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L
+#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L
+#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L
+#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L
+//DAGB0_WR_CNTL
+#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
+#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11
+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
+#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
+#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
+#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
+#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
+//DAGB0_WR_GMI_CNTL
+#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
+#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6
+#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
+#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
+#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
+//DAGB0_WR_ADDR_DAGB
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
+//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
+//DAGB0_WR_CGTT_CLK_CTRL
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST2
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
+#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
+#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
+//DAGB0_WR_DATA_DAGB_MAX_BURST0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST1
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST2
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER2
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L
+//DAGB0_WR_VC0_CNTL
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC1_CNTL
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC2_CNTL
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC3_CNTL
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC4_CNTL
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC5_CNTL
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC6_CNTL
+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_VC7_CNTL
+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
+#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
+#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
+#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
+#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
+#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
+#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
+#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
+#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
+//DAGB0_WR_CNTL_MISC
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
+#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
+#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x1a
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
+#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
+#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x7C000000L
+//DAGB0_WR_TLB_CREDIT
+#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0
+#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5
+#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
+#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf
+#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14
+#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19
+#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
+#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
+#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
+#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
+#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
+#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
+//DAGB0_WR_DATA_CREDIT
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
+//DAGB0_WR_MISC_CREDIT
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
+//DAGB0_WRCLI_ASK_PENDING
+#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GO_PENDING
+#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GBLSEND_PENDING
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_TLB_PENDING
+#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_OARB_PENDING
+#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_OSD_PENDING
+#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_ASK_PENDING
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_GO_PENDING
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
+//DAGB0_DAGB_DLY
+#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0
+#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8
+#define DAGB0_DAGB_DLY__POS__SHIFT 0x10
+#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL
+#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L
+#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L
+//DAGB0_CNTL_MISC
+#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
+#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
+#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
+#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
+#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
+#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
+#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
+#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
+#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
+#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
+#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
+#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
+#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
+#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
+#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
+#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
+//DAGB0_CNTL_MISC2
+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
+#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
+#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0xb
+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
+#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
+#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000800L
+//DAGB0_FIFO_EMPTY
+#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0
+#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
+//DAGB0_FIFO_FULL
+#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0
+#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL
+//DAGB0_WR_CREDITS_FULL
+#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL
+//DAGB0_RD_CREDITS_FULL
+#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0
+#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
+//DAGB0_PERFCOUNTER_LO
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//DAGB0_PERFCOUNTER_HI
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//DAGB0_PERFCOUNTER0_CFG
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER1_CFG
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER2_CFG
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//DAGB0_PERFCOUNTER_RSLT_CNTL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//DAGB0_RESERVE0
+#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE1
+#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE2
+#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE3
+#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE4
+#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE5
+#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE6
+#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE7
+#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE8
+#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE9
+#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE10
+#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE11
+#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE12
+#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE13
+#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE14
+#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE15
+#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE16
+#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE17
+#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE18
+#define DAGB0_RESERVE18__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE19
+#define DAGB0_RESERVE19__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE20
+#define DAGB0_RESERVE20__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE21
+#define DAGB0_RESERVE21__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE22
+#define DAGB0_RESERVE22__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE23
+#define DAGB0_RESERVE23__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE24
+#define DAGB0_RESERVE24__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE25
+#define DAGB0_RESERVE25__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE26
+#define DAGB0_RESERVE26__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE27
+#define DAGB0_RESERVE27__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE28
+#define DAGB0_RESERVE28__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE29
+#define DAGB0_RESERVE29__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE30
+#define DAGB0_RESERVE30__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE31
+#define DAGB0_RESERVE31__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE32
+#define DAGB0_RESERVE32__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE33
+#define DAGB0_RESERVE33__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE34
+#define DAGB0_RESERVE34__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE35
+#define DAGB0_RESERVE35__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE36
+#define DAGB0_RESERVE36__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE37
+#define DAGB0_RESERVE37__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE38
+#define DAGB0_RESERVE38__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE39
+#define DAGB0_RESERVE39__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE40
+#define DAGB0_RESERVE40__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE41
+#define DAGB0_RESERVE41__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE42
+#define DAGB0_RESERVE42__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE43
+#define DAGB0_RESERVE43__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE44
+#define DAGB0_RESERVE44__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE45
+#define DAGB0_RESERVE45__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE46
+#define DAGB0_RESERVE46__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE47
+#define DAGB0_RESERVE47__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE48
+#define DAGB0_RESERVE48__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE49
+#define DAGB0_RESERVE49__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE50
+#define DAGB0_RESERVE50__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE51
+#define DAGB0_RESERVE51__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE52
+#define DAGB0_RESERVE52__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE53
+#define DAGB0_RESERVE53__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE54
+#define DAGB0_RESERVE54__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE55
+#define DAGB0_RESERVE55__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE56
+#define DAGB0_RESERVE56__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE57
+#define DAGB0_RESERVE57__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE58
+#define DAGB0_RESERVE58__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE59
+#define DAGB0_RESERVE59__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE60
+#define DAGB0_RESERVE60__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE61
+#define DAGB0_RESERVE61__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE62
+#define DAGB0_RESERVE62__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE63
+#define DAGB0_RESERVE63__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE64
+#define DAGB0_RESERVE64__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE65
+#define DAGB0_RESERVE65__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE66
+#define DAGB0_RESERVE66__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE67
+#define DAGB0_RESERVE67__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE68
+#define DAGB0_RESERVE68__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE69
+#define DAGB0_RESERVE69__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE70
+#define DAGB0_RESERVE70__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE71
+#define DAGB0_RESERVE71__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE72
+#define DAGB0_RESERVE72__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE73
+#define DAGB0_RESERVE73__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE74
+#define DAGB0_RESERVE74__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE75
+#define DAGB0_RESERVE75__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE76
+#define DAGB0_RESERVE76__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE77
+#define DAGB0_RESERVE77__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE78
+#define DAGB0_RESERVE78__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE79
+#define DAGB0_RESERVE79__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE80
+#define DAGB0_RESERVE80__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE81
+#define DAGB0_RESERVE81__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE82
+#define DAGB0_RESERVE82__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE83
+#define DAGB0_RESERVE83__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE84
+#define DAGB0_RESERVE84__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE85
+#define DAGB0_RESERVE85__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE86
+#define DAGB0_RESERVE86__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE87
+#define DAGB0_RESERVE87__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE88
+#define DAGB0_RESERVE88__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE89
+#define DAGB0_RESERVE89__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE90
+#define DAGB0_RESERVE90__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE91
+#define DAGB0_RESERVE91__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE92
+#define DAGB0_RESERVE92__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE93
+#define DAGB0_RESERVE93__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE94
+#define DAGB0_RESERVE94__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE95
+#define DAGB0_RESERVE95__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE96
+#define DAGB0_RESERVE96__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE97
+#define DAGB0_RESERVE97__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE98
+#define DAGB0_RESERVE98__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE99
+#define DAGB0_RESERVE99__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE100
+#define DAGB0_RESERVE100__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE101
+#define DAGB0_RESERVE101__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE102
+#define DAGB0_RESERVE102__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE102__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE103
+#define DAGB0_RESERVE103__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE103__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE104
+#define DAGB0_RESERVE104__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE104__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE105
+#define DAGB0_RESERVE105__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE105__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE106
+#define DAGB0_RESERVE106__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE106__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE107
+#define DAGB0_RESERVE107__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE107__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE108
+#define DAGB0_RESERVE108__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE108__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE109
+#define DAGB0_RESERVE109__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE109__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE110
+#define DAGB0_RESERVE110__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE110__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE111
+#define DAGB0_RESERVE111__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE111__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE112
+#define DAGB0_RESERVE112__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE112__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE113
+#define DAGB0_RESERVE113__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE113__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE114
+#define DAGB0_RESERVE114__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE114__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE115
+#define DAGB0_RESERVE115__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE115__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE116
+#define DAGB0_RESERVE116__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE116__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE117
+#define DAGB0_RESERVE117__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE117__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE118
+#define DAGB0_RESERVE118__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE118__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE119
+#define DAGB0_RESERVE119__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE119__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE120
+#define DAGB0_RESERVE120__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE120__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE121
+#define DAGB0_RESERVE121__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE121__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE122
+#define DAGB0_RESERVE122__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE122__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE123
+#define DAGB0_RESERVE123__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE123__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE124
+#define DAGB0_RESERVE124__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE124__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE125
+#define DAGB0_RESERVE125__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE125__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE126
+#define DAGB0_RESERVE126__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE126__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE127
+#define DAGB0_RESERVE127__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE127__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE128
+#define DAGB0_RESERVE128__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE128__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE129
+#define DAGB0_RESERVE129__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE129__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE130
+#define DAGB0_RESERVE130__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE130__RESERVE_MASK 0xFFFFFFFFL
+//DAGB0_RESERVE131
+#define DAGB0_RESERVE131__RESERVE__SHIFT 0x0
+#define DAGB0_RESERVE131__RESERVE_MASK 0xFFFFFFFFL
+
+
+// addressBlock: mmhub_mmea_mmeadec
+//MMEA0_DRAM_RD_CLI2GRP_MAP0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_RD_CLI2GRP_MAP1
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_WR_CLI2GRP_MAP0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_WR_CLI2GRP_MAP1
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_DRAM_RD_GRP2VC_MAP
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA0_DRAM_WR_GRP2VC_MAP
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
+//MMEA0_DRAM_RD_LAZY
+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA0_DRAM_WR_LAZY
+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b
+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L
+//MMEA0_DRAM_RD_CAM_CNTL
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA0_DRAM_WR_CAM_CNTL
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
+#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L
+//MMEA0_DRAM_PAGE_BURST
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA0_DRAM_RD_PRI_AGE
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_DRAM_WR_PRI_AGE
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_DRAM_RD_PRI_QUEUING
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_WR_PRI_QUEUING
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_RD_PRI_FIXED
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_WR_PRI_FIXED
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_DRAM_RD_PRI_URGENCY
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_DRAM_WR_PRI_URGENCY
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_ADDRNORM_BASE_ADDR0
+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR0
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_BASE_ADDR1
+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9
+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L
+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR1
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
+//MMEA0_ADDRNORM_OFFSET_ADDR1
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
+//MMEA0_ADDRNORMDRAM_HOLE_CNTL
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
+//MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L
+//MMEA0_ADDRDEC_BANK_CFG
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
+//MMEA0_ADDRDEC_MISC_CFG
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_PC
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
+//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
+//MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT 0x1c
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK 0x000FFFFFL
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK 0xF0000000L
+//MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK 0x000FFFFFL
+//MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT 0x1c
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK 0x000FFFFFL
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK 0xF0000000L
+//MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT 0x0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK 0x000FFFFFL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC0_RM_SEL_CS01
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC0_RM_SEL_CS23
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC0_RM_SEL_SECCS01
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC0_RM_SEL_SECCS23
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
+//MMEA0_ADDRDEC1_RM_SEL_CS01
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_RM_SEL_CS23
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_RM_SEL_SECCS01
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_ADDRDEC1_RM_SEL_SECCS23
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
+//MMEA0_IO_RD_CLI2GRP_MAP0
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_IO_RD_CLI2GRP_MAP1
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_IO_WR_CLI2GRP_MAP0
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
+//MMEA0_IO_WR_CLI2GRP_MAP1
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
+//MMEA0_IO_RD_COMBINE_FLUSH
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+//MMEA0_IO_WR_COMBINE_FLUSH
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
+//MMEA0_IO_GROUP_BURST
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
+//MMEA0_IO_RD_PRI_AGE
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_IO_WR_PRI_AGE
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
+//MMEA0_IO_RD_PRI_QUEUING
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_WR_PRI_QUEUING
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_RD_PRI_FIXED
+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_WR_PRI_FIXED
+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
+//MMEA0_IO_RD_PRI_URGENCY
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_IO_WR_PRI_URGENCY
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
+//MMEA0_IO_RD_PRI_URGENCY_MASKING
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA0_IO_WR_PRI_URGENCY_MASKING
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI1
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI2
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI3
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI1
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI2
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI3
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
+//MMEA0_SDP_ARB_DRAM
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
+#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
+#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L
+//MMEA0_SDP_ARB_FINAL
+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+//MMEA0_SDP_DRAM_PRIORITY
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA0_SDP_IO_PRIORITY
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
+//MMEA0_SDP_CREDITS
+#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
+#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
+//MMEA0_SDP_TAG_RESERVE0
+#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
+#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
+#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
+#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
+#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
+#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
+#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
+#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
+//MMEA0_SDP_TAG_RESERVE1
+#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
+#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
+#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
+#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
+#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
+#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
+#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
+#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
+//MMEA0_SDP_VCC_RESERVE0
+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA0_SDP_VCC_RESERVE1
+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA0_SDP_VCD_RESERVE0
+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
+//MMEA0_SDP_VCD_RESERVE1
+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
+//MMEA0_SDP_REQ_CNTL
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
+//MMEA0_MISC
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
+#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
+#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
+//MMEA0_LATENCY_SAMPLING
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
+//MMEA0_PERFCOUNTER_LO
+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMEA0_PERFCOUNTER_HI
+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//MMEA0_PERFCOUNTER0_CFG
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMEA0_PERFCOUNTER1_CFG
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMEA0_PERFCOUNTER_RSLT_CNTL
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+//MMEA0_EDC_CNT
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
+//MMEA0_EDC_CNT2
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+//MMEA0_DSM_CNTL
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
+//MMEA0_DSM_CNTLA
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
+//MMEA0_DSM_CNTL2
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
+#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
+#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
+//MMEA0_DSM_CNTL2A
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
+//MMEA0_CGTT_CLK_CTRL
+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
+#define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17
+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
+#define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L
+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
+//MMEA0_EDC_MODE
+#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11
+#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14
+#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f
+#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L
+#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L
+#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L
+#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L
+//MMEA0_ERR_STATUS
+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+//MMEA0_MISC2
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
+#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
+#define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
+#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
+#define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L
+//MMEA0_ADDRDEC_SELECT
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf
+#define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT 0x14
+#define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT 0x15
+#define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT 0x16
+#define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT 0x17
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L
+#define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK 0x00100000L
+#define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK 0x00200000L
+#define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK 0x00400000L
+#define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK 0x00800000L
+
+
+// addressBlock: mmhub_pctldec
+//PCTL_MISC
+#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0
+#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3
+#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6
+#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb
+#define PCTL_MISC__OVR_EA0_SDP_PARTACK__SHIFT 0xc
+#define PCTL_MISC__OVR_EA1_SDP_PARTACK__SHIFT 0xd
+#define PCTL_MISC__OVR_EA0_SDP_FULLACK__SHIFT 0xe
+#define PCTL_MISC__OVR_EA1_SDP_FULLACK__SHIFT 0xf
+#define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0x10
+#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L
+#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L
+#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L
+#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L
+#define PCTL_MISC__OVR_EA0_SDP_PARTACK_MASK 0x00001000L
+#define PCTL_MISC__OVR_EA1_SDP_PARTACK_MASK 0x00002000L
+#define PCTL_MISC__OVR_EA0_SDP_FULLACK_MASK 0x00004000L
+#define PCTL_MISC__OVR_EA1_SDP_FULLACK_MASK 0x00008000L
+#define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x00030000L
+//PCTL_MMHUB_DEEPSLEEP
+#define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0
+#define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1
+#define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2
+#define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3
+#define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4
+#define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5
+#define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6
+#define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7
+#define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8
+#define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9
+#define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa
+#define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb
+#define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc
+#define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd
+#define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe
+#define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf
+#define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10
+#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f
+#define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L
+#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L
+//PCTL_MMHUB_DEEPSLEEP_OVERRIDE
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L
+//PCTL_PG_IGNORE_DEEPSLEEP
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L
+//PCTL_PG_DAGB
+#define PCTL_PG_DAGB__DS0__SHIFT 0x0
+#define PCTL_PG_DAGB__DS1__SHIFT 0x1
+#define PCTL_PG_DAGB__DS2__SHIFT 0x2
+#define PCTL_PG_DAGB__DS3__SHIFT 0x3
+#define PCTL_PG_DAGB__DS4__SHIFT 0x4
+#define PCTL_PG_DAGB__DS5__SHIFT 0x5
+#define PCTL_PG_DAGB__DS6__SHIFT 0x6
+#define PCTL_PG_DAGB__DS7__SHIFT 0x7
+#define PCTL_PG_DAGB__DS8__SHIFT 0x8
+#define PCTL_PG_DAGB__DS9__SHIFT 0x9
+#define PCTL_PG_DAGB__DS10__SHIFT 0xa
+#define PCTL_PG_DAGB__DS11__SHIFT 0xb
+#define PCTL_PG_DAGB__DS12__SHIFT 0xc
+#define PCTL_PG_DAGB__DS13__SHIFT 0xd
+#define PCTL_PG_DAGB__DS14__SHIFT 0xe
+#define PCTL_PG_DAGB__DS15__SHIFT 0xf
+#define PCTL_PG_DAGB__DS16__SHIFT 0x10
+#define PCTL_PG_DAGB__DS0_MASK 0x00000001L
+#define PCTL_PG_DAGB__DS1_MASK 0x00000002L
+#define PCTL_PG_DAGB__DS2_MASK 0x00000004L
+#define PCTL_PG_DAGB__DS3_MASK 0x00000008L
+#define PCTL_PG_DAGB__DS4_MASK 0x00000010L
+#define PCTL_PG_DAGB__DS5_MASK 0x00000020L
+#define PCTL_PG_DAGB__DS6_MASK 0x00000040L
+#define PCTL_PG_DAGB__DS7_MASK 0x00000080L
+#define PCTL_PG_DAGB__DS8_MASK 0x00000100L
+#define PCTL_PG_DAGB__DS9_MASK 0x00000200L
+#define PCTL_PG_DAGB__DS10_MASK 0x00000400L
+#define PCTL_PG_DAGB__DS11_MASK 0x00000800L
+#define PCTL_PG_DAGB__DS12_MASK 0x00001000L
+#define PCTL_PG_DAGB__DS13_MASK 0x00002000L
+#define PCTL_PG_DAGB__DS14_MASK 0x00004000L
+#define PCTL_PG_DAGB__DS15_MASK 0x00008000L
+#define PCTL_PG_DAGB__DS16_MASK 0x00010000L
+//PCTL0_RENG_RAM_INDEX
+#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL
+//PCTL0_RENG_RAM_DATA
+#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
+//PCTL0_RENG_EXECUTE
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL
+#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L
+//PCTL1_RENG_RAM_INDEX
+#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL
+//PCTL1_RENG_RAM_DATA
+#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
+//PCTL1_RENG_EXECUTE
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL
+#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L
+//PCTL2_RENG_RAM_INDEX
+#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL
+//PCTL2_RENG_RAM_DATA
+#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
+//PCTL2_RENG_EXECUTE
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL
+#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L
+//PCTL0_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
+//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
+#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
+//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
+#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
+//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
+#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
+//PCTL0_MISC
+#define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb
+#define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc
+#define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf
+#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
+#define PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11
+#define PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12
+#define PCTL0_MISC__RD_TIMER_ENABLE__SHIFT 0x13
+#define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L
+#define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L
+#define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L
+#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L
+#define PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L
+#define PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L
+#define PCTL0_MISC__RD_TIMER_ENABLE_MASK 0x00080000L
+//PCTL1_MISC
+#define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11
+#define PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12
+#define PCTL1_MISC__RD_TIMER_ENABLE__SHIFT 0x13
+#define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L
+#define PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L
+#define PCTL1_MISC__RD_TIMER_ENABLE_MASK 0x00080000L
+//PCTL2_MISC
+#define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
+#define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
+#define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
+#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
+#define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
+#define PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11
+#define PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12
+#define PCTL2_MISC__RD_TIMER_ENABLE__SHIFT 0x13
+#define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
+#define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
+#define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
+#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
+#define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
+#define PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L
+#define PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L
+#define PCTL2_MISC__RD_TIMER_ENABLE_MASK 0x00080000L
+//PCTL_PERFCOUNTER_LO
+#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//PCTL_PERFCOUNTER_HI
+#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+//PCTL_PERFCOUNTER0_CFG
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//PCTL_PERFCOUNTER1_CFG
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//PCTL_PERFCOUNTER_RSLT_CNTL
+#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_l1tlb_mmvml1pfdec
+//MMMC_VM_MX_L1_TLB0_STATUS
+#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MMMC_VM_MX_L1_TLB1_STATUS
+#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MMMC_VM_MX_L1_TLB2_STATUS
+#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MMMC_VM_MX_L1_TLB3_STATUS
+#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MMMC_VM_MX_L1_TLB4_STATUS
+#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MMMC_VM_MX_L1_TLB5_STATUS
+#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MMMC_VM_MX_L1_TLB6_STATUS
+#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+//MMMC_VM_MX_L1_TLB7_STATUS
+#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
+#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
+
+
+// addressBlock: mmhub_l1tlb_mmvml1pldec
+//MMMC_VM_MX_L1_PERFCOUNTER0_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER1_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER2_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER3_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_l1tlb_mmvml1prdec
+//MMMC_VM_MX_L1_PERFCOUNTER_LO
+#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMMC_VM_MX_L1_PERFCOUNTER_HI
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+//MM_ATC_L2_CNTL
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
+#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
+#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
+#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
+#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+//MM_ATC_L2_CNTL2
+#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
+#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
+#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
+#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
+#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
+#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
+//MM_ATC_L2_CACHE_DATA0
+#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
+#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
+#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
+#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18
+#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
+#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
+#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL
+#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L
+//MM_ATC_L2_CACHE_DATA1
+#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
+//MM_ATC_L2_CACHE_DATA2
+#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
+#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
+//MM_ATC_L2_CNTL3
+#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
+#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
+#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9
+#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
+#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
+#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L
+//MM_ATC_L2_STATUS
+#define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0
+#define MM_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
+#define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L
+#define MM_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
+//MM_ATC_L2_STATUS2
+#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
+#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
+#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
+#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
+//MM_ATC_L2_MISC_CG
+#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
+#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
+#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
+#define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
+#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
+//MM_ATC_L2_MEM_POWER_LS
+#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//MM_ATC_L2_CGTT_CLK_CTRL
+#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//MM_ATC_L2_SDPPORT_CTRL
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+//MMVM_L2_CNTL
+#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
+#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
+#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
+#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
+#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
+#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
+#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
+#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
+#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
+#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
+#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
+#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
+#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
+//MMVM_L2_CNTL2
+#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
+#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
+#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
+#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
+#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
+#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
+#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
+#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
+//MMVM_L2_CNTL3
+#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
+#define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
+#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
+//MMVM_L2_STATUS
+#define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
+#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
+#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
+#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
+#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
+#define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L
+#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
+#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
+#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
+#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
+#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
+#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
+//MMVM_DUMMY_PAGE_FAULT_CNTL
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
+//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
+//MMVM_INVALIDATE_CNTL
+#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0
+#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8
+#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL
+#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L
+//MMVM_L2_PROTECTION_FAULT_CNTL
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
+#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
+#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
+#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
+#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
+#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
+#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
+#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
+//MMVM_L2_PROTECTION_FAULT_CNTL2
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
+//MMVM_L2_PROTECTION_FAULT_MM_CNTL3
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_MM_CNTL4
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_STATUS
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
+#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
+#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
+#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x3E000000L
+//MMVM_L2_PROTECTION_FAULT_ADDR_LO32
+#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_ADDR_HI32
+#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
+//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
+//MMVM_L2_CNTL4
+#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
+#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
+#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
+#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
+#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d
+#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
+#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
+#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
+#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
+#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
+#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
+#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L
+//MMVM_L2_MM_GROUP_RT_CLASSES
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
+//MMVM_L2_BANK_SELECT_RESERVED_CID
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L
+//MMVM_L2_BANK_SELECT_RESERVED_CID2
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L
+//MMVM_L2_CACHE_PARITY_CNTL
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
+//MMVM_L2_IH_LOG_CNTL
+#define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING__SHIFT 0x0
+#define MMVM_L2_IH_LOG_CNTL__USE_L_BIT__SHIFT 0x1
+#define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS__SHIFT 0x2
+#define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS__SHIFT 0x14
+#define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING_MASK 0x00000001L
+#define MMVM_L2_IH_LOG_CNTL__USE_L_BIT_MASK 0x00000002L
+#define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS_MASK 0x000FFFFCL
+#define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS_MASK 0x00100000L
+//MMVM_L2_IH_LOG_BUSY
+#define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY__SHIFT 0x0
+#define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY__SHIFT 0x10
+#define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY_MASK 0x0000FFFFL
+#define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY_MASK 0xFFFF0000L
+//MMVM_L2_CGTT_CLK_CTRL
+#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//MMVM_L2_CNTL5
+#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0
+#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5
+#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL
+#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L
+//MMVM_L2_GCR_CNTL
+#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0
+#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1
+#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L
+#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL
+//MMVML2_WALKER_MACRO_THROTTLE_TIME
+#define MMVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0
+#define MMVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL
+//MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT
+#define MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1
+#define MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL
+//MMVML2_WALKER_MICRO_THROTTLE_TIME
+#define MMVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0
+#define MMVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL
+//MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT
+#define MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1
+#define MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+//MMVM_CONTEXT0_CNTL
+#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT1_CNTL
+#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT2_CNTL
+#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT3_CNTL
+#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT4_CNTL
+#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT5_CNTL
+#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT6_CNTL
+#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT7_CNTL
+#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT8_CNTL
+#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT9_CNTL
+#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT10_CNTL
+#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT11_CNTL
+#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT12_CNTL
+#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT13_CNTL
+#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT14_CNTL
+#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXT15_CNTL
+#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
+#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
+#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
+#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
+#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
+//MMVM_CONTEXTS_DISABLE
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
+//MMVM_INVALIDATE_ENG0_SEM
+#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG1_SEM
+#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG2_SEM
+#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG3_SEM
+#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG4_SEM
+#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG5_SEM
+#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG6_SEM
+#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG7_SEM
+#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG8_SEM
+#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG9_SEM
+#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG10_SEM
+#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG11_SEM
+#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG12_SEM
+#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG13_SEM
+#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG14_SEM
+#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG15_SEM
+#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG16_SEM
+#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG17_SEM
+#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
+//MMVM_INVALIDATE_ENG0_REQ
+#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG1_REQ
+#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG2_REQ
+#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG3_REQ
+#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG4_REQ
+#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG5_REQ
+#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG6_REQ
+#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG7_REQ
+#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG8_REQ
+#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG9_REQ
+#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG10_REQ
+#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG11_REQ
+#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG12_REQ
+#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG13_REQ
+#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG14_REQ
+#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG15_REQ
+#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG16_REQ
+#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG17_REQ
+#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17
+#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18
+#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a
+#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L
+#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L
+#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L
+//MMVM_INVALIDATE_ENG0_ACK
+#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG1_ACK
+#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG2_ACK
+#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG3_ACK
+#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG4_ACK
+#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG5_ACK
+#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG6_ACK
+#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG7_ACK
+#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG8_ACK
+#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG9_ACK
+#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG10_ACK
+#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG11_ACK
+#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG12_ACK
+#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG13_ACK
+#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG14_ACK
+#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG15_ACK
+#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG16_ACK
+#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG17_ACK
+#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
+#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
+#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
+//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
+//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+//MMMC_VM_L2_PERFCOUNTER0_CFG
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER1_CFG
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER2_CFG
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER3_CFG
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER4_CFG
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER5_CFG
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER6_CFG
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER7_CFG
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
+//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+//MMMC_VM_L2_PERFCOUNTER_LO
+#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MMMC_VM_L2_PERFCOUNTER_HI
+#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+//MMMC_VM_FB_SIZE_OFFSET_VF0
+#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF1
+#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF2
+#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF3
+#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF4
+#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF5
+#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF6
+#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF7
+#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF8
+#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF9
+#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF10
+#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF11
+#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF12
+#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF13
+#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF14
+#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF15
+#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF16
+#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF17
+#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF18
+#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF19
+#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF20
+#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF21
+#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF22
+#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF23
+#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF24
+#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF25
+#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF26
+#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF27
+#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF28
+#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF29
+#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF30
+#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF31
+#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT 0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT 0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK 0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK 0xFFFF0000L
+//MMVM_IOMMU_MMIO_CNTRL_1
+#define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8
+#define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L
+//MMMC_VM_MARC_BASE_LO_0
+#define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
+#define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
+//MMMC_VM_MARC_BASE_LO_1
+#define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
+#define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
+//MMMC_VM_MARC_BASE_LO_2
+#define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
+#define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
+//MMMC_VM_MARC_BASE_LO_3
+#define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
+#define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
+//MMMC_VM_MARC_BASE_HI_0
+#define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
+#define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
+//MMMC_VM_MARC_BASE_HI_1
+#define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
+#define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
+//MMMC_VM_MARC_BASE_HI_2
+#define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
+#define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
+//MMMC_VM_MARC_BASE_HI_3
+#define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
+#define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
+//MMMC_VM_MARC_RELOC_LO_0
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
+//MMMC_VM_MARC_RELOC_LO_1
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
+//MMMC_VM_MARC_RELOC_LO_2
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
+//MMMC_VM_MARC_RELOC_LO_3
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
+//MMMC_VM_MARC_RELOC_HI_0
+#define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
+#define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
+//MMMC_VM_MARC_RELOC_HI_1
+#define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
+#define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
+//MMMC_VM_MARC_RELOC_HI_2
+#define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
+#define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
+//MMMC_VM_MARC_RELOC_HI_3
+#define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
+#define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
+//MMMC_VM_MARC_LEN_LO_0
+#define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
+#define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
+//MMMC_VM_MARC_LEN_LO_1
+#define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
+#define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
+//MMMC_VM_MARC_LEN_LO_2
+#define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
+#define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
+//MMMC_VM_MARC_LEN_LO_3
+#define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
+#define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
+//MMMC_VM_MARC_LEN_HI_0
+#define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
+#define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
+//MMMC_VM_MARC_LEN_HI_1
+#define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
+#define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
+//MMMC_VM_MARC_LEN_HI_2
+#define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
+#define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
+//MMMC_VM_MARC_LEN_HI_3
+#define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
+#define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
+//MMVM_IOMMU_CONTROL_REGISTER
+#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
+#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
+//MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
+#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
+#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
+//MMVM_PCIE_ATS_CNTL
+#define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10
+#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
+#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_0
+#define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_1
+#define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_2
+#define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_3
+#define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_4
+#define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_5
+#define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_6
+#define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_7
+#define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_8
+#define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_9
+#define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_10
+#define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_11
+#define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_12
+#define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_13
+#define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_14
+#define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_15
+#define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_16
+#define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_17
+#define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_18
+#define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_19
+#define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_20
+#define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_21
+#define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_22
+#define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_23
+#define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_24
+#define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_25
+#define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_26
+#define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_27
+#define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_28
+#define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_29
+#define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_30
+#define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_31
+#define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT 0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK 0x80000000L
+//MMUTCL2_CGTT_CLK_CTRL
+#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
+#define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
+#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
+#define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+//MMMC_SHARED_ACTIVE_FCN_ID
+#define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
+#define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+//MMMC_VM_NB_MMIOBASE
+#define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
+#define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
+//MMMC_VM_NB_MMIOLIMIT
+#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
+#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
+//MMMC_VM_NB_PCI_CTRL
+#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
+#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
+//MMMC_VM_NB_PCI_ARB
+#define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
+//MMMC_VM_NB_TOP_OF_DRAM_SLOT1
+#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
+//MMMC_VM_NB_LOWER_TOP_OF_DRAM2
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
+//MMMC_VM_NB_UPPER_TOP_OF_DRAM2
+#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
+#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
+//MMMC_VM_FB_OFFSET
+#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
+//MMMC_VM_STEERING
+#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
+//MMMC_SHARED_VIRT_RESET_REQ
+#define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
+#define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//MMMC_MEM_POWER_LS
+#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
+#define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
+//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//MMMC_VM_APT_CNTL
+#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
+#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
+#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
+#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
+//MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
+#define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
+//MMMC_VM_LOCAL_HBM_ADDRESS_START
+#define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
+#define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
+//MMMC_VM_LOCAL_HBM_ADDRESS_END
+#define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
+#define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
+//MMMC_SHARED_VIRT_RESET_REQ2
+#define MMMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT 0x0
+#define MMMC_SHARED_VIRT_RESET_REQ2__VF_MASK 0x00000001L
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+//MMMC_VM_FB_LOCATION_BASE
+#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
+#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
+//MMMC_VM_FB_LOCATION_TOP
+#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
+#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
+//MMMC_VM_AGP_TOP
+#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
+//MMMC_VM_AGP_BOT
+#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
+//MMMC_VM_AGP_BASE
+#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR
+#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
+#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
+//MMMC_VM_MX_L1_TLB_CNTL
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
+#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
+#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+//MM_ATC_L2_PERFCOUNTER_LO
+#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
+//MM_ATC_L2_PERFCOUNTER_HI
+#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
+#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+//MM_ATC_L2_PERFCOUNTER0_CFG
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
+//MM_ATC_L2_PERFCOUNTER1_CFG
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
+//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h
index 1ac8895c29a9..136fb5de6a4c 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h
@@ -262,6 +262,435 @@
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
+//MP1_FIRMWARE_FLAGS
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
+#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
+//MP1_PUB_SCRATCH0
+#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP1_PUB_SCRATCH1
+#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP1_PUB_SCRATCH2
+#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP1_PUB_SCRATCH3
+#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0
+#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_0
+#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_1
+#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_2
+#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_3
+#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_4
+#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_5
+#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_6
+#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_7
+#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_8
+#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_9
+#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_10
+#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_11
+#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_12
+#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_13
+#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_14
+#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_15
+#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_16
+#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_17
+#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_18
+#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_19
+#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_20
+#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_21
+#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_22
+#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_23
+#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_24
+#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_25
+#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_26
+#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_27
+#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_28
+#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_29
+#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_30
+#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_31
+#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_0
+#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_1
+#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_2
+#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_3
+#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0
+#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2CMSG_INTEN
+#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0
+#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
+//MP1_P2CMSG_INTSTS
+#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP1_P2SMSG_0
+#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_1
+#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_2
+#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_3
+#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0
+#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
+//MP1_P2SMSG_INTSTS
+#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
+#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
+#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
+#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
+#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
+#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
+#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
+#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
+//MP1_S2PMSG_0
+#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0
+#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_32
+#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_33
+#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_34
+#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_35
+#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_36
+#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_37
+#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_38
+#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_39
+#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_40
+#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_41
+#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_42
+#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_43
+#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_44
+#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_45
+#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_46
+#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_47
+#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_48
+#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_49
+#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_50
+#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_51
+#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_52
+#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_53
+#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_54
+#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_55
+#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_56
+#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_57
+#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_58
+#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_59
+#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_60
+#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_61
+#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_62
+#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_63
+#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_64
+#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_65
+#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_66
+#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_67
+#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_68
+#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_69
+#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_70
+#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_71
+#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_72
+#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_73
+#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_74
+#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_75
+#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_76
+#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_77
+#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_78
+#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_79
+#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_80
+#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_81
+#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_82
+#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_83
+#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_84
+#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_85
+#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_86
+#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_87
+#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_88
+#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_89
+#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_90
+#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_91
+#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_92
+#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_93
+#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_94
+#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_95
+#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_96
+#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_97
+#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_98
+#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_99
+#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_100
+#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_101
+#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_102
+#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
+//MP1_C2PMSG_103
+#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0
+#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP1_ACTIVE_FCN_ID
+#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
+#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//MP1_IH_CREDIT
+#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
+#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10
+#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
+#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
+//MP1_IH_SW_INT
+#define MP1_IH_SW_INT__ID__SHIFT 0x0
+#define MP1_IH_SW_INT__VALID__SHIFT 0x8
+#define MP1_IH_SW_INT__ID_MASK 0x000000FFL
+#define MP1_IH_SW_INT__VALID_MASK 0x00000100L
+//MP1_IH_SW_INT_CTRL
+#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
+#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
+#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
+#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
+//MP1_FPS_CNT
+#define MP1_FPS_CNT__COUNT__SHIFT 0x0
+#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
+//MP1_PUB_CTRL
+#define MP1_PUB_CTRL__RESET__SHIFT 0x0
+#define MP1_PUB_CTRL__RESET_MASK 0x00000001L
+//MP1_EXT_SCRATCH0
+#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH1
+#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH2
+#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH3
+#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH4
+#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH5
+#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH6
+#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
+//MP1_EXT_SCRATCH7
+#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0
+#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
+
+
// addressBlock: mp_SmuMp1_SmnDec
//MP1_SMN_C2PMSG_32
#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_default.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_default.h
new file mode 100644
index 000000000000..c185e9fce588
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_default.h
@@ -0,0 +1,18521 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_2_3_DEFAULT_HEADER
+#define _nbio_2_3_DEFAULT_HEADER
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+#define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
+#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
+#define mmPCIE_INDEX_DEFAULT 0x00000000
+#define mmPCIE_DATA_DEFAULT 0x00000000
+#define mmPCIE_INDEX2_DEFAULT 0x00000000
+#define mmPCIE_DATA2_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000
+#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000
+#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
+#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
+#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
+#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
+#define mmSYSHUB_INDEX_DEFAULT 0x00000000
+#define mmSYSHUB_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+#define mmRCC_BIF_STRAP0_DEFAULT 0x00040a00
+#define mmRCC_BIF_STRAP1_DEFAULT 0x00400108
+#define mmRCC_BIF_STRAP2_DEFAULT 0x000a0079
+#define mmRCC_BIF_STRAP3_DEFAULT 0x00000000
+#define mmRCC_BIF_STRAP4_DEFAULT 0x00100010
+#define mmRCC_BIF_STRAP5_DEFAULT 0x31130010
+#define mmRCC_BIF_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20
+#define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479
+#define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009
+#define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
+#define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
+#define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
+#define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02
+#define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
+#define mmRCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000
+#define mmRCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310
+#define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
+#define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000
+#define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41
+#define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000
+#define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002
+#define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001
+#define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100
+#define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38
+#define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000
+#define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1
+#define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
+#define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002
+#define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000
+#define mmEP_PCIE_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000
+#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
+#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
+#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000
+#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000
+#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000
+#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
+#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000
+#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000
+#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000
+#define mmDN_PCIE_CNTL_DEFAULT 0x00000000
+#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
+#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001
+#define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500
+#define mmPCIE_RX_CNTL_DEFAULT 0x00000000
+#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000
+#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000
+#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
+#define mmRCC_DEV0_EPF0_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+#define mmRCC_ERR_INT_CNTL_DEFAULT 0x00000000
+#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000
+#define mmRCC_RESET_EN_DEFAULT 0x00008000
+#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000
+#define mmRCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df
+#define mmRCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000
+#define mmRCC_GPUIOV_REGION_DEFAULT 0x00000000
+#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000
+#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000
+#define mmRCC_BUS_CNTL_DEFAULT 0x00000000
+#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000
+#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000
+#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000
+#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000
+#define mmRCC_XDMA_LO_DEFAULT 0x00000000
+#define mmRCC_XDMA_HI_DEFAULT 0x00000000
+#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000
+#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000
+#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000
+#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000
+#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000
+#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000
+#define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000
+#define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000
+#define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000
+#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00400000
+#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
+#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
+#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+#define mmCC_BIF_BX_STRAP0_DEFAULT 0x00000000
+#define mmCC_BIF_BX_PINSTRAP0_DEFAULT 0x00000000
+#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
+#define mmBUS_CNTL_DEFAULT 0x00000000
+#define mmBIF_SCRATCH0_DEFAULT 0x00000000
+#define mmBIF_SCRATCH1_DEFAULT 0x00000000
+#define mmBX_RESET_EN_DEFAULT 0x00010000
+#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000
+#define mmBX_RESET_CNTL_DEFAULT 0x00000000
+#define mmINTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000
+#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0
+#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00800000
+#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_FB_EN_DEFAULT 0x00000000
+#define mmBIF_INTR_CNTL_DEFAULT 0x00000000
+#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define mmBACO_CNTL_DEFAULT 0x00000000
+#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
+#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x1c000200
+#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
+#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500
+#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400
+#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000
+#define mmNBIF_GFX_ADDR_LUT_CNTL_DEFAULT 0x00000000
+#define mmNBIF_GFX_ADDR_LUT_0_DEFAULT 0x00000000
+#define mmNBIF_GFX_ADDR_LUT_1_DEFAULT 0x00000001
+#define mmNBIF_GFX_ADDR_LUT_2_DEFAULT 0x00000002
+#define mmNBIF_GFX_ADDR_LUT_3_DEFAULT 0x00000003
+#define mmNBIF_GFX_ADDR_LUT_4_DEFAULT 0x00000004
+#define mmNBIF_GFX_ADDR_LUT_5_DEFAULT 0x00000005
+#define mmNBIF_GFX_ADDR_LUT_6_DEFAULT 0x00000006
+#define mmNBIF_GFX_ADDR_LUT_7_DEFAULT 0x00000007
+#define mmNBIF_GFX_ADDR_LUT_8_DEFAULT 0x00000008
+#define mmNBIF_GFX_ADDR_LUT_9_DEFAULT 0x00000009
+#define mmNBIF_GFX_ADDR_LUT_10_DEFAULT 0x0000000a
+#define mmNBIF_GFX_ADDR_LUT_11_DEFAULT 0x0000000b
+#define mmNBIF_GFX_ADDR_LUT_12_DEFAULT 0x0000000c
+#define mmNBIF_GFX_ADDR_LUT_13_DEFAULT 0x0000000d
+#define mmNBIF_GFX_ADDR_LUT_14_DEFAULT 0x0000000e
+#define mmNBIF_GFX_ADDR_LUT_15_DEFAULT 0x0000000f
+#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
+#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
+#define mmBIF_RB_CNTL_DEFAULT 0x00000000
+#define mmBIF_RB_BASE_DEFAULT 0x00000000
+#define mmBIF_RB_RPTR_DEFAULT 0x00000000
+#define mmBIF_RB_WPTR_DEFAULT 0x00000000
+#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
+#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
+#define mmMAILBOX_INDEX_DEFAULT 0x00000000
+#define mmBIF_MP1_INTR_CTRL_DEFAULT 0x00000000
+#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
+#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
+#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
+#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
+#define mmBIF_PWRBRK_PAD_CNTL_DEFAULT 0x00000071
+#define mmBIF_WAKEB_PAD_CNTL_DEFAULT 0x00000031
+#define mmBIF_VAUX_PRESENT_PAD_CNTL_DEFAULT 0x0000000d
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+#define mmBIF_BX_PF_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_PF_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_PF_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_PF_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+#define mmA2S_CNTL_CL0_DEFAULT 0x02a80540
+#define mmA2S_CNTL_CL1_DEFAULT 0x02a825a0
+#define mmA2S_CNTL3_CL0_DEFAULT 0x00000000
+#define mmA2S_CNTL3_CL1_DEFAULT 0x00000008
+#define mmA2S_CNTL_SW0_DEFAULT 0x04040000
+#define mmA2S_CNTL_SW1_DEFAULT 0x04040200
+#define mmA2S_CNTL_SW2_DEFAULT 0x04040200
+#define mmA2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001
+#define mmA2S_TAG_ALLOC_0_DEFAULT 0x00000000
+#define mmA2S_TAG_ALLOC_1_DEFAULT 0x00000000
+#define mmA2S_MISC_CNTL_DEFAULT 0x0005000b
+#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000003f
+#define mmSHUB_REGS_IF_CTL_DEFAULT 0x00000000
+#define mmNGDC_MGCG_CTRL_DEFAULT 0x00000100
+#define mmNGDC_RESERVED_0_DEFAULT 0x00000000
+#define mmNGDC_RESERVED_1_DEFAULT 0x00000000
+#define mmNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000003f
+#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_ACV_DOORBELL_RANGE_DEFAULT 0x00000000
+#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
+#define mmS2A_MISC_CNTL_DEFAULT 0x00000000
+#define mmNGDC_PG_MISC_CTRL_DEFAULT 0x14006000
+#define mmNGDC_PGMST_CTRL_DEFAULT 0x00000000
+#define mmNGDC_PGSLV_CTRL_DEFAULT 0x00001084
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp
+#define cfgPSWUSCFG0_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_COMMAND_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LATENCY_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_HEADER_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_BIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_SECONDARY_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_CAP_PTR_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_ADAPTER_ID_W_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PMI_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PMI_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgPSWUSCFG0_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgPSWUSCFG0_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_DEVICE_CNTL_DEFAULT 0x00002910
+#define cfgPSWUSCFG0_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LINK_CAP_DEFAULT 0x00011c04
+#define cfgPSWUSCFG0_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgPSWUSCFG0_0_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgPSWUSCFG0_0_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgPSWUSCFG0_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgPSWUSCFG0_0_MSI_MSG_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_SSID_CAP_LIST_DEFAULT 0x0000c800
+#define cfgPSWUSCFG0_0_SSID_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MSI_MAP_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002
+#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002
+#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000
+#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x04400000
+#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
+#define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgPSWUSCFG0_0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgPSWUSCFG0_0_PCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgPSWUSCFG0_0_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x38000000
+#define cfgPSWUSCFG0_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x3c400000
+#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_LIST_DEFAULT 0x40000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_CTRL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000
+#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP_DEFAULT 0x80000001
+#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000
+#define cfgPSWUSCFG0_0_LINK_CAP_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID_DEFAULT 0x00007310
+#define cfgBIF_CFG_DEV0_EPF0_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_HEADER_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_DEFAULT 0x00006400
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_DEFAULT 0x0000f000
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_DEFAULT 0x00000012
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_DEFAULT 0x00000f81
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_DEFAULT 0x00000084
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000553
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025
+#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027
+#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID_DEFAULT 0x0000ab38
+#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_HEADER_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF1_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_DEFAULT 0xab381002
+#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_DEFAULT 0xab381002
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_DEFAULT 0x00006400
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_DEFAULT 0x0000f000
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_DEFAULT 0x00000012
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_DEFAULT 0x00000f81
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025
+#define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027
+#define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID_DEFAULT 0x00007316
+#define cfgBIF_CFG_DEV0_EPF2_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE_DEFAULT 0x00000030
+#define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS_DEFAULT 0x0000000c
+#define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_HEADER_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF2_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_DEFAULT 0x73161002
+#define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W_DEFAULT 0x73161002
+#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST_DEFAULT 0x00006400
+#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_DEFAULT 0x0000c800
+#define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_SBRN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_FLADJ_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP_DEFAULT 0x00000f81
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL_DEFAULT 0x00000086
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID_DEFAULT 0x00007314
+#define cfgBIF_CFG_DEV0_EPF3_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS_DEFAULT 0x0000000c
+#define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_HEADER_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF3_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_DEFAULT 0x73141002
+#define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W_DEFAULT 0x73141002
+#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST_DEFAULT 0x00006400
+#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_SBRN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_FLADJ_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP_DEFAULT 0x00000f81
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+#define smnA2S_CNTL_CL0_DEFAULT 0x02a80540
+#define smnA2S_CNTL_CL1_DEFAULT 0x02a825a0
+#define smnA2S_CNTL3_CL0_DEFAULT 0x00000000
+#define smnA2S_CNTL3_CL1_DEFAULT 0x00000008
+#define smnA2S_CNTL_SW0_DEFAULT 0x04040000
+#define smnA2S_CNTL_SW1_DEFAULT 0x04040200
+#define smnA2S_CNTL_SW2_DEFAULT 0x04040200
+#define smnA2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001
+#define smnA2S_TAG_ALLOC_0_DEFAULT 0x00000000
+#define smnA2S_TAG_ALLOC_1_DEFAULT 0x00000000
+#define smnA2S_MISC_CNTL_DEFAULT 0x0005000b
+#define smnNGDC_SDP_PORT_CTRL_DEFAULT 0x0000003f
+#define smnSHUB_REGS_IF_CTL_DEFAULT 0x00000000
+#define smnNGDC_MGCG_CTRL_DEFAULT 0x00000100
+#define smnNGDC_RESERVED_0_DEFAULT 0x00000000
+#define smnNGDC_RESERVED_1_DEFAULT 0x00000000
+#define smnNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000003f
+#define smnBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define smnBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
+#define smnBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
+#define smnBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define smnBIF_ACV_DOORBELL_RANGE_DEFAULT 0x00000000
+#define smnBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
+#define smnS2A_MISC_CNTL_DEFAULT 0x00000000
+#define smnNGDC_PG_MISC_CTRL_DEFAULT 0x14006000
+#define smnNGDC_PGMST_CTRL_DEFAULT 0x00000000
+#define smnNGDC_PGSLV_CTRL_DEFAULT 0x00001084
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect
+#define smnSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000
+#define smnSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100
+#define smnSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000
+#define smnSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000
+#define smnSYSHUB_TRANS_IDLE_SOCCLK_DEFAULT 0x00000000
+#define smnSYSHUB_HP_TIMER_SOCCLK_DEFAULT 0x00000100
+#define smnSYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000100
+#define smnSYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK_DEFAULT 0x00000000
+#define smnSYSHUB_SCRATCH_SOCCLK_DEFAULT 0x00000040
+#define smnSYSHUB_CL_MASK_SOCCLK_DEFAULT 0x00000000
+#define smnSYSHUB_HANG_CNTL_SOCCLK_DEFAULT 0x00000000
+#define smnHST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000
+#define smnHST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000
+#define smnHST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000
+#define smnHST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000
+#define smnHST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000
+#define smnHST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000
+#define smnDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
+#define smnDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000
+#define smnDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000
+#define smnSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000
+#define smnSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100
+#define smnSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000
+#define smnSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000
+#define smnSYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000100
+#define smnSYSHUB_SCRATCH_SHUBCLK_DEFAULT 0x00000040
+#define smnSYSHUB_SELECT_SHUBCLK_DEFAULT 0x00000000
+#define smnSYSHUB_SCRATCH_LCLK_DEFAULT 0x00000040
+#define smnNIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000
+#define smnNIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnNIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnNIC400_0_AMIB_2_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnNIC400_0_IB_0_FN_MOD_DEFAULT 0x00000000
+#define smnNIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000
+#define smnNIC400_1_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnNIC400_1_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnNIC400_1_AMIB_2_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnNIC400_1_IB_0_FN_MOD_DEFAULT 0x00000000
+#define smnNIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_QOS_CNTL_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_MAX_OT_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_MAX_COMB_OT_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_AW_P_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_AW_B_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_AW_R_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_AR_P_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_AR_B_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_AR_R_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_TARGET_FC_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_KI_FC_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_0_QOS_RANGE_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_QOS_CNTL_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_MAX_OT_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_MAX_COMB_OT_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_AW_P_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_AW_B_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_AW_R_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_AR_P_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_AR_B_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_AR_R_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_TARGET_FC_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_KI_FC_DEFAULT 0x00000000
+#define smnNIC400_2_ASIB_1_QOS_RANGE_DEFAULT 0x00000000
+#define smnNIC400_2_IB_0_FN_MOD_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_nbif_sion_SIONDEC
+#define smnSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
+#define smnSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
+#define smnSION_CNTL_REG0_DEFAULT 0x00000000
+#define smnSION_CNTL_REG1_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC
+#define smnSHUB_PF_FLR_RST_DEFAULT 0x00000000
+#define smnSHUB_GFX_DRV_VPU_RST_DEFAULT 0x00000000
+#define smnSHUB_LINK_RESET_DEFAULT 0x00000000
+#define smnSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000
+#define smnSHUB_HARD_RST_CTRL_DEFAULT 0x0000003b
+#define smnSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009
+#define smnSHUB_SDP_PORT_RST_DEFAULT 0x00000000
+#define smnSHUB_RST_MISC_TRL_DEFAULT 0x00100001
+
+
+// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk
+#define smnGDCL_RAS_CENTRAL_STATUS_DEFAULT 0x00000000
+#define smnGDCSOC_RAS_CENTRAL_STATUS_DEFAULT 0x00000000
+#define smnGDCSOC_RAS_LEAF0_CTRL_DEFAULT 0x00000f61
+#define smnGDCSOC_RAS_LEAF1_CTRL_DEFAULT 0x00000f61
+#define smnGDCSOC_RAS_LEAF2_CTRL_DEFAULT 0x00010f01
+#define smnGDCSOC_RAS_LEAF3_CTRL_DEFAULT 0x00000f61
+#define smnGDCSOC_RAS_LEAF4_CTRL_DEFAULT 0x00000f61
+#define smnGDCSOC_RAS_LEAF5_CTRL_DEFAULT 0x00000f61
+#define smnGDCSOC_RAS_LEAF2_MISC_CTRL_DEFAULT 0x00000202
+#define smnGDCSOC_RAS_LEAF2_MISC_CTRL2_DEFAULT 0x0013ff21
+#define smnGDCSOC_RAS_LEAF0_STATUS_DEFAULT 0x00000000
+#define smnGDCSOC_RAS_LEAF1_STATUS_DEFAULT 0x00000000
+#define smnGDCSOC_RAS_LEAF2_STATUS_DEFAULT 0x00000000
+#define smnGDCSOC_RAS_LEAF3_STATUS_DEFAULT 0x00000000
+#define smnGDCSOC_RAS_LEAF4_STATUS_DEFAULT 0x00000000
+#define smnGDCSOC_RAS_LEAF5_STATUS_DEFAULT 0x00000000
+#define smnGDCSHUB_RAS_CENTRAL_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
+#define smnBIF_CFG_DEV0_SWDS_VENDOR_ID_DEFAULT 0x00001002
+#define smnBIF_CFG_DEV0_SWDS_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_SUB_CLASS_DEFAULT 0x00000004
+#define smnBIF_CFG_DEV0_SWDS_BASE_CLASS_DEFAULT 0x00000006
+#define smnBIF_CFG_DEV0_SWDS_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define smnIO_BASE_LIMIT_DEFAULT 0x00000000
+#define smnSECONDARY_STATUS_DEFAULT 0x00000000
+#define smnMEM_BASE_LIMIT_DEFAULT 0x00000000
+#define smnPREF_BASE_LIMIT_DEFAULT 0x00000000
+#define smnPREF_BASE_UPPER_DEFAULT 0x00000000
+#define smnPREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define smnIO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_CAP_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_SWDS_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnIRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PMI_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PMI_CAP_DEFAULT 0x0000c800
+#define smnBIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_CAP_DEFAULT 0x00000062
+#define smnBIF_CFG_DEV0_SWDS_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_SWDS_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_SWDS_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LINK_STATUS_DEFAULT 0x00002001
+#define smnSLOT_CAP_DEFAULT 0x00000000
+#define smnSLOT_CNTL_DEFAULT 0x00000000
+#define smnSLOT_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_SWDS_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_SWDS_LINK_CNTL2_DEFAULT 0x00000004
+#define smnBIF_CFG_DEV0_SWDS_LINK_STATUS2_DEFAULT 0x00000000
+#define smnSLOT_CAP2_DEFAULT 0x00000000
+#define smnSLOT_CNTL2_DEFAULT 0x00000000
+#define smnSLOT_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnSSID_CAP_LIST_DEFAULT 0x00000000
+#define smnSSID_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define smnBIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000
+#define smnBIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000
+#define smnBIF_CFG_DEV0_SWDS_LINK_CAP_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c000000
+#define smnBIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+#define smnMM_INDEX_DEFAULT 0x00000000
+#define smnMM_DATA_DEFAULT 0x00000000
+#define smnMM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+#define smnSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
+#define smnSYSHUB_DATA_OVLP_DEFAULT 0x00000000
+#define smnPCIE_INDEX_DEFAULT 0x00000000
+#define smnPCIE_DATA_DEFAULT 0x00000000
+#define smnPCIE_INDEX2_DEFAULT 0x00000000
+#define smnPCIE_DATA2_DEFAULT 0x00000000
+#define smnSBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define smnSBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define smnSBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define smnSBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_4_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_5_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_6_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_7_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_8_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_9_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_10_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_11_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_12_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_13_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_14_DEFAULT 0x00000000
+#define smnBIOS_SCRATCH_15_DEFAULT 0x00000000
+#define smnBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
+#define smnBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
+#define smnBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
+#define smnGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+#define smnRCC_STRAP0_RCC_BIF_STRAP0_DEFAULT 0x00040a00
+#define smnRCC_STRAP0_RCC_BIF_STRAP1_DEFAULT 0x00400108
+#define smnRCC_STRAP0_RCC_BIF_STRAP2_DEFAULT 0x000a0079
+#define smnRCC_STRAP0_RCC_BIF_STRAP3_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_BIF_STRAP4_DEFAULT 0x00100010
+#define smnRCC_STRAP0_RCC_BIF_STRAP5_DEFAULT 0x31130010
+#define smnRCC_STRAP0_RCC_BIF_STRAP6_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310
+#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
+#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000
+#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41
+#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000
+#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002
+#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001
+#define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
+#define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+#define smnRCC_EP_DEV0_0_EP_PCIE_SCRATCH_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define smnRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
+#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define smnRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
+#define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
+#define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
+#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define smnRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIEP_RESERVED_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_DEFAULT 0x01000000
+#define smnRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+#define smnRCC_DWN_DEV0_0_DN_PCIE_RESERVED_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_0_DN_PCIE_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define smnRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_DEFAULT 0x00000001
+#define smnRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+#define smnRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define smnRCC_DWNP_DEV0_0_PCIE_RX_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+#define smnRCC_ERR_INT_CNTL_DEFAULT 0x00000000
+#define smnRCC_BACO_CNTL_MISC_DEFAULT 0x00000000
+#define smnRCC_RESET_EN_DEFAULT 0x00008000
+#define smnRCC_DEV0_0_RCC_VDM_SUPPORT_DEFAULT 0x00000000
+#define smnRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df
+#define smnRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000
+#define smnRCC_GPUIOV_REGION_DEFAULT 0x00000000
+#define smnRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000
+#define smnRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000
+#define smnRCC_DEV0_0_RCC_BUS_CNTL_DEFAULT 0x00000000
+#define smnRCC_CONFIG_CNTL_DEFAULT 0x00000000
+#define smnRCC_CONFIG_F0_BASE_DEFAULT 0x00000000
+#define smnRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000
+#define smnRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000
+#define smnRCC_XDMA_LO_DEFAULT 0x00000000
+#define smnRCC_XDMA_HI_DEFAULT 0x00000000
+#define smnRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
+#define smnRCC_BUSNUM_CNTL1_DEFAULT 0x00000000
+#define smnRCC_BUSNUM_LIST0_DEFAULT 0x00000000
+#define smnRCC_BUSNUM_LIST1_DEFAULT 0x00000000
+#define smnRCC_BUSNUM_CNTL2_DEFAULT 0x00000000
+#define smnRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000
+#define smnRCC_HOST_BUSNUM_DEFAULT 0x00000000
+#define smnRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000
+#define smnRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000
+#define smnRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000
+#define smnRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000
+#define smnRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000
+#define smnRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000
+#define smnRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000
+#define smnRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000
+#define smnRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000
+#define smnRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000
+#define smnRCC_DEV0_0_RCC_DEV0_LINK_CNTL_DEFAULT 0x00000000
+#define smnRCC_DEV0_0_RCC_CMN_LINK_CNTL_DEFAULT 0x00400000
+#define smnRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
+#define smnRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
+#define smnRCC_DEV0_0_RCC_MH_ARB_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+#define smnCC_BIF_BX_STRAP0_DEFAULT 0x00000000
+#define smnCC_BIF_BX_PINSTRAP0_DEFAULT 0x00000000
+#define smnBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
+#define smnBUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_SCRATCH0_DEFAULT 0x00000000
+#define smnBIF_SCRATCH1_DEFAULT 0x00000000
+#define smnBX_RESET_EN_DEFAULT 0x00010000
+#define smnMM_CFGREGS_CNTL_DEFAULT 0x00000000
+#define smnBX_RESET_CNTL_DEFAULT 0x00000000
+#define smnINTERRUPT_CNTL_DEFAULT 0x00000000
+#define smnINTERRUPT_CNTL2_DEFAULT 0x00000000
+#define smnCLKREQB_PAD_CNTL_DEFAULT 0x000008e0
+#define smnBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00800000
+#define smnBIF_DOORBELL_CNTL_DEFAULT 0x00000000
+#define smnBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
+#define smnBIF_FB_EN_DEFAULT 0x00000000
+#define smnBIF_INTR_CNTL_DEFAULT 0x00000000
+#define smnBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define smnBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define smnBACO_CNTL_DEFAULT 0x00000000
+#define smnBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
+#define smnBIF_BACO_EXIT_TIMER1_DEFAULT 0x1c000200
+#define smnBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
+#define smnBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500
+#define smnBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400
+#define smnMEM_TYPE_CNTL_DEFAULT 0x00000000
+#define smnNBIF_GFX_ADDR_LUT_CNTL_DEFAULT 0x00000000
+#define smnNBIF_GFX_ADDR_LUT_0_DEFAULT 0x00000000
+#define smnNBIF_GFX_ADDR_LUT_1_DEFAULT 0x00000001
+#define smnNBIF_GFX_ADDR_LUT_2_DEFAULT 0x00000002
+#define smnNBIF_GFX_ADDR_LUT_3_DEFAULT 0x00000003
+#define smnNBIF_GFX_ADDR_LUT_4_DEFAULT 0x00000004
+#define smnNBIF_GFX_ADDR_LUT_5_DEFAULT 0x00000005
+#define smnNBIF_GFX_ADDR_LUT_6_DEFAULT 0x00000006
+#define smnNBIF_GFX_ADDR_LUT_7_DEFAULT 0x00000007
+#define smnNBIF_GFX_ADDR_LUT_8_DEFAULT 0x00000008
+#define smnNBIF_GFX_ADDR_LUT_9_DEFAULT 0x00000009
+#define smnNBIF_GFX_ADDR_LUT_10_DEFAULT 0x0000000a
+#define smnNBIF_GFX_ADDR_LUT_11_DEFAULT 0x0000000b
+#define smnNBIF_GFX_ADDR_LUT_12_DEFAULT 0x0000000c
+#define smnNBIF_GFX_ADDR_LUT_13_DEFAULT 0x0000000d
+#define smnNBIF_GFX_ADDR_LUT_14_DEFAULT 0x0000000e
+#define smnNBIF_GFX_ADDR_LUT_15_DEFAULT 0x0000000f
+#define smnREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
+#define smnREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
+#define smnBIF_RB_CNTL_DEFAULT 0x00000000
+#define smnBIF_RB_BASE_DEFAULT 0x00000000
+#define smnBIF_RB_RPTR_DEFAULT 0x00000000
+#define smnBIF_RB_WPTR_DEFAULT 0x00000000
+#define smnBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
+#define smnMAILBOX_INDEX_DEFAULT 0x00000000
+#define smnBIF_MP1_INTR_CTRL_DEFAULT 0x00000000
+#define smnBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define smnBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define smnBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define smnBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
+#define smnBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
+#define smnBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
+#define smnBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
+#define smnBIF_PWRBRK_PAD_CNTL_DEFAULT 0x00000071
+#define smnBIF_WAKEB_PAD_CNTL_DEFAULT 0x00000031
+#define smnBIF_VAUX_PRESENT_PAD_CNTL_DEFAULT 0x0000000d
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+#define smnBIF_BME_STATUS_DEFAULT 0x00000000
+#define smnBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define smnDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define smnDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define smnDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define smnHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define smnHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define smnGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define smnGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define smnBIF_TRANS_PENDING_DEFAULT 0x00000000
+#define smnNBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define smnMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define smnMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define smnMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define smnMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define smnMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define smnMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define smnMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define smnMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define smnMAILBOX_CONTROL_DEFAULT 0x00000000
+#define smnMAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define smnBIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec
+#define smnSHADOW_COMMAND_DEFAULT 0x00000000
+#define smnSHADOW_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnSHADOW_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define smnSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define smnSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define smnSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define smnSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define smnSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define smnSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define smnSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define smnSUC_INDEX_DEFAULT 0x00000000
+#define smnSUC_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP8_DEFAULT 0x00000000
+#define smnRCC_DEV1_PORT_STRAP9_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP0_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP1_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP2_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP3_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP4_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP5_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP6_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP7_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP8_DEFAULT 0x00000000
+#define smnRCC_DEV2_PORT_STRAP9_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_BIF_STRAP0_DEFAULT 0x00040a00
+#define smnRCC_STRAP1_RCC_BIF_STRAP1_DEFAULT 0x00400108
+#define smnRCC_STRAP1_RCC_BIF_STRAP2_DEFAULT 0x000a0079
+#define smnRCC_STRAP1_RCC_BIF_STRAP3_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_BIF_STRAP4_DEFAULT 0x00100010
+#define smnRCC_STRAP1_RCC_BIF_STRAP5_DEFAULT 0x31130010
+#define smnRCC_STRAP1_RCC_BIF_STRAP6_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100
+#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
+#define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF2_STRAP0_DEFAULT 0x10007316
+#define smnRCC_DEV0_EPF2_STRAP2_DEFAULT 0x03002000
+#define smnRCC_DEV0_EPF2_STRAP3_DEFAULT 0x0815cc59
+#define smnRCC_DEV0_EPF2_STRAP4_DEFAULT 0x3c800000
+#define smnRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00001002
+#define smnRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000001
+#define smnRCC_DEV0_EPF2_STRAP7_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF2_STRAP13_DEFAULT 0x000c0330
+#define smnRCC_DEV0_EPF3_STRAP0_DEFAULT 0x10007314
+#define smnRCC_DEV0_EPF3_STRAP2_DEFAULT 0x01002000
+#define smnRCC_DEV0_EPF3_STRAP3_DEFAULT 0x0805cc51
+#define smnRCC_DEV0_EPF3_STRAP4_DEFAULT 0x40000000
+#define smnRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00001002
+#define smnRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000001
+#define smnRCC_DEV0_EPF3_STRAP7_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF3_STRAP13_DEFAULT 0x000c8000
+#define smnRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF4_STRAP7_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF5_STRAP7_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000
+#define smnRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000
+#define smnRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000
+#define smnRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000
+#define smnRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000
+#define smnRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000
+#define smnRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000
+#define smnRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000
+#define smnRCC_DEV1_EPF0_STRAP7_DEFAULT 0x00000000
+#define smnRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000
+#define smnRCC_DEV2_EPF0_STRAP0_DEFAULT 0x00000000
+#define smnRCC_DEV2_EPF0_STRAP2_DEFAULT 0x00000000
+#define smnRCC_DEV2_EPF0_STRAP3_DEFAULT 0x00000000
+#define smnRCC_DEV2_EPF0_STRAP4_DEFAULT 0x00000000
+#define smnRCC_DEV2_EPF0_STRAP5_DEFAULT 0x00000000
+#define smnRCC_DEV2_EPF0_STRAP6_DEFAULT 0x00000000
+#define smnRCC_DEV2_EPF0_STRAP7_DEFAULT 0x00000000
+#define smnRCC_DEV2_EPF0_STRAP13_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC
+#define smnRCC_DEV0_1_RCC_VDM_SUPPORT_DEFAULT 0x00000000
+#define smnRCC_DEV0_1_RCC_BUS_CNTL_DEFAULT 0x00000000
+#define smnRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
+#define smnRCC_DEV0_1_RCC_DEV0_LINK_CNTL_DEFAULT 0x00000000
+#define smnRCC_DEV0_1_RCC_CMN_LINK_CNTL_DEFAULT 0x00400000
+#define smnRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
+#define smnRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
+#define smnRCC_DEV0_1_RCC_MH_ARB_CNTL_DEFAULT 0x00000000
+#define smnRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df
+#define smnRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC
+#define smnRCC_EP_DEV0_1_EP_PCIE_SCRATCH_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define smnRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
+#define smnRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
+#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
+#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define smnRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIEP_RESERVED_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_DEFAULT 0x01000000
+#define smnRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC
+#define smnRCC_DWN_DEV0_1_DN_PCIE_RESERVED_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define smnRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_DEFAULT 0x00000001
+#define smnRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define smnRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC
+#define smnRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define smnRCC_DWNP_DEV0_1_PCIE_RX_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_DEFAULT 0x00000000
+#define smnRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk
+#define smnMISC_SCRATCH_DEFAULT 0x00000000
+#define smnINTR_LINE_POLARITY_DEFAULT 0x00000000
+#define smnINTR_LINE_ENABLE_DEFAULT 0x000000ff
+#define smnOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf
+#define smnBIFC_MISC_CTRL0_DEFAULT 0x08000024
+#define smnBIFC_MISC_CTRL1_DEFAULT 0x90108c04
+#define smnBIFC_BME_ERR_LOG_DEFAULT 0x00000000
+#define smnBIFC_RCCBIH_BME_ERR_LOG0_DEFAULT 0x00000000
+#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x80108010
+#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x80108010
+#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x80108010
+#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x80108010
+#define smnBIFC_DMA_ATTR_CNTL2_DEV0_DEFAULT 0x00000000
+#define smnBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa
+#define smnBIFC_THT_CNTL_DEFAULT 0x00000111
+#define smnBIFC_HSTARB_CNTL_DEFAULT 0x00000000
+#define smnBIFC_GSI_CNTL_DEFAULT 0x000057c0
+#define smnBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000
+#define smnBIFC_PASID_CHECK_DIS_DEFAULT 0x00000001
+#define smnBIFC_SDP_CNTL_0_DEFAULT 0x3f3f3f3f
+#define smnBIFC_SDP_CNTL_1_DEFAULT 0x00000000
+#define smnBIFC_PASID_STS_DEFAULT 0x00000002
+#define smnBIFC_ATHUB_ACT_CNTL_DEFAULT 0x00000004
+#define smnBIFC_PERF_CNTL_0_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNTL_1_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000
+#define smnBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000
+#define smnNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000
+#define smnNBIF_PGMST_CTRL_DEFAULT 0x00000000
+#define smnNBIF_PGSLV_CTRL_DEFAULT 0x00000004
+#define smnNBIF_PG_MISC_CTRL_DEFAULT 0x14006084
+#define smnSMN_MST_EP_CNTL3_DEFAULT 0x00000000
+#define smnSMN_MST_EP_CNTL4_DEFAULT 0x00000000
+#define smnSMN_MST_CNTL1_DEFAULT 0x00000000
+#define smnSMN_MST_EP_CNTL5_DEFAULT 0x00000000
+#define smnBIF_SELFRING_BUFFER_VID_DEFAULT 0x0061605f
+#define smnBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000
+#define smnNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000
+#define smnNBIF_INTX_DSTATE_MISC_CNTL_DEFAULT 0x00000000
+#define smnNBIF_PENDING_MISC_CNTL_DEFAULT 0x00000000
+#define smnBIF_GMI_WRR_WEIGHT_DEFAULT 0x00000000
+#define smnBIF_GMI_WRR_WEIGHT2_DEFAULT 0x04040404
+#define smnBIF_GMI_WRR_WEIGHT3_DEFAULT 0x04040404
+#define smnNBIF_PWRBRK_REQUEST_DEFAULT 0x00000000
+#define smnBIF_ATOMIC_ERR_LOG_DEV0_F0_DEFAULT 0x00000000
+#define smnBIF_ATOMIC_ERR_LOG_DEV0_F1_DEFAULT 0x00000000
+#define smnBIF_ATOMIC_ERR_LOG_DEV0_F2_DEFAULT 0x00000000
+#define smnBIF_ATOMIC_ERR_LOG_DEV0_F3_DEFAULT 0x00000000
+#define smnBIF_ATOMIC_ERR_LOG_DEV0_F4_DEFAULT 0x00000000
+#define smnBIF_ATOMIC_ERR_LOG_DEV0_F5_DEFAULT 0x00000000
+#define smnBIF_ATOMIC_ERR_LOG_DEV0_F6_DEFAULT 0x00000000
+#define smnBIF_ATOMIC_ERR_LOG_DEV0_F7_DEFAULT 0x00000000
+#define smnBIF_DMA_MP4_ERR_LOG_DEFAULT 0x00000000
+#define smnBIF_PASID_ERR_LOG_DEFAULT 0x00000000
+#define smnBIF_PASID_ERR_CLR_DEFAULT 0x00000000
+#define smnNBIF_VWIRE_CTRL_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000
+#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000
+#define smnNBIF_MGCG_CTRL_LCLK_DEFAULT 0x00000100
+#define smnNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000
+#define smnSMN_MST_CNTL0_DEFAULT 0x00000001
+#define smnSMN_MST_EP_CNTL1_DEFAULT 0x00000000
+#define smnSMN_MST_EP_CNTL2_DEFAULT 0x00000000
+#define smnNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
+#define smnNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
+#define smnNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000
+#define smnNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000
+#define smnBIFC_A2S_SDP_PORT_CTRL_DEFAULT 0x0000003f
+#define smnBIFC_A2S_CNTL_SW0_DEFAULT 0x04040000
+#define smnBIFC_A2S_MISC_CNTL_DEFAULT 0x0000000b
+#define smnBIFC_A2S_TAG_ALLOC_0_DEFAULT 0x00000000
+#define smnBIFC_A2S_TAG_ALLOC_1_DEFAULT 0x00000000
+#define smnBIFC_A2S_CNTL_CL0_DEFAULT 0x00282540
+#define smnBIFC_A2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC
+#define smnRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
+#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_usb_RCCPFCDEC
+#define smnRCC_PFC_USB_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
+#define smnRCC_PFC_USB_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
+#define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
+#define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
+#define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
+#define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
+#define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
+#define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
+#define smnRCC_PFC_USB_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_pd_controller_RCCPFCDEC
+#define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
+#define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
+#define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
+#define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
+#define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
+#define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
+#define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
+#define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
+#define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk
+#define smnHARD_RST_CTRL_DEFAULT 0xb0000055
+#define smnSELF_SOFT_RST_DEFAULT 0x00000000
+#define smnBIF_GFX_DRV_VPU_RST_DEFAULT 0x00000000
+#define smnBIF_RST_MISC_CTRL_DEFAULT 0x000e0648
+#define smnBIF_RST_MISC_CTRL2_DEFAULT 0x80070000
+#define smnBIF_RST_MISC_CTRL3_DEFAULT 0x00104900
+#define smnBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000
+#define smnDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x8206a0a9
+#define smnDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009
+#define smnBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_POWER_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000
+#define smnSELF_SOFT_RST_2_DEFAULT 0x00000000
+#define smnBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000
+#define smnBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff
+#define smnBIF_POWER_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000
+#define smnBIF_PF_FLR_RST_DEFAULT 0x00000000
+#define smnBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
+#define smnBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000
+#define smnBIF_USB_SHUB_RS_RESET_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
+#define smnBIFL_RAS_CENTRAL_CNTL_DEFAULT 0x00000000
+#define smnBIFL_RAS_CENTRAL_STATUS_DEFAULT 0x00000000
+#define smnBIFL_RAS_LEAF0_CTRL_DEFAULT 0x00000f61
+#define smnBIFL_RAS_LEAF1_CTRL_DEFAULT 0x00000f61
+#define smnBIFL_RAS_LEAF2_CTRL_DEFAULT 0x00000f61
+#define smnBIFL_RAS_LEAF3_CTRL_DEFAULT 0x00000f61
+#define smnBIFL_RAS_LEAF4_CTRL_DEFAULT 0x00000f61
+#define smnBIFL_RAS_LEAF0_STATUS_DEFAULT 0x00000000
+#define smnBIFL_RAS_LEAF1_STATUS_DEFAULT 0x00000000
+#define smnBIFL_RAS_LEAF2_STATUS_DEFAULT 0x00000000
+#define smnBIFL_RAS_LEAF3_STATUS_DEFAULT 0x00000000
+#define smnBIFL_RAS_LEAF4_STATUS_DEFAULT 0x00000000
+#define smnBIFL_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000
+#define smnBIFL_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_swus_SUMDEC
+#define smnSUM_INDEX_DEFAULT 0x00000000
+#define smnSUM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VENDOR_ID_DEFAULT 0x00001002
+#define smnBIF_CFG_DEV0_EPF0_DEVICE_ID_DEFAULT 0x00007310
+#define smnBIF_CFG_DEV0_EPF0_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_HEADER_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF0_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF0_INTERRUPT_PIN_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_ADAPTER_ID_W_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_PMI_CAP_LIST_DEFAULT 0x00006400
+#define smnBIF_CFG_DEV0_EPF0_PMI_CAP_DEFAULT 0x0000f000
+#define smnBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_CAP_DEFAULT 0x00000012
+#define smnBIF_CFG_DEV0_EPF0_DEVICE_CAP_DEFAULT 0x00000f81
+#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF0_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_LINK_CNTL2_DEFAULT 0x00000004
+#define smnBIF_CFG_DEV0_EPF0_LINK_STATUS2_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL_DEFAULT 0x00000084
+#define smnBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100
+#define smnBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000553
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025
+#define smnBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026
+#define smnBIF_CFG_DEV0_EPF0_LINK_CAP_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027
+#define smnBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF1_VENDOR_ID_DEFAULT 0x00001002
+#define smnBIF_CFG_DEV0_EPF1_DEVICE_ID_DEFAULT 0x0000ab38
+#define smnBIF_CFG_DEV0_EPF1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_HEADER_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_ADAPTER_ID_DEFAULT 0xab381002
+#define smnBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define smnBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF1_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_DEFAULT 0xab381002
+#define smnBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_DEFAULT 0x00006400
+#define smnBIF_CFG_DEV0_EPF1_PMI_CAP_DEFAULT 0x0000f000
+#define smnBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_CAP_DEFAULT 0x00000012
+#define smnBIF_CFG_DEV0_EPF1_DEVICE_CAP_DEFAULT 0x00000f81
+#define smnBIF_CFG_DEV0_EPF1_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF1_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF1_LINK_CNTL2_DEFAULT 0x00000004
+#define smnBIF_CFG_DEV0_EPF1_LINK_STATUS2_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100
+#define smnBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025
+#define smnBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026
+#define smnBIF_CFG_DEV0_EPF1_LINK_CAP_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define smnBIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027
+#define smnBIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define smnBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF2_VENDOR_ID_DEFAULT 0x00001002
+#define smnBIF_CFG_DEV0_EPF2_DEVICE_ID_DEFAULT 0x00007316
+#define smnBIF_CFG_DEV0_EPF2_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PROG_INTERFACE_DEFAULT 0x00000030
+#define smnBIF_CFG_DEV0_EPF2_SUB_CLASS_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF2_BASE_CLASS_DEFAULT 0x0000000c
+#define smnBIF_CFG_DEV0_EPF2_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_HEADER_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF2_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_ADAPTER_ID_DEFAULT 0x73161002
+#define smnBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF2_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_INTERRUPT_PIN_DEFAULT 0x00000003
+#define smnBIF_CFG_DEV0_EPF2_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_ADAPTER_ID_W_DEFAULT 0x73161002
+#define smnBIF_CFG_DEV0_EPF2_PMI_CAP_LIST_DEFAULT 0x00006400
+#define smnBIF_CFG_DEV0_EPF2_PMI_CAP_DEFAULT 0x0000c800
+#define smnBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_SBRN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_FLADJ_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF2_DBESL_DBESLD_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF2_DEVICE_CAP_DEFAULT 0x00000f81
+#define smnBIF_CFG_DEV0_EPF2_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF2_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF2_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF2_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF2_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF2_LINK_CNTL2_DEFAULT 0x00000004
+#define smnBIF_CFG_DEV0_EPF2_LINK_STATUS2_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF2_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL_DEFAULT 0x00000086
+#define smnBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_SATA_CAP_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_SATA_CAP_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_SATA_IDP_INDEX_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_SATA_IDP_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF3_VENDOR_ID_DEFAULT 0x00001002
+#define smnBIF_CFG_DEV0_EPF3_DEVICE_ID_DEFAULT 0x00007314
+#define smnBIF_CFG_DEV0_EPF3_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_SUB_CLASS_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF3_BASE_CLASS_DEFAULT 0x0000000c
+#define smnBIF_CFG_DEV0_EPF3_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_HEADER_DEFAULT 0x00000080
+#define smnBIF_CFG_DEV0_EPF3_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_ADAPTER_ID_DEFAULT 0x73141002
+#define smnBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF3_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_INTERRUPT_PIN_DEFAULT 0x00000004
+#define smnBIF_CFG_DEV0_EPF3_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_ADAPTER_ID_W_DEFAULT 0x73141002
+#define smnBIF_CFG_DEV0_EPF3_PMI_CAP_LIST_DEFAULT 0x00006400
+#define smnBIF_CFG_DEV0_EPF3_PMI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_SBRN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_FLADJ_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF3_DBESL_DBESLD_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF3_DEVICE_CAP_DEFAULT 0x00000f81
+#define smnBIF_CFG_DEV0_EPF3_DEVICE_CNTL_DEFAULT 0x00002810
+#define smnBIF_CFG_DEV0_EPF3_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF3_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_LINK_STATUS_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF3_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF3_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF3_LINK_CNTL2_DEFAULT 0x00000004
+#define smnBIF_CFG_DEV0_EPF3_LINK_STATUS2_DEFAULT 0x00000001
+#define smnBIF_CFG_DEV0_EPF3_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_SATA_CAP_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_SATA_CAP_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_SATA_IDP_INDEX_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_SATA_IDP_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define smnBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF16_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF16_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF17_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF17_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF18_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF18_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF19_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF19_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF20_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF20_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF21_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF21_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF22_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF22_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF23_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF23_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF24_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF24_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF25_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF25_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF26_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF26_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF27_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF27_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF28_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF28_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF29_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF29_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
+#define smnBIF_CFG_DEV0_EPF0_VF30_VENDOR_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_COMMAND_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_REVISION_ID_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_SUB_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_BASE_CLASS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_CACHE_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_HEADER_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_BIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID_DEFAULT 0x73101002
+#define smnBIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_CAP_PTR_DEFAULT 0x00000048
+#define smnBIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MIN_GRANT_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_DEFAULT 0x00000002
+#define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_LINK_CAP_DEFAULT 0x00000d04
+#define smnBIF_CFG_DEV0_EPF0_VF30_LINK_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_LINK_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2_DEFAULT 0x00010000
+#define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_LINK_CAP2_DEFAULT 0x0000001e
+#define smnBIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_MSIX_PBA_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_pciemsix_0_usb_MSIXTDEC
+#define smnPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT32_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT32_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT32_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT32_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT33_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT33_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT33_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT33_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT34_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT34_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT34_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT34_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT35_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT35_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT35_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT35_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT36_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT36_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT36_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT36_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT37_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT37_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT37_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT37_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT38_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT38_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT38_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT38_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT39_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT39_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT39_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT39_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT40_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT40_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT40_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT40_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT41_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT41_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT41_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT41_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT42_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT42_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT42_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT42_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT43_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT43_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT43_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT43_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT44_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT44_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT44_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT44_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT45_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT45_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT45_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT45_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT46_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT46_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT46_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT46_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT47_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT47_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT47_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT47_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT48_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT48_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT48_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT48_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT49_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT49_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT49_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT49_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT50_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT50_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT50_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT50_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT51_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT51_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT51_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT51_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT52_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT52_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT52_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT52_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT53_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT53_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT53_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT53_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT54_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT54_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT54_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT54_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT55_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT55_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT55_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT55_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT56_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT56_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT56_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT56_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT57_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT57_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT57_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT57_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT58_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT58_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT58_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT58_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT59_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT59_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT59_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT59_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT60_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT60_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT60_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT60_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT61_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT61_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT61_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT61_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT62_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT62_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT62_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT62_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT63_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT63_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT63_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT63_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT64_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT64_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT64_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT64_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT65_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT65_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT65_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT65_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT66_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT66_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT66_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT66_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT67_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT67_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT67_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT67_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT68_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT68_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT68_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT68_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT69_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT69_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT69_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT69_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT70_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT70_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT70_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT70_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT71_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT71_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT71_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT71_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT72_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT72_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT72_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT72_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT73_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT73_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT73_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT73_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT74_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT74_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT74_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT74_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT75_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT75_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT75_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT75_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT76_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT76_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT76_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT76_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT77_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT77_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT77_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT77_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT78_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT78_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT78_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT78_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT79_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT79_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT79_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT79_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT80_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT80_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT80_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT80_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT81_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT81_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT81_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT81_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT82_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT82_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT82_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT82_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT83_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT83_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT83_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT83_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT84_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT84_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT84_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT84_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT85_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT85_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT85_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT85_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT86_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT86_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT86_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT86_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT87_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT87_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT87_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT87_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT88_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT88_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT88_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT88_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT89_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT89_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT89_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT89_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT90_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT90_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT90_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT90_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT91_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT91_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT91_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT91_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT92_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT92_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT92_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT92_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT93_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT93_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT93_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT93_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT94_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT94_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT94_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT94_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT95_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT95_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT95_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT95_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT96_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT96_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT96_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT96_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT97_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT97_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT97_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT97_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT98_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT98_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT98_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT98_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT99_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT99_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT99_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT99_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT100_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT100_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT100_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT100_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT101_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT101_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT101_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT101_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT102_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT102_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT102_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT102_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT103_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT103_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT103_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT103_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT104_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT104_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT104_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT104_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT105_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT105_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT105_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT105_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT106_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT106_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT106_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT106_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT107_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT107_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT107_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT107_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT108_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT108_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT108_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT108_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT109_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT109_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT109_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT109_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT110_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT110_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT110_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT110_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT111_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT111_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT111_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT111_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT112_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT112_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT112_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT112_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT113_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT113_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT113_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT113_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT114_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT114_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT114_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT114_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT115_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT115_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT115_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT115_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT116_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT116_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT116_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT116_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT117_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT117_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT117_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT117_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT118_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT118_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT118_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT118_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT119_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT119_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT119_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT119_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT120_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT120_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT120_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT120_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT121_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT121_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT121_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT121_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT122_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT122_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT122_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT122_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT123_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT123_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT123_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT123_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT124_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT124_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT124_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT124_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT125_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT125_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT125_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT125_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT126_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT126_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT126_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT126_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT127_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT127_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT127_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT127_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT128_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT128_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT128_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT128_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT129_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT129_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT129_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT129_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT130_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT130_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT130_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT130_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT131_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT131_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT131_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT131_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT132_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT132_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT132_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT132_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT133_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT133_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT133_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT133_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT134_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT134_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT134_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT134_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT135_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT135_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT135_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT135_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT136_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT136_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT136_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT136_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT137_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT137_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT137_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT137_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT138_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT138_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT138_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT138_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT139_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT139_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT139_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT139_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT140_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT140_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT140_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT140_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT141_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT141_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT141_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT141_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT142_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT142_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT142_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT142_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT143_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT143_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT143_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT143_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT144_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT144_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT144_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT144_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT145_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT145_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT145_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT145_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT146_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT146_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT146_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT146_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT147_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT147_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT147_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT147_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT148_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT148_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT148_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT148_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT149_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT149_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT149_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT149_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT150_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT150_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT150_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT150_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT151_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT151_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT151_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT151_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT152_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT152_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT152_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT152_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT153_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT153_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT153_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT153_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT154_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT154_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT154_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT154_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT155_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT155_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT155_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT155_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT156_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT156_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT156_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT156_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT157_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT157_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT157_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT157_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT158_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT158_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT158_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT158_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT159_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT159_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT159_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT159_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT160_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT160_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT160_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT160_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT161_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT161_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT161_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT161_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT162_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT162_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT162_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT162_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT163_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT163_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT163_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT163_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT164_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT164_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT164_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT164_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT165_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT165_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT165_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT165_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT166_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT166_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT166_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT166_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT167_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT167_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT167_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT167_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT168_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT168_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT168_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT168_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT169_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT169_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT169_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT169_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT170_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT170_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT170_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT170_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT171_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT171_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT171_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT171_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT172_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT172_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT172_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT172_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT173_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT173_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT173_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT173_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT174_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT174_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT174_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT174_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT175_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT175_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT175_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT175_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT176_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT176_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT176_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT176_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT177_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT177_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT177_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT177_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT178_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT178_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT178_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT178_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT179_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT179_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT179_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT179_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT180_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT180_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT180_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT180_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT181_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT181_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT181_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT181_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT182_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT182_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT182_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT182_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT183_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT183_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT183_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT183_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT184_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT184_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT184_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT184_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT185_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT185_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT185_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT185_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT186_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT186_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT186_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT186_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT187_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT187_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT187_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT187_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT188_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT188_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT188_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT188_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT189_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT189_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT189_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT189_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT190_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT190_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT190_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT190_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT191_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT191_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT191_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT191_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT192_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT192_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT192_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT192_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT193_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT193_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT193_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT193_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT194_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT194_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT194_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT194_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT195_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT195_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT195_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT195_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT196_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT196_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT196_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT196_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT197_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT197_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT197_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT197_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT198_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT198_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT198_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT198_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT199_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT199_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT199_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT199_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT200_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT200_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT200_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT200_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT201_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT201_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT201_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT201_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT202_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT202_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT202_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT202_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT203_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT203_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT203_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT203_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT204_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT204_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT204_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT204_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT205_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT205_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT205_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT205_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT206_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT206_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT206_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT206_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT207_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT207_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT207_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT207_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT208_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT208_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT208_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT208_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT209_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT209_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT209_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT209_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT210_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT210_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT210_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT210_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT211_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT211_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT211_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT211_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT212_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT212_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT212_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT212_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT213_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT213_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT213_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT213_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT214_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT214_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT214_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT214_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT215_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT215_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT215_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT215_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT216_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT216_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT216_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT216_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT217_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT217_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT217_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT217_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT218_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT218_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT218_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT218_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT219_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT219_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT219_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT219_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT220_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT220_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT220_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT220_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT221_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT221_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT221_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT221_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT222_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT222_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT222_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT222_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT223_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT223_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT223_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT223_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT224_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT224_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT224_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT224_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT225_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT225_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT225_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT225_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT226_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT226_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT226_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT226_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT227_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT227_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT227_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT227_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT228_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT228_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT228_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT228_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT229_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT229_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT229_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT229_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT230_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT230_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT230_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT230_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT231_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT231_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT231_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT231_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT232_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT232_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT232_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT232_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT233_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT233_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT233_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT233_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT234_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT234_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT234_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT234_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT235_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT235_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT235_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT235_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT236_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT236_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT236_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT236_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT237_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT237_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT237_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT237_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT238_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT238_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT238_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT238_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT239_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT239_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT239_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT239_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT240_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT240_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT240_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT240_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT241_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT241_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT241_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT241_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT242_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT242_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT242_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT242_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT243_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT243_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT243_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT243_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT244_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT244_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT244_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT244_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT245_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT245_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT245_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT245_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT246_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT246_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT246_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT246_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT247_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT247_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT247_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT247_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT248_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT248_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT248_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT248_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT249_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT249_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT249_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT249_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT250_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT250_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT250_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT250_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT251_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT251_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT251_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT251_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT252_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT252_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT252_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT252_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT253_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT253_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT253_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT253_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT254_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT254_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT254_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT254_CONTROL_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT255_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT255_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT255_MSG_DATA_DEFAULT 0x00000000
+#define smnPCIEMSIX_VECT255_CONTROL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_pciemsix_0_usb_MSIXPDEC
+#define smnPCIEMSIX_PBA_0_DEFAULT 0x00000000
+#define smnPCIEMSIX_PBA_1_DEFAULT 0x00000000
+#define smnPCIEMSIX_PBA_2_DEFAULT 0x00000000
+#define smnPCIEMSIX_PBA_3_DEFAULT 0x00000000
+#define smnPCIEMSIX_PBA_4_DEFAULT 0x00000000
+#define smnPCIEMSIX_PBA_5_DEFAULT 0x00000000
+#define smnPCIEMSIX_PBA_6_DEFAULT 0x00000000
+#define smnPCIEMSIX_PBA_7_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_pcie0_pswusp0_pciedir_p
+#define smnPCIEP_RESERVED_DEFAULT 0x00000000
+#define smnPCIEP_SCRATCH_DEFAULT 0x00000000
+#define smnPCIEP_PORT_CNTL_DEFAULT 0x06000009
+#define smnPCIE_TX_CNTL_DEFAULT 0x00408000
+#define smnPCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
+#define smnPCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000
+#define smnPCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000
+#define smnPCIE_TX_SEQ_DEFAULT 0x00000000
+#define smnPCIE_TX_REPLAY_DEFAULT 0x00480003
+#define smnPCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000
+#define smnPCIE_TX_NOP_DLLP_DEFAULT 0x00000000
+#define smnPCIE_TX_CNTL_2_DEFAULT 0x00000004
+#define smnPCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000
+#define smnPCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333
+#define smnPCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000
+#define smnPCIE_FC_P_DEFAULT 0x00020008
+#define smnPCIE_FC_NP_DEFAULT 0x00020002
+#define smnPCIE_FC_CPL_DEFAULT 0x00000000
+#define smnPCIE_FC_P_VC1_DEFAULT 0x00020008
+#define smnPCIE_FC_NP_VC1_DEFAULT 0x00000000
+#define smnPCIE_FC_CPL_VC1_DEFAULT 0x00000000
+#define smnPSWUSP0_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define smnPSWUSP0_PCIE_RX_CNTL_DEFAULT 0x01084000
+#define smnPCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000
+#define smnPCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000
+#define smnPCIE_RX_CNTL3_DEFAULT 0x00000000
+#define smnPCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000
+#define smnPCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000
+#define smnPCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000
+#define smnPCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000
+#define smnPCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000
+#define smnPCIEP_SRIOV_PRIV_CTRL_DEFAULT 0x00000000
+#define smnPCIEP_NAK_COUNTER_DEFAULT 0x00000000
+#define smnPCIE_LC_CNTL_DEFAULT 0x40010050
+#define smnPCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880
+#define smnPCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006
+#define smnPCIE_LC_N_FTS_CNTL_DEFAULT 0x00ffc20c
+#define smnPSWUSP0_PCIE_LC_SPEED_CNTL_DEFAULT 0x10000200
+#define smnPCIE_LC_STATE0_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE1_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE2_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE3_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE4_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE5_DEFAULT 0x00000000
+#define smnPCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000
+#define smnPSWUSP0_PCIE_LC_CNTL2_DEFAULT 0x96180280
+#define smnPCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000
+#define smnPCIE_LC_CDR_CNTL_DEFAULT 0x01018060
+#define smnPCIE_LC_LANE_CNTL_DEFAULT 0x00000000
+#define smnPCIE_LC_CNTL3_DEFAULT 0xa850a020
+#define smnPCIE_LC_CNTL4_DEFAULT 0x0340048c
+#define smnPCIE_LC_CNTL5_DEFAULT 0x40200000
+#define smnPCIE_LC_FORCE_COEFF_DEFAULT 0x00080000
+#define smnPCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000
+#define smnPCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000
+#define smnPCIE_LC_CNTL6_DEFAULT 0x8a000090
+#define smnPCIE_LC_CNTL7_DEFAULT 0x010002ee
+#define smnPCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000
+#define smnPCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff
+#define smnPCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000
+#define smnPCIEP_STRAP_LC_DEFAULT 0x00000000
+#define smnPSWUSP0_PCIEP_STRAP_MISC_DEFAULT 0x00000000
+#define smnPCIEP_STRAP_LC2_DEFAULT 0x00000000
+#define smnPCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x04540000
+#define smnPCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000
+#define smnPCIE_LC_PORT_ORDER_DEFAULT 0x00000000
+#define smnPCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100
+#define smnPCIE_LC_CNTL8_DEFAULT 0x00400000
+#define smnPCIE_LC_CNTL9_DEFAULT 0xf0ffec00
+#define smnPCIE_LC_FORCE_COEFF2_DEFAULT 0x00080000
+#define smnPCIE_LC_FORCE_EQ_REQ_COEFF2_DEFAULT 0x00000000
+#define smnPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_DEFAULT 0x00000003
+#define smnPCIE_LC_CNTL10_DEFAULT 0x30000003
+#define smnPCIE_LC_CNTL11_DEFAULT 0x00602000
+#define smnPCIE_LC_CNTL12_DEFAULT 0x00000017
+#define smnPCIE_LC_SAVE_RESTORE_1_DEFAULT 0x00000000
+#define smnPCIE_LC_SAVE_RESTORE_2_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_pcie0_pciedir
+#define smnPCIE_RESERVED_DEFAULT 0x00000000
+#define smnPCIE_SCRATCH_DEFAULT 0x00000000
+#define smnPCIE_RX_NUM_NAK_DEFAULT 0x00000000
+#define smnPCIE_RX_NUM_NAK_GENERATED_DEFAULT 0x00000000
+#define smnPCIE_CNTL_DEFAULT 0x80811000
+#define smnPCIE_CONFIG_CNTL_DEFAULT 0x0000000f
+#define smnPCIE_DEBUG_CNTL_DEFAULT 0x00000001
+#define smnPCIE_TX_TRACKING_ADDR_LO_DEFAULT 0x00000000
+#define smnPCIE_TX_TRACKING_ADDR_HI_DEFAULT 0x00000000
+#define smnPCIE_TX_TRACKING_CTRL_STATUS_DEFAULT 0x00000000
+#define smnPCIE_BW_BY_UNITID_DEFAULT 0x00000000
+#define smnPCIE_CNTL2_DEFAULT 0x0e000109
+#define smnPCIE_RX_CNTL2_DEFAULT 0x00000000
+#define smnPCIE_TX_F0_ATTR_CNTL_DEFAULT 0x00000000
+#define smnPCIE_TX_SWUS_ATTR_CNTL_DEFAULT 0x00000000
+#define smnPCIE_CI_CNTL_DEFAULT 0x40000010
+#define smnPCIE_BUS_CNTL_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE6_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE7_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE8_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE9_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE10_DEFAULT 0x00000000
+#define smnPCIE_LC_STATE11_DEFAULT 0x00000000
+#define smnPCIE_LC_STATUS1_DEFAULT 0x00000000
+#define smnPCIE_LC_STATUS2_DEFAULT 0x00000000
+#define smnPCIE_TX_CNTL3_DEFAULT 0x001808c0
+#define smnPCIE_TX_STATUS_DEFAULT 0x00000000
+#define smnPCIE_WPR_CNTL_DEFAULT 0x00000005
+#define smnPCIE_RX_LAST_TLP0_DEFAULT 0x00000000
+#define smnPCIE_RX_LAST_TLP1_DEFAULT 0x00000000
+#define smnPCIE_RX_LAST_TLP2_DEFAULT 0x00000000
+#define smnPCIE_RX_LAST_TLP3_DEFAULT 0x00000000
+#define smnPCIE_TX_LAST_TLP0_DEFAULT 0x00000000
+#define smnPCIE_TX_LAST_TLP1_DEFAULT 0x00000000
+#define smnPCIE_TX_LAST_TLP2_DEFAULT 0x00000000
+#define smnPCIE_TX_LAST_TLP3_DEFAULT 0x00000000
+#define smnPCIE_I2C_REG_ADDR_EXPAND_DEFAULT 0x00000000
+#define smnPCIE_I2C_REG_DATA_DEFAULT 0x00000000
+#define smnPCIE_CFG_CNTL_DEFAULT 0x00000000
+#define smnPCIE_LC_PM_CNTL_DEFAULT 0x76543210
+#define smnPCIE_LC_PORT_ORDER_CNTL_DEFAULT 0x00000000
+#define smnPCIE_P_CNTL_DEFAULT 0x00850000
+#define smnPCIE_P_BUF_STATUS_DEFAULT 0x00000000
+#define smnPCIE_P_DECODER_STATUS_DEFAULT 0x00000000
+#define smnPCIE_P_MISC_STATUS_DEFAULT 0x00000000
+#define smnPCIE_P_RCV_L0S_FTS_DET_DEFAULT 0x000000ff
+#define smnPCIE_RX_AD_DEFAULT 0x00000003
+#define smnPCIE_SDP_CTRL_DEFAULT 0x00000002
+#define smnPCIE_SDP_SWUS_SLV_ATTR_CTRL_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT_CNTL_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_TXCLK1_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_TXCLK1_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_TXCLK1_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_TXCLK2_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_TXCLK2_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_TXCLK2_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_TXCLK3_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_TXCLK3_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_TXCLK3_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_TXCLK4_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_TXCLK4_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_TXCLK4_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_SCLK1_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_SCLK1_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_SCLK1_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_SCLK2_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT0_SCLK2_DEFAULT 0x00000000
+#define smnPCIE_PERF_COUNT1_SCLK2_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL_DEFAULT 0x00000000
+#define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL_DEFAULT 0x00000000
+#define smnPCIE_HIP_REG0_DEFAULT 0x00000000
+#define smnPCIE_HIP_REG1_DEFAULT 0x00000000
+#define smnPCIE_HIP_REG2_DEFAULT 0x00000000
+#define smnPCIE_HIP_REG3_DEFAULT 0x00000000
+#define smnPCIE_HIP_REG4_DEFAULT 0x00000000
+#define smnPCIE_HIP_REG5_DEFAULT 0x00000000
+#define smnPCIE_HIP_REG6_DEFAULT 0x00000000
+#define smnPCIE_HIP_REG7_DEFAULT 0x00000000
+#define smnPCIE_HIP_REG8_DEFAULT 0x00008000
+#define smnPCIE_STRAP_F0_DEFAULT 0x00000000
+#define smnPCIE_STRAP_MISC_DEFAULT 0x00000000
+#define smnPCIE_STRAP_MISC2_DEFAULT 0x00000000
+#define smnPCIE_STRAP_PI_DEFAULT 0x00000000
+#define smnPCIE_STRAP_I2C_BD_DEFAULT 0x00000000
+#define smnPCIE_PRBS_CLR_DEFAULT 0x00000000
+#define smnPCIE_PRBS_STATUS1_DEFAULT 0x00000000
+#define smnPCIE_PRBS_STATUS2_DEFAULT 0x00000000
+#define smnPCIE_PRBS_FREERUN_DEFAULT 0x00000000
+#define smnPCIE_PRBS_MISC_DEFAULT 0x00000000
+#define smnPCIE_PRBS_USER_PATTERN_DEFAULT 0x00000000
+#define smnPCIE_PRBS_LO_BITCNT_DEFAULT 0x00000000
+#define smnPCIE_PRBS_HI_BITCNT_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_0_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_1_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_2_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_3_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_4_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_5_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_6_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_7_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_8_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_9_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_10_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_11_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_12_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_13_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_14_DEFAULT 0x00000000
+#define smnPCIE_PRBS_ERRCNT_15_DEFAULT 0x00000000
+#define smnSWRST_COMMAND_STATUS_DEFAULT 0x00000000
+#define smnSWRST_GENERAL_CONTROL_DEFAULT 0x02001002
+#define smnSWRST_COMMAND_0_DEFAULT 0x00000000
+#define smnSWRST_COMMAND_1_DEFAULT 0x04000000
+#define smnSWRST_CONTROL_0_DEFAULT 0x5600ff00
+#define smnSWRST_CONTROL_1_DEFAULT 0xc220ffff
+#define smnSWRST_CONTROL_2_DEFAULT 0x00000000
+#define smnSWRST_CONTROL_3_DEFAULT 0x00000000
+#define smnSWRST_CONTROL_4_DEFAULT 0x5c00ff01
+#define smnSWRST_CONTROL_5_DEFAULT 0xfe20ffff
+#define smnSWRST_CONTROL_6_DEFAULT 0x000007ff
+#define smnSWRST_EP_COMMAND_0_DEFAULT 0x00000000
+#define smnSWRST_EP_CONTROL_0_DEFAULT 0x00000500
+#define smnCPM_CONTROL_DEFAULT 0x0080ca00
+#define smnCPM_SPLIT_CONTROL_DEFAULT 0x00000000
+#define smnSMN_APERTURE_ID_A_DEFAULT 0x00000000
+#define smnSMN_APERTURE_ID_B_DEFAULT 0x00000000
+#define smnLNCNT_CONTROL_DEFAULT 0x00000000
+#define smnLNCNT_QUAN_THRD_DEFAULT 0x00000000
+#define smnLNCNT_WEIGHT_DEFAULT 0x00000000
+#define smnSMU_INT_PIN_SHARING_PORT_INDICATOR_DEFAULT 0x00000000
+#define smnPCIE_PGMST_CNTL_DEFAULT 0x00000000
+#define smnPCIE_PGSLV_CNTL_DEFAULT 0x00000004
+#define smnLC_CPM_CONTROL_0_DEFAULT 0x00000000
+#define smnLC_CPM_CONTROL_1_DEFAULT 0x00000001
+#define smnPCIE_RXMARGIN_CONTROL_CAPABILITIES_DEFAULT 0x00000000
+#define smnPCIE_RXMARGIN_1_SETTINGS_DEFAULT 0x00000000
+#define smnPCIE_RXMARGIN_2_SETTINGS_DEFAULT 0x00000000
+#define smnPCIE_PRESENCE_DETECT_SELECT_DEFAULT 0x00000000
+#define smnPCIE_LC_DEBUG_CNTL_DEFAULT 0x00010000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
+#define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS_DEFAULT 0x00000006
+#define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_DEFAULT 0x0000c800
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_DEFAULT 0x00000062
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_DEFAULT 0x00002001
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000
+#define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c000000
+#define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC
+#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1
+#define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF24_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF25_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF26_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF27_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF28_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF29_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC
+#define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1
+#define cfgRCC_DEV0_EPF0_VF30_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1
+#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_PBA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp
+#define cfgPSWUSCFG0_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_COMMAND_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LATENCY_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_HEADER_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_BIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_SECONDARY_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_CAP_PTR_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_ADAPTER_ID_W_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PMI_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PMI_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgPSWUSCFG0_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgPSWUSCFG0_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_DEVICE_CNTL_DEFAULT 0x00002910
+#define cfgPSWUSCFG0_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LINK_CAP_DEFAULT 0x00011c04
+#define cfgPSWUSCFG0_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LINK_STATUS_DEFAULT 0x00000001
+#define cfgPSWUSCFG0_1_DEVICE_CAP2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgPSWUSCFG0_1_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgPSWUSCFG0_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgPSWUSCFG0_1_MSI_MSG_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_SSID_CAP_LIST_DEFAULT 0x0000c800
+#define cfgPSWUSCFG0_1_SSID_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MSI_MAP_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002
+#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002
+#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000
+#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x04400000
+#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
+#define cfgPSWUSCFG0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgPSWUSCFG0_1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgPSWUSCFG0_1_PCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgPSWUSCFG0_1_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x38000000
+#define cfgPSWUSCFG0_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x3c400000
+#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_LIST_DEFAULT 0x40000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_CTRL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000
+#define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP_DEFAULT 0x80000001
+#define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000
+#define cfgPSWUSCFG0_1_LINK_CAP_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CCIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_1_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_2_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CCIX_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_STATUS_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_CNTL_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff
+#define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CAP_DEFAULT 0x00000000
+#define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1
+#define cfgBIF_BX_PF0_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_PF0_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_PF0_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_swus_SUMDEC
+#define cfgSUM_INDEX_DEFAULT 0x00000000
+#define cfgSUM_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
+#define cfgBIF_CFG_DEV0_SWDS1_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SUB_CLASS_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_SWDS1_BASE_CLASS_DEFAULT 0x00000006
+#define cfgBIF_CFG_DEV0_SWDS1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SECONDARY_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_CAP_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP_DEFAULT 0x0000c800
+#define cfgBIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP_DEFAULT 0x00000062
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS_DEFAULT 0x00002001
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000
+#define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c000000
+#define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID_DEFAULT 0x00007310
+#define cfgBIF_CFG_DEV0_EPF0_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_HEADER_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF0_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST_DEFAULT 0x00006400
+#define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_DEFAULT 0x0000f000
+#define cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_DEFAULT 0x00000012
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP_DEFAULT 0x00000f81
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL_DEFAULT 0x00000084
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000553
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025
+#define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027
+#define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID_DEFAULT 0x0000ab38
+#define cfgBIF_CFG_DEV0_EPF1_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_HEADER_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF1_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_DEFAULT 0xab381002
+#define cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE_DEFAULT 0x000000ff
+#define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W_DEFAULT 0xab381002
+#define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST_DEFAULT 0x00006400
+#define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_DEFAULT 0x0000f000
+#define cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_DEFAULT 0x00000012
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP_DEFAULT 0x00000f81
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025
+#define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027
+#define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID_DEFAULT 0x00007316
+#define cfgBIF_CFG_DEV0_EPF2_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE_DEFAULT 0x00000030
+#define cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS_DEFAULT 0x0000000c
+#define cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_HEADER_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF2_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_DEFAULT 0x73161002
+#define cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN_DEFAULT 0x00000003
+#define cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W_DEFAULT 0x73161002
+#define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST_DEFAULT 0x00006400
+#define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_DEFAULT 0x0000c800
+#define cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_SBRN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_FLADJ_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP_DEFAULT 0x00000f81
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL_DEFAULT 0x00000086
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID_DEFAULT 0x00001002
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID_DEFAULT 0x00007314
+#define cfgBIF_CFG_DEV0_EPF3_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS_DEFAULT 0x0000000c
+#define cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_HEADER_DEFAULT 0x00000080
+#define cfgBIF_CFG_DEV0_EPF3_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_DEFAULT 0x73141002
+#define cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W_DEFAULT 0x73141002
+#define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST_DEFAULT 0x00006400
+#define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_SBRN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_FLADJ_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP_DEFAULT 0x00000f81
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL_DEFAULT 0x00002810
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2_DEFAULT 0x00000004
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2_DEFAULT 0x00000001
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS_DEFAULT 0x00000100
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP_DEFAULT 0x00001000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_COMMAND_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_HEADER_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID_DEFAULT 0x73101002
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR_DEFAULT 0x00000048
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_DEFAULT 0x00000002
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP_DEFAULT 0x00000d04
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2_DEFAULT 0x00010000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2_DEFAULT 0x0000001e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST_DEFAULT 0x0000c000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL_DEFAULT 0x00000082
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP_DEFAULT 0x00000000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec
+#define cfgSHADOW_COMMAND_DEFAULT 0x00000000
+#define cfgSHADOW_BASE_ADDR_1_DEFAULT 0x00000000
+#define cfgSHADOW_BASE_ADDR_2_DEFAULT 0x00000000
+#define cfgSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
+#define cfgSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000
+#define cfgSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000
+#define cfgSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000
+#define cfgSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
+#define cfgSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
+#define cfgSUC_INDEX_DEFAULT 0x00000000
+#define cfgSUC_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+#define cfgBIF_BX_PF1_MM_INDEX_DEFAULT 0x00000000
+#define cfgBIF_BX_PF1_MM_DATA_DEFAULT 0x00000000
+#define cfgBIF_BX_PF1_MM_INDEX_HI_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+#define cfgSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
+#define cfgSYSHUB_DATA_OVLP_DEFAULT 0x00000000
+#define cfgPCIE_INDEX_DEFAULT 0x00000000
+#define cfgPCIE_DATA_DEFAULT 0x00000000
+#define cfgPCIE_INDEX2_DEFAULT 0x00000000
+#define cfgPCIE_DATA2_DEFAULT 0x00000000
+#define cfgSBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define cfgSBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define cfgSBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define cfgSBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_0_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_1_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_2_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_3_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_4_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_5_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_6_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_7_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_8_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_9_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_10_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_11_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_12_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_13_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_14_DEFAULT 0x00000000
+#define cfgBIOS_SCRATCH_15_DEFAULT 0x00000000
+#define cfgBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
+#define cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
+#define cfgSYSHUB_INDEX_DEFAULT 0x00000000
+#define cfgSYSHUB_DATA_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+#define cfgRCC_BIF_STRAP0_DEFAULT 0x00040a00
+#define cfgRCC_BIF_STRAP1_DEFAULT 0x00400108
+#define cfgRCC_BIF_STRAP2_DEFAULT 0x000a0079
+#define cfgRCC_BIF_STRAP3_DEFAULT 0x00000000
+#define cfgRCC_BIF_STRAP4_DEFAULT 0x00100010
+#define cfgRCC_BIF_STRAP5_DEFAULT 0x31130010
+#define cfgRCC_BIF_STRAP6_DEFAULT 0x00000000
+#define cfgRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20
+#define cfgRCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479
+#define cfgRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009
+#define cfgRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
+#define cfgRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
+#define cfgRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
+#define cfgRCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02
+#define cfgRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
+#define cfgRCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000
+#define cfgRCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310
+#define cfgRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
+#define cfgRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000
+#define cfgRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41
+#define cfgRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000
+#define cfgRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002
+#define cfgRCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001
+#define cfgRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100
+#define cfgRCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38
+#define cfgRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000
+#define cfgRCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1
+#define cfgRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000
+#define cfgRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002
+#define cfgRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+#define cfgEP_PCIE_SCRATCH_DEFAULT 0x00000000
+#define cfgEP_PCIE_CNTL_DEFAULT 0x00000000
+#define cfgEP_PCIE_INT_CNTL_DEFAULT 0x00000000
+#define cfgEP_PCIE_INT_STATUS_DEFAULT 0x00000000
+#define cfgEP_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define cfgEP_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define cfgEP_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define cfgEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define cfgEP_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define cfgEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+#define cfgEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
+#define cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
+#define cfgEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
+#define cfgEP_PCIE_PME_CONTROL_DEFAULT 0x00000000
+#define cfgEP_PCIEP_RESERVED_DEFAULT 0x00000000
+#define cfgEP_PCIE_TX_CNTL_DEFAULT 0x00000000
+#define cfgEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
+#define cfgEP_PCIE_ERR_CNTL_DEFAULT 0x00000500
+#define cfgEP_PCIE_RX_CNTL_DEFAULT 0x01000000
+#define cfgEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+#define cfgDN_PCIE_RESERVED_DEFAULT 0x00000000
+#define cfgDN_PCIE_SCRATCH_DEFAULT 0x00000000
+#define cfgDN_PCIE_CNTL_DEFAULT 0x00000000
+#define cfgDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
+#define cfgDN_PCIE_RX_CNTL2_DEFAULT 0x00000000
+#define cfgDN_PCIE_BUS_CNTL_DEFAULT 0x00000080
+#define cfgDN_PCIE_CFG_CNTL_DEFAULT 0x00000000
+#define cfgDN_PCIE_STRAP_F0_DEFAULT 0x00000001
+#define cfgDN_PCIE_STRAP_MISC_DEFAULT 0x00000000
+#define cfgDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+#define cfgPCIE_ERR_CNTL_DEFAULT 0x00000500
+#define cfgPCIE_RX_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
+#define cfgPCIE_LC_CNTL2_DEFAULT 0x00000000
+#define cfgPCIEP_STRAP_MISC_DEFAULT 0x00000000
+#define cfgLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
+#define cfgRCC_DEV0_EPF0_RCC_ERR_LOG_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+#define cfgRCC_ERR_INT_CNTL_DEFAULT 0x00000000
+#define cfgRCC_BACO_CNTL_MISC_DEFAULT 0x00000000
+#define cfgRCC_RESET_EN_DEFAULT 0x00008000
+#define cfgRCC_VDM_SUPPORT_DEFAULT 0x00000000
+#define cfgRCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df
+#define cfgRCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000
+#define cfgRCC_GPUIOV_REGION_DEFAULT 0x00000000
+#define cfgRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000
+#define cfgRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000
+#define cfgRCC_BUS_CNTL_DEFAULT 0x00000000
+#define cfgRCC_CONFIG_CNTL_DEFAULT 0x00000000
+#define cfgRCC_CONFIG_F0_BASE_DEFAULT 0x00000000
+#define cfgRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000
+#define cfgRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000
+#define cfgRCC_XDMA_LO_DEFAULT 0x00000000
+#define cfgRCC_XDMA_HI_DEFAULT 0x00000000
+#define cfgRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
+#define cfgRCC_BUSNUM_CNTL1_DEFAULT 0x00000000
+#define cfgRCC_BUSNUM_LIST0_DEFAULT 0x00000000
+#define cfgRCC_BUSNUM_LIST1_DEFAULT 0x00000000
+#define cfgRCC_BUSNUM_CNTL2_DEFAULT 0x00000000
+#define cfgRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000
+#define cfgRCC_HOST_BUSNUM_DEFAULT 0x00000000
+#define cfgRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000
+#define cfgRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000
+#define cfgRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000
+#define cfgRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000
+#define cfgRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000
+#define cfgRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000
+#define cfgRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000
+#define cfgRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000
+#define cfgRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000
+#define cfgRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000
+#define cfgRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000
+#define cfgRCC_CMN_LINK_CNTL_DEFAULT 0x00400000
+#define cfgRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
+#define cfgRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
+#define cfgRCC_MH_ARB_CNTL_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+#define cfgCC_BIF_BX_STRAP0_DEFAULT 0x00000000
+#define cfgCC_BIF_BX_PINSTRAP0_DEFAULT 0x00000000
+#define cfgBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
+#define cfgBUS_CNTL_DEFAULT 0x00000000
+#define cfgBIF_SCRATCH0_DEFAULT 0x00000000
+#define cfgBIF_SCRATCH1_DEFAULT 0x00000000
+#define cfgBX_RESET_EN_DEFAULT 0x00010000
+#define cfgMM_CFGREGS_CNTL_DEFAULT 0x00000000
+#define cfgBX_RESET_CNTL_DEFAULT 0x00000000
+#define cfgINTERRUPT_CNTL_DEFAULT 0x00000000
+#define cfgINTERRUPT_CNTL2_DEFAULT 0x00000000
+#define cfgCLKREQB_PAD_CNTL_DEFAULT 0x000008e0
+#define cfgBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00800000
+#define cfgBIF_DOORBELL_CNTL_DEFAULT 0x00000000
+#define cfgBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_FB_EN_DEFAULT 0x00000000
+#define cfgBIF_INTR_CNTL_DEFAULT 0x00000000
+#define cfgBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define cfgBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
+#define cfgBACO_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
+#define cfgBIF_BACO_EXIT_TIMER1_DEFAULT 0x1c000200
+#define cfgBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
+#define cfgBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500
+#define cfgBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400
+#define cfgMEM_TYPE_CNTL_DEFAULT 0x00000000
+#define cfgNBIF_GFX_ADDR_LUT_CNTL_DEFAULT 0x00000000
+#define cfgNBIF_GFX_ADDR_LUT_0_DEFAULT 0x00000000
+#define cfgNBIF_GFX_ADDR_LUT_1_DEFAULT 0x00000001
+#define cfgNBIF_GFX_ADDR_LUT_2_DEFAULT 0x00000002
+#define cfgNBIF_GFX_ADDR_LUT_3_DEFAULT 0x00000003
+#define cfgNBIF_GFX_ADDR_LUT_4_DEFAULT 0x00000004
+#define cfgNBIF_GFX_ADDR_LUT_5_DEFAULT 0x00000005
+#define cfgNBIF_GFX_ADDR_LUT_6_DEFAULT 0x00000006
+#define cfgNBIF_GFX_ADDR_LUT_7_DEFAULT 0x00000007
+#define cfgNBIF_GFX_ADDR_LUT_8_DEFAULT 0x00000008
+#define cfgNBIF_GFX_ADDR_LUT_9_DEFAULT 0x00000009
+#define cfgNBIF_GFX_ADDR_LUT_10_DEFAULT 0x0000000a
+#define cfgNBIF_GFX_ADDR_LUT_11_DEFAULT 0x0000000b
+#define cfgNBIF_GFX_ADDR_LUT_12_DEFAULT 0x0000000c
+#define cfgNBIF_GFX_ADDR_LUT_13_DEFAULT 0x0000000d
+#define cfgNBIF_GFX_ADDR_LUT_14_DEFAULT 0x0000000e
+#define cfgNBIF_GFX_ADDR_LUT_15_DEFAULT 0x0000000f
+#define cfgREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
+#define cfgREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
+#define cfgBIF_RB_CNTL_DEFAULT 0x00000000
+#define cfgBIF_RB_BASE_DEFAULT 0x00000000
+#define cfgBIF_RB_RPTR_DEFAULT 0x00000000
+#define cfgBIF_RB_WPTR_DEFAULT 0x00000000
+#define cfgBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
+#define cfgBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
+#define cfgMAILBOX_INDEX_DEFAULT 0x00000000
+#define cfgBIF_MP1_INTR_CTRL_DEFAULT 0x00000000
+#define cfgBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define cfgBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
+#define cfgBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
+#define cfgBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
+#define cfgBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
+#define cfgBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
+#define cfgBIF_PWRBRK_PAD_CNTL_DEFAULT 0x00000071
+#define cfgBIF_WAKEB_PAD_CNTL_DEFAULT 0x00000031
+#define cfgBIF_VAUX_PRESENT_PAD_CNTL_DEFAULT 0x0000000d
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+#define cfgBIF_BX_PF_BIF_BME_STATUS_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
+#define cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_BIF_TRANS_PENDING_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_CONTROL_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_MAILBOX_INT_CNTL_DEFAULT 0x00000000
+#define cfgBIF_BX_PF_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+#define cfgA2S_CNTL_CL0_DEFAULT 0x02a80540
+#define cfgA2S_CNTL_CL1_DEFAULT 0x02a825a0
+#define cfgA2S_CNTL3_CL0_DEFAULT 0x00000000
+#define cfgA2S_CNTL3_CL1_DEFAULT 0x00000008
+#define cfgA2S_CNTL_SW0_DEFAULT 0x04040000
+#define cfgA2S_CNTL_SW1_DEFAULT 0x04040200
+#define cfgA2S_CNTL_SW2_DEFAULT 0x04040200
+#define cfgA2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001
+#define cfgA2S_TAG_ALLOC_0_DEFAULT 0x00000000
+#define cfgA2S_TAG_ALLOC_1_DEFAULT 0x00000000
+#define cfgA2S_MISC_CNTL_DEFAULT 0x0005000b
+#define cfgNGDC_SDP_PORT_CTRL_DEFAULT 0x0000003f
+#define cfgSHUB_REGS_IF_CTL_DEFAULT 0x00000000
+#define cfgNGDC_MGCG_CTRL_DEFAULT 0x00000100
+#define cfgNGDC_RESERVED_0_DEFAULT 0x00000000
+#define cfgNGDC_RESERVED_1_DEFAULT 0x00000000
+#define cfgNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000003f
+#define cfgBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define cfgBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
+#define cfgBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
+#define cfgBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
+#define cfgBIF_ACV_DOORBELL_RANGE_DEFAULT 0x00000000
+#define cfgBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
+#define cfgS2A_MISC_CNTL_DEFAULT 0x00000000
+#define cfgNGDC_PG_MISC_CTRL_DEFAULT 0x14006000
+#define cfgNGDC_PGMST_CTRL_DEFAULT 0x00000000
+#define cfgNGDC_PGSLV_CTRL_DEFAULT 0x00001084
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001
+#define cfgRCC_DEV0_EPF0_GFXMSIX_PBA_DEFAULT 0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h
new file mode 100644
index 000000000000..944e1548f638
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h
@@ -0,0 +1,14663 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_2_3_OFFSET_HEADER
+#define _nbio_2_3_OFFSET_HEADER
+
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_PF_MM_INDEX 0x0000
+#define mmBIF_BX_PF_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_PF_MM_DATA 0x0001
+#define mmBIF_BX_PF_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_PF_MM_INDEX_HI 0x0006
+#define mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+// base address: 0x0
+#define mmSYSHUB_INDEX_OVLP 0x0008
+#define mmSYSHUB_INDEX_OVLP_BASE_IDX 0
+#define mmSYSHUB_DATA_OVLP 0x0009
+#define mmSYSHUB_DATA_OVLP_BASE_IDX 0
+#define mmPCIE_INDEX 0x000c
+#define mmPCIE_INDEX_BASE_IDX 0
+#define mmPCIE_DATA 0x000d
+#define mmPCIE_DATA_BASE_IDX 0
+#define mmPCIE_INDEX2 0x000e
+#define mmPCIE_INDEX2_BASE_IDX 0
+#define mmPCIE_DATA2 0x000f
+#define mmPCIE_DATA2_BASE_IDX 0
+#define mmSBIOS_SCRATCH_0 0x0034
+#define mmSBIOS_SCRATCH_0_BASE_IDX 1
+#define mmSBIOS_SCRATCH_1 0x0035
+#define mmSBIOS_SCRATCH_1_BASE_IDX 1
+#define mmSBIOS_SCRATCH_2 0x0036
+#define mmSBIOS_SCRATCH_2_BASE_IDX 1
+#define mmSBIOS_SCRATCH_3 0x0037
+#define mmSBIOS_SCRATCH_3_BASE_IDX 1
+#define mmBIOS_SCRATCH_0 0x0038
+#define mmBIOS_SCRATCH_0_BASE_IDX 1
+#define mmBIOS_SCRATCH_1 0x0039
+#define mmBIOS_SCRATCH_1_BASE_IDX 1
+#define mmBIOS_SCRATCH_2 0x003a
+#define mmBIOS_SCRATCH_2_BASE_IDX 1
+#define mmBIOS_SCRATCH_3 0x003b
+#define mmBIOS_SCRATCH_3_BASE_IDX 1
+#define mmBIOS_SCRATCH_4 0x003c
+#define mmBIOS_SCRATCH_4_BASE_IDX 1
+#define mmBIOS_SCRATCH_5 0x003d
+#define mmBIOS_SCRATCH_5_BASE_IDX 1
+#define mmBIOS_SCRATCH_6 0x003e
+#define mmBIOS_SCRATCH_6_BASE_IDX 1
+#define mmBIOS_SCRATCH_7 0x003f
+#define mmBIOS_SCRATCH_7_BASE_IDX 1
+#define mmBIOS_SCRATCH_8 0x0040
+#define mmBIOS_SCRATCH_8_BASE_IDX 1
+#define mmBIOS_SCRATCH_9 0x0041
+#define mmBIOS_SCRATCH_9_BASE_IDX 1
+#define mmBIOS_SCRATCH_10 0x0042
+#define mmBIOS_SCRATCH_10_BASE_IDX 1
+#define mmBIOS_SCRATCH_11 0x0043
+#define mmBIOS_SCRATCH_11_BASE_IDX 1
+#define mmBIOS_SCRATCH_12 0x0044
+#define mmBIOS_SCRATCH_12_BASE_IDX 1
+#define mmBIOS_SCRATCH_13 0x0045
+#define mmBIOS_SCRATCH_13_BASE_IDX 1
+#define mmBIOS_SCRATCH_14 0x0046
+#define mmBIOS_SCRATCH_14_BASE_IDX 1
+#define mmBIOS_SCRATCH_15 0x0047
+#define mmBIOS_SCRATCH_15_BASE_IDX 1
+#define mmBIF_RLC_INTR_CNTL 0x004c
+#define mmBIF_RLC_INTR_CNTL_BASE_IDX 1
+#define mmBIF_VCE_INTR_CNTL 0x004d
+#define mmBIF_VCE_INTR_CNTL_BASE_IDX 1
+#define mmBIF_UVD_INTR_CNTL 0x004e
+#define mmBIF_UVD_INTR_CNTL_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR0 0x006c
+#define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR1 0x006e
+#define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR2 0x0070
+#define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR3 0x0072
+#define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR4 0x0074
+#define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR5 0x0076
+#define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR6 0x0078
+#define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ADDR7 0x007a
+#define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b
+#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_CNTL 0x007c
+#define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d
+#define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e
+#define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1
+#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f
+#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
+// base address: 0x0
+#define mmSYSHUB_INDEX 0x0008
+#define mmSYSHUB_INDEX_BASE_IDX 0
+#define mmSYSHUB_DATA 0x0009
+#define mmSYSHUB_DATA_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+// base address: 0x0
+#define mmRCC_BIF_STRAP0 0x0000
+#define mmRCC_BIF_STRAP0_BASE_IDX 2
+#define mmRCC_BIF_STRAP1 0x0001
+#define mmRCC_BIF_STRAP1_BASE_IDX 2
+#define mmRCC_BIF_STRAP2 0x0002
+#define mmRCC_BIF_STRAP2_BASE_IDX 2
+#define mmRCC_BIF_STRAP3 0x0003
+#define mmRCC_BIF_STRAP3_BASE_IDX 2
+#define mmRCC_BIF_STRAP4 0x0004
+#define mmRCC_BIF_STRAP4_BASE_IDX 2
+#define mmRCC_BIF_STRAP5 0x0005
+#define mmRCC_BIF_STRAP5_BASE_IDX 2
+#define mmRCC_BIF_STRAP6 0x0006
+#define mmRCC_BIF_STRAP6_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP0 0x0007
+#define mmRCC_DEV0_PORT_STRAP0_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP1 0x0008
+#define mmRCC_DEV0_PORT_STRAP1_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP2 0x0009
+#define mmRCC_DEV0_PORT_STRAP2_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP3 0x000a
+#define mmRCC_DEV0_PORT_STRAP3_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP4 0x000b
+#define mmRCC_DEV0_PORT_STRAP4_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP5 0x000c
+#define mmRCC_DEV0_PORT_STRAP5_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP6 0x000d
+#define mmRCC_DEV0_PORT_STRAP6_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP7 0x000e
+#define mmRCC_DEV0_PORT_STRAP7_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP8 0x000f
+#define mmRCC_DEV0_PORT_STRAP8_BASE_IDX 2
+#define mmRCC_DEV0_PORT_STRAP9 0x0010
+#define mmRCC_DEV0_PORT_STRAP9_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_STRAP0 0x0011
+#define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_STRAP1 0x0012
+#define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_STRAP13 0x0013
+#define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_STRAP2 0x0014
+#define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_STRAP3 0x0015
+#define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_STRAP4 0x0016
+#define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_STRAP5 0x0017
+#define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_STRAP8 0x0018
+#define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_STRAP9 0x0019
+#define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP0 0x001a
+#define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP10 0x001b
+#define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP11 0x001c
+#define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP12 0x001d
+#define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP13 0x001e
+#define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP2 0x001f
+#define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP3 0x0020
+#define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP4 0x0021
+#define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP5 0x0022
+#define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP6 0x0023
+#define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX 2
+#define mmRCC_DEV0_EPF1_STRAP7 0x0024
+#define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+// base address: 0x0
+#define mmEP_PCIE_SCRATCH 0x0025
+#define mmEP_PCIE_SCRATCH_BASE_IDX 2
+#define mmEP_PCIE_CNTL 0x0027
+#define mmEP_PCIE_CNTL_BASE_IDX 2
+#define mmEP_PCIE_INT_CNTL 0x0028
+#define mmEP_PCIE_INT_CNTL_BASE_IDX 2
+#define mmEP_PCIE_INT_STATUS 0x0029
+#define mmEP_PCIE_INT_STATUS_BASE_IDX 2
+#define mmEP_PCIE_RX_CNTL2 0x002a
+#define mmEP_PCIE_RX_CNTL2_BASE_IDX 2
+#define mmEP_PCIE_BUS_CNTL 0x002b
+#define mmEP_PCIE_BUS_CNTL_BASE_IDX 2
+#define mmEP_PCIE_CFG_CNTL 0x002c
+#define mmEP_PCIE_CFG_CNTL_BASE_IDX 2
+#define mmEP_PCIE_TX_LTR_CNTL 0x002e
+#define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002f
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002f
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002f
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002f
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0030
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0030
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0030
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0030
+#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
+#define mmEP_PCIE_STRAP_MISC 0x0031
+#define mmEP_PCIE_STRAP_MISC_BASE_IDX 2
+#define mmEP_PCIE_STRAP_MISC2 0x0032
+#define mmEP_PCIE_STRAP_MISC2_BASE_IDX 2
+#define mmEP_PCIE_F0_DPA_CAP 0x0034
+#define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2
+#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0035
+#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2
+#define mmEP_PCIE_F0_DPA_CNTL 0x0035
+#define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0035
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0036
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0036
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0036
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0036
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0037
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0037
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0037
+#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
+#define mmEP_PCIE_PME_CONTROL 0x0037
+#define mmEP_PCIE_PME_CONTROL_BASE_IDX 2
+#define mmEP_PCIEP_RESERVED 0x0038
+#define mmEP_PCIEP_RESERVED_BASE_IDX 2
+#define mmEP_PCIE_TX_CNTL 0x003a
+#define mmEP_PCIE_TX_CNTL_BASE_IDX 2
+#define mmEP_PCIE_TX_REQUESTER_ID 0x003b
+#define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2
+#define mmEP_PCIE_ERR_CNTL 0x003c
+#define mmEP_PCIE_ERR_CNTL_BASE_IDX 2
+#define mmEP_PCIE_RX_CNTL 0x003d
+#define mmEP_PCIE_RX_CNTL_BASE_IDX 2
+#define mmEP_PCIE_LC_SPEED_CNTL 0x003e
+#define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+// base address: 0x0
+#define mmDN_PCIE_RESERVED 0x0040
+#define mmDN_PCIE_RESERVED_BASE_IDX 2
+#define mmDN_PCIE_SCRATCH 0x0041
+#define mmDN_PCIE_SCRATCH_BASE_IDX 2
+#define mmDN_PCIE_CNTL 0x0043
+#define mmDN_PCIE_CNTL_BASE_IDX 2
+#define mmDN_PCIE_CONFIG_CNTL 0x0044
+#define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2
+#define mmDN_PCIE_RX_CNTL2 0x0045
+#define mmDN_PCIE_RX_CNTL2_BASE_IDX 2
+#define mmDN_PCIE_BUS_CNTL 0x0046
+#define mmDN_PCIE_BUS_CNTL_BASE_IDX 2
+#define mmDN_PCIE_CFG_CNTL 0x0047
+#define mmDN_PCIE_CFG_CNTL_BASE_IDX 2
+#define mmDN_PCIE_STRAP_F0 0x0048
+#define mmDN_PCIE_STRAP_F0_BASE_IDX 2
+#define mmDN_PCIE_STRAP_MISC 0x0049
+#define mmDN_PCIE_STRAP_MISC_BASE_IDX 2
+#define mmDN_PCIE_STRAP_MISC2 0x004a
+#define mmDN_PCIE_STRAP_MISC2_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+// base address: 0x0
+#define mmPCIE_ERR_CNTL 0x004f
+#define mmPCIE_ERR_CNTL_BASE_IDX 2
+#define mmPCIE_RX_CNTL 0x0050
+#define mmPCIE_RX_CNTL_BASE_IDX 2
+#define mmPCIE_LC_SPEED_CNTL 0x0051
+#define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2
+#define mmPCIE_LC_CNTL2 0x0052
+#define mmPCIE_LC_CNTL2_BASE_IDX 2
+#define mmPCIEP_STRAP_MISC 0x0053
+#define mmPCIEP_STRAP_MISC_BASE_IDX 2
+#define mmLTR_MSG_INFO_FROM_EP 0x0054
+#define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
+// base address: 0x3480
+#define mmRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+// base address: 0x0
+#define mmRCC_ERR_INT_CNTL 0x0086
+#define mmRCC_ERR_INT_CNTL_BASE_IDX 2
+#define mmRCC_BACO_CNTL_MISC 0x0087
+#define mmRCC_BACO_CNTL_MISC_BASE_IDX 2
+#define mmRCC_RESET_EN 0x0088
+#define mmRCC_RESET_EN_BASE_IDX 2
+#define mmRCC_VDM_SUPPORT 0x0089
+#define mmRCC_VDM_SUPPORT_BASE_IDX 2
+#define mmRCC_MARGIN_PARAM_CNTL0 0x008a
+#define mmRCC_MARGIN_PARAM_CNTL0_BASE_IDX 2
+#define mmRCC_MARGIN_PARAM_CNTL1 0x008b
+#define mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX 2
+#define mmRCC_GPUIOV_REGION 0x008c
+#define mmRCC_GPUIOV_REGION_BASE_IDX 2
+#define mmRCC_PEER_REG_RANGE0 0x00be
+#define mmRCC_PEER_REG_RANGE0_BASE_IDX 2
+#define mmRCC_PEER_REG_RANGE1 0x00bf
+#define mmRCC_PEER_REG_RANGE1_BASE_IDX 2
+#define mmRCC_BUS_CNTL 0x00c1
+#define mmRCC_BUS_CNTL_BASE_IDX 2
+#define mmRCC_CONFIG_CNTL 0x00c2
+#define mmRCC_CONFIG_CNTL_BASE_IDX 2
+#define mmRCC_CONFIG_F0_BASE 0x00c6
+#define mmRCC_CONFIG_F0_BASE_BASE_IDX 2
+#define mmRCC_CONFIG_APER_SIZE 0x00c7
+#define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2
+#define mmRCC_CONFIG_REG_APER_SIZE 0x00c8
+#define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2
+#define mmRCC_XDMA_LO 0x00c9
+#define mmRCC_XDMA_LO_BASE_IDX 2
+#define mmRCC_XDMA_HI 0x00ca
+#define mmRCC_XDMA_HI_BASE_IDX 2
+#define mmRCC_FEATURES_CONTROL_MISC 0x00cb
+#define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2
+#define mmRCC_BUSNUM_CNTL1 0x00cc
+#define mmRCC_BUSNUM_CNTL1_BASE_IDX 2
+#define mmRCC_BUSNUM_LIST0 0x00cd
+#define mmRCC_BUSNUM_LIST0_BASE_IDX 2
+#define mmRCC_BUSNUM_LIST1 0x00ce
+#define mmRCC_BUSNUM_LIST1_BASE_IDX 2
+#define mmRCC_BUSNUM_CNTL2 0x00cf
+#define mmRCC_BUSNUM_CNTL2_BASE_IDX 2
+#define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0
+#define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2
+#define mmRCC_HOST_BUSNUM 0x00d1
+#define mmRCC_HOST_BUSNUM_BASE_IDX 2
+#define mmRCC_PEER0_FB_OFFSET_HI 0x00d2
+#define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2
+#define mmRCC_PEER0_FB_OFFSET_LO 0x00d3
+#define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2
+#define mmRCC_PEER1_FB_OFFSET_HI 0x00d4
+#define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2
+#define mmRCC_PEER1_FB_OFFSET_LO 0x00d5
+#define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2
+#define mmRCC_PEER2_FB_OFFSET_HI 0x00d6
+#define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2
+#define mmRCC_PEER2_FB_OFFSET_LO 0x00d7
+#define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2
+#define mmRCC_PEER3_FB_OFFSET_HI 0x00d8
+#define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2
+#define mmRCC_PEER3_FB_OFFSET_LO 0x00d9
+#define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2
+#define mmRCC_DEVFUNCNUM_LIST0 0x00da
+#define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX 2
+#define mmRCC_DEVFUNCNUM_LIST1 0x00db
+#define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX 2
+#define mmRCC_DEV0_LINK_CNTL 0x00dd
+#define mmRCC_DEV0_LINK_CNTL_BASE_IDX 2
+#define mmRCC_CMN_LINK_CNTL 0x00de
+#define mmRCC_CMN_LINK_CNTL_BASE_IDX 2
+#define mmRCC_EP_REQUESTERID_RESTORE 0x00df
+#define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2
+#define mmRCC_LTR_LSWITCH_CNTL 0x00e0
+#define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2
+#define mmRCC_MH_ARB_CNTL 0x00e1
+#define mmRCC_MH_ARB_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+// base address: 0x0
+#define mmCC_BIF_BX_STRAP0 0x00e2
+#define mmCC_BIF_BX_STRAP0_BASE_IDX 2
+#define mmCC_BIF_BX_PINSTRAP0 0x00e4
+#define mmCC_BIF_BX_PINSTRAP0_BASE_IDX 2
+#define mmBIF_MM_INDACCESS_CNTL 0x00e6
+#define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2
+#define mmBUS_CNTL 0x00e7
+#define mmBUS_CNTL_BASE_IDX 2
+#define mmBIF_SCRATCH0 0x00e8
+#define mmBIF_SCRATCH0_BASE_IDX 2
+#define mmBIF_SCRATCH1 0x00e9
+#define mmBIF_SCRATCH1_BASE_IDX 2
+#define mmBX_RESET_EN 0x00ed
+#define mmBX_RESET_EN_BASE_IDX 2
+#define mmMM_CFGREGS_CNTL 0x00ee
+#define mmMM_CFGREGS_CNTL_BASE_IDX 2
+#define mmBX_RESET_CNTL 0x00f0
+#define mmBX_RESET_CNTL_BASE_IDX 2
+#define mmINTERRUPT_CNTL 0x00f1
+#define mmINTERRUPT_CNTL_BASE_IDX 2
+#define mmINTERRUPT_CNTL2 0x00f2
+#define mmINTERRUPT_CNTL2_BASE_IDX 2
+#define mmCLKREQB_PAD_CNTL 0x00f8
+#define mmCLKREQB_PAD_CNTL_BASE_IDX 2
+#define mmBIF_FEATURES_CONTROL_MISC 0x00fb
+#define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2
+#define mmBIF_DOORBELL_CNTL 0x00fc
+#define mmBIF_DOORBELL_CNTL_BASE_IDX 2
+#define mmBIF_DOORBELL_INT_CNTL 0x00fd
+#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2
+#define mmBIF_FB_EN 0x00ff
+#define mmBIF_FB_EN_BASE_IDX 2
+#define mmBIF_INTR_CNTL 0x0100
+#define mmBIF_INTR_CNTL_BASE_IDX 2
+#define mmBIF_MST_TRANS_PENDING_VF 0x0109
+#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2
+#define mmBIF_SLV_TRANS_PENDING_VF 0x010a
+#define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2
+#define mmBACO_CNTL 0x010b
+#define mmBACO_CNTL_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIME0 0x010c
+#define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIMER1 0x010d
+#define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIMER2 0x010e
+#define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIMER3 0x010f
+#define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2
+#define mmBIF_BACO_EXIT_TIMER4 0x0110
+#define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2
+#define mmMEM_TYPE_CNTL 0x0111
+#define mmMEM_TYPE_CNTL_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_CNTL 0x0113
+#define mmNBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_0 0x0114
+#define mmNBIF_GFX_ADDR_LUT_0_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_1 0x0115
+#define mmNBIF_GFX_ADDR_LUT_1_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_2 0x0116
+#define mmNBIF_GFX_ADDR_LUT_2_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_3 0x0117
+#define mmNBIF_GFX_ADDR_LUT_3_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_4 0x0118
+#define mmNBIF_GFX_ADDR_LUT_4_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_5 0x0119
+#define mmNBIF_GFX_ADDR_LUT_5_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_6 0x011a
+#define mmNBIF_GFX_ADDR_LUT_6_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_7 0x011b
+#define mmNBIF_GFX_ADDR_LUT_7_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_8 0x011c
+#define mmNBIF_GFX_ADDR_LUT_8_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_9 0x011d
+#define mmNBIF_GFX_ADDR_LUT_9_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_10 0x011e
+#define mmNBIF_GFX_ADDR_LUT_10_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_11 0x011f
+#define mmNBIF_GFX_ADDR_LUT_11_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_12 0x0120
+#define mmNBIF_GFX_ADDR_LUT_12_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_13 0x0121
+#define mmNBIF_GFX_ADDR_LUT_13_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_14 0x0122
+#define mmNBIF_GFX_ADDR_LUT_14_BASE_IDX 2
+#define mmNBIF_GFX_ADDR_LUT_15 0x0123
+#define mmNBIF_GFX_ADDR_LUT_15_BASE_IDX 2
+#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d
+#define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2
+#define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e
+#define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_RB_CNTL 0x012f
+#define mmBIF_RB_CNTL_BASE_IDX 2
+#define mmBIF_RB_BASE 0x0130
+#define mmBIF_RB_BASE_BASE_IDX 2
+#define mmBIF_RB_RPTR 0x0131
+#define mmBIF_RB_RPTR_BASE_IDX 2
+#define mmBIF_RB_WPTR 0x0132
+#define mmBIF_RB_WPTR_BASE_IDX 2
+#define mmBIF_RB_WPTR_ADDR_HI 0x0133
+#define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2
+#define mmBIF_RB_WPTR_ADDR_LO 0x0134
+#define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2
+#define mmMAILBOX_INDEX 0x0135
+#define mmMAILBOX_INDEX_BASE_IDX 2
+#define mmBIF_MP1_INTR_CTRL 0x0142
+#define mmBIF_MP1_INTR_CTRL_BASE_IDX 2
+#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143
+#define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2
+#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144
+#define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2
+#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145
+#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2
+#define mmBIF_PERSTB_PAD_CNTL 0x0148
+#define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2
+#define mmBIF_PX_EN_PAD_CNTL 0x0149
+#define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2
+#define mmBIF_REFPADKIN_PAD_CNTL 0x014a
+#define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2
+#define mmBIF_CLKREQB_PAD_CNTL 0x014b
+#define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2
+#define mmBIF_PWRBRK_PAD_CNTL 0x014c
+#define mmBIF_PWRBRK_PAD_CNTL_BASE_IDX 2
+#define mmBIF_WAKEB_PAD_CNTL 0x014d
+#define mmBIF_WAKEB_PAD_CNTL_BASE_IDX 2
+#define mmBIF_VAUX_PRESENT_PAD_CNTL 0x014e
+#define mmBIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_PF_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_PF_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_PF_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_PF_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_PF_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_PF_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_PF_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_PF_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_PF_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+// base address: 0x0
+#define mmA2S_CNTL_CL0 0x0190
+#define mmA2S_CNTL_CL0_BASE_IDX 2
+#define mmA2S_CNTL_CL1 0x0191
+#define mmA2S_CNTL_CL1_BASE_IDX 2
+#define mmA2S_CNTL3_CL0 0x01a0
+#define mmA2S_CNTL3_CL0_BASE_IDX 2
+#define mmA2S_CNTL3_CL1 0x01a1
+#define mmA2S_CNTL3_CL1_BASE_IDX 2
+#define mmA2S_CNTL_SW0 0x01b0
+#define mmA2S_CNTL_SW0_BASE_IDX 2
+#define mmA2S_CNTL_SW1 0x01b1
+#define mmA2S_CNTL_SW1_BASE_IDX 2
+#define mmA2S_CNTL_SW2 0x01b2
+#define mmA2S_CNTL_SW2_BASE_IDX 2
+#define mmA2S_CPLBUF_ALLOC_CNTL 0x01bc
+#define mmA2S_CPLBUF_ALLOC_CNTL_BASE_IDX 2
+#define mmA2S_TAG_ALLOC_0 0x01bd
+#define mmA2S_TAG_ALLOC_0_BASE_IDX 2
+#define mmA2S_TAG_ALLOC_1 0x01be
+#define mmA2S_TAG_ALLOC_1_BASE_IDX 2
+#define mmA2S_MISC_CNTL 0x01c1
+#define mmA2S_MISC_CNTL_BASE_IDX 2
+#define mmNGDC_SDP_PORT_CTRL 0x01c2
+#define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2
+#define mmSHUB_REGS_IF_CTL 0x01c3
+#define mmSHUB_REGS_IF_CTL_BASE_IDX 2
+#define mmNGDC_MGCG_CTRL 0x01ca
+#define mmNGDC_MGCG_CTRL_BASE_IDX 2
+#define mmNGDC_RESERVED_0 0x01cb
+#define mmNGDC_RESERVED_0_BASE_IDX 2
+#define mmNGDC_RESERVED_1 0x01cc
+#define mmNGDC_RESERVED_1_BASE_IDX 2
+#define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd
+#define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2
+#define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0
+#define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1
+#define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_IH_DOORBELL_RANGE 0x01d2
+#define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3
+#define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_ACV_DOORBELL_RANGE 0x01d4
+#define mmBIF_ACV_DOORBELL_RANGE_BASE_IDX 2
+#define mmBIF_DOORBELL_FENCE_CNTL 0x01de
+#define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2
+#define mmS2A_MISC_CNTL 0x01df
+#define mmS2A_MISC_CNTL_BASE_IDX 2
+#define mmNGDC_PG_MISC_CTRL 0x01f0
+#define mmNGDC_PG_MISC_CTRL_BASE_IDX 2
+#define mmNGDC_PGMST_CTRL 0x01f1
+#define mmNGDC_PGMST_CTRL_BASE_IDX 2
+#define mmNGDC_PGSLV_CTRL 0x01f2
+#define mmNGDC_PGSLV_CTRL_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp
+// base address: 0x0
+#define cfgPSWUSCFG0_0_VENDOR_ID 0x0000
+#define cfgPSWUSCFG0_0_DEVICE_ID 0x0002
+#define cfgPSWUSCFG0_0_COMMAND 0x0004
+#define cfgPSWUSCFG0_0_STATUS 0x0006
+#define cfgPSWUSCFG0_0_REVISION_ID 0x0008
+#define cfgPSWUSCFG0_0_PROG_INTERFACE 0x0009
+#define cfgPSWUSCFG0_0_SUB_CLASS 0x000a
+#define cfgPSWUSCFG0_0_BASE_CLASS 0x000b
+#define cfgPSWUSCFG0_0_CACHE_LINE 0x000c
+#define cfgPSWUSCFG0_0_LATENCY 0x000d
+#define cfgPSWUSCFG0_0_HEADER 0x000e
+#define cfgPSWUSCFG0_0_BIST 0x000f
+#define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY 0x0018
+#define cfgPSWUSCFG0_0_IO_BASE_LIMIT 0x001c
+#define cfgPSWUSCFG0_0_SECONDARY_STATUS 0x001e
+#define cfgPSWUSCFG0_0_MEM_BASE_LIMIT 0x0020
+#define cfgPSWUSCFG0_0_PREF_BASE_LIMIT 0x0024
+#define cfgPSWUSCFG0_0_PREF_BASE_UPPER 0x0028
+#define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER 0x002c
+#define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI 0x0030
+#define cfgPSWUSCFG0_0_CAP_PTR 0x0034
+#define cfgPSWUSCFG0_0_ROM_BASE_ADDR 0x0038
+#define cfgPSWUSCFG0_0_INTERRUPT_LINE 0x003c
+#define cfgPSWUSCFG0_0_INTERRUPT_PIN 0x003d
+#define cfgPSWUSCFG0_0_IRQ_BRIDGE_CNTL 0x003e
+#define cfgPSWUSCFG0_0_EXT_BRIDGE_CNTL 0x0040
+#define cfgPSWUSCFG0_0_VENDOR_CAP_LIST 0x0048
+#define cfgPSWUSCFG0_0_ADAPTER_ID_W 0x004c
+#define cfgPSWUSCFG0_0_PMI_CAP_LIST 0x0050
+#define cfgPSWUSCFG0_0_PMI_CAP 0x0052
+#define cfgPSWUSCFG0_0_PMI_STATUS_CNTL 0x0054
+#define cfgPSWUSCFG0_0_PCIE_CAP_LIST 0x0058
+#define cfgPSWUSCFG0_0_PCIE_CAP 0x005a
+#define cfgPSWUSCFG0_0_DEVICE_CAP 0x005c
+#define cfgPSWUSCFG0_0_DEVICE_CNTL 0x0060
+#define cfgPSWUSCFG0_0_DEVICE_STATUS 0x0062
+#define cfgPSWUSCFG0_0_LINK_CAP 0x0064
+#define cfgPSWUSCFG0_0_LINK_CNTL 0x0068
+#define cfgPSWUSCFG0_0_LINK_STATUS 0x006a
+#define cfgPSWUSCFG0_0_DEVICE_CAP2 0x007c
+#define cfgPSWUSCFG0_0_DEVICE_CNTL2 0x0080
+#define cfgPSWUSCFG0_0_DEVICE_STATUS2 0x0082
+#define cfgPSWUSCFG0_0_LINK_CAP2 0x0084
+#define cfgPSWUSCFG0_0_LINK_CNTL2 0x0088
+#define cfgPSWUSCFG0_0_LINK_STATUS2 0x008a
+#define cfgPSWUSCFG0_0_MSI_CAP_LIST 0x00a0
+#define cfgPSWUSCFG0_0_MSI_MSG_CNTL 0x00a2
+#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgPSWUSCFG0_0_MSI_MSG_DATA 0x00a8
+#define cfgPSWUSCFG0_0_MSI_MSG_DATA_64 0x00ac
+#define cfgPSWUSCFG0_0_SSID_CAP_LIST 0x00c0
+#define cfgPSWUSCFG0_0_SSID_CAP 0x00c4
+#define cfgPSWUSCFG0_0_MSI_MAP_CAP_LIST 0x00c8
+#define cfgPSWUSCFG0_0_MSI_MAP_CAP 0x00ca
+#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST 0x0110
+#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1 0x0114
+#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2 0x0118
+#define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL 0x011c
+#define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS 0x011e
+#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP 0x0120
+#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL 0x0124
+#define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS 0x012a
+#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP 0x012c
+#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL 0x0130
+#define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS 0x0136
+#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgPSWUSCFG0_0_PCIE_HDR_LOG0 0x016c
+#define cfgPSWUSCFG0_0_PCIE_HDR_LOG1 0x0170
+#define cfgPSWUSCFG0_0_PCIE_HDR_LOG2 0x0174
+#define cfgPSWUSCFG0_0_PCIE_HDR_LOG3 0x0178
+#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3 0x0274
+#define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgPSWUSCFG0_0_PCIE_ACS_CAP 0x02a4
+#define cfgPSWUSCFG0_0_PCIE_ACS_CNTL 0x02a6
+#define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST 0x02f0
+#define cfgPSWUSCFG0_0_PCIE_MC_CAP 0x02f4
+#define cfgPSWUSCFG0_0_PCIE_MC_CNTL 0x02f6
+#define cfgPSWUSCFG0_0_PCIE_MC_ADDR0 0x02f8
+#define cfgPSWUSCFG0_0_PCIE_MC_ADDR1 0x02fc
+#define cfgPSWUSCFG0_0_PCIE_MC_RCV0 0x0300
+#define cfgPSWUSCFG0_0_PCIE_MC_RCV1 0x0304
+#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0 0x0308
+#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1 0x030c
+#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310
+#define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314
+#define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0 0x0318
+#define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1 0x031c
+#define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST 0x0320
+#define cfgPSWUSCFG0_0_PCIE_LTR_CAP 0x0324
+#define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgPSWUSCFG0_0_PCIE_ARI_CAP 0x032c
+#define cfgPSWUSCFG0_0_PCIE_ARI_CNTL 0x032e
+#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370
+#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP 0x0374
+#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL 0x0378
+#define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2 0x037c
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_LIST 0x03c4
+#define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_1 0x03c8
+#define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_2 0x03cc
+#define cfgPSWUSCFG0_0_PCIE_ESM_STATUS 0x03ce
+#define cfgPSWUSCFG0_0_PCIE_ESM_CTRL 0x03d0
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_1 0x03d4
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_2 0x03d8
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_3 0x03dc
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_4 0x03e0
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_5 0x03e4
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_6 0x03e8
+#define cfgPSWUSCFG0_0_PCIE_ESM_CAP_7 0x03ec
+#define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST 0x0400
+#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP 0x0404
+#define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS 0x0408
+#define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410
+#define cfgPSWUSCFG0_0_LINK_CAP_16GT 0x0414
+#define cfgPSWUSCFG0_0_LINK_CNTL_16GT 0x0418
+#define cfgPSWUSCFG0_0_LINK_STATUS_16GT 0x041c
+#define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420
+#define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424
+#define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428
+#define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430
+#define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431
+#define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432
+#define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433
+#define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434
+#define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435
+#define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436
+#define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437
+#define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438
+#define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439
+#define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a
+#define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b
+#define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c
+#define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d
+#define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e
+#define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f
+#define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST 0x0440
+#define cfgPSWUSCFG0_0_MARGINING_PORT_CAP 0x0444
+#define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS 0x0446
+#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL 0x0448
+#define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS 0x044a
+#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL 0x044c
+#define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS 0x044e
+#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL 0x0450
+#define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS 0x0452
+#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL 0x0454
+#define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS 0x0456
+#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL 0x0458
+#define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS 0x045a
+#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL 0x045c
+#define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS 0x045e
+#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL 0x0460
+#define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS 0x0462
+#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL 0x0464
+#define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS 0x0466
+#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL 0x0468
+#define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS 0x046a
+#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL 0x046c
+#define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS 0x046e
+#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL 0x0470
+#define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS 0x0472
+#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL 0x0474
+#define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS 0x0476
+#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL 0x0478
+#define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS 0x047a
+#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL 0x047c
+#define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS 0x047e
+#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL 0x0480
+#define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS 0x0482
+#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL 0x0484
+#define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS 0x0486
+#define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_LIST 0x0488
+#define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_1 0x048c
+#define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_2 0x0490
+#define cfgPSWUSCFG0_0_PCIE_CCIX_CAP 0x0492
+#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP 0x0494
+#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP 0x0498
+#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_STATUS 0x049c
+#define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_CNTL 0x04a0
+#define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x04a4
+#define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x04a5
+#define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x04a6
+#define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x04a7
+#define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x04a8
+#define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x04a9
+#define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x04aa
+#define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x04ab
+#define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x04ac
+#define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x04ad
+#define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x04ae
+#define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x04af
+#define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x04b0
+#define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x04b1
+#define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x04b2
+#define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x04b3
+#define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x04b4
+#define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x04b5
+#define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x04b6
+#define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x04b7
+#define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x04b8
+#define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x04b9
+#define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x04ba
+#define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x04bb
+#define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x04bc
+#define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x04bd
+#define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x04be
+#define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x04bf
+#define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x04c0
+#define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x04c1
+#define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x04c2
+#define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x04c3
+#define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CAP 0x04c4
+#define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL 0x04c8
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048
+#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x0374
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x0378
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x0400
+#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x0404
+#define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x0408
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x0414
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x0418
+#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x041c
+#define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420
+#define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424
+#define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x0440
+#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x0444
+#define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x0446
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x0448
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x044a
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x044c
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x044e
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x0450
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x0452
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x0454
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x0456
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x0458
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x045a
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x045c
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x045e
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x0460
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x0462
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x0464
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x0466
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x0468
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x046a
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x046c
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x046e
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x0470
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x0472
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x0474
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x0476
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x0478
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x047a
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x047c
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x047e
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x0480
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x0482
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x0484
+#define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x0486
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0530
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0534
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0538
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x053c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0540
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0544
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0548
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x054c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0550
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0554
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0558
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x055c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0560
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0564
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0568
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x056c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0570
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0574
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0578
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x057c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0580
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0584
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0588
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x058c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0590
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0594
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0598
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x059c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x05a0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05ac
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05b0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05c0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05c4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05c8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05cc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05d0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05d4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05d8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05dc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05e0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05f0
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05f4
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05f8
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05fc
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x0600
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x0604
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x060c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0610
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0620
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0624
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0628
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x062c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0630
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0634
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0638
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x063c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0640
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0650
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0654
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0658
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x065c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0660
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0664
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0668
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x066c
+#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0670
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048
+#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x0374
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x0378
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST 0x0400
+#define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP 0x0404
+#define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS 0x0408
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT 0x0414
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT 0x0418
+#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT 0x041c
+#define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420
+#define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424
+#define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST 0x0440
+#define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 0x0444
+#define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS 0x0446
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL 0x0448
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS 0x044a
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL 0x044c
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS 0x044e
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL 0x0450
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS 0x0452
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL 0x0454
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS 0x0456
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL 0x0458
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS 0x045a
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL 0x045c
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS 0x045e
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL 0x0460
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS 0x0462
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL 0x0464
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS 0x0466
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL 0x0468
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS 0x046a
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL 0x046c
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS 0x046e
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL 0x0470
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS 0x0472
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL 0x0474
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS 0x0476
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL 0x0478
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS 0x047a
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL 0x047c
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS 0x047e
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL 0x0480
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS 0x0482
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL 0x0484
+#define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS 0x0486
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0508
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x050c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0510
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0514
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0518
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x051c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0520
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0530
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0534
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0538
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x053c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0540
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0544
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0548
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x054c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0550
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0554
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0558
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x055c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0560
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0564
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0568
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x056c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0570
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0574
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0578
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x057c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0580
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0584
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0588
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x058c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0590
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0594
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0598
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x059c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x05a0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05ac
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05b0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x05c0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x05c4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x05c8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x05cc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x05d0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x05d4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x05d8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x05dc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x05e0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x05f0
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x05f4
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x05f8
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x05fc
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x0600
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x0604
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x0608
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x060c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0610
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x0620
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x0624
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x0628
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x062c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x0630
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x0634
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x0638
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x063c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x0640
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0650
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0654
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0658
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x065c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0660
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0664
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0668
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x066c
+#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0670
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF2_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF2_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF2_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF2_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF2_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0x0048
+#define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0x004c
+#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_EPF2_0_SBRN 0x0060
+#define cfgBIF_CFG_DEV0_EPF2_0_FLADJ 0x0061
+#define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0x0062
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0 0x00d0
+#define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1 0x00d4
+#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX 0x00d8
+#define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA 0x00dc
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x0200
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0x0204
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0x0208
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0x020c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0x0210
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0x0214
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0x0218
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0x021c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0x0220
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0x0224
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0x0228
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0x022c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0x0230
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0x0248
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x0250
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0x0254
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x0258
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0x025c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0x025e
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0x02a6
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0x02d0
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP 0x02d4
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL 0x02d6
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0x032e
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP 0x0374
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL 0x0378
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0 0x037c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1 0x037e
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2 0x0380
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3 0x0382
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4 0x0384
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5 0x0386
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6 0x0388
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7 0x038a
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8 0x038c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9 0x038e
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10 0x0390
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11 0x0392
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12 0x0394
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13 0x0396
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14 0x0398
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15 0x039a
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16 0x039c
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17 0x039e
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18 0x03a0
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19 0x03a2
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20 0x03a4
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21 0x03a6
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22 0x03a8
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23 0x03aa
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24 0x03ac
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25 0x03ae
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26 0x03b0
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27 0x03b2
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28 0x03b4
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29 0x03b6
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30 0x03b8
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31 0x03ba
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32 0x03bc
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33 0x03be
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34 0x03c0
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35 0x03c2
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36 0x03c4
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37 0x03c6
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38 0x03c8
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39 0x03ca
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40 0x03cc
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41 0x03ce
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42 0x03d0
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43 0x03d2
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44 0x03d4
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45 0x03d6
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46 0x03d8
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47 0x03da
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48 0x03dc
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49 0x03de
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50 0x03e0
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51 0x03e2
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52 0x03e4
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53 0x03e6
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54 0x03e8
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55 0x03ea
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56 0x03ec
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57 0x03ee
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58 0x03f0
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59 0x03f2
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60 0x03f4
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61 0x03f6
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62 0x03f8
+#define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63 0x03fa
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF3_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF3_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF3_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF3_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF3_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0x0048
+#define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0x004c
+#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_EPF3_0_SBRN 0x0060
+#define cfgBIF_CFG_DEV0_EPF3_0_FLADJ 0x0061
+#define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0x0062
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0 0x00d0
+#define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1 0x00d4
+#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX 0x00d8
+#define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA 0x00dc
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0x0200
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0x0204
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0x0208
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0x020c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0x0210
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0x0214
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0x0218
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0x021c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0x0220
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0x0224
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0x0228
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0x022c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0x0230
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0x0248
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0x024c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0x0250
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0x0254
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0x0258
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0x025c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0x025e
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0x02a6
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST 0x02d0
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP 0x02d4
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL 0x02d6
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0x032e
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP 0x0374
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL 0x0378
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0 0x037c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1 0x037e
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2 0x0380
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3 0x0382
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4 0x0384
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5 0x0386
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6 0x0388
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7 0x038a
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8 0x038c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9 0x038e
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10 0x0390
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11 0x0392
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12 0x0394
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13 0x0396
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14 0x0398
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15 0x039a
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16 0x039c
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17 0x039e
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18 0x03a0
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19 0x03a2
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20 0x03a4
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21 0x03a6
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22 0x03a8
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23 0x03aa
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24 0x03ac
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25 0x03ae
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26 0x03b0
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27 0x03b2
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28 0x03b4
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29 0x03b6
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30 0x03b8
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31 0x03ba
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32 0x03bc
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33 0x03be
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34 0x03c0
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35 0x03c2
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36 0x03c4
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37 0x03c6
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38 0x03c8
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39 0x03ca
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40 0x03cc
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41 0x03ce
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42 0x03d0
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43 0x03d2
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44 0x03d4
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45 0x03d6
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46 0x03d8
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47 0x03da
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48 0x03dc
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49 0x03de
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50 0x03e0
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51 0x03e2
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52 0x03e4
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53 0x03e6
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54 0x03e8
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55 0x03ea
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56 0x03ec
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57 0x03ee
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58 0x03f0
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59 0x03f2
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60 0x03f4
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61 0x03f6
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62 0x03f8
+#define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63 0x03fa
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018
+#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c
+#define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e
+#define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028
+#define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c
+#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030
+#define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR 0x0038
+#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052
+#define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080
+#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090
+#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST 0x0400
+#define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP 0x0404
+#define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS 0x0408
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT 0x0414
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT 0x0418
+#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT 0x041c
+#define cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420
+#define cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424
+#define cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f
+#define cfgBIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST 0x0440
+#define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP 0x0444
+#define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS 0x0446
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL 0x0448
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS 0x044a
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL 0x044c
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS 0x044e
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL 0x0450
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS 0x0452
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL 0x0454
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS 0x0456
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL 0x0458
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS 0x045a
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL 0x045c
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS 0x045e
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL 0x0460
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS 0x0462
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL 0x0464
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS 0x0466
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL 0x0468
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS 0x046a
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL 0x046c
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS 0x046e
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL 0x0470
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS 0x0472
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL 0x0474
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS 0x0476
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL 0x0478
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS 0x047a
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL 0x047c
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS 0x047e
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL 0x0480
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS 0x0482
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL 0x0484
+#define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS 0x0486
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID 0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID 0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_COMMAND 0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_STATUS 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID 0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE 0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS 0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LATENCY 0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_HEADER 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BIST 0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1 0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2 0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3 0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4 0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5 0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6 0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR 0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR 0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR 0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE 0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN 0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT 0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY 0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST 0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP 0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL 0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS 0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP 0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL 0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS 0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2 0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2 0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2 0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2 0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2 0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST 0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL 0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO 0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA 0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64 0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING 0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64 0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST 0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL 0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA 0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1 0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2 0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS 0x0154
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK 0x0158
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS 0x0160
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK 0x0164
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0 0x016c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1 0x0170
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2 0x0174
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3 0x0178
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0 0x0188
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1 0x018c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2 0x0190
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3 0x0194
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP 0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL 0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST 0x0328
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP 0x032c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL 0x032e
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX 0x0000
+#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA 0x0001
+#define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA_BASE_IDX 0
+#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI 0x0006
+#define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI_BASE_IDX 0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG 0x0085
+#define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN 0x00c0
+#define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE 0x00c3
+#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED 0x00c4
+#define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED_BASE_IDX 2
+#define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER 0x00c5
+#define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1
+// base address: 0x0
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS 0x00eb
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG 0x00ec
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
+#define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ 0x0106
+#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE 0x0107
+#define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING 0x0108
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS 0x0112
+#define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0 0x0136
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1 0x0137
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2 0x0138
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3 0x0139
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0 0x013a
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1 0x013b
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2 0x013c
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3 0x013d
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL 0x013e
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL 0x013f
+#define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL_BASE_IDX 2
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX 0x0140
+#define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX_BASE_IDX 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2
+// base address: 0x0
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO 0x0400
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI 0x0401
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA 0x0402
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL 0x0403
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO 0x0404
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI 0x0405
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA 0x0406
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL 0x0407
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO 0x0408
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI 0x0409
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA 0x040a
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL 0x040b
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO 0x040c
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI 0x040d
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA 0x040e
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL 0x040f
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL_BASE_IDX 3
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA 0x0800
+#define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA_BASE_IDX 3
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+// base address: 0xd0000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0xd0000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA 0xd0000004
+#define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0xd0000018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0xd0000000
+#define cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0xd0003694
+#define cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0xd0003780
+#define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0xd000378c
+#define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0xd0003790
+#define cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0xd0003794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0xd0000000
+#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0xd000382c
+#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0xd0003830
+#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd000384c
+#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0003850
+#define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0003854
+#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0003858
+#define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd000385c
+#define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0xd0003898
+#define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0xd000389c
+#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0xd00038a0
+#define cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0xd00038c8
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0xd0003958
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0xd000395c
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0xd0003960
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0xd0003964
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0xd0003968
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0xd000396c
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0xd0003970
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0xd0003974
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0xd0003978
+#define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0xd000397c
+#define cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0xd0003980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2
+// base address: 0xd0000000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0xd0042000
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0xd0042004
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0xd0042008
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0xd004200c
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0xd0042010
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0xd0042014
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0xd0042018
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0xd004201c
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0xd0042020
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0xd0042024
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0xd0042028
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0xd004202c
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0xd0042030
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0xd0042034
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0xd0042038
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0xd004203c
+#define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0xd0043000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+// base address: 0xd0080000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0xd0080000
+#define cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA 0xd0080004
+#define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0xd0080018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1
+// base address: 0xd0080000
+#define cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0xd0083694
+#define cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0xd0083780
+#define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0xd008378c
+#define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0xd0083790
+#define cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0xd0083794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+// base address: 0xd0080000
+#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0xd008382c
+#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0xd0083830
+#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd008384c
+#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0083850
+#define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0083854
+#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0083858
+#define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd008385c
+#define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0xd0083898
+#define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0xd008389c
+#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0xd00838a0
+#define cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0xd00838c8
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0xd0083958
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0xd008395c
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0xd0083960
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0xd0083964
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0xd0083968
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0xd008396c
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0xd0083970
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0xd0083974
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0xd0083978
+#define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0xd008397c
+#define cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0xd0083980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2
+// base address: 0xd0080000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0xd00c2000
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0xd00c2004
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0xd00c2008
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0xd00c200c
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0xd00c2010
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0xd00c2014
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0xd00c2018
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0xd00c201c
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0xd00c2020
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0xd00c2024
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0xd00c2028
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0xd00c202c
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0xd00c2030
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0xd00c2034
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0xd00c2038
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0xd00c203c
+#define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0xd00c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+// base address: 0xd0100000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0xd0100000
+#define cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA 0xd0100004
+#define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0xd0100018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1
+// base address: 0xd0100000
+#define cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0xd0103694
+#define cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0xd0103780
+#define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0xd010378c
+#define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0xd0103790
+#define cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0xd0103794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+// base address: 0xd0100000
+#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0xd010382c
+#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0xd0103830
+#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd010384c
+#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0103850
+#define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0103854
+#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0103858
+#define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd010385c
+#define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0xd0103898
+#define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0xd010389c
+#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0xd01038a0
+#define cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0xd01038c8
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0xd0103958
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0xd010395c
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0xd0103960
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0xd0103964
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0xd0103968
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0xd010396c
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0xd0103970
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0xd0103974
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0xd0103978
+#define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0xd010397c
+#define cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0xd0103980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2
+// base address: 0xd0100000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0xd0142000
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0xd0142004
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0xd0142008
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0xd014200c
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0xd0142010
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0xd0142014
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0xd0142018
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0xd014201c
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0xd0142020
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0xd0142024
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0xd0142028
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0xd014202c
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0xd0142030
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0xd0142034
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0xd0142038
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0xd014203c
+#define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0xd0143000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+// base address: 0xd0180000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0xd0180000
+#define cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA 0xd0180004
+#define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0xd0180018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1
+// base address: 0xd0180000
+#define cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0xd0183694
+#define cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0xd0183780
+#define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0xd018378c
+#define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0xd0183790
+#define cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0xd0183794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+// base address: 0xd0180000
+#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0xd018382c
+#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0xd0183830
+#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd018384c
+#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0183850
+#define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0183854
+#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0183858
+#define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd018385c
+#define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0xd0183898
+#define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0xd018389c
+#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0xd01838a0
+#define cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0xd01838c8
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0xd0183958
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0xd018395c
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0xd0183960
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0xd0183964
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0xd0183968
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0xd018396c
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0xd0183970
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0xd0183974
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0xd0183978
+#define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0xd018397c
+#define cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0xd0183980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2
+// base address: 0xd0180000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0xd01c2000
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0xd01c2004
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0xd01c2008
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0xd01c200c
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0xd01c2010
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0xd01c2014
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0xd01c2018
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0xd01c201c
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0xd01c2020
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0xd01c2024
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0xd01c2028
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0xd01c202c
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0xd01c2030
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0xd01c2034
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0xd01c2038
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0xd01c203c
+#define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0xd01c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+// base address: 0xd0200000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0xd0200000
+#define cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA 0xd0200004
+#define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0xd0200018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1
+// base address: 0xd0200000
+#define cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0xd0203694
+#define cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0xd0203780
+#define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0xd020378c
+#define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0xd0203790
+#define cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0xd0203794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+// base address: 0xd0200000
+#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0xd020382c
+#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0xd0203830
+#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd020384c
+#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0203850
+#define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0203854
+#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0203858
+#define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd020385c
+#define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0xd0203898
+#define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0xd020389c
+#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0xd02038a0
+#define cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0xd02038c8
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0xd0203958
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0xd020395c
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0xd0203960
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0xd0203964
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0xd0203968
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0xd020396c
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0xd0203970
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0xd0203974
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0xd0203978
+#define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0xd020397c
+#define cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0xd0203980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2
+// base address: 0xd0200000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0xd0242000
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0xd0242004
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0xd0242008
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0xd024200c
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0xd0242010
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0xd0242014
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0xd0242018
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0xd024201c
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0xd0242020
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0xd0242024
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0xd0242028
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0xd024202c
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0xd0242030
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0xd0242034
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0xd0242038
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0xd024203c
+#define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0xd0243000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+// base address: 0xd0280000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0xd0280000
+#define cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA 0xd0280004
+#define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0xd0280018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1
+// base address: 0xd0280000
+#define cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0xd0283694
+#define cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0xd0283780
+#define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0xd028378c
+#define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0xd0283790
+#define cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0xd0283794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+// base address: 0xd0280000
+#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0xd028382c
+#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0xd0283830
+#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd028384c
+#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0283850
+#define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0283854
+#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0283858
+#define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd028385c
+#define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0xd0283898
+#define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0xd028389c
+#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0xd02838a0
+#define cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0xd02838c8
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0xd0283958
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0xd028395c
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0xd0283960
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0xd0283964
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0xd0283968
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0xd028396c
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0xd0283970
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0xd0283974
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0xd0283978
+#define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0xd028397c
+#define cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0xd0283980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2
+// base address: 0xd0280000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0xd02c2000
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0xd02c2004
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0xd02c2008
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0xd02c200c
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0xd02c2010
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0xd02c2014
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0xd02c2018
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0xd02c201c
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0xd02c2020
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0xd02c2024
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0xd02c2028
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0xd02c202c
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0xd02c2030
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0xd02c2034
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0xd02c2038
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0xd02c203c
+#define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0xd02c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+// base address: 0xd0300000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0xd0300000
+#define cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA 0xd0300004
+#define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0xd0300018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1
+// base address: 0xd0300000
+#define cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0xd0303694
+#define cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0xd0303780
+#define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0xd030378c
+#define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0xd0303790
+#define cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0xd0303794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+// base address: 0xd0300000
+#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0xd030382c
+#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0xd0303830
+#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd030384c
+#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0303850
+#define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0303854
+#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0303858
+#define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd030385c
+#define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0xd0303898
+#define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0xd030389c
+#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0xd03038a0
+#define cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0xd03038c8
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0xd0303958
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0xd030395c
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0xd0303960
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0xd0303964
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0xd0303968
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0xd030396c
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0xd0303970
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0xd0303974
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0xd0303978
+#define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0xd030397c
+#define cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0xd0303980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2
+// base address: 0xd0300000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0xd0342000
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0xd0342004
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0xd0342008
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0xd034200c
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0xd0342010
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0xd0342014
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0xd0342018
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0xd034201c
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0xd0342020
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0xd0342024
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0xd0342028
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0xd034202c
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0xd0342030
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0xd0342034
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0xd0342038
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0xd034203c
+#define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0xd0343000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+// base address: 0xd0380000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0xd0380000
+#define cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA 0xd0380004
+#define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0xd0380018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1
+// base address: 0xd0380000
+#define cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0xd0383694
+#define cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0xd0383780
+#define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0xd038378c
+#define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0xd0383790
+#define cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0xd0383794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+// base address: 0xd0380000
+#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0xd038382c
+#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0xd0383830
+#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd038384c
+#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0383850
+#define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0383854
+#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0383858
+#define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd038385c
+#define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0xd0383898
+#define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0xd038389c
+#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0xd03838a0
+#define cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0xd03838c8
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0xd0383958
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0xd038395c
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0xd0383960
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0xd0383964
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0xd0383968
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0xd038396c
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0xd0383970
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0xd0383974
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0xd0383978
+#define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0xd038397c
+#define cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0xd0383980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2
+// base address: 0xd0380000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0xd03c2000
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0xd03c2004
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0xd03c2008
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0xd03c200c
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0xd03c2010
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0xd03c2014
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0xd03c2018
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0xd03c201c
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0xd03c2020
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0xd03c2024
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0xd03c2028
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0xd03c202c
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0xd03c2030
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0xd03c2034
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0xd03c2038
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0xd03c203c
+#define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0xd03c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+// base address: 0xd0400000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0xd0400000
+#define cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA 0xd0400004
+#define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0xd0400018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1
+// base address: 0xd0400000
+#define cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0xd0403694
+#define cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0xd0403780
+#define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0xd040378c
+#define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0xd0403790
+#define cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0xd0403794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+// base address: 0xd0400000
+#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0xd040382c
+#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0xd0403830
+#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd040384c
+#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0403850
+#define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0403854
+#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0403858
+#define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd040385c
+#define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0xd0403898
+#define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0xd040389c
+#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0xd04038a0
+#define cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0xd04038c8
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0xd0403958
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0xd040395c
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0xd0403960
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0xd0403964
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0xd0403968
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0xd040396c
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0xd0403970
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0xd0403974
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0xd0403978
+#define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0xd040397c
+#define cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0xd0403980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2
+// base address: 0xd0400000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0xd0442000
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0xd0442004
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0xd0442008
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0xd044200c
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0xd0442010
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0xd0442014
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0xd0442018
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0xd044201c
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0xd0442020
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0xd0442024
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0xd0442028
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0xd044202c
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0xd0442030
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0xd0442034
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0xd0442038
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0xd044203c
+#define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0xd0443000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+// base address: 0xd0480000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0xd0480000
+#define cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA 0xd0480004
+#define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0xd0480018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1
+// base address: 0xd0480000
+#define cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0xd0483694
+#define cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0xd0483780
+#define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0xd048378c
+#define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0xd0483790
+#define cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0xd0483794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+// base address: 0xd0480000
+#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0xd048382c
+#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0xd0483830
+#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd048384c
+#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0483850
+#define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0483854
+#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0483858
+#define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd048385c
+#define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0xd0483898
+#define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0xd048389c
+#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0xd04838a0
+#define cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0xd04838c8
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0xd0483958
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0xd048395c
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0xd0483960
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0xd0483964
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0xd0483968
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0xd048396c
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0xd0483970
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0xd0483974
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0xd0483978
+#define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0xd048397c
+#define cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0xd0483980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2
+// base address: 0xd0480000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0xd04c2000
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0xd04c2004
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0xd04c2008
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0xd04c200c
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0xd04c2010
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0xd04c2014
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0xd04c2018
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0xd04c201c
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0xd04c2020
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0xd04c2024
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0xd04c2028
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0xd04c202c
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0xd04c2030
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0xd04c2034
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0xd04c2038
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0xd04c203c
+#define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0xd04c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+// base address: 0xd0500000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0xd0500000
+#define cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA 0xd0500004
+#define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0xd0500018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1
+// base address: 0xd0500000
+#define cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0xd0503694
+#define cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0xd0503780
+#define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0xd050378c
+#define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0xd0503790
+#define cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0xd0503794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+// base address: 0xd0500000
+#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0xd050382c
+#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0xd0503830
+#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd050384c
+#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0503850
+#define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0503854
+#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0503858
+#define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd050385c
+#define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0xd0503898
+#define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0xd050389c
+#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0xd05038a0
+#define cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0xd05038c8
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0xd0503958
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0xd050395c
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0xd0503960
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0xd0503964
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0xd0503968
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0xd050396c
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0xd0503970
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0xd0503974
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0xd0503978
+#define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0xd050397c
+#define cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0xd0503980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2
+// base address: 0xd0500000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0xd0542000
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0xd0542004
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0xd0542008
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0xd054200c
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0xd0542010
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0xd0542014
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0xd0542018
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0xd054201c
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0xd0542020
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0xd0542024
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0xd0542028
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0xd054202c
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0xd0542030
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0xd0542034
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0xd0542038
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0xd054203c
+#define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0xd0543000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+// base address: 0xd0580000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0xd0580000
+#define cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA 0xd0580004
+#define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0xd0580018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1
+// base address: 0xd0580000
+#define cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0xd0583694
+#define cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0xd0583780
+#define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0xd058378c
+#define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0xd0583790
+#define cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0xd0583794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+// base address: 0xd0580000
+#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0xd058382c
+#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0xd0583830
+#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd058384c
+#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0583850
+#define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0583854
+#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0583858
+#define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd058385c
+#define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0xd0583898
+#define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0xd058389c
+#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0xd05838a0
+#define cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0xd05838c8
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0xd0583958
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0xd058395c
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0xd0583960
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0xd0583964
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0xd0583968
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0xd058396c
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0xd0583970
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0xd0583974
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0xd0583978
+#define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0xd058397c
+#define cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0xd0583980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2
+// base address: 0xd0580000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0xd05c2000
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0xd05c2004
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0xd05c2008
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0xd05c200c
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0xd05c2010
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0xd05c2014
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0xd05c2018
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0xd05c201c
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0xd05c2020
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0xd05c2024
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0xd05c2028
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0xd05c202c
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0xd05c2030
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0xd05c2034
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0xd05c2038
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0xd05c203c
+#define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0xd05c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+// base address: 0xd0600000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0xd0600000
+#define cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA 0xd0600004
+#define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0xd0600018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1
+// base address: 0xd0600000
+#define cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0xd0603694
+#define cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0xd0603780
+#define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0xd060378c
+#define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0xd0603790
+#define cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0xd0603794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+// base address: 0xd0600000
+#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0xd060382c
+#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0xd0603830
+#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd060384c
+#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0603850
+#define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0603854
+#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0603858
+#define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd060385c
+#define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0xd0603898
+#define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0xd060389c
+#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0xd06038a0
+#define cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0xd06038c8
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0xd0603958
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0xd060395c
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0xd0603960
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0xd0603964
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0xd0603968
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0xd060396c
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0xd0603970
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0xd0603974
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0xd0603978
+#define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0xd060397c
+#define cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0xd0603980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2
+// base address: 0xd0600000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0xd0642000
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0xd0642004
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0xd0642008
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0xd064200c
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0xd0642010
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0xd0642014
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0xd0642018
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0xd064201c
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0xd0642020
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0xd0642024
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0xd0642028
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0xd064202c
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0xd0642030
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0xd0642034
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0xd0642038
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0xd064203c
+#define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0xd0643000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+// base address: 0xd0680000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0xd0680000
+#define cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA 0xd0680004
+#define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0xd0680018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1
+// base address: 0xd0680000
+#define cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0xd0683694
+#define cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0xd0683780
+#define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0xd068378c
+#define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0xd0683790
+#define cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0xd0683794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+// base address: 0xd0680000
+#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0xd068382c
+#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0xd0683830
+#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd068384c
+#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0683850
+#define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0683854
+#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0683858
+#define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd068385c
+#define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0xd0683898
+#define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0xd068389c
+#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0xd06838a0
+#define cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0xd06838c8
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0xd0683958
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0xd068395c
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0xd0683960
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0xd0683964
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0xd0683968
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0xd068396c
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0xd0683970
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0xd0683974
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0xd0683978
+#define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0xd068397c
+#define cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0xd0683980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2
+// base address: 0xd0680000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0xd06c2000
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0xd06c2004
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0xd06c2008
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0xd06c200c
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0xd06c2010
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0xd06c2014
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0xd06c2018
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0xd06c201c
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0xd06c2020
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0xd06c2024
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0xd06c2028
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0xd06c202c
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0xd06c2030
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0xd06c2034
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0xd06c2038
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0xd06c203c
+#define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0xd06c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+// base address: 0xd0700000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0xd0700000
+#define cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA 0xd0700004
+#define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0xd0700018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1
+// base address: 0xd0700000
+#define cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0xd0703694
+#define cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0xd0703780
+#define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0xd070378c
+#define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0xd0703790
+#define cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0xd0703794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+// base address: 0xd0700000
+#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0xd070382c
+#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0xd0703830
+#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd070384c
+#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0703850
+#define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0703854
+#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0703858
+#define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd070385c
+#define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0xd0703898
+#define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0xd070389c
+#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0xd07038a0
+#define cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0xd07038c8
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0xd0703958
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0xd070395c
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0xd0703960
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0xd0703964
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0xd0703968
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0xd070396c
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0xd0703970
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0xd0703974
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0xd0703978
+#define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0xd070397c
+#define cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0xd0703980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2
+// base address: 0xd0700000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0xd0742000
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0xd0742004
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0xd0742008
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0xd074200c
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0xd0742010
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0xd0742014
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0xd0742018
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0xd074201c
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0xd0742020
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0xd0742024
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0xd0742028
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0xd074202c
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0xd0742030
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0xd0742034
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0xd0742038
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0xd074203c
+#define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0xd0743000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+// base address: 0xd0780000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0xd0780000
+#define cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA 0xd0780004
+#define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0xd0780018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1
+// base address: 0xd0780000
+#define cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0xd0783694
+#define cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0xd0783780
+#define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0xd078378c
+#define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0xd0783790
+#define cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0xd0783794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+// base address: 0xd0780000
+#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0xd078382c
+#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0xd0783830
+#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd078384c
+#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0783850
+#define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0783854
+#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0783858
+#define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd078385c
+#define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0xd0783898
+#define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0xd078389c
+#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0xd07838a0
+#define cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0xd07838c8
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0xd0783958
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0xd078395c
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0xd0783960
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0xd0783964
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0xd0783968
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0xd078396c
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0xd0783970
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0xd0783974
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0xd0783978
+#define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0xd078397c
+#define cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0xd0783980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2
+// base address: 0xd0780000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0xd07c2000
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0xd07c2004
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0xd07c2008
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0xd07c200c
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0xd07c2010
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0xd07c2014
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0xd07c2018
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0xd07c201c
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0xd07c2020
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0xd07c2024
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0xd07c2028
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0xd07c202c
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0xd07c2030
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0xd07c2034
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0xd07c2038
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0xd07c203c
+#define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0xd07c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC
+// base address: 0xd0800000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX 0xd0800000
+#define cfgBIF_BX_DEV0_EPF0_VF16_MM_DATA 0xd0800004
+#define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI 0xd0800018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1
+// base address: 0xd0800000
+#define cfgRCC_DEV0_EPF0_VF16_RCC_ERR_LOG 0xd0803694
+#define cfgRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN 0xd0803780
+#define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE 0xd080378c
+#define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED 0xd0803790
+#define cfgRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER 0xd0803794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1
+// base address: 0xd0800000
+#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS 0xd080382c
+#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG 0xd0803830
+#define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd080384c
+#define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0803850
+#define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0803854
+#define cfgBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0803858
+#define cfgBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd080385c
+#define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ 0xd0803898
+#define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE 0xd080389c
+#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING 0xd08038a0
+#define cfgBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS 0xd08038c8
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0 0xd0803958
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1 0xd080395c
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2 0xd0803960
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3 0xd0803964
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0 0xd0803968
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1 0xd080396c
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2 0xd0803970
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3 0xd0803974
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL 0xd0803978
+#define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL 0xd080397c
+#define cfgBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX 0xd0803980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2
+// base address: 0xd0800000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO 0xd0842000
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI 0xd0842004
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA 0xd0842008
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL 0xd084200c
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO 0xd0842010
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI 0xd0842014
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA 0xd0842018
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL 0xd084201c
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO 0xd0842020
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI 0xd0842024
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA 0xd0842028
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL 0xd084202c
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO 0xd0842030
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI 0xd0842034
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA 0xd0842038
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL 0xd084203c
+#define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_PBA 0xd0843000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC
+// base address: 0xd0880000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX 0xd0880000
+#define cfgBIF_BX_DEV0_EPF0_VF17_MM_DATA 0xd0880004
+#define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI 0xd0880018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1
+// base address: 0xd0880000
+#define cfgRCC_DEV0_EPF0_VF17_RCC_ERR_LOG 0xd0883694
+#define cfgRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN 0xd0883780
+#define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE 0xd088378c
+#define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED 0xd0883790
+#define cfgRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER 0xd0883794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1
+// base address: 0xd0880000
+#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS 0xd088382c
+#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG 0xd0883830
+#define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd088384c
+#define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0883850
+#define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0883854
+#define cfgBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0883858
+#define cfgBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd088385c
+#define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ 0xd0883898
+#define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE 0xd088389c
+#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING 0xd08838a0
+#define cfgBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS 0xd08838c8
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0 0xd0883958
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1 0xd088395c
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2 0xd0883960
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3 0xd0883964
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0 0xd0883968
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1 0xd088396c
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2 0xd0883970
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3 0xd0883974
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL 0xd0883978
+#define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL 0xd088397c
+#define cfgBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX 0xd0883980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2
+// base address: 0xd0880000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO 0xd08c2000
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI 0xd08c2004
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA 0xd08c2008
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL 0xd08c200c
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO 0xd08c2010
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI 0xd08c2014
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA 0xd08c2018
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL 0xd08c201c
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO 0xd08c2020
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI 0xd08c2024
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA 0xd08c2028
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL 0xd08c202c
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO 0xd08c2030
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI 0xd08c2034
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA 0xd08c2038
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL 0xd08c203c
+#define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_PBA 0xd08c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC
+// base address: 0xd0900000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX 0xd0900000
+#define cfgBIF_BX_DEV0_EPF0_VF18_MM_DATA 0xd0900004
+#define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI 0xd0900018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1
+// base address: 0xd0900000
+#define cfgRCC_DEV0_EPF0_VF18_RCC_ERR_LOG 0xd0903694
+#define cfgRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN 0xd0903780
+#define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE 0xd090378c
+#define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED 0xd0903790
+#define cfgRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER 0xd0903794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1
+// base address: 0xd0900000
+#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS 0xd090382c
+#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG 0xd0903830
+#define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd090384c
+#define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0903850
+#define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0903854
+#define cfgBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0903858
+#define cfgBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd090385c
+#define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ 0xd0903898
+#define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE 0xd090389c
+#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING 0xd09038a0
+#define cfgBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS 0xd09038c8
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0 0xd0903958
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1 0xd090395c
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2 0xd0903960
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3 0xd0903964
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0 0xd0903968
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1 0xd090396c
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2 0xd0903970
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3 0xd0903974
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL 0xd0903978
+#define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL 0xd090397c
+#define cfgBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX 0xd0903980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2
+// base address: 0xd0900000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO 0xd0942000
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI 0xd0942004
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA 0xd0942008
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL 0xd094200c
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO 0xd0942010
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI 0xd0942014
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA 0xd0942018
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL 0xd094201c
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO 0xd0942020
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI 0xd0942024
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA 0xd0942028
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL 0xd094202c
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO 0xd0942030
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI 0xd0942034
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA 0xd0942038
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL 0xd094203c
+#define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_PBA 0xd0943000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC
+// base address: 0xd0980000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX 0xd0980000
+#define cfgBIF_BX_DEV0_EPF0_VF19_MM_DATA 0xd0980004
+#define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI 0xd0980018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1
+// base address: 0xd0980000
+#define cfgRCC_DEV0_EPF0_VF19_RCC_ERR_LOG 0xd0983694
+#define cfgRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN 0xd0983780
+#define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE 0xd098378c
+#define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED 0xd0983790
+#define cfgRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER 0xd0983794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1
+// base address: 0xd0980000
+#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS 0xd098382c
+#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG 0xd0983830
+#define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd098384c
+#define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0983850
+#define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0983854
+#define cfgBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0983858
+#define cfgBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd098385c
+#define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ 0xd0983898
+#define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE 0xd098389c
+#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING 0xd09838a0
+#define cfgBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS 0xd09838c8
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0 0xd0983958
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1 0xd098395c
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2 0xd0983960
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3 0xd0983964
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0 0xd0983968
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1 0xd098396c
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2 0xd0983970
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3 0xd0983974
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL 0xd0983978
+#define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL 0xd098397c
+#define cfgBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX 0xd0983980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2
+// base address: 0xd0980000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO 0xd09c2000
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI 0xd09c2004
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA 0xd09c2008
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL 0xd09c200c
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO 0xd09c2010
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI 0xd09c2014
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA 0xd09c2018
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL 0xd09c201c
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO 0xd09c2020
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI 0xd09c2024
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA 0xd09c2028
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL 0xd09c202c
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO 0xd09c2030
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI 0xd09c2034
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA 0xd09c2038
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL 0xd09c203c
+#define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_PBA 0xd09c3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC
+// base address: 0xd0a00000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX 0xd0a00000
+#define cfgBIF_BX_DEV0_EPF0_VF20_MM_DATA 0xd0a00004
+#define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI 0xd0a00018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1
+// base address: 0xd0a00000
+#define cfgRCC_DEV0_EPF0_VF20_RCC_ERR_LOG 0xd0a03694
+#define cfgRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN 0xd0a03780
+#define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE 0xd0a0378c
+#define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED 0xd0a03790
+#define cfgRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER 0xd0a03794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1
+// base address: 0xd0a00000
+#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS 0xd0a0382c
+#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG 0xd0a03830
+#define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0a0384c
+#define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0a03850
+#define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0a03854
+#define cfgBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0a03858
+#define cfgBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0a0385c
+#define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ 0xd0a03898
+#define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE 0xd0a0389c
+#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING 0xd0a038a0
+#define cfgBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS 0xd0a038c8
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0 0xd0a03958
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1 0xd0a0395c
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2 0xd0a03960
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3 0xd0a03964
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0 0xd0a03968
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1 0xd0a0396c
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2 0xd0a03970
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3 0xd0a03974
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL 0xd0a03978
+#define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL 0xd0a0397c
+#define cfgBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX 0xd0a03980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2
+// base address: 0xd0a00000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO 0xd0a42000
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI 0xd0a42004
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA 0xd0a42008
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL 0xd0a4200c
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO 0xd0a42010
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI 0xd0a42014
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA 0xd0a42018
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL 0xd0a4201c
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO 0xd0a42020
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI 0xd0a42024
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA 0xd0a42028
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL 0xd0a4202c
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO 0xd0a42030
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI 0xd0a42034
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA 0xd0a42038
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL 0xd0a4203c
+#define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_PBA 0xd0a43000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC
+// base address: 0xd0a80000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX 0xd0a80000
+#define cfgBIF_BX_DEV0_EPF0_VF21_MM_DATA 0xd0a80004
+#define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI 0xd0a80018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1
+// base address: 0xd0a80000
+#define cfgRCC_DEV0_EPF0_VF21_RCC_ERR_LOG 0xd0a83694
+#define cfgRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN 0xd0a83780
+#define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE 0xd0a8378c
+#define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED 0xd0a83790
+#define cfgRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER 0xd0a83794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1
+// base address: 0xd0a80000
+#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS 0xd0a8382c
+#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG 0xd0a83830
+#define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0a8384c
+#define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0a83850
+#define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0a83854
+#define cfgBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0a83858
+#define cfgBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0a8385c
+#define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ 0xd0a83898
+#define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE 0xd0a8389c
+#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING 0xd0a838a0
+#define cfgBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS 0xd0a838c8
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0 0xd0a83958
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1 0xd0a8395c
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2 0xd0a83960
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3 0xd0a83964
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0 0xd0a83968
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1 0xd0a8396c
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2 0xd0a83970
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3 0xd0a83974
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL 0xd0a83978
+#define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL 0xd0a8397c
+#define cfgBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX 0xd0a83980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2
+// base address: 0xd0a80000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO 0xd0ac2000
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI 0xd0ac2004
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA 0xd0ac2008
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL 0xd0ac200c
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO 0xd0ac2010
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI 0xd0ac2014
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA 0xd0ac2018
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL 0xd0ac201c
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO 0xd0ac2020
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI 0xd0ac2024
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA 0xd0ac2028
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL 0xd0ac202c
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO 0xd0ac2030
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI 0xd0ac2034
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA 0xd0ac2038
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL 0xd0ac203c
+#define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_PBA 0xd0ac3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC
+// base address: 0xd0b00000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX 0xd0b00000
+#define cfgBIF_BX_DEV0_EPF0_VF22_MM_DATA 0xd0b00004
+#define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI 0xd0b00018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1
+// base address: 0xd0b00000
+#define cfgRCC_DEV0_EPF0_VF22_RCC_ERR_LOG 0xd0b03694
+#define cfgRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN 0xd0b03780
+#define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE 0xd0b0378c
+#define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED 0xd0b03790
+#define cfgRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER 0xd0b03794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1
+// base address: 0xd0b00000
+#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS 0xd0b0382c
+#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG 0xd0b03830
+#define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0b0384c
+#define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0b03850
+#define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0b03854
+#define cfgBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0b03858
+#define cfgBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0b0385c
+#define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ 0xd0b03898
+#define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE 0xd0b0389c
+#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING 0xd0b038a0
+#define cfgBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS 0xd0b038c8
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0 0xd0b03958
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1 0xd0b0395c
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2 0xd0b03960
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3 0xd0b03964
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0 0xd0b03968
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1 0xd0b0396c
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2 0xd0b03970
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3 0xd0b03974
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL 0xd0b03978
+#define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL 0xd0b0397c
+#define cfgBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX 0xd0b03980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2
+// base address: 0xd0b00000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO 0xd0b42000
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI 0xd0b42004
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA 0xd0b42008
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL 0xd0b4200c
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO 0xd0b42010
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI 0xd0b42014
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA 0xd0b42018
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL 0xd0b4201c
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO 0xd0b42020
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI 0xd0b42024
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA 0xd0b42028
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL 0xd0b4202c
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO 0xd0b42030
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI 0xd0b42034
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA 0xd0b42038
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL 0xd0b4203c
+#define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_PBA 0xd0b43000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC
+// base address: 0xd0b80000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX 0xd0b80000
+#define cfgBIF_BX_DEV0_EPF0_VF23_MM_DATA 0xd0b80004
+#define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI 0xd0b80018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1
+// base address: 0xd0b80000
+#define cfgRCC_DEV0_EPF0_VF23_RCC_ERR_LOG 0xd0b83694
+#define cfgRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN 0xd0b83780
+#define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE 0xd0b8378c
+#define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED 0xd0b83790
+#define cfgRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER 0xd0b83794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1
+// base address: 0xd0b80000
+#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS 0xd0b8382c
+#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG 0xd0b83830
+#define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0b8384c
+#define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0b83850
+#define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0b83854
+#define cfgBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0b83858
+#define cfgBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0b8385c
+#define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ 0xd0b83898
+#define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE 0xd0b8389c
+#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING 0xd0b838a0
+#define cfgBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS 0xd0b838c8
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0 0xd0b83958
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1 0xd0b8395c
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2 0xd0b83960
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3 0xd0b83964
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0 0xd0b83968
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1 0xd0b8396c
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2 0xd0b83970
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3 0xd0b83974
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL 0xd0b83978
+#define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL 0xd0b8397c
+#define cfgBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX 0xd0b83980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2
+// base address: 0xd0b80000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO 0xd0bc2000
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI 0xd0bc2004
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA 0xd0bc2008
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL 0xd0bc200c
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO 0xd0bc2010
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI 0xd0bc2014
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA 0xd0bc2018
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL 0xd0bc201c
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO 0xd0bc2020
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI 0xd0bc2024
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA 0xd0bc2028
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL 0xd0bc202c
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO 0xd0bc2030
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI 0xd0bc2034
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA 0xd0bc2038
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL 0xd0bc203c
+#define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_PBA 0xd0bc3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC
+// base address: 0xd0c00000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX 0xd0c00000
+#define cfgBIF_BX_DEV0_EPF0_VF24_MM_DATA 0xd0c00004
+#define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI 0xd0c00018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1
+// base address: 0xd0c00000
+#define cfgRCC_DEV0_EPF0_VF24_RCC_ERR_LOG 0xd0c03694
+#define cfgRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN 0xd0c03780
+#define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE 0xd0c0378c
+#define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED 0xd0c03790
+#define cfgRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER 0xd0c03794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1
+// base address: 0xd0c00000
+#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS 0xd0c0382c
+#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG 0xd0c03830
+#define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0c0384c
+#define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0c03850
+#define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0c03854
+#define cfgBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0c03858
+#define cfgBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0c0385c
+#define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ 0xd0c03898
+#define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE 0xd0c0389c
+#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING 0xd0c038a0
+#define cfgBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS 0xd0c038c8
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0 0xd0c03958
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1 0xd0c0395c
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2 0xd0c03960
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3 0xd0c03964
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0 0xd0c03968
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1 0xd0c0396c
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2 0xd0c03970
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3 0xd0c03974
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL 0xd0c03978
+#define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL 0xd0c0397c
+#define cfgBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX 0xd0c03980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2
+// base address: 0xd0c00000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO 0xd0c42000
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI 0xd0c42004
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA 0xd0c42008
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL 0xd0c4200c
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO 0xd0c42010
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI 0xd0c42014
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA 0xd0c42018
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL 0xd0c4201c
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO 0xd0c42020
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI 0xd0c42024
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA 0xd0c42028
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL 0xd0c4202c
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO 0xd0c42030
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI 0xd0c42034
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA 0xd0c42038
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL 0xd0c4203c
+#define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_PBA 0xd0c43000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC
+// base address: 0xd0c80000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX 0xd0c80000
+#define cfgBIF_BX_DEV0_EPF0_VF25_MM_DATA 0xd0c80004
+#define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI 0xd0c80018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1
+// base address: 0xd0c80000
+#define cfgRCC_DEV0_EPF0_VF25_RCC_ERR_LOG 0xd0c83694
+#define cfgRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN 0xd0c83780
+#define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE 0xd0c8378c
+#define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED 0xd0c83790
+#define cfgRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER 0xd0c83794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1
+// base address: 0xd0c80000
+#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS 0xd0c8382c
+#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG 0xd0c83830
+#define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0c8384c
+#define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0c83850
+#define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0c83854
+#define cfgBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0c83858
+#define cfgBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0c8385c
+#define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ 0xd0c83898
+#define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE 0xd0c8389c
+#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING 0xd0c838a0
+#define cfgBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS 0xd0c838c8
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0 0xd0c83958
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1 0xd0c8395c
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2 0xd0c83960
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3 0xd0c83964
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0 0xd0c83968
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1 0xd0c8396c
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2 0xd0c83970
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3 0xd0c83974
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL 0xd0c83978
+#define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL 0xd0c8397c
+#define cfgBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX 0xd0c83980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2
+// base address: 0xd0c80000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO 0xd0cc2000
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI 0xd0cc2004
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA 0xd0cc2008
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL 0xd0cc200c
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO 0xd0cc2010
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI 0xd0cc2014
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA 0xd0cc2018
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL 0xd0cc201c
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO 0xd0cc2020
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI 0xd0cc2024
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA 0xd0cc2028
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL 0xd0cc202c
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO 0xd0cc2030
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI 0xd0cc2034
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA 0xd0cc2038
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL 0xd0cc203c
+#define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_PBA 0xd0cc3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC
+// base address: 0xd0d00000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX 0xd0d00000
+#define cfgBIF_BX_DEV0_EPF0_VF26_MM_DATA 0xd0d00004
+#define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI 0xd0d00018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1
+// base address: 0xd0d00000
+#define cfgRCC_DEV0_EPF0_VF26_RCC_ERR_LOG 0xd0d03694
+#define cfgRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN 0xd0d03780
+#define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE 0xd0d0378c
+#define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED 0xd0d03790
+#define cfgRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER 0xd0d03794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1
+// base address: 0xd0d00000
+#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS 0xd0d0382c
+#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG 0xd0d03830
+#define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0d0384c
+#define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0d03850
+#define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0d03854
+#define cfgBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0d03858
+#define cfgBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0d0385c
+#define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ 0xd0d03898
+#define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE 0xd0d0389c
+#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING 0xd0d038a0
+#define cfgBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS 0xd0d038c8
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0 0xd0d03958
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1 0xd0d0395c
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2 0xd0d03960
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3 0xd0d03964
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0 0xd0d03968
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1 0xd0d0396c
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2 0xd0d03970
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3 0xd0d03974
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL 0xd0d03978
+#define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL 0xd0d0397c
+#define cfgBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX 0xd0d03980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2
+// base address: 0xd0d00000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO 0xd0d42000
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI 0xd0d42004
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA 0xd0d42008
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL 0xd0d4200c
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO 0xd0d42010
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI 0xd0d42014
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA 0xd0d42018
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL 0xd0d4201c
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO 0xd0d42020
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI 0xd0d42024
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA 0xd0d42028
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL 0xd0d4202c
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO 0xd0d42030
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI 0xd0d42034
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA 0xd0d42038
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL 0xd0d4203c
+#define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_PBA 0xd0d43000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC
+// base address: 0xd0d80000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX 0xd0d80000
+#define cfgBIF_BX_DEV0_EPF0_VF27_MM_DATA 0xd0d80004
+#define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI 0xd0d80018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1
+// base address: 0xd0d80000
+#define cfgRCC_DEV0_EPF0_VF27_RCC_ERR_LOG 0xd0d83694
+#define cfgRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN 0xd0d83780
+#define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE 0xd0d8378c
+#define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED 0xd0d83790
+#define cfgRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER 0xd0d83794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1
+// base address: 0xd0d80000
+#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS 0xd0d8382c
+#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG 0xd0d83830
+#define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0d8384c
+#define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0d83850
+#define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0d83854
+#define cfgBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0d83858
+#define cfgBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0d8385c
+#define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ 0xd0d83898
+#define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE 0xd0d8389c
+#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING 0xd0d838a0
+#define cfgBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS 0xd0d838c8
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0 0xd0d83958
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1 0xd0d8395c
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2 0xd0d83960
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3 0xd0d83964
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0 0xd0d83968
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1 0xd0d8396c
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2 0xd0d83970
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3 0xd0d83974
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL 0xd0d83978
+#define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL 0xd0d8397c
+#define cfgBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX 0xd0d83980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2
+// base address: 0xd0d80000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO 0xd0dc2000
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI 0xd0dc2004
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA 0xd0dc2008
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL 0xd0dc200c
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO 0xd0dc2010
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI 0xd0dc2014
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA 0xd0dc2018
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL 0xd0dc201c
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO 0xd0dc2020
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI 0xd0dc2024
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA 0xd0dc2028
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL 0xd0dc202c
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO 0xd0dc2030
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI 0xd0dc2034
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA 0xd0dc2038
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL 0xd0dc203c
+#define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_PBA 0xd0dc3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC
+// base address: 0xd0e00000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX 0xd0e00000
+#define cfgBIF_BX_DEV0_EPF0_VF28_MM_DATA 0xd0e00004
+#define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI 0xd0e00018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1
+// base address: 0xd0e00000
+#define cfgRCC_DEV0_EPF0_VF28_RCC_ERR_LOG 0xd0e03694
+#define cfgRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN 0xd0e03780
+#define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE 0xd0e0378c
+#define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED 0xd0e03790
+#define cfgRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER 0xd0e03794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1
+// base address: 0xd0e00000
+#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS 0xd0e0382c
+#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG 0xd0e03830
+#define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0e0384c
+#define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0e03850
+#define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0e03854
+#define cfgBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0e03858
+#define cfgBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0e0385c
+#define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ 0xd0e03898
+#define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE 0xd0e0389c
+#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING 0xd0e038a0
+#define cfgBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS 0xd0e038c8
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0 0xd0e03958
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1 0xd0e0395c
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2 0xd0e03960
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3 0xd0e03964
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0 0xd0e03968
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1 0xd0e0396c
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2 0xd0e03970
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3 0xd0e03974
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL 0xd0e03978
+#define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL 0xd0e0397c
+#define cfgBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX 0xd0e03980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2
+// base address: 0xd0e00000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO 0xd0e42000
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI 0xd0e42004
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA 0xd0e42008
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL 0xd0e4200c
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO 0xd0e42010
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI 0xd0e42014
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA 0xd0e42018
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL 0xd0e4201c
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO 0xd0e42020
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI 0xd0e42024
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA 0xd0e42028
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL 0xd0e4202c
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO 0xd0e42030
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI 0xd0e42034
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA 0xd0e42038
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL 0xd0e4203c
+#define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_PBA 0xd0e43000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC
+// base address: 0xd0e80000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX 0xd0e80000
+#define cfgBIF_BX_DEV0_EPF0_VF29_MM_DATA 0xd0e80004
+#define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI 0xd0e80018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1
+// base address: 0xd0e80000
+#define cfgRCC_DEV0_EPF0_VF29_RCC_ERR_LOG 0xd0e83694
+#define cfgRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN 0xd0e83780
+#define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE 0xd0e8378c
+#define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED 0xd0e83790
+#define cfgRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER 0xd0e83794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1
+// base address: 0xd0e80000
+#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS 0xd0e8382c
+#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG 0xd0e83830
+#define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0e8384c
+#define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0e83850
+#define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0e83854
+#define cfgBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0e83858
+#define cfgBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0e8385c
+#define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ 0xd0e83898
+#define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE 0xd0e8389c
+#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING 0xd0e838a0
+#define cfgBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS 0xd0e838c8
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0 0xd0e83958
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1 0xd0e8395c
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2 0xd0e83960
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3 0xd0e83964
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0 0xd0e83968
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1 0xd0e8396c
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2 0xd0e83970
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3 0xd0e83974
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL 0xd0e83978
+#define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL 0xd0e8397c
+#define cfgBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX 0xd0e83980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2
+// base address: 0xd0e80000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO 0xd0ec2000
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI 0xd0ec2004
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA 0xd0ec2008
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL 0xd0ec200c
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO 0xd0ec2010
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI 0xd0ec2014
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA 0xd0ec2018
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL 0xd0ec201c
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO 0xd0ec2020
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI 0xd0ec2024
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA 0xd0ec2028
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL 0xd0ec202c
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO 0xd0ec2030
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI 0xd0ec2034
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA 0xd0ec2038
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL 0xd0ec203c
+#define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_PBA 0xd0ec3000
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC
+// base address: 0xd0f00000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX 0xd0f00000
+#define cfgBIF_BX_DEV0_EPF0_VF30_MM_DATA 0xd0f00004
+#define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI 0xd0f00018
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1
+// base address: 0xd0f00000
+#define cfgRCC_DEV0_EPF0_VF30_RCC_ERR_LOG 0xd0f03694
+#define cfgRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN 0xd0f03780
+#define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE 0xd0f0378c
+#define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED 0xd0f03790
+#define cfgRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER 0xd0f03794
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1
+// base address: 0xd0f00000
+#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS 0xd0f0382c
+#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG 0xd0f03830
+#define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0f0384c
+#define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0f03850
+#define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0f03854
+#define cfgBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0f03858
+#define cfgBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0f0385c
+#define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ 0xd0f03898
+#define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE 0xd0f0389c
+#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING 0xd0f038a0
+#define cfgBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS 0xd0f038c8
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0 0xd0f03958
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1 0xd0f0395c
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2 0xd0f03960
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3 0xd0f03964
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0 0xd0f03968
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1 0xd0f0396c
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2 0xd0f03970
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3 0xd0f03974
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL 0xd0f03978
+#define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL 0xd0f0397c
+#define cfgBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX 0xd0f03980
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2
+// base address: 0xd0f00000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO 0xd0f42000
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI 0xd0f42004
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA 0xd0f42008
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL 0xd0f4200c
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO 0xd0f42010
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI 0xd0f42014
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA 0xd0f42018
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL 0xd0f4201c
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO 0xd0f42020
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI 0xd0f42024
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA 0xd0f42028
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL 0xd0f4202c
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO 0xd0f42030
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI 0xd0f42034
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA 0xd0f42038
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL 0xd0f4203c
+#define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_PBA 0xd0f43000
+
+
+// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp
+// base address: 0xfffe00000000
+#define cfgPSWUSCFG0_1_VENDOR_ID 0xfffe00000000
+#define cfgPSWUSCFG0_1_DEVICE_ID 0xfffe00000002
+#define cfgPSWUSCFG0_1_COMMAND 0xfffe00000004
+#define cfgPSWUSCFG0_1_STATUS 0xfffe00000006
+#define cfgPSWUSCFG0_1_REVISION_ID 0xfffe00000008
+#define cfgPSWUSCFG0_1_PROG_INTERFACE 0xfffe00000009
+#define cfgPSWUSCFG0_1_SUB_CLASS 0xfffe0000000a
+#define cfgPSWUSCFG0_1_BASE_CLASS 0xfffe0000000b
+#define cfgPSWUSCFG0_1_CACHE_LINE 0xfffe0000000c
+#define cfgPSWUSCFG0_1_LATENCY 0xfffe0000000d
+#define cfgPSWUSCFG0_1_HEADER 0xfffe0000000e
+#define cfgPSWUSCFG0_1_BIST 0xfffe0000000f
+#define cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY 0xfffe00000018
+#define cfgPSWUSCFG0_1_IO_BASE_LIMIT 0xfffe0000001c
+#define cfgPSWUSCFG0_1_SECONDARY_STATUS 0xfffe0000001e
+#define cfgPSWUSCFG0_1_MEM_BASE_LIMIT 0xfffe00000020
+#define cfgPSWUSCFG0_1_PREF_BASE_LIMIT 0xfffe00000024
+#define cfgPSWUSCFG0_1_PREF_BASE_UPPER 0xfffe00000028
+#define cfgPSWUSCFG0_1_PREF_LIMIT_UPPER 0xfffe0000002c
+#define cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI 0xfffe00000030
+#define cfgPSWUSCFG0_1_CAP_PTR 0xfffe00000034
+#define cfgPSWUSCFG0_1_ROM_BASE_ADDR 0xfffe00000038
+#define cfgPSWUSCFG0_1_INTERRUPT_LINE 0xfffe0000003c
+#define cfgPSWUSCFG0_1_INTERRUPT_PIN 0xfffe0000003d
+#define cfgPSWUSCFG0_1_IRQ_BRIDGE_CNTL 0xfffe0000003e
+#define cfgPSWUSCFG0_1_EXT_BRIDGE_CNTL 0xfffe00000040
+#define cfgPSWUSCFG0_1_VENDOR_CAP_LIST 0xfffe00000048
+#define cfgPSWUSCFG0_1_ADAPTER_ID_W 0xfffe0000004c
+#define cfgPSWUSCFG0_1_PMI_CAP_LIST 0xfffe00000050
+#define cfgPSWUSCFG0_1_PMI_CAP 0xfffe00000052
+#define cfgPSWUSCFG0_1_PMI_STATUS_CNTL 0xfffe00000054
+#define cfgPSWUSCFG0_1_PCIE_CAP_LIST 0xfffe00000058
+#define cfgPSWUSCFG0_1_PCIE_CAP 0xfffe0000005a
+#define cfgPSWUSCFG0_1_DEVICE_CAP 0xfffe0000005c
+#define cfgPSWUSCFG0_1_DEVICE_CNTL 0xfffe00000060
+#define cfgPSWUSCFG0_1_DEVICE_STATUS 0xfffe00000062
+#define cfgPSWUSCFG0_1_LINK_CAP 0xfffe00000064
+#define cfgPSWUSCFG0_1_LINK_CNTL 0xfffe00000068
+#define cfgPSWUSCFG0_1_LINK_STATUS 0xfffe0000006a
+#define cfgPSWUSCFG0_1_DEVICE_CAP2 0xfffe0000007c
+#define cfgPSWUSCFG0_1_DEVICE_CNTL2 0xfffe00000080
+#define cfgPSWUSCFG0_1_DEVICE_STATUS2 0xfffe00000082
+#define cfgPSWUSCFG0_1_LINK_CAP2 0xfffe00000084
+#define cfgPSWUSCFG0_1_LINK_CNTL2 0xfffe00000088
+#define cfgPSWUSCFG0_1_LINK_STATUS2 0xfffe0000008a
+#define cfgPSWUSCFG0_1_MSI_CAP_LIST 0xfffe000000a0
+#define cfgPSWUSCFG0_1_MSI_MSG_CNTL 0xfffe000000a2
+#define cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO 0xfffe000000a4
+#define cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI 0xfffe000000a8
+#define cfgPSWUSCFG0_1_MSI_MSG_DATA 0xfffe000000a8
+#define cfgPSWUSCFG0_1_MSI_MSG_DATA_64 0xfffe000000ac
+#define cfgPSWUSCFG0_1_SSID_CAP_LIST 0xfffe000000c0
+#define cfgPSWUSCFG0_1_SSID_CAP 0xfffe000000c4
+#define cfgPSWUSCFG0_1_MSI_MAP_CAP_LIST 0xfffe000000c8
+#define cfgPSWUSCFG0_1_MSI_MAP_CAP 0xfffe000000ca
+#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe00000100
+#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe00000104
+#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1 0xfffe00000108
+#define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2 0xfffe0000010c
+#define cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST 0xfffe00000110
+#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1 0xfffe00000114
+#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2 0xfffe00000118
+#define cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL 0xfffe0000011c
+#define cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS 0xfffe0000011e
+#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP 0xfffe00000120
+#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL 0xfffe00000124
+#define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS 0xfffe0000012a
+#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP 0xfffe0000012c
+#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL 0xfffe00000130
+#define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS 0xfffe00000136
+#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe00000140
+#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe00000144
+#define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe00000148
+#define cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe00000150
+#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS 0xfffe00000154
+#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK 0xfffe00000158
+#define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe0000015c
+#define cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS 0xfffe00000160
+#define cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK 0xfffe00000164
+#define cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe00000168
+#define cfgPSWUSCFG0_1_PCIE_HDR_LOG0 0xfffe0000016c
+#define cfgPSWUSCFG0_1_PCIE_HDR_LOG1 0xfffe00000170
+#define cfgPSWUSCFG0_1_PCIE_HDR_LOG2 0xfffe00000174
+#define cfgPSWUSCFG0_1_PCIE_HDR_LOG3 0xfffe00000178
+#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0 0xfffe00000188
+#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1 0xfffe0000018c
+#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2 0xfffe00000190
+#define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3 0xfffe00000194
+#define cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe00000270
+#define cfgPSWUSCFG0_1_PCIE_LINK_CNTL3 0xfffe00000274
+#define cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS 0xfffe00000278
+#define cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe0000027c
+#define cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe0000027e
+#define cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe00000280
+#define cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe00000282
+#define cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe00000284
+#define cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe00000286
+#define cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe00000288
+#define cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe0000028a
+#define cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe0000028c
+#define cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe0000028e
+#define cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe00000290
+#define cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe00000292
+#define cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe00000294
+#define cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe00000296
+#define cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe00000298
+#define cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe0000029a
+#define cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST 0xfffe000002a0
+#define cfgPSWUSCFG0_1_PCIE_ACS_CAP 0xfffe000002a4
+#define cfgPSWUSCFG0_1_PCIE_ACS_CNTL 0xfffe000002a6
+#define cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST 0xfffe000002f0
+#define cfgPSWUSCFG0_1_PCIE_MC_CAP 0xfffe000002f4
+#define cfgPSWUSCFG0_1_PCIE_MC_CNTL 0xfffe000002f6
+#define cfgPSWUSCFG0_1_PCIE_MC_ADDR0 0xfffe000002f8
+#define cfgPSWUSCFG0_1_PCIE_MC_ADDR1 0xfffe000002fc
+#define cfgPSWUSCFG0_1_PCIE_MC_RCV0 0xfffe00000300
+#define cfgPSWUSCFG0_1_PCIE_MC_RCV1 0xfffe00000304
+#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0 0xfffe00000308
+#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1 0xfffe0000030c
+#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe00000310
+#define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe00000314
+#define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0 0xfffe00000318
+#define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1 0xfffe0000031c
+#define cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST 0xfffe00000320
+#define cfgPSWUSCFG0_1_PCIE_LTR_CAP 0xfffe00000324
+#define cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST 0xfffe00000328
+#define cfgPSWUSCFG0_1_PCIE_ARI_CAP 0xfffe0000032c
+#define cfgPSWUSCFG0_1_PCIE_ARI_CNTL 0xfffe0000032e
+#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST 0xfffe00000370
+#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP 0xfffe00000374
+#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL 0xfffe00000378
+#define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2 0xfffe0000037c
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_LIST 0xfffe000003c4
+#define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_1 0xfffe000003c8
+#define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_2 0xfffe000003cc
+#define cfgPSWUSCFG0_1_PCIE_ESM_STATUS 0xfffe000003ce
+#define cfgPSWUSCFG0_1_PCIE_ESM_CTRL 0xfffe000003d0
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_1 0xfffe000003d4
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_2 0xfffe000003d8
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_3 0xfffe000003dc
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_4 0xfffe000003e0
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_5 0xfffe000003e4
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_6 0xfffe000003e8
+#define cfgPSWUSCFG0_1_PCIE_ESM_CAP_7 0xfffe000003ec
+#define cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST 0xfffe00000400
+#define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP 0xfffe00000404
+#define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS 0xfffe00000408
+#define cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe00000410
+#define cfgPSWUSCFG0_1_LINK_CAP_16GT 0xfffe00000414
+#define cfgPSWUSCFG0_1_LINK_CNTL_16GT 0xfffe00000418
+#define cfgPSWUSCFG0_1_LINK_STATUS_16GT 0xfffe0000041c
+#define cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe00000420
+#define cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe00000424
+#define cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe00000428
+#define cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe00000430
+#define cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe00000431
+#define cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe00000432
+#define cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe00000433
+#define cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe00000434
+#define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe00000435
+#define cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe00000436
+#define cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe00000437
+#define cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe00000438
+#define cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe00000439
+#define cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe0000043a
+#define cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe0000043b
+#define cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe0000043c
+#define cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe0000043d
+#define cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe0000043e
+#define cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe0000043f
+#define cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe00000440
+#define cfgPSWUSCFG0_1_MARGINING_PORT_CAP 0xfffe00000444
+#define cfgPSWUSCFG0_1_MARGINING_PORT_STATUS 0xfffe00000446
+#define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL 0xfffe00000448
+#define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS 0xfffe0000044a
+#define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL 0xfffe0000044c
+#define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS 0xfffe0000044e
+#define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL 0xfffe00000450
+#define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS 0xfffe00000452
+#define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL 0xfffe00000454
+#define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS 0xfffe00000456
+#define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL 0xfffe00000458
+#define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS 0xfffe0000045a
+#define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL 0xfffe0000045c
+#define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS 0xfffe0000045e
+#define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL 0xfffe00000460
+#define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS 0xfffe00000462
+#define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL 0xfffe00000464
+#define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS 0xfffe00000466
+#define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL 0xfffe00000468
+#define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS 0xfffe0000046a
+#define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL 0xfffe0000046c
+#define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS 0xfffe0000046e
+#define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL 0xfffe00000470
+#define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS 0xfffe00000472
+#define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL 0xfffe00000474
+#define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS 0xfffe00000476
+#define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL 0xfffe00000478
+#define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS 0xfffe0000047a
+#define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL 0xfffe0000047c
+#define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS 0xfffe0000047e
+#define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL 0xfffe00000480
+#define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS 0xfffe00000482
+#define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL 0xfffe00000484
+#define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS 0xfffe00000486
+#define cfgPSWUSCFG0_1_PCIE_CCIX_CAP_LIST 0xfffe00000488
+#define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_1 0xfffe0000048c
+#define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_2 0xfffe00000490
+#define cfgPSWUSCFG0_1_PCIE_CCIX_CAP 0xfffe00000492
+#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP 0xfffe00000494
+#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP 0xfffe00000498
+#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_STATUS 0xfffe0000049c
+#define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_CNTL 0xfffe000004a0
+#define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0xfffe000004a4
+#define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0xfffe000004a5
+#define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0xfffe000004a6
+#define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0xfffe000004a7
+#define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0xfffe000004a8
+#define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0xfffe000004a9
+#define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0xfffe000004aa
+#define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0xfffe000004ab
+#define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0xfffe000004ac
+#define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0xfffe000004ad
+#define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0xfffe000004ae
+#define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0xfffe000004af
+#define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0xfffe000004b0
+#define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0xfffe000004b1
+#define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0xfffe000004b2
+#define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0xfffe000004b3
+#define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0xfffe000004b4
+#define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0xfffe000004b5
+#define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0xfffe000004b6
+#define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0xfffe000004b7
+#define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0xfffe000004b8
+#define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0xfffe000004b9
+#define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0xfffe000004ba
+#define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0xfffe000004bb
+#define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0xfffe000004bc
+#define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0xfffe000004bd
+#define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0xfffe000004be
+#define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0xfffe000004bf
+#define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0xfffe000004c0
+#define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0xfffe000004c1
+#define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0xfffe000004c2
+#define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0xfffe000004c3
+#define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CAP 0xfffe000004c4
+#define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL 0xfffe000004c8
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1
+// base address: 0x0
+#define cfgBIF_BX_PF0_MM_INDEX 0x0000
+#define cfgBIF_BX_PF0_MM_DATA 0x0004
+#define cfgBIF_BX_PF0_MM_INDEX_HI 0x0018
+
+
+// addressBlock: nbio_nbif0_bif_swus_SUMDEC
+// base address: 0x100000
+#define cfgSUM_INDEX 0x1000e0
+#define cfgSUM_DATA 0x1000e4
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
+// base address: 0xfffe10100000
+#define cfgBIF_CFG_DEV0_SWDS1_VENDOR_ID 0xfffe10100000
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_ID 0xfffe10100002
+#define cfgBIF_CFG_DEV0_SWDS1_COMMAND 0xfffe10100004
+#define cfgBIF_CFG_DEV0_SWDS1_STATUS 0xfffe10100006
+#define cfgBIF_CFG_DEV0_SWDS1_REVISION_ID 0xfffe10100008
+#define cfgBIF_CFG_DEV0_SWDS1_PROG_INTERFACE 0xfffe10100009
+#define cfgBIF_CFG_DEV0_SWDS1_SUB_CLASS 0xfffe1010000a
+#define cfgBIF_CFG_DEV0_SWDS1_BASE_CLASS 0xfffe1010000b
+#define cfgBIF_CFG_DEV0_SWDS1_CACHE_LINE 0xfffe1010000c
+#define cfgBIF_CFG_DEV0_SWDS1_LATENCY 0xfffe1010000d
+#define cfgBIF_CFG_DEV0_SWDS1_HEADER 0xfffe1010000e
+#define cfgBIF_CFG_DEV0_SWDS1_BIST 0xfffe1010000f
+#define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_1 0xfffe10100010
+#define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_2 0xfffe10100014
+#define cfgBIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY 0xfffe10100018
+#define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT 0xfffe1010001c
+#define cfgBIF_CFG_DEV0_SWDS1_SECONDARY_STATUS 0xfffe1010001e
+#define cfgBIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT 0xfffe10100020
+#define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT 0xfffe10100024
+#define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER 0xfffe10100028
+#define cfgBIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER 0xfffe1010002c
+#define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI 0xfffe10100030
+#define cfgBIF_CFG_DEV0_SWDS1_CAP_PTR 0xfffe10100034
+#define cfgBIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR 0xfffe10100038
+#define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_LINE 0xfffe1010003c
+#define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_PIN 0xfffe1010003d
+#define cfgBIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL 0xfffe1010003e
+#define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP_LIST 0xfffe10100050
+#define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP 0xfffe10100052
+#define cfgBIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL 0xfffe10100054
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST 0xfffe10100058
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP 0xfffe1010005a
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP 0xfffe1010005c
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL 0xfffe10100060
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS 0xfffe10100062
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP 0xfffe10100064
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL 0xfffe10100068
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS 0xfffe1010006a
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP 0xfffe1010006c
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL 0xfffe10100070
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS 0xfffe10100072
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP2 0xfffe1010007c
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL2 0xfffe10100080
+#define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS2 0xfffe10100082
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP2 0xfffe10100084
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL2 0xfffe10100088
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS2 0xfffe1010008a
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP2 0xfffe1010008c
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL2 0xfffe10100090
+#define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS2 0xfffe10100092
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_CAP_LIST 0xfffe101000a0
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL 0xfffe101000a2
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO 0xfffe101000a4
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI 0xfffe101000a8
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA 0xfffe101000a8
+#define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64 0xfffe101000ac
+#define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP_LIST 0xfffe101000c0
+#define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP 0xfffe101000c4
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10100100
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10100104
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1 0xfffe10100108
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2 0xfffe1010010c
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST 0xfffe10100110
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1 0xfffe10100114
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2 0xfffe10100118
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL 0xfffe1010011c
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS 0xfffe1010011e
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP 0xfffe10100120
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL 0xfffe10100124
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS 0xfffe1010012a
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP 0xfffe1010012c
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL 0xfffe10100130
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS 0xfffe10100136
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10100140
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10100144
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10100148
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10100150
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS 0xfffe10100154
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK 0xfffe10100158
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1010015c
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS 0xfffe10100160
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK 0xfffe10100164
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10100168
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0 0xfffe1010016c
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1 0xfffe10100170
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2 0xfffe10100174
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3 0xfffe10100178
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0 0xfffe10100188
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1 0xfffe1010018c
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2 0xfffe10100190
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3 0xfffe10100194
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10100270
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3 0xfffe10100274
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS 0xfffe10100278
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1010027c
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1010027e
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10100280
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10100282
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10100284
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10100286
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10100288
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1010028a
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1010028c
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1010028e
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10100290
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10100292
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10100294
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10100296
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10100298
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1010029a
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST 0xfffe101002a0
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP 0xfffe101002a4
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL 0xfffe101002a6
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST 0xfffe10100400
+#define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP 0xfffe10100404
+#define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS 0xfffe10100408
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10100410
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP_16GT 0xfffe10100414
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT 0xfffe10100418
+#define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT 0xfffe1010041c
+#define cfgBIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10100420
+#define cfgBIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10100424
+#define cfgBIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10100428
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10100430
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10100431
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10100432
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10100433
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10100434
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10100435
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10100436
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10100437
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10100438
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10100439
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1010043a
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1010043b
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1010043c
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1010043d
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1010043e
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1010043f
+#define cfgBIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10100440
+#define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP 0xfffe10100444
+#define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS 0xfffe10100446
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL 0xfffe10100448
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS 0xfffe1010044a
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL 0xfffe1010044c
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS 0xfffe1010044e
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL 0xfffe10100450
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS 0xfffe10100452
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL 0xfffe10100454
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS 0xfffe10100456
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL 0xfffe10100458
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS 0xfffe1010045a
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL 0xfffe1010045c
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS 0xfffe1010045e
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL 0xfffe10100460
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS 0xfffe10100462
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL 0xfffe10100464
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS 0xfffe10100466
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL 0xfffe10100468
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS 0xfffe1010046a
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL 0xfffe1010046c
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS 0xfffe1010046e
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL 0xfffe10100470
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS 0xfffe10100472
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL 0xfffe10100474
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS 0xfffe10100476
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL 0xfffe10100478
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS 0xfffe1010047a
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL 0xfffe1010047c
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS 0xfffe1010047e
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL 0xfffe10100480
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS 0xfffe10100482
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL 0xfffe10100484
+#define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS 0xfffe10100486
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0xfffe10200000
+#define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID 0xfffe10200000
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID 0xfffe10200002
+#define cfgBIF_CFG_DEV0_EPF0_1_COMMAND 0xfffe10200004
+#define cfgBIF_CFG_DEV0_EPF0_1_STATUS 0xfffe10200006
+#define cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID 0xfffe10200008
+#define cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE 0xfffe10200009
+#define cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS 0xfffe1020000a
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS 0xfffe1020000b
+#define cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE 0xfffe1020000c
+#define cfgBIF_CFG_DEV0_EPF0_1_LATENCY 0xfffe1020000d
+#define cfgBIF_CFG_DEV0_EPF0_1_HEADER 0xfffe1020000e
+#define cfgBIF_CFG_DEV0_EPF0_1_BIST 0xfffe1020000f
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 0xfffe10200010
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 0xfffe10200014
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 0xfffe10200018
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 0xfffe1020001c
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 0xfffe10200020
+#define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 0xfffe10200024
+#define cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR 0xfffe10200028
+#define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID 0xfffe1020002c
+#define cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR 0xfffe10200030
+#define cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR 0xfffe10200034
+#define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE 0xfffe1020003c
+#define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN 0xfffe1020003d
+#define cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT 0xfffe1020003e
+#define cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY 0xfffe1020003f
+#define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST 0xfffe10200048
+#define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W 0xfffe1020004c
+#define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST 0xfffe10200050
+#define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP 0xfffe10200052
+#define cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL 0xfffe10200054
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST 0xfffe10200064
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP 0xfffe10200066
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP 0xfffe10200068
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL 0xfffe1020006c
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS 0xfffe1020006e
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP 0xfffe10200070
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL 0xfffe10200074
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS 0xfffe10200076
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 0xfffe10200088
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 0xfffe1020008c
+#define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 0xfffe1020008e
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2 0xfffe10200090
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2 0xfffe10200094
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2 0xfffe10200096
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST 0xfffe102000a0
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL 0xfffe102000a2
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO 0xfffe102000a4
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI 0xfffe102000a8
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA 0xfffe102000a8
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK 0xfffe102000ac
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 0xfffe102000ac
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64 0xfffe102000b0
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING 0xfffe102000b0
+#define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 0xfffe102000b4
+#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST 0xfffe102000c0
+#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL 0xfffe102000c2
+#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE 0xfffe102000c4
+#define cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA 0xfffe102000c8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10200100
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10200104
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 0xfffe10200108
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020010c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST 0xfffe10200110
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 0xfffe10200114
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 0xfffe10200118
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL 0xfffe1020011c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS 0xfffe1020011e
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP 0xfffe10200120
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0xfffe10200124
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0xfffe1020012a
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP 0xfffe1020012c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0xfffe10200130
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0xfffe10200136
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10200140
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10200144
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10200148
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10200150
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS 0xfffe10200154
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK 0xfffe10200158
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020015c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS 0xfffe10200160
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK 0xfffe10200164
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10200168
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 0xfffe1020016c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 0xfffe10200170
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 0xfffe10200174
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 0xfffe10200178
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 0xfffe10200188
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020018c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 0xfffe10200190
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 0xfffe10200194
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10200200
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP 0xfffe10200204
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL 0xfffe10200208
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP 0xfffe1020020c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL 0xfffe10200210
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP 0xfffe10200214
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL 0xfffe10200218
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP 0xfffe1020021c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL 0xfffe10200220
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP 0xfffe10200224
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL 0xfffe10200228
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP 0xfffe1020022c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL 0xfffe10200230
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10200240
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10200244
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA 0xfffe10200248
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP 0xfffe1020024c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10200250
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP 0xfffe10200254
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10200258
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS 0xfffe1020025c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL 0xfffe1020025e
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10200260
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10200261
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10200262
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10200263
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10200264
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10200265
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10200266
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10200267
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10200270
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 0xfffe10200274
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS 0xfffe10200278
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020027c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020027e
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10200280
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10200282
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10200284
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10200286
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10200288
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020028a
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020028c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020028e
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10200290
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10200292
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10200294
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10200296
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10200298
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020029a
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102002a0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP 0xfffe102002a4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL 0xfffe102002a6
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST 0xfffe102002b0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP 0xfffe102002b4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL 0xfffe102002b6
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0xfffe102002c0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL 0xfffe102002c4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS 0xfffe102002c6
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xfffe102002c8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0xfffe102002cc
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102002d0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP 0xfffe102002d4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL 0xfffe102002d6
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST 0xfffe102002f0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP 0xfffe102002f4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL 0xfffe102002f6
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 0xfffe102002f8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 0xfffe102002fc
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 0xfffe10200300
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 0xfffe10200304
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 0xfffe10200308
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 0xfffe1020030c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10200310
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10200314
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0xfffe10200320
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP 0xfffe10200324
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10200328
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP 0xfffe1020032c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL 0xfffe1020032e
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10200330
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP 0xfffe10200334
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL 0xfffe10200338
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS 0xfffe1020033a
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS 0xfffe1020033c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS 0xfffe1020033e
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS 0xfffe10200340
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10200342
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10200344
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE 0xfffe10200346
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020034a
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020034c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10200350
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10200354
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10200358
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020035c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10200360
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10200364
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10200368
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020036c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10200370
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP 0xfffe10200374
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL 0xfffe10200378
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0xfffe10200400
+#define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP 0xfffe10200404
+#define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS 0xfffe10200408
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10200410
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT 0xfffe10200414
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT 0xfffe10200418
+#define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT 0xfffe1020041c
+#define cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10200420
+#define cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10200424
+#define cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10200428
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10200430
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10200431
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10200432
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10200433
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10200434
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10200435
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10200436
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10200437
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10200438
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10200439
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1020043a
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1020043b
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1020043c
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1020043d
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1020043e
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1020043f
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10200440
+#define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP 0xfffe10200444
+#define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS 0xfffe10200446
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0xfffe10200448
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0xfffe1020044a
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0xfffe1020044c
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0xfffe1020044e
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0xfffe10200450
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0xfffe10200452
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0xfffe10200454
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0xfffe10200456
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0xfffe10200458
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0xfffe1020045a
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0xfffe1020045c
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0xfffe1020045e
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0xfffe10200460
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0xfffe10200462
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0xfffe10200464
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0xfffe10200466
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0xfffe10200468
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0xfffe1020046a
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0xfffe1020046c
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0xfffe1020046e
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0xfffe10200470
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0xfffe10200472
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0xfffe10200474
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0xfffe10200476
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0xfffe10200478
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0xfffe1020047a
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0xfffe1020047c
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0xfffe1020047e
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0xfffe10200480
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0xfffe10200482
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0xfffe10200484
+#define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0xfffe10200486
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102004c0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102004c4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102004c8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102004cc
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102004d0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102004d4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102004d8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102004dc
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102004e0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102004e4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102004e8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102004ec
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102004f0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0xfffe10200500
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0xfffe10200504
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0xfffe10200508
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0xfffe1020050c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0xfffe10200510
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0xfffe10200514
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0xfffe10200518
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0xfffe1020051c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0xfffe10200520
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0xfffe10200524
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0xfffe10200528
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0xfffe1020052c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0xfffe10200530
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0xfffe10200534
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0xfffe10200538
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0xfffe1020053c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0xfffe10200540
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0xfffe10200544
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0xfffe10200548
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0xfffe1020054c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0xfffe10200550
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0xfffe10200554
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0xfffe10200558
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0xfffe1020055c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0xfffe10200560
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0xfffe10200564
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0xfffe10200568
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0xfffe1020056c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0xfffe10200570
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0xfffe10200574
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0xfffe10200578
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0xfffe1020057c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0xfffe10200580
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0xfffe10200584
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0xfffe10200588
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0xfffe1020058c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0xfffe10200590
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0xfffe10200594
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0xfffe10200598
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0xfffe1020059c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0xfffe102005a0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0xfffe102005a4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0xfffe102005a8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0xfffe102005ac
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0xfffe102005b0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0xfffe102005c0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0xfffe102005c4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0xfffe102005c8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0xfffe102005cc
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0xfffe102005d0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0xfffe102005d4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0xfffe102005d8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0xfffe102005dc
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0xfffe102005e0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0xfffe102005f0
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0xfffe102005f4
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0xfffe102005f8
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0xfffe102005fc
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0xfffe10200600
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0xfffe10200604
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0xfffe10200608
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0xfffe1020060c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0xfffe10200610
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0xfffe10200620
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0xfffe10200624
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0xfffe10200628
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0xfffe1020062c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0xfffe10200630
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0xfffe10200634
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0xfffe10200638
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0xfffe1020063c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0xfffe10200640
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0xfffe10200650
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0xfffe10200654
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0xfffe10200658
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0xfffe1020065c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0xfffe10200660
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0xfffe10200664
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0xfffe10200668
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0xfffe1020066c
+#define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0xfffe10200670
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+// base address: 0xfffe10201000
+#define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID 0xfffe10201000
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID 0xfffe10201002
+#define cfgBIF_CFG_DEV0_EPF1_1_COMMAND 0xfffe10201004
+#define cfgBIF_CFG_DEV0_EPF1_1_STATUS 0xfffe10201006
+#define cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID 0xfffe10201008
+#define cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE 0xfffe10201009
+#define cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS 0xfffe1020100a
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS 0xfffe1020100b
+#define cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE 0xfffe1020100c
+#define cfgBIF_CFG_DEV0_EPF1_1_LATENCY 0xfffe1020100d
+#define cfgBIF_CFG_DEV0_EPF1_1_HEADER 0xfffe1020100e
+#define cfgBIF_CFG_DEV0_EPF1_1_BIST 0xfffe1020100f
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 0xfffe10201010
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 0xfffe10201014
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 0xfffe10201018
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 0xfffe1020101c
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 0xfffe10201020
+#define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 0xfffe10201024
+#define cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR 0xfffe10201028
+#define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID 0xfffe1020102c
+#define cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR 0xfffe10201030
+#define cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR 0xfffe10201034
+#define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE 0xfffe1020103c
+#define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN 0xfffe1020103d
+#define cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT 0xfffe1020103e
+#define cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY 0xfffe1020103f
+#define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST 0xfffe10201048
+#define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W 0xfffe1020104c
+#define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST 0xfffe10201050
+#define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP 0xfffe10201052
+#define cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL 0xfffe10201054
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST 0xfffe10201064
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP 0xfffe10201066
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP 0xfffe10201068
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL 0xfffe1020106c
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS 0xfffe1020106e
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP 0xfffe10201070
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL 0xfffe10201074
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS 0xfffe10201076
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 0xfffe10201088
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 0xfffe1020108c
+#define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 0xfffe1020108e
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2 0xfffe10201090
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2 0xfffe10201094
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2 0xfffe10201096
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST 0xfffe102010a0
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL 0xfffe102010a2
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO 0xfffe102010a4
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI 0xfffe102010a8
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA 0xfffe102010a8
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK 0xfffe102010ac
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 0xfffe102010ac
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64 0xfffe102010b0
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING 0xfffe102010b0
+#define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 0xfffe102010b4
+#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST 0xfffe102010c0
+#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL 0xfffe102010c2
+#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE 0xfffe102010c4
+#define cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA 0xfffe102010c8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10201100
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10201104
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 0xfffe10201108
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020110c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST 0xfffe10201110
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1 0xfffe10201114
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2 0xfffe10201118
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL 0xfffe1020111c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS 0xfffe1020111e
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP 0xfffe10201120
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL 0xfffe10201124
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS 0xfffe1020112a
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP 0xfffe1020112c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL 0xfffe10201130
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS 0xfffe10201136
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10201140
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10201144
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10201148
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10201150
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS 0xfffe10201154
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK 0xfffe10201158
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020115c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS 0xfffe10201160
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK 0xfffe10201164
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10201168
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 0xfffe1020116c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 0xfffe10201170
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 0xfffe10201174
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 0xfffe10201178
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 0xfffe10201188
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020118c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 0xfffe10201190
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 0xfffe10201194
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10201200
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP 0xfffe10201204
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL 0xfffe10201208
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP 0xfffe1020120c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL 0xfffe10201210
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP 0xfffe10201214
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL 0xfffe10201218
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP 0xfffe1020121c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL 0xfffe10201220
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP 0xfffe10201224
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL 0xfffe10201228
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP 0xfffe1020122c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL 0xfffe10201230
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10201240
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10201244
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA 0xfffe10201248
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP 0xfffe1020124c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10201250
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP 0xfffe10201254
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10201258
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS 0xfffe1020125c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL 0xfffe1020125e
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10201260
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10201261
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10201262
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10201263
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10201264
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10201265
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10201266
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10201267
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10201270
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 0xfffe10201274
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS 0xfffe10201278
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020127c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020127e
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10201280
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10201282
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10201284
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10201286
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10201288
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020128a
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020128c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020128e
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10201290
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10201292
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10201294
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10201296
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10201298
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020129a
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102012a0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP 0xfffe102012a4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL 0xfffe102012a6
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST 0xfffe102012b0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP 0xfffe102012b4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL 0xfffe102012b6
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0xfffe102012c0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL 0xfffe102012c4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS 0xfffe102012c6
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xfffe102012c8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0xfffe102012cc
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102012d0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP 0xfffe102012d4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL 0xfffe102012d6
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST 0xfffe102012f0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP 0xfffe102012f4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL 0xfffe102012f6
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 0xfffe102012f8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 0xfffe102012fc
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 0xfffe10201300
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 0xfffe10201304
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 0xfffe10201308
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 0xfffe1020130c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10201310
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10201314
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST 0xfffe10201320
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP 0xfffe10201324
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10201328
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP 0xfffe1020132c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL 0xfffe1020132e
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10201330
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP 0xfffe10201334
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL 0xfffe10201338
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS 0xfffe1020133a
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS 0xfffe1020133c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS 0xfffe1020133e
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS 0xfffe10201340
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10201342
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10201344
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE 0xfffe10201346
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020134a
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020134c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10201350
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10201354
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10201358
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020135c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10201360
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10201364
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10201368
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xfffe1020136c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10201370
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP 0xfffe10201374
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL 0xfffe10201378
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST 0xfffe10201400
+#define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP 0xfffe10201404
+#define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS 0xfffe10201408
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10201410
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT 0xfffe10201414
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT 0xfffe10201418
+#define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT 0xfffe1020141c
+#define cfgBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10201420
+#define cfgBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10201424
+#define cfgBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10201428
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10201430
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10201431
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10201432
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10201433
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10201434
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10201435
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10201436
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10201437
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10201438
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10201439
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1020143a
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1020143b
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1020143c
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1020143d
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1020143e
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1020143f
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10201440
+#define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP 0xfffe10201444
+#define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS 0xfffe10201446
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL 0xfffe10201448
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS 0xfffe1020144a
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL 0xfffe1020144c
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS 0xfffe1020144e
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL 0xfffe10201450
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS 0xfffe10201452
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL 0xfffe10201454
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS 0xfffe10201456
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL 0xfffe10201458
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS 0xfffe1020145a
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL 0xfffe1020145c
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS 0xfffe1020145e
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL 0xfffe10201460
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS 0xfffe10201462
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL 0xfffe10201464
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS 0xfffe10201466
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL 0xfffe10201468
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS 0xfffe1020146a
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL 0xfffe1020146c
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS 0xfffe1020146e
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL 0xfffe10201470
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS 0xfffe10201472
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL 0xfffe10201474
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS 0xfffe10201476
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL 0xfffe10201478
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS 0xfffe1020147a
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL 0xfffe1020147c
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS 0xfffe1020147e
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL 0xfffe10201480
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS 0xfffe10201482
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL 0xfffe10201484
+#define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS 0xfffe10201486
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102014c0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102014c4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102014c8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102014cc
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102014d0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102014d4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102014d8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102014dc
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102014e0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102014e4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102014e8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102014ec
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102014f0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0xfffe10201500
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0xfffe10201504
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0xfffe10201508
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0xfffe1020150c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0xfffe10201510
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0xfffe10201514
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0xfffe10201518
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0xfffe1020151c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0xfffe10201520
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0xfffe10201524
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0xfffe10201528
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0xfffe1020152c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0xfffe10201530
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0xfffe10201534
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0xfffe10201538
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0xfffe1020153c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0xfffe10201540
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0xfffe10201544
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0xfffe10201548
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0xfffe1020154c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0xfffe10201550
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0xfffe10201554
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0xfffe10201558
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0xfffe1020155c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0xfffe10201560
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0xfffe10201564
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0xfffe10201568
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0xfffe1020156c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0xfffe10201570
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0xfffe10201574
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0xfffe10201578
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0xfffe1020157c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0xfffe10201580
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0xfffe10201584
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0xfffe10201588
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0xfffe1020158c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0xfffe10201590
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0xfffe10201594
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0xfffe10201598
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0xfffe1020159c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0xfffe102015a0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0xfffe102015a4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0xfffe102015a8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0xfffe102015ac
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0xfffe102015b0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0xfffe102015c0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0xfffe102015c4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0xfffe102015c8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0xfffe102015cc
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0xfffe102015d0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0xfffe102015d4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0xfffe102015d8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0xfffe102015dc
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0xfffe102015e0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0xfffe102015f0
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0xfffe102015f4
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0xfffe102015f8
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0xfffe102015fc
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0xfffe10201600
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0xfffe10201604
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0xfffe10201608
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0xfffe1020160c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0xfffe10201610
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0xfffe10201620
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0xfffe10201624
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0xfffe10201628
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0xfffe1020162c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0xfffe10201630
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0xfffe10201634
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0xfffe10201638
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0xfffe1020163c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0xfffe10201640
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0xfffe10201650
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0xfffe10201654
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0xfffe10201658
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0xfffe1020165c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0xfffe10201660
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0xfffe10201664
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0xfffe10201668
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0xfffe1020166c
+#define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0xfffe10201670
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+// base address: 0xfffe10202000
+#define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID 0xfffe10202000
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID 0xfffe10202002
+#define cfgBIF_CFG_DEV0_EPF2_1_COMMAND 0xfffe10202004
+#define cfgBIF_CFG_DEV0_EPF2_1_STATUS 0xfffe10202006
+#define cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID 0xfffe10202008
+#define cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE 0xfffe10202009
+#define cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS 0xfffe1020200a
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS 0xfffe1020200b
+#define cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE 0xfffe1020200c
+#define cfgBIF_CFG_DEV0_EPF2_1_LATENCY 0xfffe1020200d
+#define cfgBIF_CFG_DEV0_EPF2_1_HEADER 0xfffe1020200e
+#define cfgBIF_CFG_DEV0_EPF2_1_BIST 0xfffe1020200f
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 0xfffe10202010
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 0xfffe10202014
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 0xfffe10202018
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 0xfffe1020201c
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 0xfffe10202020
+#define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 0xfffe10202024
+#define cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR 0xfffe10202028
+#define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID 0xfffe1020202c
+#define cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR 0xfffe10202030
+#define cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR 0xfffe10202034
+#define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE 0xfffe1020203c
+#define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN 0xfffe1020203d
+#define cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT 0xfffe1020203e
+#define cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY 0xfffe1020203f
+#define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST 0xfffe10202048
+#define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W 0xfffe1020204c
+#define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST 0xfffe10202050
+#define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP 0xfffe10202052
+#define cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL 0xfffe10202054
+#define cfgBIF_CFG_DEV0_EPF2_1_SBRN 0xfffe10202060
+#define cfgBIF_CFG_DEV0_EPF2_1_FLADJ 0xfffe10202061
+#define cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD 0xfffe10202062
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST 0xfffe10202064
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP 0xfffe10202066
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP 0xfffe10202068
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL 0xfffe1020206c
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS 0xfffe1020206e
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP 0xfffe10202070
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL 0xfffe10202074
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS 0xfffe10202076
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 0xfffe10202088
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 0xfffe1020208c
+#define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 0xfffe1020208e
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2 0xfffe10202090
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2 0xfffe10202094
+#define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2 0xfffe10202096
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST 0xfffe102020a0
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL 0xfffe102020a2
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO 0xfffe102020a4
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI 0xfffe102020a8
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA 0xfffe102020a8
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK 0xfffe102020ac
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 0xfffe102020ac
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64 0xfffe102020b0
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING 0xfffe102020b0
+#define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 0xfffe102020b4
+#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST 0xfffe102020c0
+#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL 0xfffe102020c2
+#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE 0xfffe102020c4
+#define cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA 0xfffe102020c8
+#define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_0 0xfffe102020d0
+#define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_1 0xfffe102020d4
+#define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX 0xfffe102020d8
+#define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA 0xfffe102020dc
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10202100
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10202104
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 0xfffe10202108
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020210c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10202150
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS 0xfffe10202154
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK 0xfffe10202158
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020215c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS 0xfffe10202160
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK 0xfffe10202164
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10202168
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 0xfffe1020216c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 0xfffe10202170
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 0xfffe10202174
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 0xfffe10202178
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 0xfffe10202188
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020218c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 0xfffe10202190
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 0xfffe10202194
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10202200
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP 0xfffe10202204
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL 0xfffe10202208
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP 0xfffe1020220c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL 0xfffe10202210
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP 0xfffe10202214
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL 0xfffe10202218
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP 0xfffe1020221c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL 0xfffe10202220
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP 0xfffe10202224
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL 0xfffe10202228
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP 0xfffe1020222c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL 0xfffe10202230
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10202240
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10202244
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA 0xfffe10202248
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP 0xfffe1020224c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10202250
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP 0xfffe10202254
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10202258
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS 0xfffe1020225c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL 0xfffe1020225e
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10202260
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10202261
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10202262
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10202263
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10202264
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10202265
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10202266
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10202267
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102022a0
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP 0xfffe102022a4
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL 0xfffe102022a6
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102022d0
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP 0xfffe102022d4
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL 0xfffe102022d6
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10202328
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP 0xfffe1020232c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL 0xfffe1020232e
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10202370
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP 0xfffe10202374
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL 0xfffe10202378
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0 0xfffe1020237c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1 0xfffe1020237e
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2 0xfffe10202380
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3 0xfffe10202382
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4 0xfffe10202384
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5 0xfffe10202386
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6 0xfffe10202388
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7 0xfffe1020238a
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8 0xfffe1020238c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9 0xfffe1020238e
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10 0xfffe10202390
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11 0xfffe10202392
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12 0xfffe10202394
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13 0xfffe10202396
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14 0xfffe10202398
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15 0xfffe1020239a
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16 0xfffe1020239c
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17 0xfffe1020239e
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18 0xfffe102023a0
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19 0xfffe102023a2
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20 0xfffe102023a4
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21 0xfffe102023a6
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22 0xfffe102023a8
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23 0xfffe102023aa
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24 0xfffe102023ac
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25 0xfffe102023ae
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26 0xfffe102023b0
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27 0xfffe102023b2
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28 0xfffe102023b4
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29 0xfffe102023b6
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30 0xfffe102023b8
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31 0xfffe102023ba
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32 0xfffe102023bc
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33 0xfffe102023be
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34 0xfffe102023c0
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35 0xfffe102023c2
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36 0xfffe102023c4
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37 0xfffe102023c6
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38 0xfffe102023c8
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39 0xfffe102023ca
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40 0xfffe102023cc
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41 0xfffe102023ce
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42 0xfffe102023d0
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43 0xfffe102023d2
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44 0xfffe102023d4
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45 0xfffe102023d6
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46 0xfffe102023d8
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47 0xfffe102023da
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48 0xfffe102023dc
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49 0xfffe102023de
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50 0xfffe102023e0
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51 0xfffe102023e2
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52 0xfffe102023e4
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53 0xfffe102023e6
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54 0xfffe102023e8
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55 0xfffe102023ea
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56 0xfffe102023ec
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57 0xfffe102023ee
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58 0xfffe102023f0
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59 0xfffe102023f2
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60 0xfffe102023f4
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61 0xfffe102023f6
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62 0xfffe102023f8
+#define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63 0xfffe102023fa
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+// base address: 0xfffe10203000
+#define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID 0xfffe10203000
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID 0xfffe10203002
+#define cfgBIF_CFG_DEV0_EPF3_1_COMMAND 0xfffe10203004
+#define cfgBIF_CFG_DEV0_EPF3_1_STATUS 0xfffe10203006
+#define cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID 0xfffe10203008
+#define cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE 0xfffe10203009
+#define cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS 0xfffe1020300a
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS 0xfffe1020300b
+#define cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE 0xfffe1020300c
+#define cfgBIF_CFG_DEV0_EPF3_1_LATENCY 0xfffe1020300d
+#define cfgBIF_CFG_DEV0_EPF3_1_HEADER 0xfffe1020300e
+#define cfgBIF_CFG_DEV0_EPF3_1_BIST 0xfffe1020300f
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 0xfffe10203010
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 0xfffe10203014
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 0xfffe10203018
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 0xfffe1020301c
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 0xfffe10203020
+#define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 0xfffe10203024
+#define cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR 0xfffe10203028
+#define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID 0xfffe1020302c
+#define cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR 0xfffe10203030
+#define cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR 0xfffe10203034
+#define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE 0xfffe1020303c
+#define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN 0xfffe1020303d
+#define cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT 0xfffe1020303e
+#define cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY 0xfffe1020303f
+#define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST 0xfffe10203048
+#define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W 0xfffe1020304c
+#define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST 0xfffe10203050
+#define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP 0xfffe10203052
+#define cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL 0xfffe10203054
+#define cfgBIF_CFG_DEV0_EPF3_1_SBRN 0xfffe10203060
+#define cfgBIF_CFG_DEV0_EPF3_1_FLADJ 0xfffe10203061
+#define cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD 0xfffe10203062
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST 0xfffe10203064
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP 0xfffe10203066
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP 0xfffe10203068
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL 0xfffe1020306c
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS 0xfffe1020306e
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP 0xfffe10203070
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL 0xfffe10203074
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS 0xfffe10203076
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 0xfffe10203088
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 0xfffe1020308c
+#define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 0xfffe1020308e
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2 0xfffe10203090
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2 0xfffe10203094
+#define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2 0xfffe10203096
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST 0xfffe102030a0
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL 0xfffe102030a2
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO 0xfffe102030a4
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI 0xfffe102030a8
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA 0xfffe102030a8
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK 0xfffe102030ac
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 0xfffe102030ac
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64 0xfffe102030b0
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING 0xfffe102030b0
+#define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 0xfffe102030b4
+#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST 0xfffe102030c0
+#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL 0xfffe102030c2
+#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE 0xfffe102030c4
+#define cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA 0xfffe102030c8
+#define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_0 0xfffe102030d0
+#define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_1 0xfffe102030d4
+#define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX 0xfffe102030d8
+#define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA 0xfffe102030dc
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10203100
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10203104
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 0xfffe10203108
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020310c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10203150
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS 0xfffe10203154
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK 0xfffe10203158
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020315c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS 0xfffe10203160
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK 0xfffe10203164
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10203168
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 0xfffe1020316c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 0xfffe10203170
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 0xfffe10203174
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 0xfffe10203178
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 0xfffe10203188
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020318c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 0xfffe10203190
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 0xfffe10203194
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10203200
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP 0xfffe10203204
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL 0xfffe10203208
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP 0xfffe1020320c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL 0xfffe10203210
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP 0xfffe10203214
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL 0xfffe10203218
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP 0xfffe1020321c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL 0xfffe10203220
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP 0xfffe10203224
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL 0xfffe10203228
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP 0xfffe1020322c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL 0xfffe10203230
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10203240
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10203244
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA 0xfffe10203248
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP 0xfffe1020324c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10203250
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP 0xfffe10203254
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10203258
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS 0xfffe1020325c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL 0xfffe1020325e
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10203260
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10203261
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10203262
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10203263
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10203264
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10203265
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10203266
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10203267
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102032a0
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP 0xfffe102032a4
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL 0xfffe102032a6
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102032d0
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP 0xfffe102032d4
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL 0xfffe102032d6
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10203328
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP 0xfffe1020332c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL 0xfffe1020332e
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10203370
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP 0xfffe10203374
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL 0xfffe10203378
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0 0xfffe1020337c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1 0xfffe1020337e
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2 0xfffe10203380
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3 0xfffe10203382
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4 0xfffe10203384
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5 0xfffe10203386
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6 0xfffe10203388
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7 0xfffe1020338a
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8 0xfffe1020338c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9 0xfffe1020338e
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10 0xfffe10203390
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11 0xfffe10203392
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12 0xfffe10203394
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13 0xfffe10203396
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14 0xfffe10203398
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15 0xfffe1020339a
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16 0xfffe1020339c
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17 0xfffe1020339e
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18 0xfffe102033a0
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19 0xfffe102033a2
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20 0xfffe102033a4
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21 0xfffe102033a6
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22 0xfffe102033a8
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23 0xfffe102033aa
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24 0xfffe102033ac
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25 0xfffe102033ae
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26 0xfffe102033b0
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27 0xfffe102033b2
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28 0xfffe102033b4
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29 0xfffe102033b6
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30 0xfffe102033b8
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31 0xfffe102033ba
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32 0xfffe102033bc
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33 0xfffe102033be
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34 0xfffe102033c0
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35 0xfffe102033c2
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36 0xfffe102033c4
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37 0xfffe102033c6
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38 0xfffe102033c8
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39 0xfffe102033ca
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40 0xfffe102033cc
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41 0xfffe102033ce
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42 0xfffe102033d0
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43 0xfffe102033d2
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44 0xfffe102033d4
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45 0xfffe102033d6
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46 0xfffe102033d8
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47 0xfffe102033da
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48 0xfffe102033dc
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49 0xfffe102033de
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50 0xfffe102033e0
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51 0xfffe102033e2
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52 0xfffe102033e4
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53 0xfffe102033e6
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54 0xfffe102033e8
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55 0xfffe102033ea
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56 0xfffe102033ec
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57 0xfffe102033ee
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58 0xfffe102033f0
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59 0xfffe102033f2
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60 0xfffe102033f4
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61 0xfffe102033f6
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62 0xfffe102033f8
+#define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63 0xfffe102033fa
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+// base address: 0xfffe10300000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID 0xfffe10300000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID 0xfffe10300002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND 0xfffe10300004
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS 0xfffe10300006
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID 0xfffe10300008
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE 0xfffe10300009
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS 0xfffe1030000a
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS 0xfffe1030000b
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE 0xfffe1030000c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY 0xfffe1030000d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER 0xfffe1030000e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST 0xfffe1030000f
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1 0xfffe10300010
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2 0xfffe10300014
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3 0xfffe10300018
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4 0xfffe1030001c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5 0xfffe10300020
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6 0xfffe10300024
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR 0xfffe10300028
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID 0xfffe1030002c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR 0xfffe10300030
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR 0xfffe10300034
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE 0xfffe1030003c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN 0xfffe1030003d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT 0xfffe1030003e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY 0xfffe1030003f
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST 0xfffe10300064
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP 0xfffe10300066
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP 0xfffe10300068
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL 0xfffe1030006c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS 0xfffe1030006e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP 0xfffe10300070
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL 0xfffe10300074
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS 0xfffe10300076
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2 0xfffe10300088
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2 0xfffe1030008c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2 0xfffe1030008e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2 0xfffe10300090
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2 0xfffe10300094
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2 0xfffe10300096
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST 0xfffe103000a0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL 0xfffe103000a2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO 0xfffe103000a4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI 0xfffe103000a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA 0xfffe103000a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK 0xfffe103000ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64 0xfffe103000ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64 0xfffe103000b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING 0xfffe103000b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64 0xfffe103000b4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST 0xfffe103000c0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL 0xfffe103000c2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE 0xfffe103000c4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA 0xfffe103000c8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10300100
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10300104
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1 0xfffe10300108
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030010c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10300150
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS 0xfffe10300154
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK 0xfffe10300158
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030015c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS 0xfffe10300160
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK 0xfffe10300164
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10300168
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0 0xfffe1030016c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1 0xfffe10300170
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2 0xfffe10300174
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3 0xfffe10300178
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0 0xfffe10300188
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030018c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2 0xfffe10300190
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3 0xfffe10300194
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103002b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP 0xfffe103002b4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL 0xfffe103002b6
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10300328
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP 0xfffe1030032c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL 0xfffe1030032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+// base address: 0xfffe10301000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID 0xfffe10301000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID 0xfffe10301002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND 0xfffe10301004
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS 0xfffe10301006
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID 0xfffe10301008
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE 0xfffe10301009
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS 0xfffe1030100a
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS 0xfffe1030100b
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE 0xfffe1030100c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY 0xfffe1030100d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER 0xfffe1030100e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST 0xfffe1030100f
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1 0xfffe10301010
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2 0xfffe10301014
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3 0xfffe10301018
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4 0xfffe1030101c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5 0xfffe10301020
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6 0xfffe10301024
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR 0xfffe10301028
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID 0xfffe1030102c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR 0xfffe10301030
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR 0xfffe10301034
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE 0xfffe1030103c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN 0xfffe1030103d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT 0xfffe1030103e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY 0xfffe1030103f
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST 0xfffe10301064
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP 0xfffe10301066
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP 0xfffe10301068
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL 0xfffe1030106c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS 0xfffe1030106e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP 0xfffe10301070
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL 0xfffe10301074
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS 0xfffe10301076
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2 0xfffe10301088
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2 0xfffe1030108c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2 0xfffe1030108e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2 0xfffe10301090
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2 0xfffe10301094
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2 0xfffe10301096
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST 0xfffe103010a0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL 0xfffe103010a2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO 0xfffe103010a4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI 0xfffe103010a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA 0xfffe103010a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK 0xfffe103010ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64 0xfffe103010ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64 0xfffe103010b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING 0xfffe103010b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64 0xfffe103010b4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST 0xfffe103010c0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL 0xfffe103010c2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE 0xfffe103010c4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA 0xfffe103010c8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10301100
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10301104
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1 0xfffe10301108
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030110c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10301150
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS 0xfffe10301154
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK 0xfffe10301158
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030115c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS 0xfffe10301160
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK 0xfffe10301164
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10301168
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0 0xfffe1030116c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1 0xfffe10301170
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2 0xfffe10301174
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3 0xfffe10301178
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0 0xfffe10301188
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030118c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2 0xfffe10301190
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3 0xfffe10301194
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103012b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP 0xfffe103012b4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL 0xfffe103012b6
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10301328
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP 0xfffe1030132c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL 0xfffe1030132e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+// base address: 0xfffe10302000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID 0xfffe10302000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID 0xfffe10302002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND 0xfffe10302004
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS 0xfffe10302006
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID 0xfffe10302008
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE 0xfffe10302009
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS 0xfffe1030200a
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS 0xfffe1030200b
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE 0xfffe1030200c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY 0xfffe1030200d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER 0xfffe1030200e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST 0xfffe1030200f
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1 0xfffe10302010
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2 0xfffe10302014
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3 0xfffe10302018
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4 0xfffe1030201c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5 0xfffe10302020
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6 0xfffe10302024
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR 0xfffe10302028
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID 0xfffe1030202c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR 0xfffe10302030
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR 0xfffe10302034
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE 0xfffe1030203c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN 0xfffe1030203d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT 0xfffe1030203e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY 0xfffe1030203f
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST 0xfffe10302064
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP 0xfffe10302066
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP 0xfffe10302068
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL 0xfffe1030206c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS 0xfffe1030206e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP 0xfffe10302070
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL 0xfffe10302074
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS 0xfffe10302076
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2 0xfffe10302088
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2 0xfffe1030208c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2 0xfffe1030208e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2 0xfffe10302090
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2 0xfffe10302094
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2 0xfffe10302096
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST 0xfffe103020a0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL 0xfffe103020a2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO 0xfffe103020a4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI 0xfffe103020a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA 0xfffe103020a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK 0xfffe103020ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64 0xfffe103020ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64 0xfffe103020b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING 0xfffe103020b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64 0xfffe103020b4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST 0xfffe103020c0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL 0xfffe103020c2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE 0xfffe103020c4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA 0xfffe103020c8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10302100
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10302104
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1 0xfffe10302108
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030210c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10302150
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS 0xfffe10302154
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK 0xfffe10302158
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030215c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS 0xfffe10302160
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK 0xfffe10302164
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10302168
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0 0xfffe1030216c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1 0xfffe10302170
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2 0xfffe10302174
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3 0xfffe10302178
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0 0xfffe10302188
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030218c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2 0xfffe10302190
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3 0xfffe10302194
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103022b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP 0xfffe103022b4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL 0xfffe103022b6
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10302328
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP 0xfffe1030232c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL 0xfffe1030232e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+// base address: 0xfffe10303000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID 0xfffe10303000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID 0xfffe10303002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND 0xfffe10303004
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS 0xfffe10303006
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID 0xfffe10303008
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE 0xfffe10303009
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS 0xfffe1030300a
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS 0xfffe1030300b
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE 0xfffe1030300c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY 0xfffe1030300d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER 0xfffe1030300e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST 0xfffe1030300f
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1 0xfffe10303010
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2 0xfffe10303014
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3 0xfffe10303018
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4 0xfffe1030301c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5 0xfffe10303020
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6 0xfffe10303024
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR 0xfffe10303028
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID 0xfffe1030302c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR 0xfffe10303030
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR 0xfffe10303034
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE 0xfffe1030303c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN 0xfffe1030303d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT 0xfffe1030303e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY 0xfffe1030303f
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST 0xfffe10303064
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP 0xfffe10303066
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP 0xfffe10303068
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL 0xfffe1030306c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS 0xfffe1030306e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP 0xfffe10303070
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL 0xfffe10303074
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS 0xfffe10303076
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2 0xfffe10303088
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2 0xfffe1030308c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2 0xfffe1030308e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2 0xfffe10303090
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2 0xfffe10303094
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2 0xfffe10303096
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST 0xfffe103030a0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL 0xfffe103030a2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO 0xfffe103030a4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI 0xfffe103030a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA 0xfffe103030a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK 0xfffe103030ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64 0xfffe103030ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64 0xfffe103030b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING 0xfffe103030b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64 0xfffe103030b4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST 0xfffe103030c0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL 0xfffe103030c2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE 0xfffe103030c4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA 0xfffe103030c8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10303100
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10303104
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1 0xfffe10303108
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030310c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10303150
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS 0xfffe10303154
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK 0xfffe10303158
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030315c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS 0xfffe10303160
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK 0xfffe10303164
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10303168
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0 0xfffe1030316c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1 0xfffe10303170
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2 0xfffe10303174
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3 0xfffe10303178
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0 0xfffe10303188
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030318c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2 0xfffe10303190
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3 0xfffe10303194
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103032b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP 0xfffe103032b4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL 0xfffe103032b6
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10303328
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP 0xfffe1030332c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL 0xfffe1030332e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+// base address: 0xfffe10304000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID 0xfffe10304000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID 0xfffe10304002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND 0xfffe10304004
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS 0xfffe10304006
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID 0xfffe10304008
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE 0xfffe10304009
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS 0xfffe1030400a
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS 0xfffe1030400b
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE 0xfffe1030400c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY 0xfffe1030400d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER 0xfffe1030400e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST 0xfffe1030400f
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1 0xfffe10304010
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2 0xfffe10304014
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3 0xfffe10304018
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4 0xfffe1030401c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5 0xfffe10304020
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6 0xfffe10304024
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR 0xfffe10304028
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID 0xfffe1030402c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR 0xfffe10304030
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR 0xfffe10304034
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE 0xfffe1030403c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN 0xfffe1030403d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT 0xfffe1030403e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY 0xfffe1030403f
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST 0xfffe10304064
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP 0xfffe10304066
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP 0xfffe10304068
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL 0xfffe1030406c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS 0xfffe1030406e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP 0xfffe10304070
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL 0xfffe10304074
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS 0xfffe10304076
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2 0xfffe10304088
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2 0xfffe1030408c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2 0xfffe1030408e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2 0xfffe10304090
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2 0xfffe10304094
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2 0xfffe10304096
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST 0xfffe103040a0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL 0xfffe103040a2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO 0xfffe103040a4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI 0xfffe103040a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA 0xfffe103040a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK 0xfffe103040ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64 0xfffe103040ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64 0xfffe103040b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING 0xfffe103040b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64 0xfffe103040b4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST 0xfffe103040c0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL 0xfffe103040c2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE 0xfffe103040c4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA 0xfffe103040c8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10304100
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10304104
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1 0xfffe10304108
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030410c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10304150
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS 0xfffe10304154
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK 0xfffe10304158
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030415c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS 0xfffe10304160
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK 0xfffe10304164
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10304168
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0 0xfffe1030416c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1 0xfffe10304170
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2 0xfffe10304174
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3 0xfffe10304178
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0 0xfffe10304188
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030418c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2 0xfffe10304190
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3 0xfffe10304194
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103042b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP 0xfffe103042b4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL 0xfffe103042b6
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10304328
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP 0xfffe1030432c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL 0xfffe1030432e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+// base address: 0xfffe10305000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID 0xfffe10305000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID 0xfffe10305002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND 0xfffe10305004
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS 0xfffe10305006
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID 0xfffe10305008
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE 0xfffe10305009
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS 0xfffe1030500a
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS 0xfffe1030500b
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE 0xfffe1030500c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY 0xfffe1030500d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER 0xfffe1030500e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST 0xfffe1030500f
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1 0xfffe10305010
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2 0xfffe10305014
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3 0xfffe10305018
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4 0xfffe1030501c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5 0xfffe10305020
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6 0xfffe10305024
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR 0xfffe10305028
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID 0xfffe1030502c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR 0xfffe10305030
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR 0xfffe10305034
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE 0xfffe1030503c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN 0xfffe1030503d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT 0xfffe1030503e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY 0xfffe1030503f
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST 0xfffe10305064
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP 0xfffe10305066
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP 0xfffe10305068
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL 0xfffe1030506c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS 0xfffe1030506e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP 0xfffe10305070
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL 0xfffe10305074
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS 0xfffe10305076
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2 0xfffe10305088
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2 0xfffe1030508c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2 0xfffe1030508e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2 0xfffe10305090
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2 0xfffe10305094
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2 0xfffe10305096
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST 0xfffe103050a0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL 0xfffe103050a2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO 0xfffe103050a4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI 0xfffe103050a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA 0xfffe103050a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK 0xfffe103050ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64 0xfffe103050ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64 0xfffe103050b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING 0xfffe103050b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64 0xfffe103050b4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST 0xfffe103050c0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL 0xfffe103050c2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE 0xfffe103050c4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA 0xfffe103050c8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10305100
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10305104
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1 0xfffe10305108
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030510c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10305150
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS 0xfffe10305154
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK 0xfffe10305158
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030515c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS 0xfffe10305160
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK 0xfffe10305164
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10305168
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0 0xfffe1030516c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1 0xfffe10305170
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2 0xfffe10305174
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3 0xfffe10305178
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0 0xfffe10305188
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030518c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2 0xfffe10305190
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3 0xfffe10305194
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103052b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP 0xfffe103052b4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL 0xfffe103052b6
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10305328
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP 0xfffe1030532c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL 0xfffe1030532e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+// base address: 0xfffe10306000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID 0xfffe10306000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID 0xfffe10306002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND 0xfffe10306004
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS 0xfffe10306006
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID 0xfffe10306008
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE 0xfffe10306009
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS 0xfffe1030600a
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS 0xfffe1030600b
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE 0xfffe1030600c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY 0xfffe1030600d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER 0xfffe1030600e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST 0xfffe1030600f
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1 0xfffe10306010
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2 0xfffe10306014
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3 0xfffe10306018
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4 0xfffe1030601c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5 0xfffe10306020
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6 0xfffe10306024
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR 0xfffe10306028
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID 0xfffe1030602c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR 0xfffe10306030
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR 0xfffe10306034
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE 0xfffe1030603c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN 0xfffe1030603d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT 0xfffe1030603e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY 0xfffe1030603f
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST 0xfffe10306064
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP 0xfffe10306066
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP 0xfffe10306068
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL 0xfffe1030606c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS 0xfffe1030606e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP 0xfffe10306070
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL 0xfffe10306074
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS 0xfffe10306076
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2 0xfffe10306088
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2 0xfffe1030608c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2 0xfffe1030608e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2 0xfffe10306090
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2 0xfffe10306094
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2 0xfffe10306096
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST 0xfffe103060a0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL 0xfffe103060a2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO 0xfffe103060a4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI 0xfffe103060a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA 0xfffe103060a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK 0xfffe103060ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64 0xfffe103060ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64 0xfffe103060b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING 0xfffe103060b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64 0xfffe103060b4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST 0xfffe103060c0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL 0xfffe103060c2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE 0xfffe103060c4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA 0xfffe103060c8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10306100
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10306104
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1 0xfffe10306108
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030610c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10306150
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS 0xfffe10306154
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK 0xfffe10306158
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030615c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS 0xfffe10306160
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK 0xfffe10306164
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10306168
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0 0xfffe1030616c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1 0xfffe10306170
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2 0xfffe10306174
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3 0xfffe10306178
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0 0xfffe10306188
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030618c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2 0xfffe10306190
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3 0xfffe10306194
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103062b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP 0xfffe103062b4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL 0xfffe103062b6
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10306328
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP 0xfffe1030632c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL 0xfffe1030632e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+// base address: 0xfffe10307000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID 0xfffe10307000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID 0xfffe10307002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND 0xfffe10307004
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS 0xfffe10307006
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID 0xfffe10307008
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE 0xfffe10307009
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS 0xfffe1030700a
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS 0xfffe1030700b
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE 0xfffe1030700c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY 0xfffe1030700d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER 0xfffe1030700e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST 0xfffe1030700f
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1 0xfffe10307010
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2 0xfffe10307014
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3 0xfffe10307018
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4 0xfffe1030701c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5 0xfffe10307020
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6 0xfffe10307024
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR 0xfffe10307028
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID 0xfffe1030702c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR 0xfffe10307030
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR 0xfffe10307034
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE 0xfffe1030703c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN 0xfffe1030703d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT 0xfffe1030703e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY 0xfffe1030703f
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST 0xfffe10307064
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP 0xfffe10307066
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP 0xfffe10307068
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL 0xfffe1030706c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS 0xfffe1030706e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP 0xfffe10307070
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL 0xfffe10307074
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS 0xfffe10307076
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2 0xfffe10307088
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2 0xfffe1030708c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2 0xfffe1030708e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2 0xfffe10307090
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2 0xfffe10307094
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2 0xfffe10307096
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST 0xfffe103070a0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL 0xfffe103070a2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO 0xfffe103070a4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI 0xfffe103070a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA 0xfffe103070a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK 0xfffe103070ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64 0xfffe103070ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64 0xfffe103070b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING 0xfffe103070b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64 0xfffe103070b4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST 0xfffe103070c0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL 0xfffe103070c2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE 0xfffe103070c4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA 0xfffe103070c8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10307100
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10307104
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1 0xfffe10307108
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030710c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10307150
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS 0xfffe10307154
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK 0xfffe10307158
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030715c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS 0xfffe10307160
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK 0xfffe10307164
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10307168
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0 0xfffe1030716c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1 0xfffe10307170
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2 0xfffe10307174
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3 0xfffe10307178
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0 0xfffe10307188
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030718c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2 0xfffe10307190
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3 0xfffe10307194
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103072b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP 0xfffe103072b4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL 0xfffe103072b6
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10307328
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP 0xfffe1030732c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL 0xfffe1030732e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+// base address: 0xfffe10308000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID 0xfffe10308000
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID 0xfffe10308002
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND 0xfffe10308004
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS 0xfffe10308006
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID 0xfffe10308008
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE 0xfffe10308009
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS 0xfffe1030800a
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS 0xfffe1030800b
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE 0xfffe1030800c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY 0xfffe1030800d
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER 0xfffe1030800e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST 0xfffe1030800f
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1 0xfffe10308010
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2 0xfffe10308014
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3 0xfffe10308018
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4 0xfffe1030801c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5 0xfffe10308020
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6 0xfffe10308024
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR 0xfffe10308028
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID 0xfffe1030802c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR 0xfffe10308030
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR 0xfffe10308034
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE 0xfffe1030803c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN 0xfffe1030803d
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT 0xfffe1030803e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY 0xfffe1030803f
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST 0xfffe10308064
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP 0xfffe10308066
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP 0xfffe10308068
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL 0xfffe1030806c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS 0xfffe1030806e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP 0xfffe10308070
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL 0xfffe10308074
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS 0xfffe10308076
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2 0xfffe10308088
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2 0xfffe1030808c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2 0xfffe1030808e
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2 0xfffe10308090
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2 0xfffe10308094
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2 0xfffe10308096
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST 0xfffe103080a0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL 0xfffe103080a2
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO 0xfffe103080a4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI 0xfffe103080a8
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA 0xfffe103080a8
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK 0xfffe103080ac
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64 0xfffe103080ac
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64 0xfffe103080b0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING 0xfffe103080b0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64 0xfffe103080b4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST 0xfffe103080c0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL 0xfffe103080c2
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE 0xfffe103080c4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA 0xfffe103080c8
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10308100
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10308104
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1 0xfffe10308108
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030810c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10308150
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS 0xfffe10308154
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK 0xfffe10308158
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030815c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS 0xfffe10308160
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK 0xfffe10308164
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10308168
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0 0xfffe1030816c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1 0xfffe10308170
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2 0xfffe10308174
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3 0xfffe10308178
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0 0xfffe10308188
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030818c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2 0xfffe10308190
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3 0xfffe10308194
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103082b0
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP 0xfffe103082b4
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL 0xfffe103082b6
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10308328
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP 0xfffe1030832c
+#define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL 0xfffe1030832e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+// base address: 0xfffe10309000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID 0xfffe10309000
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID 0xfffe10309002
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND 0xfffe10309004
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS 0xfffe10309006
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID 0xfffe10309008
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE 0xfffe10309009
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS 0xfffe1030900a
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS 0xfffe1030900b
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE 0xfffe1030900c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY 0xfffe1030900d
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER 0xfffe1030900e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST 0xfffe1030900f
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1 0xfffe10309010
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2 0xfffe10309014
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3 0xfffe10309018
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4 0xfffe1030901c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5 0xfffe10309020
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6 0xfffe10309024
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR 0xfffe10309028
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID 0xfffe1030902c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR 0xfffe10309030
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR 0xfffe10309034
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE 0xfffe1030903c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN 0xfffe1030903d
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT 0xfffe1030903e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY 0xfffe1030903f
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST 0xfffe10309064
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP 0xfffe10309066
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP 0xfffe10309068
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL 0xfffe1030906c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS 0xfffe1030906e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP 0xfffe10309070
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL 0xfffe10309074
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS 0xfffe10309076
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2 0xfffe10309088
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2 0xfffe1030908c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2 0xfffe1030908e
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2 0xfffe10309090
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2 0xfffe10309094
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2 0xfffe10309096
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST 0xfffe103090a0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL 0xfffe103090a2
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO 0xfffe103090a4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI 0xfffe103090a8
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA 0xfffe103090a8
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK 0xfffe103090ac
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64 0xfffe103090ac
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64 0xfffe103090b0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING 0xfffe103090b0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64 0xfffe103090b4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST 0xfffe103090c0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL 0xfffe103090c2
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE 0xfffe103090c4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA 0xfffe103090c8
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10309100
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10309104
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1 0xfffe10309108
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030910c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10309150
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS 0xfffe10309154
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK 0xfffe10309158
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030915c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS 0xfffe10309160
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK 0xfffe10309164
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10309168
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0 0xfffe1030916c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1 0xfffe10309170
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2 0xfffe10309174
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3 0xfffe10309178
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0 0xfffe10309188
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030918c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2 0xfffe10309190
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3 0xfffe10309194
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103092b0
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP 0xfffe103092b4
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL 0xfffe103092b6
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10309328
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP 0xfffe1030932c
+#define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL 0xfffe1030932e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+// base address: 0xfffe1030a000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID 0xfffe1030a000
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID 0xfffe1030a002
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND 0xfffe1030a004
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS 0xfffe1030a006
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID 0xfffe1030a008
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE 0xfffe1030a009
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS 0xfffe1030a00a
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS 0xfffe1030a00b
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE 0xfffe1030a00c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY 0xfffe1030a00d
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER 0xfffe1030a00e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST 0xfffe1030a00f
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1 0xfffe1030a010
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2 0xfffe1030a014
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3 0xfffe1030a018
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4 0xfffe1030a01c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5 0xfffe1030a020
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6 0xfffe1030a024
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR 0xfffe1030a028
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID 0xfffe1030a02c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR 0xfffe1030a030
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR 0xfffe1030a034
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE 0xfffe1030a03c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN 0xfffe1030a03d
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT 0xfffe1030a03e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY 0xfffe1030a03f
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST 0xfffe1030a064
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP 0xfffe1030a066
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP 0xfffe1030a068
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL 0xfffe1030a06c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS 0xfffe1030a06e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP 0xfffe1030a070
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL 0xfffe1030a074
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS 0xfffe1030a076
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2 0xfffe1030a088
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2 0xfffe1030a08c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2 0xfffe1030a08e
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2 0xfffe1030a090
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2 0xfffe1030a094
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2 0xfffe1030a096
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST 0xfffe1030a0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL 0xfffe1030a0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO 0xfffe1030a0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI 0xfffe1030a0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA 0xfffe1030a0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK 0xfffe1030a0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64 0xfffe1030a0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64 0xfffe1030a0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING 0xfffe1030a0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64 0xfffe1030a0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST 0xfffe1030a0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL 0xfffe1030a0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE 0xfffe1030a0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA 0xfffe1030a0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030a100
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030a104
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030a108
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030a10c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030a150
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030a154
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK 0xfffe1030a158
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030a15c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS 0xfffe1030a160
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK 0xfffe1030a164
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030a168
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0 0xfffe1030a16c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1 0xfffe1030a170
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2 0xfffe1030a174
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3 0xfffe1030a178
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030a188
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030a18c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030a190
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030a194
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030a2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP 0xfffe1030a2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL 0xfffe1030a2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030a328
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP 0xfffe1030a32c
+#define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL 0xfffe1030a32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+// base address: 0xfffe1030b000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID 0xfffe1030b000
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID 0xfffe1030b002
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND 0xfffe1030b004
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS 0xfffe1030b006
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID 0xfffe1030b008
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE 0xfffe1030b009
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS 0xfffe1030b00a
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS 0xfffe1030b00b
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE 0xfffe1030b00c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY 0xfffe1030b00d
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER 0xfffe1030b00e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST 0xfffe1030b00f
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1 0xfffe1030b010
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2 0xfffe1030b014
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3 0xfffe1030b018
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4 0xfffe1030b01c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5 0xfffe1030b020
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6 0xfffe1030b024
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR 0xfffe1030b028
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID 0xfffe1030b02c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR 0xfffe1030b030
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR 0xfffe1030b034
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE 0xfffe1030b03c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN 0xfffe1030b03d
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT 0xfffe1030b03e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY 0xfffe1030b03f
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST 0xfffe1030b064
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP 0xfffe1030b066
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP 0xfffe1030b068
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL 0xfffe1030b06c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS 0xfffe1030b06e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP 0xfffe1030b070
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL 0xfffe1030b074
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS 0xfffe1030b076
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2 0xfffe1030b088
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2 0xfffe1030b08c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2 0xfffe1030b08e
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2 0xfffe1030b090
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2 0xfffe1030b094
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2 0xfffe1030b096
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST 0xfffe1030b0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL 0xfffe1030b0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO 0xfffe1030b0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI 0xfffe1030b0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA 0xfffe1030b0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK 0xfffe1030b0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64 0xfffe1030b0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64 0xfffe1030b0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING 0xfffe1030b0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64 0xfffe1030b0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST 0xfffe1030b0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL 0xfffe1030b0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE 0xfffe1030b0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA 0xfffe1030b0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030b100
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030b104
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030b108
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030b10c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030b150
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030b154
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK 0xfffe1030b158
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030b15c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS 0xfffe1030b160
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK 0xfffe1030b164
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030b168
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0 0xfffe1030b16c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1 0xfffe1030b170
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2 0xfffe1030b174
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3 0xfffe1030b178
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030b188
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030b18c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030b190
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030b194
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030b2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP 0xfffe1030b2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL 0xfffe1030b2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030b328
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP 0xfffe1030b32c
+#define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL 0xfffe1030b32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+// base address: 0xfffe1030c000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID 0xfffe1030c000
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID 0xfffe1030c002
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND 0xfffe1030c004
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS 0xfffe1030c006
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID 0xfffe1030c008
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE 0xfffe1030c009
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS 0xfffe1030c00a
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS 0xfffe1030c00b
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE 0xfffe1030c00c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY 0xfffe1030c00d
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER 0xfffe1030c00e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST 0xfffe1030c00f
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1 0xfffe1030c010
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2 0xfffe1030c014
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3 0xfffe1030c018
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4 0xfffe1030c01c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5 0xfffe1030c020
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6 0xfffe1030c024
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR 0xfffe1030c028
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID 0xfffe1030c02c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR 0xfffe1030c030
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR 0xfffe1030c034
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE 0xfffe1030c03c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN 0xfffe1030c03d
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT 0xfffe1030c03e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY 0xfffe1030c03f
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST 0xfffe1030c064
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP 0xfffe1030c066
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP 0xfffe1030c068
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL 0xfffe1030c06c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS 0xfffe1030c06e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP 0xfffe1030c070
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL 0xfffe1030c074
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS 0xfffe1030c076
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2 0xfffe1030c088
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2 0xfffe1030c08c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2 0xfffe1030c08e
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2 0xfffe1030c090
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2 0xfffe1030c094
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2 0xfffe1030c096
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST 0xfffe1030c0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL 0xfffe1030c0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO 0xfffe1030c0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI 0xfffe1030c0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA 0xfffe1030c0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK 0xfffe1030c0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64 0xfffe1030c0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64 0xfffe1030c0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING 0xfffe1030c0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64 0xfffe1030c0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST 0xfffe1030c0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL 0xfffe1030c0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE 0xfffe1030c0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA 0xfffe1030c0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030c100
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030c104
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030c108
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030c10c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030c150
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030c154
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK 0xfffe1030c158
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030c15c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS 0xfffe1030c160
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK 0xfffe1030c164
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030c168
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0 0xfffe1030c16c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1 0xfffe1030c170
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2 0xfffe1030c174
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3 0xfffe1030c178
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030c188
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030c18c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030c190
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030c194
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030c2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP 0xfffe1030c2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL 0xfffe1030c2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030c328
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP 0xfffe1030c32c
+#define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL 0xfffe1030c32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+// base address: 0xfffe1030d000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID 0xfffe1030d000
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID 0xfffe1030d002
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND 0xfffe1030d004
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS 0xfffe1030d006
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID 0xfffe1030d008
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE 0xfffe1030d009
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS 0xfffe1030d00a
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS 0xfffe1030d00b
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE 0xfffe1030d00c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY 0xfffe1030d00d
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER 0xfffe1030d00e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST 0xfffe1030d00f
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1 0xfffe1030d010
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2 0xfffe1030d014
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3 0xfffe1030d018
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4 0xfffe1030d01c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5 0xfffe1030d020
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6 0xfffe1030d024
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR 0xfffe1030d028
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID 0xfffe1030d02c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR 0xfffe1030d030
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR 0xfffe1030d034
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE 0xfffe1030d03c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN 0xfffe1030d03d
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT 0xfffe1030d03e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY 0xfffe1030d03f
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST 0xfffe1030d064
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP 0xfffe1030d066
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP 0xfffe1030d068
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL 0xfffe1030d06c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS 0xfffe1030d06e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP 0xfffe1030d070
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL 0xfffe1030d074
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS 0xfffe1030d076
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2 0xfffe1030d088
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2 0xfffe1030d08c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2 0xfffe1030d08e
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2 0xfffe1030d090
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2 0xfffe1030d094
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2 0xfffe1030d096
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST 0xfffe1030d0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL 0xfffe1030d0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO 0xfffe1030d0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI 0xfffe1030d0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA 0xfffe1030d0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK 0xfffe1030d0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64 0xfffe1030d0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64 0xfffe1030d0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING 0xfffe1030d0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64 0xfffe1030d0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST 0xfffe1030d0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL 0xfffe1030d0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE 0xfffe1030d0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA 0xfffe1030d0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030d100
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030d104
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030d108
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030d10c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030d150
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030d154
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK 0xfffe1030d158
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030d15c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS 0xfffe1030d160
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK 0xfffe1030d164
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030d168
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0 0xfffe1030d16c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1 0xfffe1030d170
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2 0xfffe1030d174
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3 0xfffe1030d178
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030d188
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030d18c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030d190
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030d194
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030d2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP 0xfffe1030d2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL 0xfffe1030d2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030d328
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP 0xfffe1030d32c
+#define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL 0xfffe1030d32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+// base address: 0xfffe1030e000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID 0xfffe1030e000
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID 0xfffe1030e002
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND 0xfffe1030e004
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS 0xfffe1030e006
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID 0xfffe1030e008
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE 0xfffe1030e009
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS 0xfffe1030e00a
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS 0xfffe1030e00b
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE 0xfffe1030e00c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY 0xfffe1030e00d
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER 0xfffe1030e00e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST 0xfffe1030e00f
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1 0xfffe1030e010
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2 0xfffe1030e014
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3 0xfffe1030e018
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4 0xfffe1030e01c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5 0xfffe1030e020
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6 0xfffe1030e024
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR 0xfffe1030e028
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID 0xfffe1030e02c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR 0xfffe1030e030
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR 0xfffe1030e034
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE 0xfffe1030e03c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN 0xfffe1030e03d
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT 0xfffe1030e03e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY 0xfffe1030e03f
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST 0xfffe1030e064
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP 0xfffe1030e066
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP 0xfffe1030e068
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL 0xfffe1030e06c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS 0xfffe1030e06e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP 0xfffe1030e070
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL 0xfffe1030e074
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS 0xfffe1030e076
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2 0xfffe1030e088
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2 0xfffe1030e08c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2 0xfffe1030e08e
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2 0xfffe1030e090
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2 0xfffe1030e094
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2 0xfffe1030e096
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST 0xfffe1030e0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL 0xfffe1030e0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO 0xfffe1030e0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI 0xfffe1030e0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA 0xfffe1030e0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK 0xfffe1030e0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64 0xfffe1030e0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64 0xfffe1030e0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING 0xfffe1030e0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64 0xfffe1030e0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST 0xfffe1030e0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL 0xfffe1030e0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE 0xfffe1030e0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA 0xfffe1030e0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030e100
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030e104
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030e108
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030e10c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030e150
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030e154
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK 0xfffe1030e158
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030e15c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS 0xfffe1030e160
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK 0xfffe1030e164
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030e168
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0 0xfffe1030e16c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1 0xfffe1030e170
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2 0xfffe1030e174
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3 0xfffe1030e178
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030e188
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030e18c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030e190
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030e194
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030e2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP 0xfffe1030e2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL 0xfffe1030e2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030e328
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP 0xfffe1030e32c
+#define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL 0xfffe1030e32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+// base address: 0xfffe1030f000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID 0xfffe1030f000
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID 0xfffe1030f002
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND 0xfffe1030f004
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS 0xfffe1030f006
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID 0xfffe1030f008
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE 0xfffe1030f009
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS 0xfffe1030f00a
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS 0xfffe1030f00b
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE 0xfffe1030f00c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY 0xfffe1030f00d
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER 0xfffe1030f00e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST 0xfffe1030f00f
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1 0xfffe1030f010
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2 0xfffe1030f014
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3 0xfffe1030f018
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4 0xfffe1030f01c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5 0xfffe1030f020
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6 0xfffe1030f024
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR 0xfffe1030f028
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID 0xfffe1030f02c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR 0xfffe1030f030
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR 0xfffe1030f034
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE 0xfffe1030f03c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN 0xfffe1030f03d
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT 0xfffe1030f03e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY 0xfffe1030f03f
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST 0xfffe1030f064
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP 0xfffe1030f066
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP 0xfffe1030f068
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL 0xfffe1030f06c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS 0xfffe1030f06e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP 0xfffe1030f070
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL 0xfffe1030f074
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS 0xfffe1030f076
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2 0xfffe1030f088
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2 0xfffe1030f08c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2 0xfffe1030f08e
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2 0xfffe1030f090
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2 0xfffe1030f094
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2 0xfffe1030f096
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST 0xfffe1030f0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL 0xfffe1030f0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO 0xfffe1030f0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI 0xfffe1030f0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA 0xfffe1030f0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK 0xfffe1030f0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64 0xfffe1030f0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64 0xfffe1030f0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING 0xfffe1030f0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64 0xfffe1030f0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST 0xfffe1030f0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL 0xfffe1030f0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE 0xfffe1030f0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA 0xfffe1030f0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030f100
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030f104
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030f108
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030f10c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030f150
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030f154
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK 0xfffe1030f158
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030f15c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS 0xfffe1030f160
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK 0xfffe1030f164
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030f168
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0 0xfffe1030f16c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1 0xfffe1030f170
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2 0xfffe1030f174
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3 0xfffe1030f178
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030f188
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030f18c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030f190
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030f194
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030f2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP 0xfffe1030f2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL 0xfffe1030f2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030f328
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP 0xfffe1030f32c
+#define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL 0xfffe1030f32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
+// base address: 0xfffe10310000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID 0xfffe10310000
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID 0xfffe10310002
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_COMMAND 0xfffe10310004
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_STATUS 0xfffe10310006
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID 0xfffe10310008
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE 0xfffe10310009
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS 0xfffe1031000a
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS 0xfffe1031000b
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE 0xfffe1031000c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LATENCY 0xfffe1031000d
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_HEADER 0xfffe1031000e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BIST 0xfffe1031000f
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1 0xfffe10310010
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2 0xfffe10310014
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3 0xfffe10310018
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4 0xfffe1031001c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5 0xfffe10310020
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6 0xfffe10310024
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR 0xfffe10310028
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID 0xfffe1031002c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR 0xfffe10310030
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR 0xfffe10310034
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE 0xfffe1031003c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN 0xfffe1031003d
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT 0xfffe1031003e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY 0xfffe1031003f
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST 0xfffe10310064
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP 0xfffe10310066
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP 0xfffe10310068
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL 0xfffe1031006c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS 0xfffe1031006e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP 0xfffe10310070
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL 0xfffe10310074
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS 0xfffe10310076
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2 0xfffe10310088
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2 0xfffe1031008c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2 0xfffe1031008e
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2 0xfffe10310090
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2 0xfffe10310094
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2 0xfffe10310096
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST 0xfffe103100a0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL 0xfffe103100a2
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO 0xfffe103100a4
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI 0xfffe103100a8
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA 0xfffe103100a8
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK 0xfffe103100ac
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64 0xfffe103100ac
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64 0xfffe103100b0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING 0xfffe103100b0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64 0xfffe103100b4
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST 0xfffe103100c0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL 0xfffe103100c2
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE 0xfffe103100c4
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA 0xfffe103100c8
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10310100
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10310104
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1 0xfffe10310108
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031010c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10310150
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS 0xfffe10310154
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK 0xfffe10310158
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031015c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS 0xfffe10310160
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK 0xfffe10310164
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10310168
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0 0xfffe1031016c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1 0xfffe10310170
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2 0xfffe10310174
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3 0xfffe10310178
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0 0xfffe10310188
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031018c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2 0xfffe10310190
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3 0xfffe10310194
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103102b0
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP 0xfffe103102b4
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL 0xfffe103102b6
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10310328
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP 0xfffe1031032c
+#define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL 0xfffe1031032e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
+// base address: 0xfffe10311000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID 0xfffe10311000
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID 0xfffe10311002
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_COMMAND 0xfffe10311004
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_STATUS 0xfffe10311006
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID 0xfffe10311008
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE 0xfffe10311009
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS 0xfffe1031100a
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS 0xfffe1031100b
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE 0xfffe1031100c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LATENCY 0xfffe1031100d
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_HEADER 0xfffe1031100e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BIST 0xfffe1031100f
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1 0xfffe10311010
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2 0xfffe10311014
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3 0xfffe10311018
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4 0xfffe1031101c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5 0xfffe10311020
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6 0xfffe10311024
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR 0xfffe10311028
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID 0xfffe1031102c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR 0xfffe10311030
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR 0xfffe10311034
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE 0xfffe1031103c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN 0xfffe1031103d
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT 0xfffe1031103e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY 0xfffe1031103f
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST 0xfffe10311064
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP 0xfffe10311066
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP 0xfffe10311068
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL 0xfffe1031106c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS 0xfffe1031106e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP 0xfffe10311070
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL 0xfffe10311074
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS 0xfffe10311076
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2 0xfffe10311088
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2 0xfffe1031108c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2 0xfffe1031108e
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2 0xfffe10311090
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2 0xfffe10311094
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2 0xfffe10311096
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST 0xfffe103110a0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL 0xfffe103110a2
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO 0xfffe103110a4
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI 0xfffe103110a8
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA 0xfffe103110a8
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK 0xfffe103110ac
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64 0xfffe103110ac
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64 0xfffe103110b0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING 0xfffe103110b0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64 0xfffe103110b4
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST 0xfffe103110c0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL 0xfffe103110c2
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE 0xfffe103110c4
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA 0xfffe103110c8
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10311100
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10311104
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1 0xfffe10311108
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031110c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10311150
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS 0xfffe10311154
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK 0xfffe10311158
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031115c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS 0xfffe10311160
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK 0xfffe10311164
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10311168
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0 0xfffe1031116c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1 0xfffe10311170
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2 0xfffe10311174
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3 0xfffe10311178
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0 0xfffe10311188
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031118c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2 0xfffe10311190
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3 0xfffe10311194
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103112b0
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP 0xfffe103112b4
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL 0xfffe103112b6
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10311328
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP 0xfffe1031132c
+#define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL 0xfffe1031132e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
+// base address: 0xfffe10312000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID 0xfffe10312000
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID 0xfffe10312002
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_COMMAND 0xfffe10312004
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_STATUS 0xfffe10312006
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID 0xfffe10312008
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE 0xfffe10312009
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS 0xfffe1031200a
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS 0xfffe1031200b
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE 0xfffe1031200c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LATENCY 0xfffe1031200d
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_HEADER 0xfffe1031200e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BIST 0xfffe1031200f
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1 0xfffe10312010
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2 0xfffe10312014
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3 0xfffe10312018
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4 0xfffe1031201c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5 0xfffe10312020
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6 0xfffe10312024
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR 0xfffe10312028
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID 0xfffe1031202c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR 0xfffe10312030
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR 0xfffe10312034
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE 0xfffe1031203c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN 0xfffe1031203d
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT 0xfffe1031203e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY 0xfffe1031203f
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST 0xfffe10312064
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP 0xfffe10312066
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP 0xfffe10312068
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL 0xfffe1031206c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS 0xfffe1031206e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP 0xfffe10312070
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL 0xfffe10312074
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS 0xfffe10312076
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2 0xfffe10312088
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2 0xfffe1031208c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2 0xfffe1031208e
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2 0xfffe10312090
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2 0xfffe10312094
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2 0xfffe10312096
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST 0xfffe103120a0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL 0xfffe103120a2
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO 0xfffe103120a4
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI 0xfffe103120a8
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA 0xfffe103120a8
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK 0xfffe103120ac
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64 0xfffe103120ac
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64 0xfffe103120b0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING 0xfffe103120b0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64 0xfffe103120b4
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST 0xfffe103120c0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL 0xfffe103120c2
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE 0xfffe103120c4
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA 0xfffe103120c8
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10312100
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10312104
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1 0xfffe10312108
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031210c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10312150
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS 0xfffe10312154
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK 0xfffe10312158
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031215c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS 0xfffe10312160
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK 0xfffe10312164
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10312168
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0 0xfffe1031216c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1 0xfffe10312170
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2 0xfffe10312174
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3 0xfffe10312178
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0 0xfffe10312188
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031218c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2 0xfffe10312190
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3 0xfffe10312194
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103122b0
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP 0xfffe103122b4
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL 0xfffe103122b6
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10312328
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP 0xfffe1031232c
+#define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL 0xfffe1031232e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
+// base address: 0xfffe10313000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID 0xfffe10313000
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID 0xfffe10313002
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_COMMAND 0xfffe10313004
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_STATUS 0xfffe10313006
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID 0xfffe10313008
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE 0xfffe10313009
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS 0xfffe1031300a
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS 0xfffe1031300b
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE 0xfffe1031300c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LATENCY 0xfffe1031300d
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_HEADER 0xfffe1031300e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BIST 0xfffe1031300f
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1 0xfffe10313010
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2 0xfffe10313014
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3 0xfffe10313018
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4 0xfffe1031301c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5 0xfffe10313020
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6 0xfffe10313024
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR 0xfffe10313028
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID 0xfffe1031302c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR 0xfffe10313030
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR 0xfffe10313034
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE 0xfffe1031303c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN 0xfffe1031303d
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT 0xfffe1031303e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY 0xfffe1031303f
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST 0xfffe10313064
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP 0xfffe10313066
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP 0xfffe10313068
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL 0xfffe1031306c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS 0xfffe1031306e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP 0xfffe10313070
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL 0xfffe10313074
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS 0xfffe10313076
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2 0xfffe10313088
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2 0xfffe1031308c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2 0xfffe1031308e
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2 0xfffe10313090
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2 0xfffe10313094
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2 0xfffe10313096
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST 0xfffe103130a0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL 0xfffe103130a2
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO 0xfffe103130a4
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI 0xfffe103130a8
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA 0xfffe103130a8
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK 0xfffe103130ac
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64 0xfffe103130ac
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64 0xfffe103130b0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING 0xfffe103130b0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64 0xfffe103130b4
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST 0xfffe103130c0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL 0xfffe103130c2
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE 0xfffe103130c4
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA 0xfffe103130c8
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10313100
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10313104
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1 0xfffe10313108
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031310c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10313150
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS 0xfffe10313154
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK 0xfffe10313158
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031315c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS 0xfffe10313160
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK 0xfffe10313164
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10313168
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0 0xfffe1031316c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1 0xfffe10313170
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2 0xfffe10313174
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3 0xfffe10313178
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0 0xfffe10313188
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031318c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2 0xfffe10313190
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3 0xfffe10313194
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103132b0
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP 0xfffe103132b4
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL 0xfffe103132b6
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10313328
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP 0xfffe1031332c
+#define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL 0xfffe1031332e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
+// base address: 0xfffe10314000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID 0xfffe10314000
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID 0xfffe10314002
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_COMMAND 0xfffe10314004
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_STATUS 0xfffe10314006
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID 0xfffe10314008
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE 0xfffe10314009
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS 0xfffe1031400a
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS 0xfffe1031400b
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE 0xfffe1031400c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LATENCY 0xfffe1031400d
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_HEADER 0xfffe1031400e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BIST 0xfffe1031400f
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1 0xfffe10314010
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2 0xfffe10314014
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3 0xfffe10314018
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4 0xfffe1031401c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5 0xfffe10314020
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6 0xfffe10314024
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR 0xfffe10314028
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID 0xfffe1031402c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR 0xfffe10314030
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR 0xfffe10314034
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE 0xfffe1031403c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN 0xfffe1031403d
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT 0xfffe1031403e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY 0xfffe1031403f
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST 0xfffe10314064
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP 0xfffe10314066
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP 0xfffe10314068
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL 0xfffe1031406c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS 0xfffe1031406e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP 0xfffe10314070
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL 0xfffe10314074
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS 0xfffe10314076
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2 0xfffe10314088
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2 0xfffe1031408c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2 0xfffe1031408e
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2 0xfffe10314090
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2 0xfffe10314094
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2 0xfffe10314096
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST 0xfffe103140a0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL 0xfffe103140a2
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO 0xfffe103140a4
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI 0xfffe103140a8
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA 0xfffe103140a8
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK 0xfffe103140ac
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64 0xfffe103140ac
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64 0xfffe103140b0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING 0xfffe103140b0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64 0xfffe103140b4
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST 0xfffe103140c0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL 0xfffe103140c2
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE 0xfffe103140c4
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA 0xfffe103140c8
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10314100
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10314104
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1 0xfffe10314108
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031410c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10314150
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS 0xfffe10314154
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK 0xfffe10314158
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031415c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS 0xfffe10314160
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK 0xfffe10314164
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10314168
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0 0xfffe1031416c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1 0xfffe10314170
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2 0xfffe10314174
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3 0xfffe10314178
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0 0xfffe10314188
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031418c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2 0xfffe10314190
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3 0xfffe10314194
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103142b0
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP 0xfffe103142b4
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL 0xfffe103142b6
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10314328
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP 0xfffe1031432c
+#define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL 0xfffe1031432e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
+// base address: 0xfffe10315000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID 0xfffe10315000
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID 0xfffe10315002
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_COMMAND 0xfffe10315004
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_STATUS 0xfffe10315006
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID 0xfffe10315008
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE 0xfffe10315009
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS 0xfffe1031500a
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS 0xfffe1031500b
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE 0xfffe1031500c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LATENCY 0xfffe1031500d
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_HEADER 0xfffe1031500e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BIST 0xfffe1031500f
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1 0xfffe10315010
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2 0xfffe10315014
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3 0xfffe10315018
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4 0xfffe1031501c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5 0xfffe10315020
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6 0xfffe10315024
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR 0xfffe10315028
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID 0xfffe1031502c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR 0xfffe10315030
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR 0xfffe10315034
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE 0xfffe1031503c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN 0xfffe1031503d
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT 0xfffe1031503e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY 0xfffe1031503f
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST 0xfffe10315064
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP 0xfffe10315066
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP 0xfffe10315068
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL 0xfffe1031506c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS 0xfffe1031506e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP 0xfffe10315070
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL 0xfffe10315074
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS 0xfffe10315076
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2 0xfffe10315088
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2 0xfffe1031508c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2 0xfffe1031508e
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2 0xfffe10315090
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2 0xfffe10315094
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2 0xfffe10315096
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST 0xfffe103150a0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL 0xfffe103150a2
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO 0xfffe103150a4
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI 0xfffe103150a8
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA 0xfffe103150a8
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK 0xfffe103150ac
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64 0xfffe103150ac
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64 0xfffe103150b0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING 0xfffe103150b0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64 0xfffe103150b4
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST 0xfffe103150c0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL 0xfffe103150c2
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE 0xfffe103150c4
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA 0xfffe103150c8
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10315100
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10315104
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1 0xfffe10315108
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031510c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10315150
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS 0xfffe10315154
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK 0xfffe10315158
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031515c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS 0xfffe10315160
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK 0xfffe10315164
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10315168
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0 0xfffe1031516c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1 0xfffe10315170
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2 0xfffe10315174
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3 0xfffe10315178
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0 0xfffe10315188
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031518c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2 0xfffe10315190
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3 0xfffe10315194
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103152b0
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP 0xfffe103152b4
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL 0xfffe103152b6
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10315328
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP 0xfffe1031532c
+#define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL 0xfffe1031532e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
+// base address: 0xfffe10316000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID 0xfffe10316000
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID 0xfffe10316002
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_COMMAND 0xfffe10316004
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_STATUS 0xfffe10316006
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID 0xfffe10316008
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE 0xfffe10316009
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS 0xfffe1031600a
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS 0xfffe1031600b
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE 0xfffe1031600c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LATENCY 0xfffe1031600d
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_HEADER 0xfffe1031600e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BIST 0xfffe1031600f
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1 0xfffe10316010
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2 0xfffe10316014
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3 0xfffe10316018
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4 0xfffe1031601c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5 0xfffe10316020
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6 0xfffe10316024
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR 0xfffe10316028
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID 0xfffe1031602c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR 0xfffe10316030
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR 0xfffe10316034
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE 0xfffe1031603c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN 0xfffe1031603d
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT 0xfffe1031603e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY 0xfffe1031603f
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST 0xfffe10316064
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP 0xfffe10316066
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP 0xfffe10316068
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL 0xfffe1031606c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS 0xfffe1031606e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP 0xfffe10316070
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL 0xfffe10316074
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS 0xfffe10316076
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2 0xfffe10316088
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2 0xfffe1031608c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2 0xfffe1031608e
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2 0xfffe10316090
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2 0xfffe10316094
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2 0xfffe10316096
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST 0xfffe103160a0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL 0xfffe103160a2
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO 0xfffe103160a4
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI 0xfffe103160a8
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA 0xfffe103160a8
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK 0xfffe103160ac
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64 0xfffe103160ac
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64 0xfffe103160b0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING 0xfffe103160b0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64 0xfffe103160b4
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST 0xfffe103160c0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL 0xfffe103160c2
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE 0xfffe103160c4
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA 0xfffe103160c8
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10316100
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10316104
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1 0xfffe10316108
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031610c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10316150
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS 0xfffe10316154
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK 0xfffe10316158
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031615c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS 0xfffe10316160
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK 0xfffe10316164
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10316168
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0 0xfffe1031616c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1 0xfffe10316170
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2 0xfffe10316174
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3 0xfffe10316178
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0 0xfffe10316188
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031618c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2 0xfffe10316190
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3 0xfffe10316194
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103162b0
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP 0xfffe103162b4
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL 0xfffe103162b6
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10316328
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP 0xfffe1031632c
+#define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL 0xfffe1031632e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
+// base address: 0xfffe10317000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID 0xfffe10317000
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID 0xfffe10317002
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_COMMAND 0xfffe10317004
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_STATUS 0xfffe10317006
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID 0xfffe10317008
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE 0xfffe10317009
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS 0xfffe1031700a
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS 0xfffe1031700b
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE 0xfffe1031700c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LATENCY 0xfffe1031700d
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_HEADER 0xfffe1031700e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BIST 0xfffe1031700f
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1 0xfffe10317010
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2 0xfffe10317014
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3 0xfffe10317018
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4 0xfffe1031701c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5 0xfffe10317020
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6 0xfffe10317024
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR 0xfffe10317028
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID 0xfffe1031702c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR 0xfffe10317030
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR 0xfffe10317034
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE 0xfffe1031703c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN 0xfffe1031703d
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT 0xfffe1031703e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY 0xfffe1031703f
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST 0xfffe10317064
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP 0xfffe10317066
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP 0xfffe10317068
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL 0xfffe1031706c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS 0xfffe1031706e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP 0xfffe10317070
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL 0xfffe10317074
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS 0xfffe10317076
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2 0xfffe10317088
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2 0xfffe1031708c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2 0xfffe1031708e
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2 0xfffe10317090
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2 0xfffe10317094
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2 0xfffe10317096
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST 0xfffe103170a0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL 0xfffe103170a2
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO 0xfffe103170a4
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI 0xfffe103170a8
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA 0xfffe103170a8
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK 0xfffe103170ac
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64 0xfffe103170ac
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64 0xfffe103170b0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING 0xfffe103170b0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64 0xfffe103170b4
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST 0xfffe103170c0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL 0xfffe103170c2
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE 0xfffe103170c4
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA 0xfffe103170c8
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10317100
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10317104
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1 0xfffe10317108
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031710c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10317150
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS 0xfffe10317154
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK 0xfffe10317158
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031715c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS 0xfffe10317160
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK 0xfffe10317164
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10317168
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0 0xfffe1031716c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1 0xfffe10317170
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2 0xfffe10317174
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3 0xfffe10317178
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0 0xfffe10317188
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031718c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2 0xfffe10317190
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3 0xfffe10317194
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103172b0
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP 0xfffe103172b4
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL 0xfffe103172b6
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10317328
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP 0xfffe1031732c
+#define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL 0xfffe1031732e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
+// base address: 0xfffe10318000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID 0xfffe10318000
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID 0xfffe10318002
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_COMMAND 0xfffe10318004
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_STATUS 0xfffe10318006
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID 0xfffe10318008
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE 0xfffe10318009
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS 0xfffe1031800a
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS 0xfffe1031800b
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE 0xfffe1031800c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LATENCY 0xfffe1031800d
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_HEADER 0xfffe1031800e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BIST 0xfffe1031800f
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1 0xfffe10318010
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2 0xfffe10318014
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3 0xfffe10318018
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4 0xfffe1031801c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5 0xfffe10318020
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6 0xfffe10318024
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR 0xfffe10318028
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID 0xfffe1031802c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR 0xfffe10318030
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR 0xfffe10318034
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE 0xfffe1031803c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN 0xfffe1031803d
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT 0xfffe1031803e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY 0xfffe1031803f
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST 0xfffe10318064
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP 0xfffe10318066
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP 0xfffe10318068
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL 0xfffe1031806c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS 0xfffe1031806e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP 0xfffe10318070
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL 0xfffe10318074
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS 0xfffe10318076
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2 0xfffe10318088
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2 0xfffe1031808c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2 0xfffe1031808e
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2 0xfffe10318090
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2 0xfffe10318094
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2 0xfffe10318096
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST 0xfffe103180a0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL 0xfffe103180a2
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO 0xfffe103180a4
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI 0xfffe103180a8
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA 0xfffe103180a8
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK 0xfffe103180ac
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64 0xfffe103180ac
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64 0xfffe103180b0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING 0xfffe103180b0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64 0xfffe103180b4
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST 0xfffe103180c0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL 0xfffe103180c2
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE 0xfffe103180c4
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA 0xfffe103180c8
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10318100
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10318104
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1 0xfffe10318108
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031810c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10318150
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS 0xfffe10318154
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK 0xfffe10318158
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031815c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS 0xfffe10318160
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK 0xfffe10318164
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10318168
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0 0xfffe1031816c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1 0xfffe10318170
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2 0xfffe10318174
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3 0xfffe10318178
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0 0xfffe10318188
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031818c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2 0xfffe10318190
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3 0xfffe10318194
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103182b0
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP 0xfffe103182b4
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL 0xfffe103182b6
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10318328
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP 0xfffe1031832c
+#define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL 0xfffe1031832e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
+// base address: 0xfffe10319000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID 0xfffe10319000
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID 0xfffe10319002
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_COMMAND 0xfffe10319004
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_STATUS 0xfffe10319006
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID 0xfffe10319008
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE 0xfffe10319009
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS 0xfffe1031900a
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS 0xfffe1031900b
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE 0xfffe1031900c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LATENCY 0xfffe1031900d
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_HEADER 0xfffe1031900e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BIST 0xfffe1031900f
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1 0xfffe10319010
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2 0xfffe10319014
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3 0xfffe10319018
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4 0xfffe1031901c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5 0xfffe10319020
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6 0xfffe10319024
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR 0xfffe10319028
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID 0xfffe1031902c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR 0xfffe10319030
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR 0xfffe10319034
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE 0xfffe1031903c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN 0xfffe1031903d
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT 0xfffe1031903e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY 0xfffe1031903f
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST 0xfffe10319064
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP 0xfffe10319066
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP 0xfffe10319068
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL 0xfffe1031906c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS 0xfffe1031906e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP 0xfffe10319070
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL 0xfffe10319074
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS 0xfffe10319076
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2 0xfffe10319088
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2 0xfffe1031908c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2 0xfffe1031908e
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2 0xfffe10319090
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2 0xfffe10319094
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2 0xfffe10319096
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST 0xfffe103190a0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL 0xfffe103190a2
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO 0xfffe103190a4
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI 0xfffe103190a8
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA 0xfffe103190a8
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK 0xfffe103190ac
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64 0xfffe103190ac
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64 0xfffe103190b0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING 0xfffe103190b0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64 0xfffe103190b4
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST 0xfffe103190c0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL 0xfffe103190c2
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE 0xfffe103190c4
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA 0xfffe103190c8
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10319100
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10319104
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1 0xfffe10319108
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031910c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10319150
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS 0xfffe10319154
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK 0xfffe10319158
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031915c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS 0xfffe10319160
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK 0xfffe10319164
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10319168
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0 0xfffe1031916c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1 0xfffe10319170
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2 0xfffe10319174
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3 0xfffe10319178
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0 0xfffe10319188
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031918c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2 0xfffe10319190
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3 0xfffe10319194
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103192b0
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP 0xfffe103192b4
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL 0xfffe103192b6
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10319328
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP 0xfffe1031932c
+#define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL 0xfffe1031932e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
+// base address: 0xfffe1031a000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID 0xfffe1031a000
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID 0xfffe1031a002
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_COMMAND 0xfffe1031a004
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_STATUS 0xfffe1031a006
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID 0xfffe1031a008
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE 0xfffe1031a009
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS 0xfffe1031a00a
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS 0xfffe1031a00b
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE 0xfffe1031a00c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LATENCY 0xfffe1031a00d
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_HEADER 0xfffe1031a00e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BIST 0xfffe1031a00f
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1 0xfffe1031a010
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2 0xfffe1031a014
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3 0xfffe1031a018
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4 0xfffe1031a01c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5 0xfffe1031a020
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6 0xfffe1031a024
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR 0xfffe1031a028
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID 0xfffe1031a02c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR 0xfffe1031a030
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR 0xfffe1031a034
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE 0xfffe1031a03c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN 0xfffe1031a03d
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT 0xfffe1031a03e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY 0xfffe1031a03f
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST 0xfffe1031a064
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP 0xfffe1031a066
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP 0xfffe1031a068
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL 0xfffe1031a06c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS 0xfffe1031a06e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP 0xfffe1031a070
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL 0xfffe1031a074
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS 0xfffe1031a076
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2 0xfffe1031a088
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2 0xfffe1031a08c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2 0xfffe1031a08e
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2 0xfffe1031a090
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2 0xfffe1031a094
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2 0xfffe1031a096
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST 0xfffe1031a0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL 0xfffe1031a0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO 0xfffe1031a0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI 0xfffe1031a0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA 0xfffe1031a0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK 0xfffe1031a0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64 0xfffe1031a0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64 0xfffe1031a0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING 0xfffe1031a0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64 0xfffe1031a0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST 0xfffe1031a0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL 0xfffe1031a0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE 0xfffe1031a0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA 0xfffe1031a0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031a100
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031a104
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031a108
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031a10c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031a150
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031a154
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK 0xfffe1031a158
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031a15c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS 0xfffe1031a160
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK 0xfffe1031a164
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031a168
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0 0xfffe1031a16c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1 0xfffe1031a170
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2 0xfffe1031a174
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3 0xfffe1031a178
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031a188
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031a18c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031a190
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031a194
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031a2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP 0xfffe1031a2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL 0xfffe1031a2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031a328
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP 0xfffe1031a32c
+#define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL 0xfffe1031a32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
+// base address: 0xfffe1031b000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID 0xfffe1031b000
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID 0xfffe1031b002
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_COMMAND 0xfffe1031b004
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_STATUS 0xfffe1031b006
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID 0xfffe1031b008
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE 0xfffe1031b009
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS 0xfffe1031b00a
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS 0xfffe1031b00b
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE 0xfffe1031b00c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LATENCY 0xfffe1031b00d
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_HEADER 0xfffe1031b00e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BIST 0xfffe1031b00f
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1 0xfffe1031b010
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2 0xfffe1031b014
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3 0xfffe1031b018
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4 0xfffe1031b01c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5 0xfffe1031b020
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6 0xfffe1031b024
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR 0xfffe1031b028
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID 0xfffe1031b02c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR 0xfffe1031b030
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR 0xfffe1031b034
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE 0xfffe1031b03c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN 0xfffe1031b03d
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT 0xfffe1031b03e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY 0xfffe1031b03f
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST 0xfffe1031b064
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP 0xfffe1031b066
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP 0xfffe1031b068
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL 0xfffe1031b06c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS 0xfffe1031b06e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP 0xfffe1031b070
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL 0xfffe1031b074
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS 0xfffe1031b076
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2 0xfffe1031b088
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2 0xfffe1031b08c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2 0xfffe1031b08e
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2 0xfffe1031b090
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2 0xfffe1031b094
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2 0xfffe1031b096
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST 0xfffe1031b0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL 0xfffe1031b0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO 0xfffe1031b0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI 0xfffe1031b0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA 0xfffe1031b0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK 0xfffe1031b0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64 0xfffe1031b0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64 0xfffe1031b0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING 0xfffe1031b0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64 0xfffe1031b0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST 0xfffe1031b0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL 0xfffe1031b0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE 0xfffe1031b0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA 0xfffe1031b0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031b100
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031b104
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031b108
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031b10c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031b150
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031b154
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK 0xfffe1031b158
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031b15c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS 0xfffe1031b160
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK 0xfffe1031b164
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031b168
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0 0xfffe1031b16c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1 0xfffe1031b170
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2 0xfffe1031b174
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3 0xfffe1031b178
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031b188
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031b18c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031b190
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031b194
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031b2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP 0xfffe1031b2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL 0xfffe1031b2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031b328
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP 0xfffe1031b32c
+#define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL 0xfffe1031b32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
+// base address: 0xfffe1031c000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID 0xfffe1031c000
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID 0xfffe1031c002
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_COMMAND 0xfffe1031c004
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_STATUS 0xfffe1031c006
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID 0xfffe1031c008
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE 0xfffe1031c009
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS 0xfffe1031c00a
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS 0xfffe1031c00b
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE 0xfffe1031c00c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LATENCY 0xfffe1031c00d
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_HEADER 0xfffe1031c00e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BIST 0xfffe1031c00f
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1 0xfffe1031c010
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2 0xfffe1031c014
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3 0xfffe1031c018
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4 0xfffe1031c01c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5 0xfffe1031c020
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6 0xfffe1031c024
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR 0xfffe1031c028
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID 0xfffe1031c02c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR 0xfffe1031c030
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR 0xfffe1031c034
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE 0xfffe1031c03c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN 0xfffe1031c03d
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT 0xfffe1031c03e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY 0xfffe1031c03f
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST 0xfffe1031c064
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP 0xfffe1031c066
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP 0xfffe1031c068
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL 0xfffe1031c06c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS 0xfffe1031c06e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP 0xfffe1031c070
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL 0xfffe1031c074
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS 0xfffe1031c076
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2 0xfffe1031c088
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2 0xfffe1031c08c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2 0xfffe1031c08e
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2 0xfffe1031c090
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2 0xfffe1031c094
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2 0xfffe1031c096
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST 0xfffe1031c0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL 0xfffe1031c0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO 0xfffe1031c0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI 0xfffe1031c0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA 0xfffe1031c0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK 0xfffe1031c0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64 0xfffe1031c0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64 0xfffe1031c0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING 0xfffe1031c0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64 0xfffe1031c0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST 0xfffe1031c0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL 0xfffe1031c0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE 0xfffe1031c0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA 0xfffe1031c0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031c100
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031c104
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031c108
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031c10c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031c150
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031c154
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK 0xfffe1031c158
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031c15c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS 0xfffe1031c160
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK 0xfffe1031c164
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031c168
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0 0xfffe1031c16c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1 0xfffe1031c170
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2 0xfffe1031c174
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3 0xfffe1031c178
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031c188
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031c18c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031c190
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031c194
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031c2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP 0xfffe1031c2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL 0xfffe1031c2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031c328
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP 0xfffe1031c32c
+#define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL 0xfffe1031c32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
+// base address: 0xfffe1031d000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID 0xfffe1031d000
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID 0xfffe1031d002
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_COMMAND 0xfffe1031d004
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_STATUS 0xfffe1031d006
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID 0xfffe1031d008
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE 0xfffe1031d009
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS 0xfffe1031d00a
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS 0xfffe1031d00b
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE 0xfffe1031d00c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LATENCY 0xfffe1031d00d
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_HEADER 0xfffe1031d00e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BIST 0xfffe1031d00f
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1 0xfffe1031d010
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2 0xfffe1031d014
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3 0xfffe1031d018
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4 0xfffe1031d01c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5 0xfffe1031d020
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6 0xfffe1031d024
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR 0xfffe1031d028
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID 0xfffe1031d02c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR 0xfffe1031d030
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR 0xfffe1031d034
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE 0xfffe1031d03c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN 0xfffe1031d03d
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT 0xfffe1031d03e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY 0xfffe1031d03f
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST 0xfffe1031d064
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP 0xfffe1031d066
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP 0xfffe1031d068
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL 0xfffe1031d06c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS 0xfffe1031d06e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP 0xfffe1031d070
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL 0xfffe1031d074
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS 0xfffe1031d076
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2 0xfffe1031d088
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2 0xfffe1031d08c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2 0xfffe1031d08e
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2 0xfffe1031d090
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2 0xfffe1031d094
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2 0xfffe1031d096
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST 0xfffe1031d0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL 0xfffe1031d0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO 0xfffe1031d0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI 0xfffe1031d0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA 0xfffe1031d0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK 0xfffe1031d0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64 0xfffe1031d0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64 0xfffe1031d0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING 0xfffe1031d0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64 0xfffe1031d0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST 0xfffe1031d0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL 0xfffe1031d0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE 0xfffe1031d0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA 0xfffe1031d0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031d100
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031d104
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031d108
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031d10c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031d150
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031d154
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK 0xfffe1031d158
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031d15c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS 0xfffe1031d160
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK 0xfffe1031d164
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031d168
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0 0xfffe1031d16c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1 0xfffe1031d170
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2 0xfffe1031d174
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3 0xfffe1031d178
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031d188
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031d18c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031d190
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031d194
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031d2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP 0xfffe1031d2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL 0xfffe1031d2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031d328
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP 0xfffe1031d32c
+#define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL 0xfffe1031d32e
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
+// base address: 0xfffe1031e000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID 0xfffe1031e000
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID 0xfffe1031e002
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_COMMAND 0xfffe1031e004
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_STATUS 0xfffe1031e006
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID 0xfffe1031e008
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE 0xfffe1031e009
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS 0xfffe1031e00a
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS 0xfffe1031e00b
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE 0xfffe1031e00c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LATENCY 0xfffe1031e00d
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_HEADER 0xfffe1031e00e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BIST 0xfffe1031e00f
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1 0xfffe1031e010
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2 0xfffe1031e014
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3 0xfffe1031e018
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4 0xfffe1031e01c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5 0xfffe1031e020
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6 0xfffe1031e024
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR 0xfffe1031e028
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID 0xfffe1031e02c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR 0xfffe1031e030
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR 0xfffe1031e034
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE 0xfffe1031e03c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN 0xfffe1031e03d
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT 0xfffe1031e03e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY 0xfffe1031e03f
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST 0xfffe1031e064
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP 0xfffe1031e066
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP 0xfffe1031e068
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL 0xfffe1031e06c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS 0xfffe1031e06e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP 0xfffe1031e070
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL 0xfffe1031e074
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS 0xfffe1031e076
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2 0xfffe1031e088
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2 0xfffe1031e08c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2 0xfffe1031e08e
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2 0xfffe1031e090
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2 0xfffe1031e094
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2 0xfffe1031e096
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST 0xfffe1031e0a0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL 0xfffe1031e0a2
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO 0xfffe1031e0a4
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI 0xfffe1031e0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA 0xfffe1031e0a8
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK 0xfffe1031e0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64 0xfffe1031e0ac
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64 0xfffe1031e0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING 0xfffe1031e0b0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64 0xfffe1031e0b4
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST 0xfffe1031e0c0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL 0xfffe1031e0c2
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE 0xfffe1031e0c4
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA 0xfffe1031e0c8
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031e100
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031e104
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031e108
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031e10c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031e150
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031e154
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK 0xfffe1031e158
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031e15c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS 0xfffe1031e160
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK 0xfffe1031e164
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031e168
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0 0xfffe1031e16c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1 0xfffe1031e170
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2 0xfffe1031e174
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3 0xfffe1031e178
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031e188
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031e18c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031e190
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031e194
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031e2b0
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP 0xfffe1031e2b4
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL 0xfffe1031e2b6
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031e328
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP 0xfffe1031e32c
+#define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL 0xfffe1031e32e
+
+
+// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec
+// base address: 0xfffe30000000
+#define cfgSHADOW_COMMAND 0xfffe30000004
+#define cfgSHADOW_BASE_ADDR_1 0xfffe30000010
+#define cfgSHADOW_BASE_ADDR_2 0xfffe30000014
+#define cfgSHADOW_SUB_BUS_NUMBER_LATENCY 0xfffe30000018
+#define cfgSHADOW_IO_BASE_LIMIT 0xfffe3000001c
+#define cfgSHADOW_MEM_BASE_LIMIT 0xfffe30000020
+#define cfgSHADOW_PREF_BASE_LIMIT 0xfffe30000024
+#define cfgSHADOW_PREF_BASE_UPPER 0xfffe30000028
+#define cfgSHADOW_PREF_LIMIT_UPPER 0xfffe3000002c
+#define cfgSHADOW_IO_BASE_LIMIT_HI 0xfffe30000030
+#define cfgSHADOW_IRQ_BRIDGE_CNTL 0xfffe3000003e
+#define cfgSUC_INDEX 0xfffe300000e0
+#define cfgSUC_DATA 0xfffe300000e4
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+// base address: 0x30300000
+#define cfgBIF_BX_PF1_MM_INDEX 0x30300000
+#define cfgBIF_BX_PF1_MM_DATA 0x30300004
+#define cfgBIF_BX_PF1_MM_INDEX_HI 0x30300018
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+// base address: 0x30300000
+#define cfgSYSHUB_INDEX_OVLP 0x30300020
+#define cfgSYSHUB_DATA_OVLP 0x30300024
+#define cfgPCIE_INDEX 0x30300030
+#define cfgPCIE_DATA 0x30300034
+#define cfgPCIE_INDEX2 0x30300038
+#define cfgPCIE_DATA2 0x3030003c
+#define cfgSBIOS_SCRATCH_0 0x30300120
+#define cfgSBIOS_SCRATCH_1 0x30300124
+#define cfgSBIOS_SCRATCH_2 0x30300128
+#define cfgSBIOS_SCRATCH_3 0x3030012c
+#define cfgBIOS_SCRATCH_0 0x30300130
+#define cfgBIOS_SCRATCH_1 0x30300134
+#define cfgBIOS_SCRATCH_2 0x30300138
+#define cfgBIOS_SCRATCH_3 0x3030013c
+#define cfgBIOS_SCRATCH_4 0x30300140
+#define cfgBIOS_SCRATCH_5 0x30300144
+#define cfgBIOS_SCRATCH_6 0x30300148
+#define cfgBIOS_SCRATCH_7 0x3030014c
+#define cfgBIOS_SCRATCH_8 0x30300150
+#define cfgBIOS_SCRATCH_9 0x30300154
+#define cfgBIOS_SCRATCH_10 0x30300158
+#define cfgBIOS_SCRATCH_11 0x3030015c
+#define cfgBIOS_SCRATCH_12 0x30300160
+#define cfgBIOS_SCRATCH_13 0x30300164
+#define cfgBIOS_SCRATCH_14 0x30300168
+#define cfgBIOS_SCRATCH_15 0x3030016c
+#define cfgBIF_RLC_INTR_CNTL 0x30300180
+#define cfgBIF_VCE_INTR_CNTL 0x30300184
+#define cfgBIF_UVD_INTR_CNTL 0x30300188
+#define cfgGFX_MMIOREG_CAM_ADDR0 0x30300200
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR0 0x30300204
+#define cfgGFX_MMIOREG_CAM_ADDR1 0x30300208
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR1 0x3030020c
+#define cfgGFX_MMIOREG_CAM_ADDR2 0x30300210
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR2 0x30300214
+#define cfgGFX_MMIOREG_CAM_ADDR3 0x30300218
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR3 0x3030021c
+#define cfgGFX_MMIOREG_CAM_ADDR4 0x30300220
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR4 0x30300224
+#define cfgGFX_MMIOREG_CAM_ADDR5 0x30300228
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR5 0x3030022c
+#define cfgGFX_MMIOREG_CAM_ADDR6 0x30300230
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR6 0x30300234
+#define cfgGFX_MMIOREG_CAM_ADDR7 0x30300238
+#define cfgGFX_MMIOREG_CAM_REMAP_ADDR7 0x3030023c
+#define cfgGFX_MMIOREG_CAM_CNTL 0x30300240
+#define cfgGFX_MMIOREG_CAM_ZERO_CPL 0x30300244
+#define cfgGFX_MMIOREG_CAM_ONE_CPL 0x30300248
+#define cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x3030024c
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
+// base address: 0x30300000
+#define cfgSYSHUB_INDEX 0x30300020
+#define cfgSYSHUB_DATA 0x30300024
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+// base address: 0x30300000
+#define cfgRCC_BIF_STRAP0 0x30303480
+#define cfgRCC_BIF_STRAP1 0x30303484
+#define cfgRCC_BIF_STRAP2 0x30303488
+#define cfgRCC_BIF_STRAP3 0x3030348c
+#define cfgRCC_BIF_STRAP4 0x30303490
+#define cfgRCC_BIF_STRAP5 0x30303494
+#define cfgRCC_BIF_STRAP6 0x30303498
+#define cfgRCC_DEV0_PORT_STRAP0 0x3030349c
+#define cfgRCC_DEV0_PORT_STRAP1 0x303034a0
+#define cfgRCC_DEV0_PORT_STRAP2 0x303034a4
+#define cfgRCC_DEV0_PORT_STRAP3 0x303034a8
+#define cfgRCC_DEV0_PORT_STRAP4 0x303034ac
+#define cfgRCC_DEV0_PORT_STRAP5 0x303034b0
+#define cfgRCC_DEV0_PORT_STRAP6 0x303034b4
+#define cfgRCC_DEV0_PORT_STRAP7 0x303034b8
+#define cfgRCC_DEV0_PORT_STRAP8 0x303034bc
+#define cfgRCC_DEV0_PORT_STRAP9 0x303034c0
+#define cfgRCC_DEV0_EPF0_STRAP0 0x303034c4
+#define cfgRCC_DEV0_EPF0_STRAP1 0x303034c8
+#define cfgRCC_DEV0_EPF0_STRAP13 0x303034cc
+#define cfgRCC_DEV0_EPF0_STRAP2 0x303034d0
+#define cfgRCC_DEV0_EPF0_STRAP3 0x303034d4
+#define cfgRCC_DEV0_EPF0_STRAP4 0x303034d8
+#define cfgRCC_DEV0_EPF0_STRAP5 0x303034dc
+#define cfgRCC_DEV0_EPF0_STRAP8 0x303034e0
+#define cfgRCC_DEV0_EPF0_STRAP9 0x303034e4
+#define cfgRCC_DEV0_EPF1_STRAP0 0x303034e8
+#define cfgRCC_DEV0_EPF1_STRAP10 0x303034ec
+#define cfgRCC_DEV0_EPF1_STRAP11 0x303034f0
+#define cfgRCC_DEV0_EPF1_STRAP12 0x303034f4
+#define cfgRCC_DEV0_EPF1_STRAP13 0x303034f8
+#define cfgRCC_DEV0_EPF1_STRAP2 0x303034fc
+#define cfgRCC_DEV0_EPF1_STRAP3 0x30303500
+#define cfgRCC_DEV0_EPF1_STRAP4 0x30303504
+#define cfgRCC_DEV0_EPF1_STRAP5 0x30303508
+#define cfgRCC_DEV0_EPF1_STRAP6 0x3030350c
+#define cfgRCC_DEV0_EPF1_STRAP7 0x30303510
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+// base address: 0x30300000
+#define cfgEP_PCIE_SCRATCH 0x30303514
+#define cfgEP_PCIE_CNTL 0x3030351c
+#define cfgEP_PCIE_INT_CNTL 0x30303520
+#define cfgEP_PCIE_INT_STATUS 0x30303524
+#define cfgEP_PCIE_RX_CNTL2 0x30303528
+#define cfgEP_PCIE_BUS_CNTL 0x3030352c
+#define cfgEP_PCIE_CFG_CNTL 0x30303530
+#define cfgEP_PCIE_TX_LTR_CNTL 0x30303538
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x3030353c
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x3030353d
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x3030353e
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x3030353f
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x30303540
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x30303541
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x30303542
+#define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x30303543
+#define cfgEP_PCIE_STRAP_MISC 0x30303544
+#define cfgEP_PCIE_STRAP_MISC2 0x30303548
+#define cfgEP_PCIE_F0_DPA_CAP 0x30303550
+#define cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x30303554
+#define cfgEP_PCIE_F0_DPA_CNTL 0x30303555
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x30303557
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x30303558
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x30303559
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x3030355a
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x3030355b
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x3030355c
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x3030355d
+#define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x3030355e
+#define cfgEP_PCIE_PME_CONTROL 0x3030355f
+#define cfgEP_PCIEP_RESERVED 0x30303560
+#define cfgEP_PCIE_TX_CNTL 0x30303568
+#define cfgEP_PCIE_TX_REQUESTER_ID 0x3030356c
+#define cfgEP_PCIE_ERR_CNTL 0x30303570
+#define cfgEP_PCIE_RX_CNTL 0x30303574
+#define cfgEP_PCIE_LC_SPEED_CNTL 0x30303578
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+// base address: 0x30300000
+#define cfgDN_PCIE_RESERVED 0x30303580
+#define cfgDN_PCIE_SCRATCH 0x30303584
+#define cfgDN_PCIE_CNTL 0x3030358c
+#define cfgDN_PCIE_CONFIG_CNTL 0x30303590
+#define cfgDN_PCIE_RX_CNTL2 0x30303594
+#define cfgDN_PCIE_BUS_CNTL 0x30303598
+#define cfgDN_PCIE_CFG_CNTL 0x3030359c
+#define cfgDN_PCIE_STRAP_F0 0x303035a0
+#define cfgDN_PCIE_STRAP_MISC 0x303035a4
+#define cfgDN_PCIE_STRAP_MISC2 0x303035a8
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+// base address: 0x30300000
+#define cfgPCIE_ERR_CNTL 0x303035bc
+#define cfgPCIE_RX_CNTL 0x303035c0
+#define cfgPCIE_LC_SPEED_CNTL 0x303035c4
+#define cfgPCIE_LC_CNTL2 0x303035c8
+#define cfgPCIEP_STRAP_MISC 0x303035cc
+#define cfgLTR_MSG_INFO_FROM_EP 0x303035d0
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
+// base address: 0x30303480
+#define cfgRCC_DEV0_EPF0_RCC_ERR_LOG 0x30303694
+#define cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x30303780
+#define cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x3030378c
+#define cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x30303790
+#define cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x30303794
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+// base address: 0x30300000
+#define cfgRCC_ERR_INT_CNTL 0x30303698
+#define cfgRCC_BACO_CNTL_MISC 0x3030369c
+#define cfgRCC_RESET_EN 0x303036a0
+#define cfgRCC_VDM_SUPPORT 0x303036a4
+#define cfgRCC_MARGIN_PARAM_CNTL0 0x303036a8
+#define cfgRCC_MARGIN_PARAM_CNTL1 0x303036ac
+#define cfgRCC_GPUIOV_REGION 0x303036b0
+#define cfgRCC_PEER_REG_RANGE0 0x30303778
+#define cfgRCC_PEER_REG_RANGE1 0x3030377c
+#define cfgRCC_BUS_CNTL 0x30303784
+#define cfgRCC_CONFIG_CNTL 0x30303788
+#define cfgRCC_CONFIG_F0_BASE 0x30303798
+#define cfgRCC_CONFIG_APER_SIZE 0x3030379c
+#define cfgRCC_CONFIG_REG_APER_SIZE 0x303037a0
+#define cfgRCC_XDMA_LO 0x303037a4
+#define cfgRCC_XDMA_HI 0x303037a8
+#define cfgRCC_FEATURES_CONTROL_MISC 0x303037ac
+#define cfgRCC_BUSNUM_CNTL1 0x303037b0
+#define cfgRCC_BUSNUM_LIST0 0x303037b4
+#define cfgRCC_BUSNUM_LIST1 0x303037b8
+#define cfgRCC_BUSNUM_CNTL2 0x303037bc
+#define cfgRCC_CAPTURE_HOST_BUSNUM 0x303037c0
+#define cfgRCC_HOST_BUSNUM 0x303037c4
+#define cfgRCC_PEER0_FB_OFFSET_HI 0x303037c8
+#define cfgRCC_PEER0_FB_OFFSET_LO 0x303037cc
+#define cfgRCC_PEER1_FB_OFFSET_HI 0x303037d0
+#define cfgRCC_PEER1_FB_OFFSET_LO 0x303037d4
+#define cfgRCC_PEER2_FB_OFFSET_HI 0x303037d8
+#define cfgRCC_PEER2_FB_OFFSET_LO 0x303037dc
+#define cfgRCC_PEER3_FB_OFFSET_HI 0x303037e0
+#define cfgRCC_PEER3_FB_OFFSET_LO 0x303037e4
+#define cfgRCC_DEVFUNCNUM_LIST0 0x303037e8
+#define cfgRCC_DEVFUNCNUM_LIST1 0x303037ec
+#define cfgRCC_DEV0_LINK_CNTL 0x303037f4
+#define cfgRCC_CMN_LINK_CNTL 0x303037f8
+#define cfgRCC_EP_REQUESTERID_RESTORE 0x303037fc
+#define cfgRCC_LTR_LSWITCH_CNTL 0x30303800
+#define cfgRCC_MH_ARB_CNTL 0x30303804
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+// base address: 0x30300000
+#define cfgCC_BIF_BX_STRAP0 0x30303808
+#define cfgCC_BIF_BX_PINSTRAP0 0x30303810
+#define cfgBIF_MM_INDACCESS_CNTL 0x30303818
+#define cfgBUS_CNTL 0x3030381c
+#define cfgBIF_SCRATCH0 0x30303820
+#define cfgBIF_SCRATCH1 0x30303824
+#define cfgBX_RESET_EN 0x30303834
+#define cfgMM_CFGREGS_CNTL 0x30303838
+#define cfgBX_RESET_CNTL 0x30303840
+#define cfgINTERRUPT_CNTL 0x30303844
+#define cfgINTERRUPT_CNTL2 0x30303848
+#define cfgCLKREQB_PAD_CNTL 0x30303860
+#define cfgBIF_FEATURES_CONTROL_MISC 0x3030386c
+#define cfgBIF_DOORBELL_CNTL 0x30303870
+#define cfgBIF_DOORBELL_INT_CNTL 0x30303874
+#define cfgBIF_FB_EN 0x3030387c
+#define cfgBIF_INTR_CNTL 0x30303880
+#define cfgBIF_MST_TRANS_PENDING_VF 0x303038a4
+#define cfgBIF_SLV_TRANS_PENDING_VF 0x303038a8
+#define cfgBACO_CNTL 0x303038ac
+#define cfgBIF_BACO_EXIT_TIME0 0x303038b0
+#define cfgBIF_BACO_EXIT_TIMER1 0x303038b4
+#define cfgBIF_BACO_EXIT_TIMER2 0x303038b8
+#define cfgBIF_BACO_EXIT_TIMER3 0x303038bc
+#define cfgBIF_BACO_EXIT_TIMER4 0x303038c0
+#define cfgMEM_TYPE_CNTL 0x303038c4
+#define cfgNBIF_GFX_ADDR_LUT_CNTL 0x303038cc
+#define cfgNBIF_GFX_ADDR_LUT_0 0x303038d0
+#define cfgNBIF_GFX_ADDR_LUT_1 0x303038d4
+#define cfgNBIF_GFX_ADDR_LUT_2 0x303038d8
+#define cfgNBIF_GFX_ADDR_LUT_3 0x303038dc
+#define cfgNBIF_GFX_ADDR_LUT_4 0x303038e0
+#define cfgNBIF_GFX_ADDR_LUT_5 0x303038e4
+#define cfgNBIF_GFX_ADDR_LUT_6 0x303038e8
+#define cfgNBIF_GFX_ADDR_LUT_7 0x303038ec
+#define cfgNBIF_GFX_ADDR_LUT_8 0x303038f0
+#define cfgNBIF_GFX_ADDR_LUT_9 0x303038f4
+#define cfgNBIF_GFX_ADDR_LUT_10 0x303038f8
+#define cfgNBIF_GFX_ADDR_LUT_11 0x303038fc
+#define cfgNBIF_GFX_ADDR_LUT_12 0x30303900
+#define cfgNBIF_GFX_ADDR_LUT_13 0x30303904
+#define cfgNBIF_GFX_ADDR_LUT_14 0x30303908
+#define cfgNBIF_GFX_ADDR_LUT_15 0x3030390c
+#define cfgREMAP_HDP_MEM_FLUSH_CNTL 0x30303934
+#define cfgREMAP_HDP_REG_FLUSH_CNTL 0x30303938
+#define cfgBIF_RB_CNTL 0x3030393c
+#define cfgBIF_RB_BASE 0x30303940
+#define cfgBIF_RB_RPTR 0x30303944
+#define cfgBIF_RB_WPTR 0x30303948
+#define cfgBIF_RB_WPTR_ADDR_HI 0x3030394c
+#define cfgBIF_RB_WPTR_ADDR_LO 0x30303950
+#define cfgMAILBOX_INDEX 0x30303954
+#define cfgBIF_MP1_INTR_CTRL 0x30303988
+#define cfgBIF_UVD_GPUIOV_CFG_SIZE 0x3030398c
+#define cfgBIF_VCE_GPUIOV_CFG_SIZE 0x30303990
+#define cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x30303994
+#define cfgBIF_PERSTB_PAD_CNTL 0x303039a0
+#define cfgBIF_PX_EN_PAD_CNTL 0x303039a4
+#define cfgBIF_REFPADKIN_PAD_CNTL 0x303039a8
+#define cfgBIF_CLKREQB_PAD_CNTL 0x303039ac
+#define cfgBIF_PWRBRK_PAD_CNTL 0x303039b0
+#define cfgBIF_WAKEB_PAD_CNTL 0x303039b4
+#define cfgBIF_VAUX_PRESENT_PAD_CNTL 0x303039b8
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+// base address: 0x30300000
+#define cfgBIF_BX_PF_BIF_BME_STATUS 0x3030382c
+#define cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG 0x30303830
+#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x3030384c
+#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x30303850
+#define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL 0x30303854
+#define cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL 0x30303858
+#define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL 0x3030385c
+#define cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ 0x30303898
+#define cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE 0x3030389c
+#define cfgBIF_BX_PF_BIF_TRANS_PENDING 0x303038a0
+#define cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS 0x303038c8
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 0x30303958
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 0x3030395c
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 0x30303960
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x30303964
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 0x30303968
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 0x3030396c
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 0x30303970
+#define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 0x30303974
+#define cfgBIF_BX_PF_MAILBOX_CONTROL 0x30303978
+#define cfgBIF_BX_PF_MAILBOX_INT_CNTL 0x3030397c
+#define cfgBIF_BX_PF_BIF_VMHV_MAILBOX 0x30303980
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+// base address: 0x30300000
+#define cfgA2S_CNTL_CL0 0x30303ac0
+#define cfgA2S_CNTL_CL1 0x30303ac4
+#define cfgA2S_CNTL3_CL0 0x30303b00
+#define cfgA2S_CNTL3_CL1 0x30303b04
+#define cfgA2S_CNTL_SW0 0x30303b40
+#define cfgA2S_CNTL_SW1 0x30303b44
+#define cfgA2S_CNTL_SW2 0x30303b48
+#define cfgA2S_CPLBUF_ALLOC_CNTL 0x30303b70
+#define cfgA2S_TAG_ALLOC_0 0x30303b74
+#define cfgA2S_TAG_ALLOC_1 0x30303b78
+#define cfgA2S_MISC_CNTL 0x30303b84
+#define cfgNGDC_SDP_PORT_CTRL 0x30303b88
+#define cfgSHUB_REGS_IF_CTL 0x30303b8c
+#define cfgNGDC_MGCG_CTRL 0x30303ba8
+#define cfgNGDC_RESERVED_0 0x30303bac
+#define cfgNGDC_RESERVED_1 0x30303bb0
+#define cfgNGDC_SDP_PORT_CTRL_SOCCLK 0x30303bb4
+#define cfgBIF_SDMA0_DOORBELL_RANGE 0x30303bc0
+#define cfgBIF_SDMA1_DOORBELL_RANGE 0x30303bc4
+#define cfgBIF_IH_DOORBELL_RANGE 0x30303bc8
+#define cfgBIF_MMSCH0_DOORBELL_RANGE 0x30303bcc
+#define cfgBIF_ACV_DOORBELL_RANGE 0x30303bd0
+#define cfgBIF_DOORBELL_FENCE_CNTL 0x30303bf8
+#define cfgS2A_MISC_CNTL 0x30303bfc
+#define cfgNGDC_PG_MISC_CTRL 0x30303c40
+#define cfgNGDC_PGMST_CTRL 0x30303c44
+#define cfgNGDC_PGSLV_CTRL 0x30303c48
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+// base address: 0x30300000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x30342000
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x30342004
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x30342008
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x3034200c
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x30342010
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x30342014
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x30342018
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x3034201c
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x30342020
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x30342024
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x30342028
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x3034202c
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x30342030
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x30342034
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x30342038
+#define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x3034203c
+#define cfgRCC_DEV0_EPF0_GFXMSIX_PBA 0x30343000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h
new file mode 100644
index 000000000000..198c14a3b3d3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h
@@ -0,0 +1,120339 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_2_3_SH_MASK_HEADER
+#define _nbio_2_3_SH_MASK_HEADER
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF_MM_INDEX
+#define BIF_BX_PF_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF_MM_DATA
+#define BIF_BX_PF_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF_MM_INDEX_HI
+#define BIF_BX_PF_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+//SYSHUB_INDEX_OVLP
+#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0
+#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL
+//SYSHUB_DATA_OVLP
+#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0
+#define SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL
+//PCIE_INDEX
+#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//PCIE_DATA
+#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//PCIE_INDEX2
+#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//PCIE_DATA2
+#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_0
+#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_1
+#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_2
+#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//SBIOS_SCRATCH_3
+#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_0
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_1
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_2
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_3
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_4
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_5
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_6
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_7
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_8
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_9
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_10
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_11
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_12
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_13
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_14
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIOS_SCRATCH_15
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_RLC_INTR_CNTL
+#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_VCE_INTR_CNTL
+#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_UVD_INTR_CNTL
+#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT 0x1c
+#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L
+#define BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK 0xF0000000L
+//GFX_MMIOREG_CAM_ADDR0
+#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR0
+#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR1
+#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR1
+#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR2
+#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR2
+#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR3
+#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR3
+#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR4
+#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR4
+#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR5
+#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR5
+#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR6
+#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR6
+#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_ADDR7
+#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_REMAP_ADDR7
+#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//GFX_MMIOREG_CAM_CNTL
+#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//GFX_MMIOREG_CAM_ZERO_CPL
+#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//GFX_MMIOREG_CAM_ONE_CPL
+#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
+//SYSHUB_INDEX
+#define SYSHUB_INDEX__INDEX__SHIFT 0x0
+#define SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL
+//SYSHUB_DATA
+#define SYSHUB_DATA__DATA__SHIFT 0x0
+#define SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_BIF_STRAP0
+#define RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0
+#define RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT 0x1
+#define RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6
+#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12
+#define RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L
+#define RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK 0x00000002L
+#define RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L
+#define RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L
+#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L
+#define RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_BIF_STRAP1
+#define RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0
+#define RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2
+#define RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT 0x4
+#define RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18
+#define RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19
+#define RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L
+#define RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L
+#define RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK 0x00000010L
+#define RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L
+#define RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L
+#define RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+//RCC_BIF_STRAP2
+#define RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xc
+#define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00003000L
+#define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+//RCC_BIF_STRAP3
+#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_BIF_STRAP4
+#define RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_BIF_STRAP5
+#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+//RCC_BIF_STRAP6
+#define RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT 0x0
+#define RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK 0xFFFFFFFFL
+//RCC_DEV0_PORT_STRAP0
+#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
+#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
+#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
+#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
+#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
+#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L
+#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L
+#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L
+#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_DEV0_PORT_STRAP1
+#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_DEV0_PORT_STRAP2
+#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
+#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12
+#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L
+#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_DEV0_PORT_STRAP3
+#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e
+#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK 0x40000000L
+#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_DEV0_PORT_STRAP4
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_DEV0_PORT_STRAP5
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_DEV0_PORT_STRAP6
+#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2
+#define RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L
+#define RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+//RCC_DEV0_PORT_STRAP7
+#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_DEV0_PORT_STRAP8
+#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_DEV0_PORT_STRAP9
+#define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+//RCC_DEV0_EPF0_STRAP0
+#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_DEV0_EPF0_STRAP1
+#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_DEV0_EPF0_STRAP13
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+//RCC_DEV0_EPF0_STRAP2
+#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
+#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL
+#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_DEV0_EPF0_STRAP3
+#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
+#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19
+#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK 0x02000000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+//RCC_DEV0_EPF0_STRAP4
+#define RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_DEV0_EPF0_STRAP5
+#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_DEV0_EPF0_STRAP8
+#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4
+#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5
+#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xf
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x11
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x18
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00000010L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00000060L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x00006000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00018000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x000E0000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00F00000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03000000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_DEV0_EPF0_STRAP9
+#define RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+//RCC_DEV0_EPF1_STRAP0
+#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_DEV0_EPF1_STRAP10
+#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL
+//RCC_DEV0_EPF1_STRAP11
+#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL
+//RCC_DEV0_EPF1_STRAP12
+#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL
+//RCC_DEV0_EPF1_STRAP13
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L
+#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L
+//RCC_DEV0_EPF1_STRAP2
+#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_DEV0_EPF1_STRAP3
+#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
+#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19
+#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK 0x02000000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+//RCC_DEV0_EPF1_STRAP4
+#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_DEV0_EPF1_STRAP5
+#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+//RCC_DEV0_EPF1_STRAP6
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK 0x00000070L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L
+#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L
+//RCC_DEV0_EPF1_STRAP7
+#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0
+#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1__SHIFT 0x14
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1__SHIFT 0x16
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1__SHIFT 0x17
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1__SHIFT 0x18
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1__SHIFT 0x1a
+#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK 0x0000001EL
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1_MASK 0x00300000L
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1_MASK 0x00800000L
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1_MASK 0x03000000L
+#define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1_MASK 0xFC000000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+//EP_PCIE_SCRATCH
+#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//EP_PCIE_CNTL
+#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//EP_PCIE_INT_CNTL
+#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//EP_PCIE_INT_STATUS
+#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//EP_PCIE_RX_CNTL2
+#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//EP_PCIE_BUS_CNTL
+#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//EP_PCIE_CFG_CNTL
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//EP_PCIE_TX_LTR_CNTL
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//EP_PCIE_STRAP_MISC
+#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//EP_PCIE_STRAP_MISC2
+#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//EP_PCIE_F0_DPA_CAP
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//EP_PCIE_F0_DPA_CNTL
+#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//EP_PCIE_PME_CONTROL
+#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//EP_PCIEP_RESERVED
+#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//EP_PCIE_TX_CNTL
+#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//EP_PCIE_TX_REQUESTER_ID
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//EP_PCIE_ERR_CNTL
+#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//EP_PCIE_RX_CNTL
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//EP_PCIE_LC_SPEED_CNTL
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+//DN_PCIE_RESERVED
+#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//DN_PCIE_SCRATCH
+#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//DN_PCIE_CNTL
+#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//DN_PCIE_CONFIG_CNTL
+#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//DN_PCIE_RX_CNTL2
+#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//DN_PCIE_BUS_CNTL
+#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//DN_PCIE_CFG_CNTL
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//DN_PCIE_STRAP_F0
+#define DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//DN_PCIE_STRAP_MISC
+#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//DN_PCIE_STRAP_MISC2
+#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+//PCIE_ERR_CNTL
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//PCIE_RX_CNTL
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//PCIE_LC_SPEED_CNTL
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+//PCIE_LC_CNTL2
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//PCIEP_STRAP_MISC
+#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//LTR_MSG_INFO_FROM_EP
+#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
+//RCC_DEV0_EPF0_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+//RCC_ERR_INT_CNTL
+#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0
+#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L
+//RCC_BACO_CNTL_MISC
+#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L
+#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L
+//RCC_RESET_EN
+#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+#define RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L
+//RCC_VDM_SUPPORT
+#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_MARGIN_PARAM_CNTL0
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_MARGIN_PARAM_CNTL1
+#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+//RCC_GPUIOV_REGION
+#define RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define RCC_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define RCC_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//RCC_PEER_REG_RANGE0
+#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL
+#define RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L
+//RCC_PEER_REG_RANGE1
+#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL
+#define RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L
+//RCC_BUS_CNTL
+#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_CONFIG_CNTL
+#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L
+#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L
+#define RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L
+//RCC_CONFIG_F0_BASE
+#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL
+//RCC_CONFIG_APER_SIZE
+#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL
+//RCC_CONFIG_REG_APER_SIZE
+#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000FFFFFL
+//RCC_XDMA_LO
+#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL
+#define RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L
+//RCC_XDMA_HI
+#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL
+//RCC_FEATURES_CONTROL_MISC
+#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
+#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L
+#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L
+#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L
+#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_BUSNUM_CNTL1
+#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL
+//RCC_BUSNUM_LIST0
+#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL
+#define RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L
+#define RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L
+#define RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L
+//RCC_BUSNUM_LIST1
+#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL
+#define RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L
+#define RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L
+#define RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L
+//RCC_BUSNUM_CNTL2
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL
+#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
+#define RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
+#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
+//RCC_CAPTURE_HOST_BUSNUM
+#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L
+//RCC_HOST_BUSNUM
+#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL
+//RCC_PEER0_FB_OFFSET_HI
+#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER0_FB_OFFSET_LO
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L
+//RCC_PEER1_FB_OFFSET_HI
+#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER1_FB_OFFSET_LO
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L
+//RCC_PEER2_FB_OFFSET_HI
+#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER2_FB_OFFSET_LO
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L
+//RCC_PEER3_FB_OFFSET_HI
+#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_PEER3_FB_OFFSET_LO
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L
+//RCC_DEVFUNCNUM_LIST0
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L
+#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L
+//RCC_DEVFUNCNUM_LIST1
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L
+#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L
+//RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+//RCC_CMN_LINK_CNTL
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_EP_REQUESTERID_RESTORE
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_LTR_LSWITCH_CNTL
+#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_MH_ARB_CNTL
+#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+//CC_BIF_BX_STRAP0
+#define CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19
+#define CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L
+//CC_BIF_BX_PINSTRAP0
+//BIF_MM_INDACCESS_CNTL
+#define BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BUS_CNTL
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a
+#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L
+#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_SCRATCH0
+#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_SCRATCH1
+#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BX_RESET_EN
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//MM_CFGREGS_CNTL
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BX_RESET_CNTL
+#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//INTERRUPT_CNTL
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+#define INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L
+//INTERRUPT_CNTL2
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//CLKREQB_PAD_CNTL
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_FEATURES_CONTROL_MISC
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10
+#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x00FF0000L
+#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L
+//BIF_DOORBELL_CNTL
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_DOORBELL_INT_CNTL
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
+#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19
+#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a
+#define BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c
+#define BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d
+#define BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L
+#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L
+#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
+#define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L
+#define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L
+#define BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L
+#define BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L
+#define BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L
+//BIF_FB_EN
+#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_INTR_CNTL
+#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0
+#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L
+//BIF_MST_TRANS_PENDING_VF
+#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_SLV_TRANS_PENDING_VF
+#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BACO_CNTL
+#define BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10
+#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+#define BACO_CNTL__BACO_EN_MASK 0x00000001L
+#define BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L
+#define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
+#define BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L
+#define BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L
+#define BACO_CNTL__BACO_MODE_MASK 0x00000100L
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L
+#define BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L
+#define BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L
+//BIF_BACO_EXIT_TIME0
+#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER1
+#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L
+#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L
+#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L
+#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L
+#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L
+//BIF_BACO_EXIT_TIMER2
+#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER3
+#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BACO_EXIT_TIMER4
+#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL
+//MEM_TYPE_CNTL
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//NBIF_GFX_ADDR_LUT_CNTL
+#define NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1
+#define NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L
+#define NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L
+//NBIF_GFX_ADDR_LUT_0
+#define NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_1
+#define NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_2
+#define NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_3
+#define NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_4
+#define NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_5
+#define NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_6
+#define NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_7
+#define NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_8
+#define NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_9
+#define NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_10
+#define NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_11
+#define NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_12
+#define NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_13
+#define NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_14
+#define NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL
+//NBIF_GFX_ADDR_LUT_15
+#define NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL
+//REMAP_HDP_MEM_FLUSH_CNTL
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//REMAP_HDP_REG_FLUSH_CNTL
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_RB_CNTL
+#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a
+#define BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d
+#define BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L
+#define BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L
+#define BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_RB_BASE
+#define BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_RB_RPTR
+#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_RB_WPTR
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_RB_WPTR_ADDR_HI
+#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_RB_WPTR_ADDR_LO
+#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//MAILBOX_INDEX
+#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_MP1_INTR_CTRL
+#define BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0
+#define BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L
+//BIF_UVD_GPUIOV_CFG_SIZE
+#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_VCE_GPUIOV_CFG_SIZE
+#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_PERSTB_PAD_CNTL
+#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_PX_EN_PAD_CNTL
+#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL
+//BIF_REFPADKIN_PAD_CNTL
+#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_CLKREQB_PAD_CNTL
+#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL
+//BIF_PWRBRK_PAD_CNTL
+#define BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0
+#define BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL
+//BIF_WAKEB_PAD_CNTL
+#define BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT 0x0
+#define BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT 0x1
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT 0x2
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT 0x3
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT 0x4
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT 0x5
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT 0x6
+#define BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT 0x7
+#define BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK 0x00000001L
+#define BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK 0x00000002L
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK 0x00000004L
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK 0x00000008L
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK 0x00000010L
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK 0x00000020L
+#define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK 0x00000040L
+#define BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK 0x00000080L
+//BIF_VAUX_PRESENT_PAD_CNTL
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT 0x0
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT 0x1
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT 0x2
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT 0x3
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT 0x4
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT 0x5
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK 0x00000001L
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK 0x00000002L
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK 0x00000004L
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK 0x00000008L
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK 0x00000010L
+#define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK 0x00000020L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF_BIF_BME_STATUS
+#define BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_PF_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_PF_BIF_TRANS_PENDING
+#define BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF_MAILBOX_CONTROL
+#define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_PF_MAILBOX_INT_CNTL
+#define BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_PF_BIF_VMHV_MAILBOX
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+//A2S_CNTL_CL0
+#define A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0
+#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2
+#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4
+#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
+#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
+#define A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa
+#define A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc
+#define A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe
+#define A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10
+#define A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12
+#define A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14
+#define A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT 0x16
+#define A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT 0x18
+#define A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L
+#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL
+#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L
+#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L
+#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L
+#define A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L
+#define A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L
+#define A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L
+#define A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L
+#define A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L
+#define A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L
+#define A2S_CNTL_CL0__RDRSP_ERRMAP_MASK 0x00C00000L
+#define A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK 0x07000000L
+//A2S_CNTL_CL1
+#define A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0
+#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2
+#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4
+#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
+#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
+#define A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa
+#define A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc
+#define A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe
+#define A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10
+#define A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12
+#define A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14
+#define A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT 0x16
+#define A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT 0x18
+#define A2S_CNTL_CL1__NSNOOP_MAP_MASK 0x00000003L
+#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK 0x0000000CL
+#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK 0x00000030L
+#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L
+#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L
+#define A2S_CNTL_CL1__BLKLVL_MAP_MASK 0x00000C00L
+#define A2S_CNTL_CL1__DATERR_MAP_MASK 0x00003000L
+#define A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK 0x0000C000L
+#define A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK 0x00030000L
+#define A2S_CNTL_CL1__RESP_WR_MAP_MASK 0x000C0000L
+#define A2S_CNTL_CL1__RESP_RD_MAP_MASK 0x00300000L
+#define A2S_CNTL_CL1__RDRSP_ERRMAP_MASK 0x00C00000L
+#define A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK 0x07000000L
+//A2S_CNTL3_CL0
+#define A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT 0x0
+#define A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT 0x2
+#define A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT 0x3
+#define A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT 0x4
+#define A2S_CNTL3_CL0__FORCE_WR_PH_MASK 0x00000003L
+#define A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK 0x00000004L
+#define A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK 0x00000008L
+#define A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK 0x000003F0L
+//A2S_CNTL3_CL1
+#define A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT 0x0
+#define A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT 0x2
+#define A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT 0x3
+#define A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT 0x4
+#define A2S_CNTL3_CL1__FORCE_WR_PH_MASK 0x00000003L
+#define A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK 0x00000004L
+#define A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK 0x00000008L
+#define A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK 0x000003F0L
+//A2S_CNTL_SW0
+#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10
+#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18
+#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L
+#define A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L
+#define A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L
+//A2S_CNTL_SW1
+#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10
+#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18
+#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L
+#define A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00FF0000L
+#define A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xFF000000L
+//A2S_CNTL_SW2
+#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10
+#define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18
+#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK 0x00000200L
+#define A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK 0x00FF0000L
+#define A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK 0xFF000000L
+//A2S_CPLBUF_ALLOC_CNTL
+#define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD__SHIFT 0x0
+#define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD__SHIFT 0x14
+#define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD__SHIFT 0x18
+#define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD__SHIFT 0x1c
+#define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD_MASK 0x0000000FL
+#define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD_MASK 0x00F00000L
+#define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD_MASK 0x0F000000L
+#define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD_MASK 0xF0000000L
+//A2S_TAG_ALLOC_0
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L
+//A2S_TAG_ALLOC_1
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L
+//A2S_MISC_CNTL
+#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0
+#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2
+#define A2S_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x3
+#define A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4
+#define A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5
+#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6
+#define A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7
+#define A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8
+#define A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9
+#define A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa
+#define A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10
+#define A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15
+#define A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L
+#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L
+#define A2S_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000008L
+#define A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L
+#define A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L
+#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L
+#define A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L
+#define A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L
+#define A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L
+#define A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L
+#define A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L
+#define A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L
+//NGDC_SDP_PORT_CTRL
+#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+//SHUB_REGS_IF_CTL
+#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//NGDC_MGCG_CTRL
+#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0
+#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1
+#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2
+#define NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa
+#define NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb
+#define NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc
+#define NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd
+#define NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L
+#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L
+#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL
+#define NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L
+#define NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L
+#define NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L
+#define NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L
+//NGDC_RESERVED_0
+#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0
+#define NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL
+//NGDC_RESERVED_1
+#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0
+#define NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL
+//NGDC_SDP_PORT_CTRL_SOCCLK
+#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0
+#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x000000FFL
+//BIF_SDMA0_DOORBELL_RANGE
+#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_SDMA1_DOORBELL_RANGE
+#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_IH_DOORBELL_RANGE
+#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_MMSCH0_DOORBELL_RANGE
+#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_ACV_DOORBELL_RANGE
+#define BIF_ACV_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define BIF_ACV_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define BIF_ACV_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define BIF_ACV_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//BIF_DOORBELL_FENCE_CNTL
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT 0x0
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT 0x1
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT 0x2
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ACV_ENABLE__SHIFT 0x3
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x10
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK 0x00000001L
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK 0x00000002L
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK 0x00000004L
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ACV_ENABLE_MASK 0x00000008L
+#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00010000L
+//S2A_MISC_CNTL
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
+#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_ACV_DIS__SHIFT 0x4
+#define S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8
+#define S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa
+#define S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc
+#define S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L
+#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L
+#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_ACV_DIS_MASK 0x00000010L
+#define S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L
+#define S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L
+#define S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L
+#define S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L
+//NGDC_PG_MISC_CTRL
+#define NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa
+#define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0xb
+#define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0xc
+#define NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM__SHIFT 0xd
+#define NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe
+#define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0xf
+#define NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18
+#define NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f
+#define NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L
+#define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000800L
+#define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00001000L
+#define NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM_MASK 0x00002000L
+#define NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L
+#define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00008000L
+#define NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L
+#define NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L
+//NGDC_PGMST_CTRL
+#define NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0
+#define NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8
+#define NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L
+#define NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//NGDC_PGSLV_CTRL
+#define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0
+#define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5
+#define NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa
+#define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L
+#define NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp
+//PSWUSCFG0_0_VENDOR_ID
+#define PSWUSCFG0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//PSWUSCFG0_0_DEVICE_ID
+#define PSWUSCFG0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define PSWUSCFG0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//PSWUSCFG0_0_COMMAND
+#define PSWUSCFG0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define PSWUSCFG0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define PSWUSCFG0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define PSWUSCFG0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define PSWUSCFG0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define PSWUSCFG0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define PSWUSCFG0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define PSWUSCFG0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define PSWUSCFG0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define PSWUSCFG0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define PSWUSCFG0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define PSWUSCFG0_0_COMMAND__INT_DIS_MASK 0x0400L
+//PSWUSCFG0_0_STATUS
+#define PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define PSWUSCFG0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define PSWUSCFG0_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define PSWUSCFG0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define PSWUSCFG0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define PSWUSCFG0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define PSWUSCFG0_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define PSWUSCFG0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//PSWUSCFG0_0_REVISION_ID
+#define PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//PSWUSCFG0_0_PROG_INTERFACE
+#define PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//PSWUSCFG0_0_SUB_CLASS
+#define PSWUSCFG0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define PSWUSCFG0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//PSWUSCFG0_0_BASE_CLASS
+#define PSWUSCFG0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define PSWUSCFG0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//PSWUSCFG0_0_CACHE_LINE
+#define PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//PSWUSCFG0_0_LATENCY
+#define PSWUSCFG0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define PSWUSCFG0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//PSWUSCFG0_0_HEADER
+#define PSWUSCFG0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define PSWUSCFG0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define PSWUSCFG0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define PSWUSCFG0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//PSWUSCFG0_0_BIST
+#define PSWUSCFG0_0_BIST__BIST_COMP__SHIFT 0x0
+#define PSWUSCFG0_0_BIST__BIST_STRT__SHIFT 0x6
+#define PSWUSCFG0_0_BIST__BIST_CAP__SHIFT 0x7
+#define PSWUSCFG0_0_BIST__BIST_COMP_MASK 0x0FL
+#define PSWUSCFG0_0_BIST__BIST_STRT_MASK 0x40L
+#define PSWUSCFG0_0_BIST__BIST_CAP_MASK 0x80L
+//PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY
+#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//PSWUSCFG0_0_IO_BASE_LIMIT
+#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//PSWUSCFG0_0_SECONDARY_STATUS
+#define PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//PSWUSCFG0_0_MEM_BASE_LIMIT
+#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//PSWUSCFG0_0_PREF_BASE_LIMIT
+#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//PSWUSCFG0_0_PREF_BASE_UPPER
+#define PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PREF_LIMIT_UPPER
+#define PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_IO_BASE_LIMIT_HI
+#define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//PSWUSCFG0_0_CAP_PTR
+#define PSWUSCFG0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define PSWUSCFG0_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//PSWUSCFG0_0_ROM_BASE_ADDR
+#define PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_INTERRUPT_LINE
+#define PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//PSWUSCFG0_0_INTERRUPT_PIN
+#define PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//PSWUSCFG0_0_IRQ_BRIDGE_CNTL
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//PSWUSCFG0_0_EXT_BRIDGE_CNTL
+#define PSWUSCFG0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define PSWUSCFG0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//PSWUSCFG0_0_VENDOR_CAP_LIST
+#define PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//PSWUSCFG0_0_ADAPTER_ID_W
+#define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//PSWUSCFG0_0_PMI_CAP_LIST
+#define PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_0_PMI_CAP
+#define PSWUSCFG0_0_PMI_CAP__VERSION__SHIFT 0x0
+#define PSWUSCFG0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define PSWUSCFG0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define PSWUSCFG0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define PSWUSCFG0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define PSWUSCFG0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define PSWUSCFG0_0_PMI_CAP__VERSION_MASK 0x0007L
+#define PSWUSCFG0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define PSWUSCFG0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define PSWUSCFG0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define PSWUSCFG0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define PSWUSCFG0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//PSWUSCFG0_0_PMI_STATUS_CNTL
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//PSWUSCFG0_0_PCIE_CAP_LIST
+#define PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_0_PCIE_CAP
+#define PSWUSCFG0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//PSWUSCFG0_0_DEVICE_CAP
+#define PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//PSWUSCFG0_0_DEVICE_CNTL
+#define PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//PSWUSCFG0_0_DEVICE_STATUS
+#define PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//PSWUSCFG0_0_LINK_CAP
+#define PSWUSCFG0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define PSWUSCFG0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define PSWUSCFG0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define PSWUSCFG0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define PSWUSCFG0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define PSWUSCFG0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define PSWUSCFG0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define PSWUSCFG0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//PSWUSCFG0_0_LINK_CNTL
+#define PSWUSCFG0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define PSWUSCFG0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define PSWUSCFG0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define PSWUSCFG0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//PSWUSCFG0_0_LINK_STATUS
+#define PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//PSWUSCFG0_0_DEVICE_CAP2
+#define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//PSWUSCFG0_0_DEVICE_CNTL2
+#define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//PSWUSCFG0_0_DEVICE_STATUS2
+#define PSWUSCFG0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define PSWUSCFG0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//PSWUSCFG0_0_LINK_CAP2
+#define PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//PSWUSCFG0_0_LINK_CNTL2
+#define PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//PSWUSCFG0_0_LINK_STATUS2
+#define PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//PSWUSCFG0_0_MSI_CAP_LIST
+#define PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_0_MSI_MSG_CNTL
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//PSWUSCFG0_0_MSI_MSG_ADDR_LO
+#define PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PSWUSCFG0_0_MSI_MSG_ADDR_HI
+#define PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_MSI_MSG_DATA
+#define PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//PSWUSCFG0_0_MSI_MSG_DATA_64
+#define PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//PSWUSCFG0_0_SSID_CAP_LIST
+#define PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_0_SSID_CAP
+#define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//PSWUSCFG0_0_MSI_MAP_CAP_LIST
+#define PSWUSCFG0_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_0_MSI_MAP_CAP
+#define PSWUSCFG0_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define PSWUSCFG0_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define PSWUSCFG0_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define PSWUSCFG0_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define PSWUSCFG0_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define PSWUSCFG0_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PSWUSCFG0_0_PCIE_PORT_VC_CNTL
+#define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//PSWUSCFG0_0_PCIE_PORT_VC_STATUS
+#define PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//PSWUSCFG0_0_PCIE_CORR_ERR_STATUS
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//PSWUSCFG0_0_PCIE_CORR_ERR_MASK
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//PSWUSCFG0_0_PCIE_HDR_LOG0
+#define PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_HDR_LOG1
+#define PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_HDR_LOG2
+#define PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_HDR_LOG3
+#define PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0
+#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1
+#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2
+#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3
+#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_LINK_CNTL3
+#define PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS
+#define PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_ACS_CAP
+#define PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//PSWUSCFG0_0_PCIE_ACS_CNTL
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_MC_CAP
+#define PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//PSWUSCFG0_0_PCIE_MC_CNTL
+#define PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//PSWUSCFG0_0_PCIE_MC_ADDR0
+#define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//PSWUSCFG0_0_PCIE_MC_ADDR1
+#define PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_MC_RCV0
+#define PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_MC_RCV1
+#define PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0
+#define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1
+#define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0
+#define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1
+#define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_LTR_CAP
+#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_ARI_CAP
+#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//PSWUSCFG0_0_PCIE_ARI_CNTL
+#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//PSWUSCFG0_0_PCIE_ESM_CAP_LIST
+#define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_ESM_HEADER_1
+#define PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_ESM_HEADER_2
+#define PSWUSCFG0_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//PSWUSCFG0_0_PCIE_ESM_STATUS
+#define PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//PSWUSCFG0_0_PCIE_ESM_CTRL
+#define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//PSWUSCFG0_0_PCIE_ESM_CAP_1
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//PSWUSCFG0_0_PCIE_ESM_CAP_2
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//PSWUSCFG0_0_PCIE_ESM_CAP_3
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//PSWUSCFG0_0_PCIE_ESM_CAP_4
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//PSWUSCFG0_0_PCIE_ESM_CAP_5
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//PSWUSCFG0_0_PCIE_ESM_CAP_6
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//PSWUSCFG0_0_PCIE_ESM_CAP_7
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_DATA_LINK_FEATURE_CAP
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_LINK_CAP_16GT
+#define PSWUSCFG0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define PSWUSCFG0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_LINK_CNTL_16GT
+#define PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_LINK_STATUS_16GT
+#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_MARGINING_PORT_CAP
+#define PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//PSWUSCFG0_0_MARGINING_PORT_STATUS
+#define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_0_PCIE_CCIX_CAP_LIST
+#define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_CCIX_HEADER_1
+#define PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//PSWUSCFG0_0_PCIE_CCIX_HEADER_2
+#define PSWUSCFG0_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//PSWUSCFG0_0_PCIE_CCIX_CAP
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//PSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_0_PCIE_CCIX_TRANS_CAP
+#define PSWUSCFG0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL
+#define PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE__SHIFT 0x1
+#define PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+#define PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_0_STATUS
+#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_HEADER
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_0_BIST
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_COMMAND
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_0_STATUS
+#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_HEADER
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_0_BIST
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_COMMAND
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_0_STATUS
+#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_LATENCY
+#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_HEADER
+#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_0_BIST
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_SBRN
+#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_FLADJ
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF2_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_0_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_COMMAND
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_0_STATUS
+#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_LATENCY
+#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_HEADER
+#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_0_BIST
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_SBRN
+#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_FLADJ
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF3_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_0_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect
+//SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x8
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x9
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L
+#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000100L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000200L
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0x10
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00010000L
+//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0x10
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00010000L
+//SYSHUB_TRANS_IDLE_SOCCLK
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF0_SOCCLK__SHIFT 0x0
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF1_SOCCLK__SHIFT 0x1
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF2_SOCCLK__SHIFT 0x2
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF3_SOCCLK__SHIFT 0x3
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF4_SOCCLK__SHIFT 0x4
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF5_SOCCLK__SHIFT 0x5
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF6_SOCCLK__SHIFT 0x6
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF7_SOCCLK__SHIFT 0x7
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF8_SOCCLK__SHIFT 0x8
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF9_SOCCLK__SHIFT 0x9
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF10_SOCCLK__SHIFT 0xa
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF11_SOCCLK__SHIFT 0xb
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF12_SOCCLK__SHIFT 0xc
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF13_SOCCLK__SHIFT 0xd
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF14_SOCCLK__SHIFT 0xe
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF15_SOCCLK__SHIFT 0xf
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF16_SOCCLK__SHIFT 0x10
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF17_SOCCLK__SHIFT 0x11
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF18_SOCCLK__SHIFT 0x12
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF19_SOCCLK__SHIFT 0x13
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF20_SOCCLK__SHIFT 0x14
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF21_SOCCLK__SHIFT 0x15
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF22_SOCCLK__SHIFT 0x16
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF23_SOCCLK__SHIFT 0x17
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF24_SOCCLK__SHIFT 0x18
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF25_SOCCLK__SHIFT 0x19
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF26_SOCCLK__SHIFT 0x1a
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF27_SOCCLK__SHIFT 0x1b
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF28_SOCCLK__SHIFT 0x1c
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF29_SOCCLK__SHIFT 0x1d
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF30_SOCCLK__SHIFT 0x1e
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_PF_SOCCLK__SHIFT 0x1f
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF0_SOCCLK_MASK 0x00000001L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF1_SOCCLK_MASK 0x00000002L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF2_SOCCLK_MASK 0x00000004L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF3_SOCCLK_MASK 0x00000008L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF4_SOCCLK_MASK 0x00000010L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF5_SOCCLK_MASK 0x00000020L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF6_SOCCLK_MASK 0x00000040L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF7_SOCCLK_MASK 0x00000080L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF8_SOCCLK_MASK 0x00000100L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF9_SOCCLK_MASK 0x00000200L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF10_SOCCLK_MASK 0x00000400L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF11_SOCCLK_MASK 0x00000800L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF12_SOCCLK_MASK 0x00001000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF13_SOCCLK_MASK 0x00002000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF14_SOCCLK_MASK 0x00004000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF15_SOCCLK_MASK 0x00008000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF16_SOCCLK_MASK 0x00010000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF17_SOCCLK_MASK 0x00020000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF18_SOCCLK_MASK 0x00040000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF19_SOCCLK_MASK 0x00080000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF20_SOCCLK_MASK 0x00100000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF21_SOCCLK_MASK 0x00200000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF22_SOCCLK_MASK 0x00400000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF23_SOCCLK_MASK 0x00800000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF24_SOCCLK_MASK 0x01000000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF25_SOCCLK_MASK 0x02000000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF26_SOCCLK_MASK 0x04000000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF27_SOCCLK_MASK 0x08000000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF28_SOCCLK_MASK 0x10000000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF29_SOCCLK_MASK 0x20000000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF30_SOCCLK_MASK 0x40000000L
+#define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_PF_SOCCLK_MASK 0x80000000L
+//SYSHUB_HP_TIMER_SOCCLK
+#define SYSHUB_HP_TIMER_SOCCLK__SYSHUB_HP_TIMER_SOCCLK__SHIFT 0x0
+#define SYSHUB_HP_TIMER_SOCCLK__SYSHUB_HP_TIMER_SOCCLK_MASK 0xFFFFFFFFL
+//SYSHUB_MGCG_CTRL_SOCCLK
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK__SHIFT 0xc
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK_MASK 0x00001000L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L
+//SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK
+#define SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK__SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK__SHIFT 0x0
+#define SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK__SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK_MASK 0x00000001L
+//SYSHUB_SCRATCH_SOCCLK
+#define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK__SHIFT 0x0
+#define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK_MASK 0xFFFFFFFFL
+//SYSHUB_CL_MASK_SOCCLK
+#define SYSHUB_CL_MASK_SOCCLK__DBGU_MASK_DIS_SOCCLK__SHIFT 0x0
+#define SYSHUB_CL_MASK_SOCCLK__MP1DRAM_MASK_DIS_SOCCLK__SHIFT 0x1
+#define SYSHUB_CL_MASK_SOCCLK__MP1_MASK_DIS_SOCCLK__SHIFT 0x2
+#define SYSHUB_CL_MASK_SOCCLK__DBGU_MASK_DIS_SOCCLK_MASK 0x00000001L
+#define SYSHUB_CL_MASK_SOCCLK__MP1DRAM_MASK_DIS_SOCCLK_MASK 0x00000002L
+#define SYSHUB_CL_MASK_SOCCLK__MP1_MASK_DIS_SOCCLK_MASK 0x00000004L
+//SYSHUB_HANG_CNTL_SOCCLK
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL0__SHIFT 0x0
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL1__SHIFT 0x1
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL2__SHIFT 0x2
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL0__SHIFT 0x3
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL1__SHIFT 0x4
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL2__SHIFT 0x5
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL0_MASK 0x00000001L
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL1_MASK 0x00000002L
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL2_MASK 0x00000004L
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL0_MASK 0x00000008L
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL1_MASK 0x00000010L
+#define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL2_MASK 0x00000020L
+//HST_CLK0_SW0_CL0_CNTL
+#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW0_CL1_CNTL
+#define HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW0_CL2_CNTL
+#define HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW1_CL0_CNTL
+#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW1_CL1_CNTL
+#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW1_CL2_CNTL
+#define HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L
+//DMA_CLK0_SW0_CL0_CNTL
+#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//DMA_CLK0_SW0_CL1_CNTL
+#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
+#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
+#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
+#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L
+#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L
+#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L
+//SYSHUB_DS_CTRL_SHUBCLK
+#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
+#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f
+#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L
+#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L
+//SYSHUB_DS_CTRL2_SHUBCLK
+#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0
+#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL
+//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
+//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
+//SYSHUB_MGCG_CTRL_SHUBCLK
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REG_DIS_SHUBCLK__SHIFT 0xc
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_AER_DIS_SHUBCLK__SHIFT 0xd
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REG_DIS_SHUBCLK_MASK 0x00001000L
+#define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_AER_DIS_SHUBCLK_MASK 0x00002000L
+//SYSHUB_SCRATCH_SHUBCLK
+#define SYSHUB_SCRATCH_SHUBCLK__SCRATCH_SHUBCLK__SHIFT 0x0
+#define SYSHUB_SCRATCH_SHUBCLK__SCRATCH_SHUBCLK_MASK 0xFFFFFFFFL
+//SYSHUB_SELECT_SHUBCLK
+#define SYSHUB_SELECT_SHUBCLK__SELECT_USB0__SHIFT 0x0
+#define SYSHUB_SELECT_SHUBCLK__SELECT_USB1__SHIFT 0x1
+#define SYSHUB_SELECT_SHUBCLK__SELECT_USB0_MASK 0x00000001L
+#define SYSHUB_SELECT_SHUBCLK__SELECT_USB1_MASK 0x00000002L
+//SYSHUB_SCRATCH_LCLK
+#define SYSHUB_SCRATCH_LCLK__SCRATCH_LCLK__SHIFT 0x0
+#define SYSHUB_SCRATCH_LCLK__SCRATCH_LCLK_MASK 0xFFFFFFFFL
+//NIC400_0_ASIB_0_FN_MOD
+#define NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//NIC400_0_AMIB_0_FN_MOD_BM_ISS
+#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//NIC400_0_AMIB_1_FN_MOD_BM_ISS
+#define NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//NIC400_0_AMIB_2_FN_MOD_BM_ISS
+#define NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//NIC400_0_IB_0_FN_MOD
+#define NIC400_0_IB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define NIC400_0_IB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define NIC400_0_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define NIC400_0_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//NIC400_1_ASIB_0_FN_MOD
+#define NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//NIC400_1_AMIB_0_FN_MOD_BM_ISS
+#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//NIC400_1_AMIB_1_FN_MOD_BM_ISS
+#define NIC400_1_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define NIC400_1_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define NIC400_1_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define NIC400_1_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//NIC400_1_AMIB_2_FN_MOD_BM_ISS
+#define NIC400_1_AMIB_2_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define NIC400_1_AMIB_2_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define NIC400_1_AMIB_2_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define NIC400_1_AMIB_2_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//NIC400_1_IB_0_FN_MOD
+#define NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define NIC400_1_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define NIC400_1_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//NIC400_2_AMIB_0_FN_MOD_BM_ISS
+#define NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0
+#define NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1
+#define NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L
+#define NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L
+//NIC400_2_ASIB_0_FN_MOD
+#define NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+//NIC400_2_ASIB_0_QOS_CNTL
+#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT 0x0
+#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT 0x1
+#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT 0x2
+#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT 0x3
+#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT 0x4
+#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT 0x5
+#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT 0x6
+#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT 0x7
+#define NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT 0x10
+#define NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT 0x14
+#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate_MASK 0x00000001L
+#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate_MASK 0x00000002L
+#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate_MASK 0x00000004L
+#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc_MASK 0x00000008L
+#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc_MASK 0x00000010L
+#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot_MASK 0x00000020L
+#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot_MASK 0x00000040L
+#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot_MASK 0x00000080L
+#define NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc_MASK 0x00010000L
+#define NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc_MASK 0x00100000L
+//NIC400_2_ASIB_0_MAX_OT
+#define NIC400_2_ASIB_0_MAX_OT__aw_max_otf__SHIFT 0x0
+#define NIC400_2_ASIB_0_MAX_OT__aw_max_oti__SHIFT 0x8
+#define NIC400_2_ASIB_0_MAX_OT__ar_max_otf__SHIFT 0x10
+#define NIC400_2_ASIB_0_MAX_OT__ar_max_oti__SHIFT 0x18
+#define NIC400_2_ASIB_0_MAX_OT__aw_max_otf_MASK 0x000000FFL
+#define NIC400_2_ASIB_0_MAX_OT__aw_max_oti_MASK 0x00003F00L
+#define NIC400_2_ASIB_0_MAX_OT__ar_max_otf_MASK 0x00FF0000L
+#define NIC400_2_ASIB_0_MAX_OT__ar_max_oti_MASK 0x3F000000L
+//NIC400_2_ASIB_0_MAX_COMB_OT
+#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT 0x0
+#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT 0x8
+#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL
+#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L
+//NIC400_2_ASIB_0_AW_P
+#define NIC400_2_ASIB_0_AW_P__aw_p__SHIFT 0x18
+#define NIC400_2_ASIB_0_AW_P__aw_p_MASK 0xFF000000L
+//NIC400_2_ASIB_0_AW_B
+#define NIC400_2_ASIB_0_AW_B__aw_b__SHIFT 0x0
+#define NIC400_2_ASIB_0_AW_B__aw_b_MASK 0x0000FFFFL
+//NIC400_2_ASIB_0_AW_R
+#define NIC400_2_ASIB_0_AW_R__aw_r__SHIFT 0x14
+#define NIC400_2_ASIB_0_AW_R__aw_r_MASK 0xFFF00000L
+//NIC400_2_ASIB_0_AR_P
+#define NIC400_2_ASIB_0_AR_P__ar_p__SHIFT 0x18
+#define NIC400_2_ASIB_0_AR_P__ar_p_MASK 0xFF000000L
+//NIC400_2_ASIB_0_AR_B
+#define NIC400_2_ASIB_0_AR_B__ar_b__SHIFT 0x0
+#define NIC400_2_ASIB_0_AR_B__ar_b_MASK 0x0000FFFFL
+//NIC400_2_ASIB_0_AR_R
+#define NIC400_2_ASIB_0_AR_R__ar_r__SHIFT 0x14
+#define NIC400_2_ASIB_0_AR_R__ar_r_MASK 0xFFF00000L
+//NIC400_2_ASIB_0_TARGET_FC
+#define NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT 0x0
+#define NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT 0x10
+#define NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL
+#define NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L
+//NIC400_2_ASIB_0_KI_FC
+#define NIC400_2_ASIB_0_KI_FC__aw_tgt_latency__SHIFT 0x0
+#define NIC400_2_ASIB_0_KI_FC__ar_tgt_latency__SHIFT 0x8
+#define NIC400_2_ASIB_0_KI_FC__aw_tgt_latency_MASK 0x00000007L
+#define NIC400_2_ASIB_0_KI_FC__ar_tgt_latency_MASK 0x00000700L
+//NIC400_2_ASIB_0_QOS_RANGE
+#define NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT 0x0
+#define NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT 0x8
+#define NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT 0x10
+#define NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT 0x18
+#define NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos_MASK 0x0000000FL
+#define NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos_MASK 0x00000F00L
+#define NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos_MASK 0x000F0000L
+#define NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos_MASK 0x0F000000L
+//NIC400_2_ASIB_1_FN_MOD
+#define NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0
+#define NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1
+#define NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L
+#define NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L
+//NIC400_2_ASIB_1_QOS_CNTL
+#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT 0x0
+#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT 0x1
+#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT 0x2
+#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT 0x3
+#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT 0x4
+#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT 0x5
+#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT 0x6
+#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT 0x7
+#define NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT 0x10
+#define NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT 0x14
+#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate_MASK 0x00000001L
+#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate_MASK 0x00000002L
+#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate_MASK 0x00000004L
+#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc_MASK 0x00000008L
+#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc_MASK 0x00000010L
+#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot_MASK 0x00000020L
+#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot_MASK 0x00000040L
+#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot_MASK 0x00000080L
+#define NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc_MASK 0x00010000L
+#define NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc_MASK 0x00100000L
+//NIC400_2_ASIB_1_MAX_OT
+#define NIC400_2_ASIB_1_MAX_OT__aw_max_otf__SHIFT 0x0
+#define NIC400_2_ASIB_1_MAX_OT__aw_max_oti__SHIFT 0x8
+#define NIC400_2_ASIB_1_MAX_OT__ar_max_otf__SHIFT 0x10
+#define NIC400_2_ASIB_1_MAX_OT__ar_max_oti__SHIFT 0x18
+#define NIC400_2_ASIB_1_MAX_OT__aw_max_otf_MASK 0x000000FFL
+#define NIC400_2_ASIB_1_MAX_OT__aw_max_oti_MASK 0x00003F00L
+#define NIC400_2_ASIB_1_MAX_OT__ar_max_otf_MASK 0x00FF0000L
+#define NIC400_2_ASIB_1_MAX_OT__ar_max_oti_MASK 0x3F000000L
+//NIC400_2_ASIB_1_MAX_COMB_OT
+#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT 0x0
+#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT 0x8
+#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL
+#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L
+//NIC400_2_ASIB_1_AW_P
+#define NIC400_2_ASIB_1_AW_P__aw_p__SHIFT 0x18
+#define NIC400_2_ASIB_1_AW_P__aw_p_MASK 0xFF000000L
+//NIC400_2_ASIB_1_AW_B
+#define NIC400_2_ASIB_1_AW_B__aw_b__SHIFT 0x0
+#define NIC400_2_ASIB_1_AW_B__aw_b_MASK 0x0000FFFFL
+//NIC400_2_ASIB_1_AW_R
+#define NIC400_2_ASIB_1_AW_R__aw_r__SHIFT 0x14
+#define NIC400_2_ASIB_1_AW_R__aw_r_MASK 0xFFF00000L
+//NIC400_2_ASIB_1_AR_P
+#define NIC400_2_ASIB_1_AR_P__ar_p__SHIFT 0x18
+#define NIC400_2_ASIB_1_AR_P__ar_p_MASK 0xFF000000L
+//NIC400_2_ASIB_1_AR_B
+#define NIC400_2_ASIB_1_AR_B__ar_b__SHIFT 0x0
+#define NIC400_2_ASIB_1_AR_B__ar_b_MASK 0x0000FFFFL
+//NIC400_2_ASIB_1_AR_R
+#define NIC400_2_ASIB_1_AR_R__ar_r__SHIFT 0x14
+#define NIC400_2_ASIB_1_AR_R__ar_r_MASK 0xFFF00000L
+//NIC400_2_ASIB_1_TARGET_FC
+#define NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT 0x0
+#define NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT 0x10
+#define NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL
+#define NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L
+//NIC400_2_ASIB_1_KI_FC
+#define NIC400_2_ASIB_1_KI_FC__aw_tgt_latency__SHIFT 0x0
+#define NIC400_2_ASIB_1_KI_FC__ar_tgt_latency__SHIFT 0x8
+#define NIC400_2_ASIB_1_KI_FC__aw_tgt_latency_MASK 0x00000007L
+#define NIC400_2_ASIB_1_KI_FC__ar_tgt_latency_MASK 0x00000700L
+//NIC400_2_ASIB_1_QOS_RANGE
+#define NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT 0x0
+#define NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT 0x8
+#define NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT 0x10
+#define NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT 0x18
+#define NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos_MASK 0x0000000FL
+#define NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos_MASK 0x00000F00L
+#define NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos_MASK 0x000F0000L
+#define NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos_MASK 0x0F000000L
+//NIC400_2_IB_0_FN_MOD
+#define NIC400_2_IB_0_FN_MOD__read_iss_override__SHIFT 0x0
+#define NIC400_2_IB_0_FN_MOD__write_iss_override__SHIFT 0x1
+#define NIC400_2_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L
+#define NIC400_2_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_nbif_sion_SIONDEC
+//SION_CL0_RdRsp_BurstTarget_REG0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_BurstTarget_REG1
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG1
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG1
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG1
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG1
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG1
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG1
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG1
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG1
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG1
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG1
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG1
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG1
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG1
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG1
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG1
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG1
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG1
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG1
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG1
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG1
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG1
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG1
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG1
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG1
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG1
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_BurstTarget_REG0
+#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_BurstTarget_REG1
+#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_TimeSlot_REG0
+#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_RdRsp_TimeSlot_REG1
+#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_BurstTarget_REG0
+#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_BurstTarget_REG1
+#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_TimeSlot_REG0
+#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_WrRsp_TimeSlot_REG1
+#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_Req_BurstTarget_REG0
+#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_Req_BurstTarget_REG1
+#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_Req_TimeSlot_REG0
+#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_Req_TimeSlot_REG1
+#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_ReqPoolCredit_Alloc_REG0
+#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_ReqPoolCredit_Alloc_REG1
+#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_DataPoolCredit_Alloc_REG0
+#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_DataPoolCredit_Alloc_REG1
+#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_RdRspPoolCredit_Alloc_REG0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_RdRspPoolCredit_Alloc_REG1
+#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL3_WrRspPoolCredit_Alloc_REG0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL3_WrRspPoolCredit_Alloc_REG1
+#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CNTL_REG0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L
+//SION_CNTL_REG1
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK 0x0000FF00L
+
+
+// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC
+//SHUB_PF_FLR_RST
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+//SHUB_GFX_DRV_VPU_RST
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L
+//SHUB_LINK_RESET
+#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0
+#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1
+#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT 0x2
+#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L
+#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L
+#define SHUB_LINK_RESET__LINK_P2_RESET_MASK 0x00000004L
+//SHUB_PF0_VF_FLR_RST
+#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4
+#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5
+#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6
+#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7
+#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8
+#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9
+#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa
+#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb
+#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc
+#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd
+#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe
+#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf
+#define SHUB_PF0_VF_FLR_RST__PF0_VF16_FLR_RST__SHIFT 0x10
+#define SHUB_PF0_VF_FLR_RST__PF0_VF17_FLR_RST__SHIFT 0x11
+#define SHUB_PF0_VF_FLR_RST__PF0_VF18_FLR_RST__SHIFT 0x12
+#define SHUB_PF0_VF_FLR_RST__PF0_VF19_FLR_RST__SHIFT 0x13
+#define SHUB_PF0_VF_FLR_RST__PF0_VF20_FLR_RST__SHIFT 0x14
+#define SHUB_PF0_VF_FLR_RST__PF0_VF21_FLR_RST__SHIFT 0x15
+#define SHUB_PF0_VF_FLR_RST__PF0_VF22_FLR_RST__SHIFT 0x16
+#define SHUB_PF0_VF_FLR_RST__PF0_VF23_FLR_RST__SHIFT 0x17
+#define SHUB_PF0_VF_FLR_RST__PF0_VF24_FLR_RST__SHIFT 0x18
+#define SHUB_PF0_VF_FLR_RST__PF0_VF25_FLR_RST__SHIFT 0x19
+#define SHUB_PF0_VF_FLR_RST__PF0_VF26_FLR_RST__SHIFT 0x1a
+#define SHUB_PF0_VF_FLR_RST__PF0_VF27_FLR_RST__SHIFT 0x1b
+#define SHUB_PF0_VF_FLR_RST__PF0_VF28_FLR_RST__SHIFT 0x1c
+#define SHUB_PF0_VF_FLR_RST__PF0_VF29_FLR_RST__SHIFT 0x1d
+#define SHUB_PF0_VF_FLR_RST__PF0_VF30_FLR_RST__SHIFT 0x1e
+#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f
+#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF16_FLR_RST_MASK 0x00010000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF17_FLR_RST_MASK 0x00020000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF18_FLR_RST_MASK 0x00040000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF19_FLR_RST_MASK 0x00080000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF20_FLR_RST_MASK 0x00100000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF21_FLR_RST_MASK 0x00200000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF22_FLR_RST_MASK 0x00400000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF23_FLR_RST_MASK 0x00800000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF24_FLR_RST_MASK 0x01000000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF25_FLR_RST_MASK 0x02000000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF26_FLR_RST_MASK 0x04000000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF27_FLR_RST_MASK 0x08000000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF28_FLR_RST_MASK 0x10000000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF29_FLR_RST_MASK 0x20000000L
+#define SHUB_PF0_VF_FLR_RST__PF0_VF30_FLR_RST_MASK 0x40000000L
+#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L
+//SHUB_HARD_RST_CTRL
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L
+//SHUB_SOFT_RST_CTRL
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L
+//SHUB_SDP_PORT_RST
+#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT 0x0
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT 0x1
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0x2
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT 0x3
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4
+#define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST__SHIFT 0x5
+#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT 0x6
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT 0x7
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9
+#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18
+#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK 0x00000001L
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK 0x00000002L
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00000004L
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK 0x00000008L
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L
+#define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST_MASK 0x00000020L
+#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK 0x00000040L
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK 0x00000080L
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L
+#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L
+
+
+// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk
+//GDCL_RAS_CENTRAL_STATUS
+#define GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_EgStall_det__SHIFT 0x0
+#define GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_ErrEvent_det__SHIFT 0x1
+#define GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_EgStall_det__SHIFT 0x2
+#define GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_ErrEvent_det__SHIFT 0x3
+#define GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_EgStall_det_MASK 0x00000001L
+#define GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_ErrEvent_det_MASK 0x00000002L
+#define GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_EgStall_det_MASK 0x00000004L
+#define GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_ErrEvent_det_MASK 0x00000008L
+//GDCSOC_RAS_CENTRAL_STATUS
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT 0x0
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT 0x1
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT 0x2
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT 0x3
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK 0x00000001L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK 0x00000002L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK 0x00000004L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK 0x00000008L
+//GDCSOC_RAS_LEAF0_CTRL
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF1_CTRL
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF2_CTRL
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//GDCSOC_RAS_LEAF3_CTRL
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF4_CTRL
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF5_CTRL
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF2_MISC_CTRL
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT 0x8
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT 0x9
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS__SHIFT 0xc
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN__SHIFT 0x10
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT 0x11
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_MASK 0x00001000L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN_MASK 0x00010000L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK 0x00020000L
+//GDCSOC_RAS_LEAF2_MISC_CTRL2
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT 0x8
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT 0x14
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_MASK 0x0000007FL
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK 0x0003FF00L
+#define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK 0x3FF00000L
+//GDCSOC_RAS_LEAF0_STATUS
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF1_STATUS
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF2_STATUS
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF3_STATUS
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF4_STATUS
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF5_STATUS
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSHUB_RAS_CENTRAL_STATUS
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det__SHIFT 0x0
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det__SHIFT 0x1
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det__SHIFT 0x2
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det__SHIFT 0x3
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det_MASK 0x00000001L
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det_MASK 0x00000002L
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det_MASK 0x00000004L
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
+//BIF_CFG_DEV0_SWDS_VENDOR_ID
+#define BIF_CFG_DEV0_SWDS_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS_DEVICE_ID
+#define BIF_CFG_DEV0_SWDS_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS_COMMAND
+#define BIF_CFG_DEV0_SWDS_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_SWDS_STATUS
+#define BIF_CFG_DEV0_SWDS_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_SWDS_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_REVISION_ID
+#define BIF_CFG_DEV0_SWDS_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_PROG_INTERFACE
+#define BIF_CFG_DEV0_SWDS_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS_SUB_CLASS
+#define BIF_CFG_DEV0_SWDS_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS_BASE_CLASS
+#define BIF_CFG_DEV0_SWDS_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS_CACHE_LINE
+#define BIF_CFG_DEV0_SWDS_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS_LATENCY
+#define BIF_CFG_DEV0_SWDS_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS_HEADER
+#define BIF_CFG_DEV0_SWDS_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_SWDS_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_SWDS_BIST
+#define BIF_CFG_DEV0_SWDS_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_SWDS_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_SWDS_BASE_ADDR_1
+#define BIF_CFG_DEV0_SWDS_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_BASE_ADDR_2
+#define BIF_CFG_DEV0_SWDS_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//SUB_BUS_NUMBER_LATENCY
+#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//IO_BASE_LIMIT
+#define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//SECONDARY_STATUS
+#define SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//MEM_BASE_LIMIT
+#define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//PREF_BASE_LIMIT
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//PREF_BASE_UPPER
+#define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//PREF_LIMIT_UPPER
+#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//IO_BASE_LIMIT_HI
+#define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS_CAP_PTR
+#define BIF_CFG_DEV0_SWDS_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_SWDS_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_INTERRUPT_LINE
+#define BIF_CFG_DEV0_SWDS_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS_INTERRUPT_PIN
+#define BIF_CFG_DEV0_SWDS_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//IRQ_BRIDGE_CNTL
+#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV0_SWDS_PMI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_PMI_CAP
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_PCIE_CAP
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_SWDS_DEVICE_CAP
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_SWDS_DEVICE_CNTL
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_DEVICE_STATUS
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_SWDS_LINK_CAP
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS_LINK_CNTL
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_SWDS_LINK_STATUS
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//SLOT_CAP
+#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//SLOT_CNTL
+#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//SLOT_STATUS
+#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS_DEVICE_CAP2
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS_DEVICE_CNTL2
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_DEVICE_STATUS2
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS_LINK_CAP2
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS_LINK_CNTL2
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_SWDS_LINK_STATUS2
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//SLOT_CAP2
+#define SLOT_CAP2__RESERVED__SHIFT 0x0
+#define SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//SLOT_CNTL2
+#define SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//SLOT_STATUS2
+#define SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS_MSI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_MSI_MSG_DATA
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//SSID_CAP_LIST
+#define SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//SSID_CAP
+#define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_LINK_CAP_16GT
+#define BIF_CFG_DEV0_SWDS_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//MM_INDEX
+#define MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define MM_INDEX__MM_APER__SHIFT 0x1f
+#define MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define MM_INDEX__MM_APER_MASK 0x80000000L
+//MM_DATA
+#define MM_DATA__MM_DATA__SHIFT 0x0
+#define MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//MM_INDEX_HI
+#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_STRAP0_RCC_BIF_STRAP0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT 0x1
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK 0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP1
+#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT 0x4
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK 0x00000010L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+//RCC_STRAP0_RCC_BIF_STRAP2
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xc
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00003000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+//RCC_STRAP0_RCC_BIF_STRAP3
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP4
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP5
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+//RCC_STRAP0_RCC_BIF_STRAP6
+#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK 0xFFFFFFFFL
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK 0x02000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00000060L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x00006000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00018000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x000E0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK 0x02000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK 0x00000070L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK 0x0000001EL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1_MASK 0x00300000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1_MASK 0x00800000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1_MASK 0x03000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1_MASK 0xFC000000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_0_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_0_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_0_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_0_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+//RCC_DEV0_0_RCC_VDM_SUPPORT
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+//RCC_DEV0_0_RCC_BUS_CNTL
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV0_0_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+//RCC_DEV0_0_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV0_0_RCC_MH_ARB_CNTL
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BME_STATUS
+#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_ATOMIC_ERR_LOG
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//DOORBELL_SELFRING_GPA_APER_CNTL
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//HDP_REG_COHERENCY_FLUSH_CNTL
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//HDP_MEM_COHERENCY_FLUSH_CNTL
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//GPU_HDP_FLUSH_REQ
+#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//GPU_HDP_FLUSH_DONE
+#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_TRANS_PENDING
+#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//NBIF_GFX_ADDR_LUT_BYPASS
+#define NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//MAILBOX_MSGBUF_TRN_DW0
+#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_TRN_DW1
+#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_TRN_DW2
+#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_TRN_DW3
+#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW0
+#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW1
+#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW2
+#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_MSGBUF_RCV_DW3
+#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//MAILBOX_CONTROL
+#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//MAILBOX_INT_CNTL
+#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_VMHV_MAILBOX
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec
+//SHADOW_COMMAND
+#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0
+#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1
+#define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L
+#define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L
+//SHADOW_BASE_ADDR_1
+#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0
+#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL
+//SHADOW_BASE_ADDR_2
+#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0
+#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL
+//SHADOW_SUB_BUS_NUMBER_LATENCY
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000FF00L
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00FF0000L
+//SHADOW_IO_BASE_LIMIT
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x00F0L
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0xF000L
+//SHADOW_MEM_BASE_LIMIT
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000FFF0L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xFFF00000L
+//SHADOW_PREF_BASE_LIMIT
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000FFF0L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xFFF00000L
+//SHADOW_PREF_BASE_UPPER
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xFFFFFFFFL
+//SHADOW_PREF_LIMIT_UPPER
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xFFFFFFFFL
+//SHADOW_IO_BASE_LIMIT_HI
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000FFFFL
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xFFFF0000L
+//SHADOW_IRQ_BRIDGE_CNTL
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x0004L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x0008L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x0010L
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x0040L
+//SUC_INDEX
+#define SUC_INDEX__SUC_INDEX__SHIFT 0x0
+#define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL
+//SUC_DATA
+#define SUC_DATA__SUC_DATA__SHIFT 0x0
+#define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+//RCC_DEV1_PORT_STRAP0
+#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x4
+#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x5
+#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x19
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x1c
+#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x1f
+#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1_MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1_MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1_MASK 0x00000008L
+#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1_MASK 0x00000010L
+#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1_MASK 0x001FFFE0L
+#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1_MASK 0x01000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1_MASK 0x0E000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1_MASK 0x70000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1_MASK 0x80000000L
+//RCC_DEV1_PORT_STRAP1
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1_MASK 0x0000FFFFL
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1_MASK 0xFFFF0000L
+//RCC_DEV1_PORT_STRAP2
+#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x4
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT 0x5
+#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x6
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x7
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x9
+#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0xc
+#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0xd
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0xe
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0xf
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1__SHIFT 0x11
+#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x12
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x14
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x17
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x1a
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1_MASK 0x00000001L
+#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1_MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1_MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1_MASK 0x00000008L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1_MASK 0x00000010L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1_MASK 0x00000020L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1_MASK 0x00000040L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1_MASK 0x00000080L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1_MASK 0x00000100L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1_MASK 0x00000E00L
+#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1_MASK 0x00001000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1_MASK 0x00002000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1_MASK 0x00004000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1_MASK 0x00008000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1_MASK 0x00010000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1_MASK 0x00020000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1_MASK 0x000C0000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1_MASK 0x00700000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1_MASK 0x03800000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1_MASK 0x1C000000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1_MASK 0xE0000000L
+//RCC_DEV1_PORT_STRAP3
+#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x6
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x7
+#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x9
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0xb
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0xe
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0x12
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0x15
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x19
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x1b
+#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT 0x1e
+#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x1f
+#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1_MASK 0x00000001L
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1_MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1_MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1_MASK 0x00000038L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1_MASK 0x00000040L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1_MASK 0x00000080L
+#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1_MASK 0x00000100L
+#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1_MASK 0x00000600L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK 0x00003800L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1_MASK 0x0003C000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK 0x001C0000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1_MASK 0x01E00000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1_MASK 0x06000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1_MASK 0x18000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1_MASK 0x20000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1_MASK 0x40000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1_MASK 0x80000000L
+//RCC_DEV1_PORT_STRAP4
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1_MASK 0x0000FF00L
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1_MASK 0x00FF0000L
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1_MASK 0xFF000000L
+//RCC_DEV1_PORT_STRAP5
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x11
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x12
+#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x13
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x14
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x15
+#define RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1__SHIFT 0x16
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x17
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x19
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x1a
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x1b
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x1c
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x1e
+#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x1f
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1_MASK 0x0000FF00L
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1_MASK 0x00010000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1_MASK 0x00020000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1_MASK 0x00040000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1_MASK 0x00080000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1_MASK 0x00100000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1_MASK 0x00200000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1_MASK 0x00400000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1_MASK 0x00800000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1_MASK 0x01000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1_MASK 0x02000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1_MASK 0x04000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1_MASK 0x08000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1_MASK 0x10000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1_MASK 0x20000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1_MASK 0x40000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1_MASK 0x80000000L
+//RCC_DEV1_PORT_STRAP6
+#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1__SHIFT 0x4
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1__SHIFT 0x5
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT 0x6
+#define RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT 0x7
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1__SHIFT 0xc
+#define RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1_MASK 0x00000001L
+#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1_MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV1_MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1_MASK 0x00000008L
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1_MASK 0x00000010L
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1_MASK 0x00000020L
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK 0x00000040L
+#define RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK 0x00000080L
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1_MASK 0x00000F00L
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1_MASK 0x0000F000L
+#define RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1_MASK 0x00030000L
+//RCC_DEV1_PORT_STRAP7
+#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0xc
+#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1_MASK 0x00000F00L
+#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1_MASK 0x0000F000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1_MASK 0x00FF0000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1_MASK 0x1F000000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1_MASK 0xE0000000L
+//RCC_DEV1_PORT_STRAP8
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1_MASK 0x0000FF00L
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1_MASK 0x00FF0000L
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1_MASK 0xFF000000L
+//RCC_DEV1_PORT_STRAP9
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1_MASK 0x0000FF00L
+//RCC_DEV2_PORT_STRAP0
+#define RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2__SHIFT 0x1
+#define RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2__SHIFT 0x2
+#define RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2__SHIFT 0x3
+#define RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2__SHIFT 0x4
+#define RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2__SHIFT 0x5
+#define RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2__SHIFT 0x19
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2__SHIFT 0x1c
+#define RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2__SHIFT 0x1f
+#define RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2_MASK 0x00000002L
+#define RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2_MASK 0x00000004L
+#define RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2_MASK 0x00000008L
+#define RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2_MASK 0x00000010L
+#define RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2_MASK 0x001FFFE0L
+#define RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2_MASK 0x01000000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2_MASK 0x0E000000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2_MASK 0x70000000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2_MASK 0x80000000L
+//RCC_DEV2_PORT_STRAP1
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2_MASK 0x0000FFFFL
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2_MASK 0xFFFF0000L
+//RCC_DEV2_PORT_STRAP2
+#define RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2__SHIFT 0x1
+#define RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2__SHIFT 0x2
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2__SHIFT 0x3
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2__SHIFT 0x4
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV2__SHIFT 0x5
+#define RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2__SHIFT 0x6
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2__SHIFT 0x7
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2__SHIFT 0x9
+#define RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2__SHIFT 0xc
+#define RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2__SHIFT 0xd
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2__SHIFT 0xe
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2__SHIFT 0xf
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2__SHIFT 0x11
+#define RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2__SHIFT 0x12
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2__SHIFT 0x14
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2__SHIFT 0x17
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2__SHIFT 0x1a
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2__SHIFT 0x1d
+#define RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2_MASK 0x00000001L
+#define RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2_MASK 0x00000002L
+#define RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2_MASK 0x00000004L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2_MASK 0x00000008L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2_MASK 0x00000010L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV2_MASK 0x00000020L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2_MASK 0x00000040L
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2_MASK 0x00000080L
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2_MASK 0x00000100L
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2_MASK 0x00000E00L
+#define RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2_MASK 0x00001000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2_MASK 0x00002000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2_MASK 0x00004000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2_MASK 0x00008000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2_MASK 0x00010000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2_MASK 0x00020000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2_MASK 0x000C0000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2_MASK 0x00700000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2_MASK 0x03800000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2_MASK 0x1C000000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2_MASK 0xE0000000L
+//RCC_DEV2_PORT_STRAP3
+#define RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2__SHIFT 0x1
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2__SHIFT 0x2
+#define RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2__SHIFT 0x3
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2__SHIFT 0x6
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2__SHIFT 0x7
+#define RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2__SHIFT 0x9
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT 0xb
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2__SHIFT 0xe
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT 0x12
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2__SHIFT 0x15
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2__SHIFT 0x19
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2__SHIFT 0x1b
+#define RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2__SHIFT 0x1d
+#define RCC_DEV2_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV2__SHIFT 0x1e
+#define RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2__SHIFT 0x1f
+#define RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2_MASK 0x00000001L
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2_MASK 0x00000002L
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2_MASK 0x00000004L
+#define RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2_MASK 0x00000038L
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2_MASK 0x00000040L
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2_MASK 0x00000080L
+#define RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2_MASK 0x00000100L
+#define RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2_MASK 0x00000600L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK 0x00003800L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2_MASK 0x0003C000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK 0x001C0000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2_MASK 0x01E00000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2_MASK 0x06000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2_MASK 0x18000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2_MASK 0x20000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV2_MASK 0x40000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2_MASK 0x80000000L
+//RCC_DEV2_PORT_STRAP4
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2_MASK 0x0000FF00L
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2_MASK 0x00FF0000L
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2_MASK 0xFF000000L
+//RCC_DEV2_PORT_STRAP5
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2__SHIFT 0x11
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2__SHIFT 0x12
+#define RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2__SHIFT 0x13
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2__SHIFT 0x14
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2__SHIFT 0x15
+#define RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2__SHIFT 0x16
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2__SHIFT 0x17
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2__SHIFT 0x19
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2__SHIFT 0x1a
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2__SHIFT 0x1b
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2__SHIFT 0x1c
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2__SHIFT 0x1d
+#define RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2__SHIFT 0x1e
+#define RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2__SHIFT 0x1f
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2_MASK 0x0000FF00L
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2_MASK 0x00010000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2_MASK 0x00020000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2_MASK 0x00040000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2_MASK 0x00080000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2_MASK 0x00100000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2_MASK 0x00200000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2_MASK 0x00400000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2_MASK 0x00800000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2_MASK 0x01000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2_MASK 0x02000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2_MASK 0x04000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2_MASK 0x08000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2_MASK 0x10000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2_MASK 0x20000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2_MASK 0x40000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2_MASK 0x80000000L
+//RCC_DEV2_PORT_STRAP6
+#define RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2__SHIFT 0x1
+#define RCC_DEV2_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV2__SHIFT 0x2
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2__SHIFT 0x3
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2__SHIFT 0x4
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2__SHIFT 0x5
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT 0x6
+#define RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT 0x7
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2__SHIFT 0xc
+#define RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2_MASK 0x00000001L
+#define RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2_MASK 0x00000002L
+#define RCC_DEV2_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV2_MASK 0x00000004L
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2_MASK 0x00000008L
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2_MASK 0x00000010L
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2_MASK 0x00000020L
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK 0x00000040L
+#define RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK 0x00000080L
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2_MASK 0x00000F00L
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2_MASK 0x0000F000L
+#define RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2_MASK 0x00030000L
+//RCC_DEV2_PORT_STRAP7
+#define RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2__SHIFT 0xc
+#define RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2__SHIFT 0x1d
+#define RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2_MASK 0x00000F00L
+#define RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2_MASK 0x0000F000L
+#define RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2_MASK 0x00FF0000L
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2_MASK 0x1F000000L
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2_MASK 0xE0000000L
+//RCC_DEV2_PORT_STRAP8
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2_MASK 0x0000FF00L
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2_MASK 0x00FF0000L
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2_MASK 0xFF000000L
+//RCC_DEV2_PORT_STRAP9
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2_MASK 0x0000FF00L
+//RCC_STRAP1_RCC_BIF_STRAP0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT 0x1
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK 0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP1
+#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT 0x4
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK 0x00000010L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+//RCC_STRAP1_RCC_BIF_STRAP2
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xc
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00003000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+//RCC_STRAP1_RCC_BIF_STRAP3
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP4
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP5
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+//RCC_STRAP1_RCC_BIF_STRAP6
+#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK 0xFFFFFFFFL
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK 0x02000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00000060L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x00006000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00018000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x000E0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK 0x02000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK 0x00000070L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP7
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK 0x0000001EL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1_MASK 0x00300000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1_MASK 0x00800000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1_MASK 0x03000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1_MASK 0xFC000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L
+//RCC_DEV0_EPF2_STRAP0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK 0x000F0000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK 0x00F00000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK 0x10000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK 0x40000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP2
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT 0x9
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15
+#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK 0x00000080L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK 0x00000100L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK 0x00003E00L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK 0x00004000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK 0x00010000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK 0x00020000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK 0x00200000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2_MASK 0x00800000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK 0x07000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK 0x10000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK 0x40000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP3
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x1
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x2
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18
+#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT 0x19
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK 0x00000001L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK 0x00000002L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK 0x00040000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK 0x00080000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK 0x01000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2_MASK 0x02000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK 0x04000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK 0x08000000L
+//RCC_DEV0_EPF2_STRAP4
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK 0x00200000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK 0x00400000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK 0x0F800000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK 0x70000000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP5
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESEL_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESELD_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2__SHIFT 0x1b
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESEL_DEV0_F2_MASK 0x000F0000L
+#define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESELD_DEV0_F2_MASK 0x00F00000L
+#define RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2_MASK 0x38000000L
+//RCC_DEV0_EPF2_STRAP6
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x1
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT 0x4
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK 0x00000001L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2_MASK 0x00000002L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2_MASK 0x00000070L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2_MASK 0x00000100L
+//RCC_DEV0_EPF2_STRAP7
+#define RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_EN_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F2__SHIFT 0x1
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_EN_DEV0_F2__SHIFT 0x16
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F2__SHIFT 0x17
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F2__SHIFT 0x18
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F2__SHIFT 0x1a
+#define RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_EN_DEV0_F2_MASK 0x00000001L
+#define RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F2_MASK 0x0000001EL
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F2_MASK 0x00300000L
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_EN_DEV0_F2_MASK 0x00400000L
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F2_MASK 0x00800000L
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F2_MASK 0x03000000L
+#define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F2_MASK 0xFC000000L
+//RCC_DEV0_EPF2_STRAP13
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK 0x000000FFL
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK 0x0000FF00L
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK 0x00FF0000L
+//RCC_DEV0_EPF3_STRAP0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK 0x000F0000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK 0x00F00000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK 0x10000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK 0x20000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK 0x40000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP2
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3__SHIFT 0x9
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15
+#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3__SHIFT 0x1d
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK 0x00000080L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK 0x00000100L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3_MASK 0x00003E00L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK 0x00004000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK 0x00010000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK 0x00020000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK 0x00200000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3_MASK 0x00800000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK 0x07000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3_MASK 0x10000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3_MASK 0x20000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3_MASK 0x40000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP3
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x1
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x2
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18
+#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT 0x19
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK 0x00000001L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK 0x00000002L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK 0x00040000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK 0x00080000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK 0x01000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3_MASK 0x02000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK 0x04000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK 0x08000000L
+//RCC_DEV0_EPF3_STRAP4
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK 0x00200000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK 0x00400000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK 0x0F800000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK 0x70000000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP5
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3__SHIFT 0x1b
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3_MASK 0x000F0000L
+#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3_MASK 0x00F00000L
+#define RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3_MASK 0x38000000L
+//RCC_DEV0_EPF3_STRAP6
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER1_EN_DEV0_F3__SHIFT 0x8
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK 0x00000001L
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER1_EN_DEV0_F3_MASK 0x00000100L
+//RCC_DEV0_EPF3_STRAP7
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_EN_DEV0_F3__SHIFT 0x16
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F3__SHIFT 0x17
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F3__SHIFT 0x18
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F3__SHIFT 0x1a
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F3_MASK 0x00300000L
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_EN_DEV0_F3_MASK 0x00400000L
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F3_MASK 0x00800000L
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F3_MASK 0x03000000L
+#define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F3_MASK 0xFC000000L
+//RCC_DEV0_EPF3_STRAP13
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK 0x000000FFL
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK 0x0000FF00L
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK 0x00FF0000L
+//RCC_DEV0_EPF4_STRAP0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x1d
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4_MASK 0x000F0000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4_MASK 0x00F00000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4_MASK 0x10000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4_MASK 0x20000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4_MASK 0x40000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP2
+#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x7
+#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x8
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4__SHIFT 0x9
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0xe
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15
+#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x17
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x18
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4__SHIFT 0x1d
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4__SHIFT 0x1e
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4_MASK 0x00000080L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4_MASK 0x00000100L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4_MASK 0x00003E00L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4_MASK 0x00004000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4_MASK 0x00010000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4_MASK 0x00020000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4_MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4_MASK 0x00200000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4_MASK 0x00800000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4_MASK 0x07000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4_MASK 0x10000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4_MASK 0x20000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4_MASK 0x40000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP3
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x1
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x2
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x12
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x13
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18
+#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT 0x19
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4_MASK 0x00000001L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4_MASK 0x00000002L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4_MASK 0x00040000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4_MASK 0x00080000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4_MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4_MASK 0x01000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4_MASK 0x02000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4_MASK 0x04000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4_MASK 0x08000000L
+//RCC_DEV0_EPF4_STRAP4
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x15
+#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x16
+#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x17
+#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4_MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4_MASK 0x00200000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4_MASK 0x00400000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4_MASK 0x0F800000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4_MASK 0x70000000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP5
+#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4_MASK 0x000F0000L
+#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4_MASK 0x00F00000L
+//RCC_DEV0_EPF4_STRAP6
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4_MASK 0x00000001L
+//RCC_DEV0_EPF4_STRAP7
+#define RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4__SHIFT 0x5
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_EN_DEV0_F4__SHIFT 0x16
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F4__SHIFT 0x17
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F4__SHIFT 0x18
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F4__SHIFT 0x1a
+#define RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4_MASK 0x0000FFE0L
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F4_MASK 0x00300000L
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_EN_DEV0_F4_MASK 0x00400000L
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F4_MASK 0x00800000L
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F4_MASK 0x03000000L
+#define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F4_MASK 0xFC000000L
+//RCC_DEV0_EPF4_STRAP13
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x8
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4_MASK 0x000000FFL
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4_MASK 0x0000FF00L
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4_MASK 0x00FF0000L
+//RCC_DEV0_EPF5_STRAP0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x1d
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5_MASK 0x000F0000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5_MASK 0x00F00000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5_MASK 0x10000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5_MASK 0x20000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5_MASK 0x40000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP2
+#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x7
+#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x8
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5__SHIFT 0x9
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0xe
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15
+#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x17
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x18
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5__SHIFT 0x1d
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5__SHIFT 0x1e
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5_MASK 0x00000080L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5_MASK 0x00000100L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5_MASK 0x00003E00L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5_MASK 0x00004000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5_MASK 0x00010000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5_MASK 0x00020000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5_MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5_MASK 0x00200000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5_MASK 0x00800000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5_MASK 0x07000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5_MASK 0x10000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5_MASK 0x20000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5_MASK 0x40000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP3
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x1
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x2
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x12
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x13
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18
+#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT 0x19
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5_MASK 0x00000001L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5_MASK 0x00000002L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5_MASK 0x00040000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5_MASK 0x00080000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5_MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5_MASK 0x01000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5_MASK 0x02000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5_MASK 0x04000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5_MASK 0x08000000L
+//RCC_DEV0_EPF5_STRAP4
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15
+#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16
+#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17
+#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5_MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5_MASK 0x00200000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5_MASK 0x00400000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5_MASK 0x0F800000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5_MASK 0x70000000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP5
+#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESEL_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESELD_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESEL_DEV0_F5_MASK 0x000F0000L
+#define RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESELD_DEV0_F5_MASK 0x00F00000L
+//RCC_DEV0_EPF5_STRAP6
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5_MASK 0x00000001L
+//RCC_DEV0_EPF5_STRAP7
+#define RCC_DEV0_EPF5_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F5__SHIFT 0x5
+#define RCC_DEV0_EPF5_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F5_MASK 0x0000FFE0L
+//RCC_DEV0_EPF5_STRAP13
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x8
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5_MASK 0x000000FFL
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5_MASK 0x0000FF00L
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5_MASK 0x00FF0000L
+//RCC_DEV0_EPF6_STRAP0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x1d
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6_MASK 0x000F0000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6_MASK 0x00F00000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6_MASK 0x10000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6_MASK 0x20000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6_MASK 0x40000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP2
+#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x7
+#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x8
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6__SHIFT 0x9
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0xe
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15
+#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x17
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x18
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6__SHIFT 0x1d
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6__SHIFT 0x1e
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6_MASK 0x00000080L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6_MASK 0x00000100L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6_MASK 0x00003E00L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6_MASK 0x00004000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6_MASK 0x00010000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6_MASK 0x00020000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6_MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6_MASK 0x00200000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6_MASK 0x00800000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6_MASK 0x07000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6_MASK 0x10000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6_MASK 0x20000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6_MASK 0x40000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP3
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x1
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x2
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x12
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x13
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18
+#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT 0x19
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6_MASK 0x00000001L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6_MASK 0x00000002L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6_MASK 0x00040000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6_MASK 0x00080000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6_MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6_MASK 0x01000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6_MASK 0x02000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6_MASK 0x04000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6_MASK 0x08000000L
+//RCC_DEV0_EPF6_STRAP4
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x15
+#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x16
+#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x17
+#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6_MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6_MASK 0x00200000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6_MASK 0x00400000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6_MASK 0x0F800000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6_MASK 0x70000000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP5
+#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6_MASK 0x0000FFFFL
+//RCC_DEV0_EPF6_STRAP6
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6_MASK 0x00000001L
+//RCC_DEV0_EPF6_STRAP13
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x8
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6_MASK 0x000000FFL
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6_MASK 0x0000FF00L
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6_MASK 0x00FF0000L
+//RCC_DEV1_EPF0_STRAP0
+#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x10
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x1c
+#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x1d
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x1e
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x1f
+#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0_MASK 0x0000FFFFL
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0_MASK 0x000F0000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0_MASK 0x00F00000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0_MASK 0x10000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0_MASK 0x20000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0_MASK 0x40000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0_MASK 0x80000000L
+//RCC_DEV1_EPF0_STRAP2
+#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x7
+#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x8
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0__SHIFT 0x9
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0xe
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0xf
+#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x10
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x11
+#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x15
+#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x17
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x18
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0__SHIFT 0x1c
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0__SHIFT 0x1d
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0__SHIFT 0x1e
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0__SHIFT 0x1f
+#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0_MASK 0x00000080L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0_MASK 0x00000100L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0_MASK 0x00003E00L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0_MASK 0x00004000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0_MASK 0x00008000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0_MASK 0x00010000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0_MASK 0x00020000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0_MASK 0x00100000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0_MASK 0x00200000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0_MASK 0x00800000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0_MASK 0x07000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0_MASK 0x10000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0_MASK 0x20000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0_MASK 0x40000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0_MASK 0x80000000L
+//RCC_DEV1_EPF0_STRAP3
+#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x1
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x2
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x12
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x13
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x18
+#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT 0x19
+#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x1a
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x1b
+#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0_MASK 0x00000001L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0_MASK 0x00000002L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0_MASK 0x0003FFFCL
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0_MASK 0x00040000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0_MASK 0x00080000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0_MASK 0x00100000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0_MASK 0x01000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0_MASK 0x02000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0_MASK 0x04000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0_MASK 0x08000000L
+//RCC_DEV1_EPF0_STRAP4
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x15
+#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x16
+#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x17
+#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x1c
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0_MASK 0x00100000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0_MASK 0x00200000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0_MASK 0x00400000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0_MASK 0x0F800000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0_MASK 0x70000000L
+//RCC_DEV1_EPF0_STRAP5
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT 0x18
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV1_F0__SHIFT 0x19
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV1_F0__SHIFT 0x1a
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0_MASK 0x0000FFFFL
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0_MASK 0x01000000L
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV1_F0_MASK 0x02000000L
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV1_F0_MASK 0x04000000L
+//RCC_DEV1_EPF0_STRAP6
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0_MASK 0x00000001L
+//RCC_DEV1_EPF0_STRAP7
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_EN_DEV1_F0__SHIFT 0x16
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV1_F0__SHIFT 0x17
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV1_F0__SHIFT 0x18
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV1_F0__SHIFT 0x1a
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV1_F0_MASK 0x00300000L
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_EN_DEV1_F0_MASK 0x00400000L
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV1_F0_MASK 0x00800000L
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV1_F0_MASK 0x03000000L
+#define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV1_F0_MASK 0xFC000000L
+//RCC_DEV1_EPF0_STRAP13
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x8
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x10
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0_MASK 0x000000FFL
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0_MASK 0x0000FF00L
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0_MASK 0x00FF0000L
+//RCC_DEV2_EPF0_STRAP0
+#define RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0__SHIFT 0x10
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0__SHIFT 0x14
+#define RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0__SHIFT 0x1c
+#define RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0__SHIFT 0x1d
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0__SHIFT 0x1e
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0__SHIFT 0x1f
+#define RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0_MASK 0x0000FFFFL
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0_MASK 0x000F0000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0_MASK 0x00F00000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0_MASK 0x10000000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0_MASK 0x20000000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0_MASK 0x40000000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0_MASK 0x80000000L
+//RCC_DEV2_EPF0_STRAP2
+#define RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0__SHIFT 0x7
+#define RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0__SHIFT 0x8
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0__SHIFT 0x9
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0__SHIFT 0xe
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0__SHIFT 0xf
+#define RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0__SHIFT 0x10
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0__SHIFT 0x11
+#define RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0__SHIFT 0x14
+#define RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0__SHIFT 0x15
+#define RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0__SHIFT 0x17
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0__SHIFT 0x18
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0__SHIFT 0x1c
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0__SHIFT 0x1d
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0__SHIFT 0x1e
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0__SHIFT 0x1f
+#define RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK 0x00000080L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0_MASK 0x00000100L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0_MASK 0x00003E00L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0_MASK 0x00004000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0_MASK 0x00008000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0_MASK 0x00010000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0_MASK 0x00020000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0_MASK 0x00100000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0_MASK 0x00200000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0_MASK 0x00800000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0_MASK 0x07000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0_MASK 0x10000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0_MASK 0x20000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0_MASK 0x40000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0_MASK 0x80000000L
+//RCC_DEV2_EPF0_STRAP3
+#define RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0__SHIFT 0x1
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0__SHIFT 0x2
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0__SHIFT 0x12
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0__SHIFT 0x13
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0__SHIFT 0x14
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0__SHIFT 0x18
+#define RCC_DEV2_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV2_F0__SHIFT 0x19
+#define RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0__SHIFT 0x1a
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0__SHIFT 0x1b
+#define RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0_MASK 0x00000001L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0_MASK 0x00000002L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0_MASK 0x0003FFFCL
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0_MASK 0x00040000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0_MASK 0x00080000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0_MASK 0x00100000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0_MASK 0x01000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV2_F0_MASK 0x02000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0_MASK 0x04000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0_MASK 0x08000000L
+//RCC_DEV2_EPF0_STRAP4
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0__SHIFT 0x14
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0__SHIFT 0x15
+#define RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0__SHIFT 0x16
+#define RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0__SHIFT 0x17
+#define RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0__SHIFT 0x1c
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0_MASK 0x00100000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0_MASK 0x00200000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0_MASK 0x00400000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0_MASK 0x0F800000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0_MASK 0x70000000L
+//RCC_DEV2_EPF0_STRAP5
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV2_F0__SHIFT 0x18
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV2_F0__SHIFT 0x19
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV2_F0__SHIFT 0x1a
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0_MASK 0x0000FFFFL
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV2_F0_MASK 0x01000000L
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV2_F0_MASK 0x02000000L
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV2_F0_MASK 0x04000000L
+//RCC_DEV2_EPF0_STRAP6
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0_MASK 0x00000001L
+//RCC_DEV2_EPF0_STRAP7
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV2_F0__SHIFT 0x14
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_EN_DEV2_F0__SHIFT 0x16
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV2_F0__SHIFT 0x17
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV2_F0__SHIFT 0x18
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV2_F0__SHIFT 0x1a
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV2_F0_MASK 0x00300000L
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_EN_DEV2_F0_MASK 0x00400000L
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV2_F0_MASK 0x00800000L
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV2_F0_MASK 0x03000000L
+#define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV2_F0_MASK 0xFC000000L
+//RCC_DEV2_EPF0_STRAP13
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0__SHIFT 0x8
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0__SHIFT 0x10
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0_MASK 0x000000FFL
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0_MASK 0x0000FF00L
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0_MASK 0x00FF0000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC
+//RCC_DEV0_1_RCC_VDM_SUPPORT
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV0_1_RCC_BUS_CNTL
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV0_1_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+//RCC_DEV0_1_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV0_1_RCC_MH_ARB_CNTL
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC
+//RCC_EP_DEV0_1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC
+//RCC_DWN_DEV0_1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC
+//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk
+//MISC_SCRATCH
+#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0
+#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL
+//INTR_LINE_POLARITY
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL
+//INTR_LINE_ENABLE
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL
+//OUTSTANDING_VC_ALLOC
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L
+//BIFC_MISC_CTRL0
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT 0xd
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14
+#define BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS__SHIFT 0x17
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK 0x00000200L
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK 0x00002000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L
+#define BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS_MASK 0x00800000L
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x02000000L
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L
+//BIFC_MISC_CTRL1
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14
+#define BIFC_MISC_CTRL1__GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x15
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L
+#define BIFC_MISC_CTRL1__GSI_SMN_POSTWR_MULTI_EN_MASK 0x00200000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L
+//BIFC_BME_ERR_LOG
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK 0x00000080L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK 0x00800000L
+//BIFC_RCCBIH_BME_ERR_LOG0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00000080L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00800000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L
+//BIFC_DMA_ATTR_CNTL2_DEV0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L
+//BME_DUMMY_CNTL_0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L
+//BIFC_THT_CNTL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8
+#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x10
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L
+#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x00010000L
+//BIFC_HSTARB_CNTL
+#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0
+#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L
+//BIFC_GSI_CNTL
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT 0xe
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK 0x00004000L
+//BIFC_PCIEFUNC_CNTL
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L
+//BIFC_PASID_CHECK_DIS
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT 0x2
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT 0x3
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK 0x00000004L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK 0x00000008L
+//BIFC_SDP_CNTL_0
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L
+//BIFC_SDP_CNTL_1
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L
+//BIFC_PASID_STS
+#define BIFC_PASID_STS__PASID_STS__SHIFT 0x0
+#define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL
+//BIFC_ATHUB_ACT_CNTL
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS__SHIFT 0x9
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS__SHIFT 0xa
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT 0xb
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS_MASK 0x00000200L
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS_MASK 0x00000400L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK 0x00000800L
+//BIFC_PERF_CNTL_0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x003F0000L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x3F000000L
+//BIFC_PERF_CNTL_1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000100L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000200L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x003F0000L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x7F000000L
+//BIFC_PERF_CNT_MMIO_RD
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_MMIO_WR
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_RD
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_WR
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK 0xFFFFFFFFL
+//NBIF_REGIF_ERRSET_CTRL
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//NBIF_PGMST_CTRL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//NBIF_PGSLV_CTRL
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+//NBIF_PG_MISC_CTRL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0xb
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0xc
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM__SHIFT 0xd
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0xf
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000800L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00001000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM_MASK 0x00002000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00008000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L
+//SMN_MST_EP_CNTL3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L
+//SMN_MST_EP_CNTL4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L
+//SMN_MST_CNTL1
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L
+//SMN_MST_EP_CNTL5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L
+//BIF_SELFRING_BUFFER_VID
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L
+//BIF_SELFRING_VECTOR_CNTL
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L
+//NBIF_STRAP_WRITE_CTRL
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L
+//NBIF_INTX_DSTATE_MISC_CNTL
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L
+//NBIF_PENDING_MISC_CNTL
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L
+//BIF_GMI_WRR_WEIGHT
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE__SHIFT 0x1f
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE_MASK 0x80000000L
+//BIF_GMI_WRR_WEIGHT2
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L
+//BIF_GMI_WRR_WEIGHT3
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L
+//NBIF_PWRBRK_REQUEST
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L
+//BIF_ATOMIC_ERR_LOG_DEV0_F0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F4
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F5
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F6
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F7
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7_MASK 0x00080000L
+//BIF_DMA_MP4_ERR_LOG
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x0
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x1
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x10
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x11
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK 0x00000001L
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00000002L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK 0x00010000L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00020000L
+//BIF_PASID_ERR_LOG
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT 0x0
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT 0x1
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2__SHIFT 0x2
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3__SHIFT 0x3
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK 0x00000001L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK 0x00000002L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2_MASK 0x00000004L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3_MASK 0x00000008L
+//BIF_PASID_ERR_CLR
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT 0x2
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT 0x3
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK 0x00000004L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK 0x00000008L
+//NBIF_VWIRE_CTRL
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x0
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x10
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK 0x00000200L
+//NBIF_SMN_VWR_VCHG_RST_CTRL0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK 0x00000200L
+//NBIF_SMN_VWR_VCHG_TRIG
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK 0x00000200L
+//NBIF_SMN_VWR_WTRIG_CNTL
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT 0x7
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT 0x8
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT 0x9
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK 0x00000080L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK 0x00000100L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK 0x00000200L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK 0x00000200L
+//NBIF_MGCG_CTRL_LCLK
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L
+//NBIF_DS_CTRL_LCLK
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L
+//SMN_MST_CNTL0
+#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c
+#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L
+//SMN_MST_EP_CNTL1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L
+//SMN_MST_EP_CNTL2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L
+//NBIF_SDP_VWR_VCHG_DIS_CTRL
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_TRIG
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L
+//BIFC_A2S_SDP_PORT_CTRL
+#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+//BIFC_A2S_CNTL_SW0
+#define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP__SHIFT 0x0
+#define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE__SHIFT 0x2
+#define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9
+#define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10
+#define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18
+#define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP_MASK 0x00000003L
+#define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE_MASK 0x0000001CL
+#define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L
+#define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L
+#define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L
+//BIFC_A2S_MISC_CNTL
+#define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0
+#define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2
+#define BIFC_A2S_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x3
+#define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4
+#define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5
+#define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6
+#define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7
+#define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8
+#define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9
+#define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa
+#define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10
+#define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15
+#define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L
+#define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L
+#define BIFC_A2S_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000008L
+#define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L
+#define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L
+#define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L
+#define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L
+#define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L
+#define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L
+#define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L
+#define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L
+#define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L
+//BIFC_A2S_TAG_ALLOC_0
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L
+#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L
+//BIFC_A2S_TAG_ALLOC_1
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L
+#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L
+//BIFC_A2S_CNTL_CL0
+#define BIFC_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0
+#define BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2
+#define BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4
+#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
+#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
+#define BIFC_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa
+#define BIFC_A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc
+#define BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe
+#define BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10
+#define BIFC_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12
+#define BIFC_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14
+#define BIFC_A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L
+#define BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL
+#define BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L
+#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L
+#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L
+#define BIFC_A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L
+#define BIFC_A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L
+#define BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L
+#define BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L
+#define BIFC_A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L
+#define BIFC_A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L
+//BIFC_A2S_CPLBUF_ALLOC_CNTL
+#define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD__SHIFT 0x0
+#define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD__SHIFT 0x14
+#define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD__SHIFT 0x18
+#define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD__SHIFT 0x1c
+#define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD_MASK 0x0000000FL
+#define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD_MASK 0x00F00000L
+#define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD_MASK 0x0F000000L
+#define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD_MASK 0xF0000000L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC
+//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC
+//RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_usb_RCCPFCDEC
+//RCC_PFC_USB_RCC_PFC_LTR_CNTL
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_USB_RCC_PFC_PME_RESTORE
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_rcc_pfc_pd_controller_RCCPFCDEC
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL
+//RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L
+#define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk
+//HARD_RST_CTRL
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L
+#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L
+#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L
+#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L
+#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L
+//SELF_SOFT_RST
+#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1
+#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3
+#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5
+#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b
+#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c
+#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d
+#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e
+#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f
+#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L
+#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L
+#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L
+#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L
+#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L
+#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L
+#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L
+#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L
+//BIF_GFX_DRV_VPU_RST
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L
+//BIF_RST_MISC_CTRL
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L
+//BIF_RST_MISC_CTRL2
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L
+//BIF_RST_MISC_CTRL3
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L
+//BIF_RST_GFXVF_FLR_IDLE
+#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x0
+#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x1
+#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x2
+#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x3
+#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x4
+#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x5
+#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x6
+#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x7
+#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x8
+#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x9
+#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0xa
+#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0xb
+#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0xc
+#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0xd
+#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0xe
+#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0xf
+#define BIF_RST_GFXVF_FLR_IDLE__VF16_TRANS_IDLE__SHIFT 0x10
+#define BIF_RST_GFXVF_FLR_IDLE__VF17_TRANS_IDLE__SHIFT 0x11
+#define BIF_RST_GFXVF_FLR_IDLE__VF18_TRANS_IDLE__SHIFT 0x12
+#define BIF_RST_GFXVF_FLR_IDLE__VF19_TRANS_IDLE__SHIFT 0x13
+#define BIF_RST_GFXVF_FLR_IDLE__VF20_TRANS_IDLE__SHIFT 0x14
+#define BIF_RST_GFXVF_FLR_IDLE__VF21_TRANS_IDLE__SHIFT 0x15
+#define BIF_RST_GFXVF_FLR_IDLE__VF22_TRANS_IDLE__SHIFT 0x16
+#define BIF_RST_GFXVF_FLR_IDLE__VF23_TRANS_IDLE__SHIFT 0x17
+#define BIF_RST_GFXVF_FLR_IDLE__VF24_TRANS_IDLE__SHIFT 0x18
+#define BIF_RST_GFXVF_FLR_IDLE__VF25_TRANS_IDLE__SHIFT 0x19
+#define BIF_RST_GFXVF_FLR_IDLE__VF26_TRANS_IDLE__SHIFT 0x1a
+#define BIF_RST_GFXVF_FLR_IDLE__VF27_TRANS_IDLE__SHIFT 0x1b
+#define BIF_RST_GFXVF_FLR_IDLE__VF28_TRANS_IDLE__SHIFT 0x1c
+#define BIF_RST_GFXVF_FLR_IDLE__VF29_TRANS_IDLE__SHIFT 0x1d
+#define BIF_RST_GFXVF_FLR_IDLE__VF30_TRANS_IDLE__SHIFT 0x1e
+#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f
+#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE_MASK 0x00000001L
+#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE_MASK 0x00000002L
+#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE_MASK 0x00000004L
+#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE_MASK 0x00000008L
+#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE_MASK 0x00000010L
+#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE_MASK 0x00000020L
+#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE_MASK 0x00000040L
+#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE_MASK 0x00000080L
+#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE_MASK 0x00000100L
+#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE_MASK 0x00000200L
+#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE_MASK 0x00000400L
+#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE_MASK 0x00000800L
+#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE_MASK 0x00001000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE_MASK 0x00002000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE_MASK 0x00004000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE_MASK 0x00008000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF16_TRANS_IDLE_MASK 0x00010000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF17_TRANS_IDLE_MASK 0x00020000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF18_TRANS_IDLE_MASK 0x00040000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF19_TRANS_IDLE_MASK 0x00080000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF20_TRANS_IDLE_MASK 0x00100000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF21_TRANS_IDLE_MASK 0x00200000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF22_TRANS_IDLE_MASK 0x00400000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF23_TRANS_IDLE_MASK 0x00800000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF24_TRANS_IDLE_MASK 0x01000000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF25_TRANS_IDLE_MASK 0x02000000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF26_TRANS_IDLE_MASK 0x04000000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF27_TRANS_IDLE_MASK 0x08000000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF28_TRANS_IDLE_MASK 0x10000000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF29_TRANS_IDLE_MASK 0x20000000L
+#define BIF_RST_GFXVF_FLR_IDLE__VF30_TRANS_IDLE_MASK 0x40000000L
+#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE_MASK 0x80000000L
+//DEV0_PF0_FLR_RST_CTRL
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L
+//DEV0_PF1_FLR_RST_CTRL
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF2_FLR_RST_CTRL
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF3_FLR_RST_CTRL
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF4_FLR_RST_CTRL
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF5_FLR_RST_CTRL
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF6_FLR_RST_CTRL
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF7_FLR_RST_CTRL
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//BIF_INST_RESET_INTR_STS
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L
+//BIF_PF_FLR_INTR_STS
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK 0x00000080L
+//BIF_D3HOTD0_INTR_STS
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK 0x00000080L
+//BIF_POWER_INTR_STS
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L
+//BIF_PF_DSTATE_INTR_STS
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L
+//SELF_SOFT_RST_2
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x0
+#define SELF_SOFT_RST_2__NBIF_S5_RST__SHIFT 0x1e
+#define SELF_SOFT_RST_2__NBIF_S5_CDC_RST__SHIFT 0x1f
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x00000001L
+#define SELF_SOFT_RST_2__NBIF_S5_RST_MASK 0x40000000L
+#define SELF_SOFT_RST_2__NBIF_S5_CDC_RST_MASK 0x80000000L
+//BIF_PF0_VF_FLR_INTR_STS
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x0
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x1
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x2
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x3
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x4
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x5
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x6
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x7
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x8
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x9
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0xa
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0xb
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0xc
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0xd
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0xe
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0xf
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF16_FLR_INTR_STS__SHIFT 0x10
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF17_FLR_INTR_STS__SHIFT 0x11
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF18_FLR_INTR_STS__SHIFT 0x12
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF19_FLR_INTR_STS__SHIFT 0x13
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF20_FLR_INTR_STS__SHIFT 0x14
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF21_FLR_INTR_STS__SHIFT 0x15
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF22_FLR_INTR_STS__SHIFT 0x16
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF23_FLR_INTR_STS__SHIFT 0x17
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF24_FLR_INTR_STS__SHIFT 0x18
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF25_FLR_INTR_STS__SHIFT 0x19
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF26_FLR_INTR_STS__SHIFT 0x1a
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF27_FLR_INTR_STS__SHIFT 0x1b
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF28_FLR_INTR_STS__SHIFT 0x1c
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF29_FLR_INTR_STS__SHIFT 0x1d
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF30_FLR_INTR_STS__SHIFT 0x1e
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS_MASK 0x00000001L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS_MASK 0x00000002L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS_MASK 0x00000004L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS_MASK 0x00000008L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS_MASK 0x00000010L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS_MASK 0x00000020L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS_MASK 0x00000040L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS_MASK 0x00000080L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS_MASK 0x00000100L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS_MASK 0x00000200L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS_MASK 0x00000400L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS_MASK 0x00000800L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS_MASK 0x00001000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS_MASK 0x00002000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS_MASK 0x00004000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS_MASK 0x00008000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF16_FLR_INTR_STS_MASK 0x00010000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF17_FLR_INTR_STS_MASK 0x00020000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF18_FLR_INTR_STS_MASK 0x00040000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF19_FLR_INTR_STS_MASK 0x00080000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF20_FLR_INTR_STS_MASK 0x00100000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF21_FLR_INTR_STS_MASK 0x00200000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF22_FLR_INTR_STS_MASK 0x00400000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF23_FLR_INTR_STS_MASK 0x00800000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF24_FLR_INTR_STS_MASK 0x01000000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF25_FLR_INTR_STS_MASK 0x02000000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF26_FLR_INTR_STS_MASK 0x04000000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF27_FLR_INTR_STS_MASK 0x08000000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF28_FLR_INTR_STS_MASK 0x10000000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF29_FLR_INTR_STS_MASK 0x20000000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF30_FLR_INTR_STS_MASK 0x40000000L
+#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS_MASK 0x80000000L
+//BIF_INST_RESET_INTR_MASK
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L
+//BIF_PF_FLR_INTR_MASK
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK 0x00000080L
+//BIF_D3HOTD0_INTR_MASK
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK 0x00000080L
+//BIF_POWER_INTR_MASK
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L
+//BIF_PF_DSTATE_INTR_MASK
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L
+//BIF_PF0_VF_FLR_INTR_MASK
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x0
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x1
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x2
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x3
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x4
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x5
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x6
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x7
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x8
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x9
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0xa
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0xb
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0xc
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0xd
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0xe
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0xf
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF16_FLR_INTR_MASK__SHIFT 0x10
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF17_FLR_INTR_MASK__SHIFT 0x11
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF18_FLR_INTR_MASK__SHIFT 0x12
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF19_FLR_INTR_MASK__SHIFT 0x13
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF20_FLR_INTR_MASK__SHIFT 0x14
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF21_FLR_INTR_MASK__SHIFT 0x15
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF22_FLR_INTR_MASK__SHIFT 0x16
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF23_FLR_INTR_MASK__SHIFT 0x17
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF24_FLR_INTR_MASK__SHIFT 0x18
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF25_FLR_INTR_MASK__SHIFT 0x19
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF26_FLR_INTR_MASK__SHIFT 0x1a
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF27_FLR_INTR_MASK__SHIFT 0x1b
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF28_FLR_INTR_MASK__SHIFT 0x1c
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF29_FLR_INTR_MASK__SHIFT 0x1d
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF30_FLR_INTR_MASK__SHIFT 0x1e
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK_MASK 0x00000001L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK_MASK 0x00000002L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK_MASK 0x00000004L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK_MASK 0x00000008L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK_MASK 0x00000010L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK_MASK 0x00000020L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK_MASK 0x00000040L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK_MASK 0x00000080L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK_MASK 0x00000100L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK_MASK 0x00000200L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK_MASK 0x00000400L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK_MASK 0x00000800L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK_MASK 0x00001000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK_MASK 0x00002000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK_MASK 0x00004000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK_MASK 0x00008000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF16_FLR_INTR_MASK_MASK 0x00010000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF17_FLR_INTR_MASK_MASK 0x00020000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF18_FLR_INTR_MASK_MASK 0x00040000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF19_FLR_INTR_MASK_MASK 0x00080000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF20_FLR_INTR_MASK_MASK 0x00100000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF21_FLR_INTR_MASK_MASK 0x00200000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF22_FLR_INTR_MASK_MASK 0x00400000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF23_FLR_INTR_MASK_MASK 0x00800000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF24_FLR_INTR_MASK_MASK 0x01000000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF25_FLR_INTR_MASK_MASK 0x02000000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF26_FLR_INTR_MASK_MASK 0x04000000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF27_FLR_INTR_MASK_MASK 0x08000000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF28_FLR_INTR_MASK_MASK 0x10000000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF29_FLR_INTR_MASK_MASK 0x20000000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF30_FLR_INTR_MASK_MASK 0x40000000L
+#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK_MASK 0x80000000L
+//BIF_PF_FLR_RST
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L
+//BIF_PF0_VF_FLR_RST
+#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0
+#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1
+#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2
+#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3
+#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4
+#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5
+#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6
+#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7
+#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8
+#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9
+#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa
+#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb
+#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc
+#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd
+#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe
+#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf
+#define BIF_PF0_VF_FLR_RST__PF0_VF16_FLR_RST__SHIFT 0x10
+#define BIF_PF0_VF_FLR_RST__PF0_VF17_FLR_RST__SHIFT 0x11
+#define BIF_PF0_VF_FLR_RST__PF0_VF18_FLR_RST__SHIFT 0x12
+#define BIF_PF0_VF_FLR_RST__PF0_VF19_FLR_RST__SHIFT 0x13
+#define BIF_PF0_VF_FLR_RST__PF0_VF20_FLR_RST__SHIFT 0x14
+#define BIF_PF0_VF_FLR_RST__PF0_VF21_FLR_RST__SHIFT 0x15
+#define BIF_PF0_VF_FLR_RST__PF0_VF22_FLR_RST__SHIFT 0x16
+#define BIF_PF0_VF_FLR_RST__PF0_VF23_FLR_RST__SHIFT 0x17
+#define BIF_PF0_VF_FLR_RST__PF0_VF24_FLR_RST__SHIFT 0x18
+#define BIF_PF0_VF_FLR_RST__PF0_VF25_FLR_RST__SHIFT 0x19
+#define BIF_PF0_VF_FLR_RST__PF0_VF26_FLR_RST__SHIFT 0x1a
+#define BIF_PF0_VF_FLR_RST__PF0_VF27_FLR_RST__SHIFT 0x1b
+#define BIF_PF0_VF_FLR_RST__PF0_VF28_FLR_RST__SHIFT 0x1c
+#define BIF_PF0_VF_FLR_RST__PF0_VF29_FLR_RST__SHIFT 0x1d
+#define BIF_PF0_VF_FLR_RST__PF0_VF30_FLR_RST__SHIFT 0x1e
+#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f
+#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L
+#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L
+#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L
+#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L
+#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L
+#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L
+#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L
+#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L
+#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L
+#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L
+#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L
+#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L
+#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF16_FLR_RST_MASK 0x00010000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF17_FLR_RST_MASK 0x00020000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF18_FLR_RST_MASK 0x00040000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF19_FLR_RST_MASK 0x00080000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF20_FLR_RST_MASK 0x00100000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF21_FLR_RST_MASK 0x00200000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF22_FLR_RST_MASK 0x00400000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF23_FLR_RST_MASK 0x00800000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF24_FLR_RST_MASK 0x01000000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF25_FLR_RST_MASK 0x02000000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF26_FLR_RST_MASK 0x04000000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF27_FLR_RST_MASK 0x08000000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF28_FLR_RST_MASK 0x10000000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF29_FLR_RST_MASK 0x20000000L
+#define BIF_PF0_VF_FLR_RST__PF0_VF30_FLR_RST_MASK 0x40000000L
+#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L
+//BIF_DEV0_PF0_DSTATE_VALUE
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF1_DSTATE_VALUE
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF2_DSTATE_VALUE
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF3_DSTATE_VALUE
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF4_DSTATE_VALUE
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF5_DSTATE_VALUE
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF6_DSTATE_VALUE
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF7_DSTATE_VALUE
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L
+//DEV0_PF0_D3HOTD0_RST_CTRL
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF1_D3HOTD0_RST_CTRL
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF2_D3HOTD0_RST_CTRL
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF3_D3HOTD0_RST_CTRL
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF4_D3HOTD0_RST_CTRL
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF5_D3HOTD0_RST_CTRL
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF6_D3HOTD0_RST_CTRL
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF7_D3HOTD0_RST_CTRL
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//BIF_PORT0_DSTATE_VALUE
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_USB_SHUB_RS_RESET_CNTL
+#define BIF_USB_SHUB_RS_RESET_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define BIF_USB_SHUB_RS_RESET_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define BIF_USB_SHUB_RS_RESET_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define BIF_USB_SHUB_RS_RESET_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
+//BIFL_RAS_CENTRAL_CNTL
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT 0x1d
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT 0x1e
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT 0x1f
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK 0x20000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK 0x40000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK 0x80000000L
+//BIFL_RAS_CENTRAL_STATUS
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT 0x0
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT 0x1
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT 0x2
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT 0x3
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT 0x1d
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT 0x1e
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT 0x1f
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK 0x00000001L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK 0x00000002L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK 0x00000004L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK 0x00000008L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK 0x20000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK 0x40000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK 0x80000000L
+//BIFL_RAS_LEAF0_CTRL
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//BIFL_RAS_LEAF1_CTRL
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//BIFL_RAS_LEAF2_CTRL
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//BIFL_RAS_LEAF3_CTRL
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//BIFL_RAS_LEAF4_CTRL
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8
+#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L
+#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//BIFL_RAS_LEAF0_STATUS
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF1_STATUS
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF2_STATUS
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF3_STATUS
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF4_STATUS
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_IOHUB_RAS_IH_CNTL
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT 0x0
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK 0x00000001L
+//BIFL_RAS_VWR_FROM_IOHUB
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT 0x0
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_bif_swus_SUMDEC
+//SUM_INDEX
+#define SUM_INDEX__SUM_INDEX__SHIFT 0x0
+#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL
+//SUM_DATA
+#define SUM_DATA__SUM_DATA__SHIFT 0x0
+#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_COMMAND
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_STATUS
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_LATENCY
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_HEADER
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_BIST
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_COMMAND
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_STATUS
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_LATENCY
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_HEADER
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_BIST
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_COMMAND
+#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_STATUS
+#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_LATENCY
+#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_HEADER
+#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_BIST
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_SBRN
+#define BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_FLADJ
+#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF2_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_COMMAND
+#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_STATUS
+#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_LATENCY
+#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_HEADER
+#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_BIST
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_SBRN
+#define BIF_CFG_DEV0_EPF3_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_FLADJ
+#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF3_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF3_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF3_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF3_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF3_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_BIST
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_BIST
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF2_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_HEADER
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_BIST
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF3_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_HEADER
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_BIST
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF4_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_HEADER
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_BIST
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF5_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_HEADER
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_BIST
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF6_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_HEADER
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_BIST
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF7_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_HEADER
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_BIST
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF8_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_HEADER
+#define BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF8_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_BIST
+#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF8_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF9_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_HEADER
+#define BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF9_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_BIST
+#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF9_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF10_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_HEADER
+#define BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF10_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_BIST
+#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF10_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF11_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_HEADER
+#define BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF11_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_BIST
+#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF11_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF12_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_HEADER
+#define BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF12_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_BIST
+#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF12_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF13_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_HEADER
+#define BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF13_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_BIST
+#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF13_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF14_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_HEADER
+#define BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF14_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_BIST
+#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF14_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF15_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_HEADER
+#define BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF15_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_BIST
+#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF15_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF16_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF16_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF16_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF16_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF16_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF16_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF16_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_HEADER
+#define BIF_CFG_DEV0_EPF0_VF16_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF16_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF16_BIST
+#define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF16_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF16_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF16_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF17_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF17_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF17_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF17_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF17_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF17_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF17_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_HEADER
+#define BIF_CFG_DEV0_EPF0_VF17_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF17_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF17_BIST
+#define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF17_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF17_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF17_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF18_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF18_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF18_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF18_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF18_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF18_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF18_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_HEADER
+#define BIF_CFG_DEV0_EPF0_VF18_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF18_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF18_BIST
+#define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF18_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF18_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF18_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF19_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF19_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF19_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF19_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF19_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF19_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF19_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_HEADER
+#define BIF_CFG_DEV0_EPF0_VF19_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF19_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF19_BIST
+#define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF19_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF19_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF19_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF20_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF20_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF20_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF20_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF20_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF20_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF20_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_HEADER
+#define BIF_CFG_DEV0_EPF0_VF20_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF20_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF20_BIST
+#define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF20_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF20_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF20_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF21_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF21_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF21_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF21_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF21_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF21_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF21_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_HEADER
+#define BIF_CFG_DEV0_EPF0_VF21_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF21_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF21_BIST
+#define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF21_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF21_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF21_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF22_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF22_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF22_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF22_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF22_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF22_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF22_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_HEADER
+#define BIF_CFG_DEV0_EPF0_VF22_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF22_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF22_BIST
+#define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF22_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF22_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF22_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF23_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF23_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF23_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF23_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF23_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF23_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF23_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_HEADER
+#define BIF_CFG_DEV0_EPF0_VF23_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF23_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF23_BIST
+#define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF23_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF23_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF23_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF24_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF24_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF24_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF24_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF24_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF24_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF24_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_HEADER
+#define BIF_CFG_DEV0_EPF0_VF24_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF24_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF24_BIST
+#define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF24_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF24_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF24_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF25_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF25_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF25_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF25_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF25_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF25_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF25_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_HEADER
+#define BIF_CFG_DEV0_EPF0_VF25_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF25_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF25_BIST
+#define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF25_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF25_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF25_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF26_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF26_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF26_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF26_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF26_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF26_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF26_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_HEADER
+#define BIF_CFG_DEV0_EPF0_VF26_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF26_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF26_BIST
+#define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF26_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF26_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF26_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF27_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF27_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF27_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF27_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF27_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF27_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF27_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_HEADER
+#define BIF_CFG_DEV0_EPF0_VF27_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF27_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF27_BIST
+#define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF27_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF27_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF27_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF28_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF28_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF28_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF28_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF28_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF28_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF28_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_HEADER
+#define BIF_CFG_DEV0_EPF0_VF28_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF28_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF28_BIST
+#define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF28_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF28_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF28_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF29_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF29_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF29_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF29_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF29_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF29_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF29_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_HEADER
+#define BIF_CFG_DEV0_EPF0_VF29_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF29_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF29_BIST
+#define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF29_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF29_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF29_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF30_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF30_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF30_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF30_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF30_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF30_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF30_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_HEADER
+#define BIF_CFG_DEV0_EPF0_VF30_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF30_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF30_BIST
+#define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF30_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF30_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF30_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_pciemsix_0_usb_MSIXTDEC
+//PCIEMSIX_VECT0_ADDR_LO
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT0_ADDR_HI
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT0_MSG_DATA
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT0_CONTROL
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT1_ADDR_LO
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT1_ADDR_HI
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT1_MSG_DATA
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT1_CONTROL
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT2_ADDR_LO
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT2_ADDR_HI
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT2_MSG_DATA
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT2_CONTROL
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT3_ADDR_LO
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT3_ADDR_HI
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT3_MSG_DATA
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT3_CONTROL
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT4_ADDR_LO
+#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT4_ADDR_HI
+#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT4_MSG_DATA
+#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT4_CONTROL
+#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT5_ADDR_LO
+#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT5_ADDR_HI
+#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT5_MSG_DATA
+#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT5_CONTROL
+#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT6_ADDR_LO
+#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT6_ADDR_HI
+#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT6_MSG_DATA
+#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT6_CONTROL
+#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT7_ADDR_LO
+#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT7_ADDR_HI
+#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT7_MSG_DATA
+#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT7_CONTROL
+#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT8_ADDR_LO
+#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT8_ADDR_HI
+#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT8_MSG_DATA
+#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT8_CONTROL
+#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT9_ADDR_LO
+#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT9_ADDR_HI
+#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT9_MSG_DATA
+#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT9_CONTROL
+#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT10_ADDR_LO
+#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT10_ADDR_HI
+#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT10_MSG_DATA
+#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT10_CONTROL
+#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT11_ADDR_LO
+#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT11_ADDR_HI
+#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT11_MSG_DATA
+#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT11_CONTROL
+#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT12_ADDR_LO
+#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT12_ADDR_HI
+#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT12_MSG_DATA
+#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT12_CONTROL
+#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT13_ADDR_LO
+#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT13_ADDR_HI
+#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT13_MSG_DATA
+#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT13_CONTROL
+#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT14_ADDR_LO
+#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT14_ADDR_HI
+#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT14_MSG_DATA
+#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT14_CONTROL
+#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT15_ADDR_LO
+#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT15_ADDR_HI
+#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT15_MSG_DATA
+#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT15_CONTROL
+#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT16_ADDR_LO
+#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT16_ADDR_HI
+#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT16_MSG_DATA
+#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT16_CONTROL
+#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT17_ADDR_LO
+#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT17_ADDR_HI
+#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT17_MSG_DATA
+#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT17_CONTROL
+#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT18_ADDR_LO
+#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT18_ADDR_HI
+#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT18_MSG_DATA
+#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT18_CONTROL
+#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT19_ADDR_LO
+#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT19_ADDR_HI
+#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT19_MSG_DATA
+#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT19_CONTROL
+#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT20_ADDR_LO
+#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT20_ADDR_HI
+#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT20_MSG_DATA
+#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT20_CONTROL
+#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT21_ADDR_LO
+#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT21_ADDR_HI
+#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT21_MSG_DATA
+#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT21_CONTROL
+#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT22_ADDR_LO
+#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT22_ADDR_HI
+#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT22_MSG_DATA
+#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT22_CONTROL
+#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT23_ADDR_LO
+#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT23_ADDR_HI
+#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT23_MSG_DATA
+#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT23_CONTROL
+#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT24_ADDR_LO
+#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT24_ADDR_HI
+#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT24_MSG_DATA
+#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT24_CONTROL
+#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT25_ADDR_LO
+#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT25_ADDR_HI
+#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT25_MSG_DATA
+#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT25_CONTROL
+#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT26_ADDR_LO
+#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT26_ADDR_HI
+#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT26_MSG_DATA
+#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT26_CONTROL
+#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT27_ADDR_LO
+#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT27_ADDR_HI
+#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT27_MSG_DATA
+#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT27_CONTROL
+#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT28_ADDR_LO
+#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT28_ADDR_HI
+#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT28_MSG_DATA
+#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT28_CONTROL
+#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT29_ADDR_LO
+#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT29_ADDR_HI
+#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT29_MSG_DATA
+#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT29_CONTROL
+#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT30_ADDR_LO
+#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT30_ADDR_HI
+#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT30_MSG_DATA
+#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT30_CONTROL
+#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT31_ADDR_LO
+#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT31_ADDR_HI
+#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT31_MSG_DATA
+#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT31_CONTROL
+#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT32_ADDR_LO
+#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT32_ADDR_HI
+#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT32_MSG_DATA
+#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT32_CONTROL
+#define PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT33_ADDR_LO
+#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT33_ADDR_HI
+#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT33_MSG_DATA
+#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT33_CONTROL
+#define PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT34_ADDR_LO
+#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT34_ADDR_HI
+#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT34_MSG_DATA
+#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT34_CONTROL
+#define PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT35_ADDR_LO
+#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT35_ADDR_HI
+#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT35_MSG_DATA
+#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT35_CONTROL
+#define PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT36_ADDR_LO
+#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT36_ADDR_HI
+#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT36_MSG_DATA
+#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT36_CONTROL
+#define PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT37_ADDR_LO
+#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT37_ADDR_HI
+#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT37_MSG_DATA
+#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT37_CONTROL
+#define PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT38_ADDR_LO
+#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT38_ADDR_HI
+#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT38_MSG_DATA
+#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT38_CONTROL
+#define PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT39_ADDR_LO
+#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT39_ADDR_HI
+#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT39_MSG_DATA
+#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT39_CONTROL
+#define PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT40_ADDR_LO
+#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT40_ADDR_HI
+#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT40_MSG_DATA
+#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT40_CONTROL
+#define PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT41_ADDR_LO
+#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT41_ADDR_HI
+#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT41_MSG_DATA
+#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT41_CONTROL
+#define PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT42_ADDR_LO
+#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT42_ADDR_HI
+#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT42_MSG_DATA
+#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT42_CONTROL
+#define PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT43_ADDR_LO
+#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT43_ADDR_HI
+#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT43_MSG_DATA
+#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT43_CONTROL
+#define PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT44_ADDR_LO
+#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT44_ADDR_HI
+#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT44_MSG_DATA
+#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT44_CONTROL
+#define PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT45_ADDR_LO
+#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT45_ADDR_HI
+#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT45_MSG_DATA
+#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT45_CONTROL
+#define PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT46_ADDR_LO
+#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT46_ADDR_HI
+#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT46_MSG_DATA
+#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT46_CONTROL
+#define PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT47_ADDR_LO
+#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT47_ADDR_HI
+#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT47_MSG_DATA
+#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT47_CONTROL
+#define PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT48_ADDR_LO
+#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT48_ADDR_HI
+#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT48_MSG_DATA
+#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT48_CONTROL
+#define PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT49_ADDR_LO
+#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT49_ADDR_HI
+#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT49_MSG_DATA
+#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT49_CONTROL
+#define PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT50_ADDR_LO
+#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT50_ADDR_HI
+#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT50_MSG_DATA
+#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT50_CONTROL
+#define PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT51_ADDR_LO
+#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT51_ADDR_HI
+#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT51_MSG_DATA
+#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT51_CONTROL
+#define PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT52_ADDR_LO
+#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT52_ADDR_HI
+#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT52_MSG_DATA
+#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT52_CONTROL
+#define PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT53_ADDR_LO
+#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT53_ADDR_HI
+#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT53_MSG_DATA
+#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT53_CONTROL
+#define PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT54_ADDR_LO
+#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT54_ADDR_HI
+#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT54_MSG_DATA
+#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT54_CONTROL
+#define PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT55_ADDR_LO
+#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT55_ADDR_HI
+#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT55_MSG_DATA
+#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT55_CONTROL
+#define PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT56_ADDR_LO
+#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT56_ADDR_HI
+#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT56_MSG_DATA
+#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT56_CONTROL
+#define PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT57_ADDR_LO
+#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT57_ADDR_HI
+#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT57_MSG_DATA
+#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT57_CONTROL
+#define PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT58_ADDR_LO
+#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT58_ADDR_HI
+#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT58_MSG_DATA
+#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT58_CONTROL
+#define PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT59_ADDR_LO
+#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT59_ADDR_HI
+#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT59_MSG_DATA
+#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT59_CONTROL
+#define PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT60_ADDR_LO
+#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT60_ADDR_HI
+#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT60_MSG_DATA
+#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT60_CONTROL
+#define PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT61_ADDR_LO
+#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT61_ADDR_HI
+#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT61_MSG_DATA
+#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT61_CONTROL
+#define PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT62_ADDR_LO
+#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT62_ADDR_HI
+#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT62_MSG_DATA
+#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT62_CONTROL
+#define PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT63_ADDR_LO
+#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT63_ADDR_HI
+#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT63_MSG_DATA
+#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT63_CONTROL
+#define PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT64_ADDR_LO
+#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT64_ADDR_HI
+#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT64_MSG_DATA
+#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT64_CONTROL
+#define PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT65_ADDR_LO
+#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT65_ADDR_HI
+#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT65_MSG_DATA
+#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT65_CONTROL
+#define PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT66_ADDR_LO
+#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT66_ADDR_HI
+#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT66_MSG_DATA
+#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT66_CONTROL
+#define PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT67_ADDR_LO
+#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT67_ADDR_HI
+#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT67_MSG_DATA
+#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT67_CONTROL
+#define PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT68_ADDR_LO
+#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT68_ADDR_HI
+#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT68_MSG_DATA
+#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT68_CONTROL
+#define PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT69_ADDR_LO
+#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT69_ADDR_HI
+#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT69_MSG_DATA
+#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT69_CONTROL
+#define PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT70_ADDR_LO
+#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT70_ADDR_HI
+#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT70_MSG_DATA
+#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT70_CONTROL
+#define PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT71_ADDR_LO
+#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT71_ADDR_HI
+#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT71_MSG_DATA
+#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT71_CONTROL
+#define PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT72_ADDR_LO
+#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT72_ADDR_HI
+#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT72_MSG_DATA
+#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT72_CONTROL
+#define PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT73_ADDR_LO
+#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT73_ADDR_HI
+#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT73_MSG_DATA
+#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT73_CONTROL
+#define PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT74_ADDR_LO
+#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT74_ADDR_HI
+#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT74_MSG_DATA
+#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT74_CONTROL
+#define PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT75_ADDR_LO
+#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT75_ADDR_HI
+#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT75_MSG_DATA
+#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT75_CONTROL
+#define PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT76_ADDR_LO
+#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT76_ADDR_HI
+#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT76_MSG_DATA
+#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT76_CONTROL
+#define PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT77_ADDR_LO
+#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT77_ADDR_HI
+#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT77_MSG_DATA
+#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT77_CONTROL
+#define PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT78_ADDR_LO
+#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT78_ADDR_HI
+#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT78_MSG_DATA
+#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT78_CONTROL
+#define PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT79_ADDR_LO
+#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT79_ADDR_HI
+#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT79_MSG_DATA
+#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT79_CONTROL
+#define PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT80_ADDR_LO
+#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT80_ADDR_HI
+#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT80_MSG_DATA
+#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT80_CONTROL
+#define PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT81_ADDR_LO
+#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT81_ADDR_HI
+#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT81_MSG_DATA
+#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT81_CONTROL
+#define PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT82_ADDR_LO
+#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT82_ADDR_HI
+#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT82_MSG_DATA
+#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT82_CONTROL
+#define PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT83_ADDR_LO
+#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT83_ADDR_HI
+#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT83_MSG_DATA
+#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT83_CONTROL
+#define PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT84_ADDR_LO
+#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT84_ADDR_HI
+#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT84_MSG_DATA
+#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT84_CONTROL
+#define PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT85_ADDR_LO
+#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT85_ADDR_HI
+#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT85_MSG_DATA
+#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT85_CONTROL
+#define PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT86_ADDR_LO
+#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT86_ADDR_HI
+#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT86_MSG_DATA
+#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT86_CONTROL
+#define PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT87_ADDR_LO
+#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT87_ADDR_HI
+#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT87_MSG_DATA
+#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT87_CONTROL
+#define PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT88_ADDR_LO
+#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT88_ADDR_HI
+#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT88_MSG_DATA
+#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT88_CONTROL
+#define PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT89_ADDR_LO
+#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT89_ADDR_HI
+#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT89_MSG_DATA
+#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT89_CONTROL
+#define PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT90_ADDR_LO
+#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT90_ADDR_HI
+#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT90_MSG_DATA
+#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT90_CONTROL
+#define PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT91_ADDR_LO
+#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT91_ADDR_HI
+#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT91_MSG_DATA
+#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT91_CONTROL
+#define PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT92_ADDR_LO
+#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT92_ADDR_HI
+#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT92_MSG_DATA
+#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT92_CONTROL
+#define PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT93_ADDR_LO
+#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT93_ADDR_HI
+#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT93_MSG_DATA
+#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT93_CONTROL
+#define PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT94_ADDR_LO
+#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT94_ADDR_HI
+#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT94_MSG_DATA
+#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT94_CONTROL
+#define PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT95_ADDR_LO
+#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT95_ADDR_HI
+#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT95_MSG_DATA
+#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT95_CONTROL
+#define PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT96_ADDR_LO
+#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT96_ADDR_HI
+#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT96_MSG_DATA
+#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT96_CONTROL
+#define PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT97_ADDR_LO
+#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT97_ADDR_HI
+#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT97_MSG_DATA
+#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT97_CONTROL
+#define PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT98_ADDR_LO
+#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT98_ADDR_HI
+#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT98_MSG_DATA
+#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT98_CONTROL
+#define PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT99_ADDR_LO
+#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT99_ADDR_HI
+#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT99_MSG_DATA
+#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT99_CONTROL
+#define PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT100_ADDR_LO
+#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT100_ADDR_HI
+#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT100_MSG_DATA
+#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT100_CONTROL
+#define PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT101_ADDR_LO
+#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT101_ADDR_HI
+#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT101_MSG_DATA
+#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT101_CONTROL
+#define PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT102_ADDR_LO
+#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT102_ADDR_HI
+#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT102_MSG_DATA
+#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT102_CONTROL
+#define PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT103_ADDR_LO
+#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT103_ADDR_HI
+#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT103_MSG_DATA
+#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT103_CONTROL
+#define PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT104_ADDR_LO
+#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT104_ADDR_HI
+#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT104_MSG_DATA
+#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT104_CONTROL
+#define PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT105_ADDR_LO
+#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT105_ADDR_HI
+#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT105_MSG_DATA
+#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT105_CONTROL
+#define PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT106_ADDR_LO
+#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT106_ADDR_HI
+#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT106_MSG_DATA
+#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT106_CONTROL
+#define PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT107_ADDR_LO
+#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT107_ADDR_HI
+#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT107_MSG_DATA
+#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT107_CONTROL
+#define PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT108_ADDR_LO
+#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT108_ADDR_HI
+#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT108_MSG_DATA
+#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT108_CONTROL
+#define PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT109_ADDR_LO
+#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT109_ADDR_HI
+#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT109_MSG_DATA
+#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT109_CONTROL
+#define PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT110_ADDR_LO
+#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT110_ADDR_HI
+#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT110_MSG_DATA
+#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT110_CONTROL
+#define PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT111_ADDR_LO
+#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT111_ADDR_HI
+#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT111_MSG_DATA
+#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT111_CONTROL
+#define PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT112_ADDR_LO
+#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT112_ADDR_HI
+#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT112_MSG_DATA
+#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT112_CONTROL
+#define PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT113_ADDR_LO
+#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT113_ADDR_HI
+#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT113_MSG_DATA
+#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT113_CONTROL
+#define PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT114_ADDR_LO
+#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT114_ADDR_HI
+#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT114_MSG_DATA
+#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT114_CONTROL
+#define PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT115_ADDR_LO
+#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT115_ADDR_HI
+#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT115_MSG_DATA
+#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT115_CONTROL
+#define PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT116_ADDR_LO
+#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT116_ADDR_HI
+#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT116_MSG_DATA
+#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT116_CONTROL
+#define PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT117_ADDR_LO
+#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT117_ADDR_HI
+#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT117_MSG_DATA
+#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT117_CONTROL
+#define PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT118_ADDR_LO
+#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT118_ADDR_HI
+#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT118_MSG_DATA
+#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT118_CONTROL
+#define PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT119_ADDR_LO
+#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT119_ADDR_HI
+#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT119_MSG_DATA
+#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT119_CONTROL
+#define PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT120_ADDR_LO
+#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT120_ADDR_HI
+#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT120_MSG_DATA
+#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT120_CONTROL
+#define PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT121_ADDR_LO
+#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT121_ADDR_HI
+#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT121_MSG_DATA
+#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT121_CONTROL
+#define PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT122_ADDR_LO
+#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT122_ADDR_HI
+#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT122_MSG_DATA
+#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT122_CONTROL
+#define PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT123_ADDR_LO
+#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT123_ADDR_HI
+#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT123_MSG_DATA
+#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT123_CONTROL
+#define PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT124_ADDR_LO
+#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT124_ADDR_HI
+#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT124_MSG_DATA
+#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT124_CONTROL
+#define PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT125_ADDR_LO
+#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT125_ADDR_HI
+#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT125_MSG_DATA
+#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT125_CONTROL
+#define PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT126_ADDR_LO
+#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT126_ADDR_HI
+#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT126_MSG_DATA
+#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT126_CONTROL
+#define PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT127_ADDR_LO
+#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT127_ADDR_HI
+#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT127_MSG_DATA
+#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT127_CONTROL
+#define PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT128_ADDR_LO
+#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT128_ADDR_HI
+#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT128_MSG_DATA
+#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT128_CONTROL
+#define PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT129_ADDR_LO
+#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT129_ADDR_HI
+#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT129_MSG_DATA
+#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT129_CONTROL
+#define PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT130_ADDR_LO
+#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT130_ADDR_HI
+#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT130_MSG_DATA
+#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT130_CONTROL
+#define PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT131_ADDR_LO
+#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT131_ADDR_HI
+#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT131_MSG_DATA
+#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT131_CONTROL
+#define PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT132_ADDR_LO
+#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT132_ADDR_HI
+#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT132_MSG_DATA
+#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT132_CONTROL
+#define PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT133_ADDR_LO
+#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT133_ADDR_HI
+#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT133_MSG_DATA
+#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT133_CONTROL
+#define PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT134_ADDR_LO
+#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT134_ADDR_HI
+#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT134_MSG_DATA
+#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT134_CONTROL
+#define PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT135_ADDR_LO
+#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT135_ADDR_HI
+#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT135_MSG_DATA
+#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT135_CONTROL
+#define PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT136_ADDR_LO
+#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT136_ADDR_HI
+#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT136_MSG_DATA
+#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT136_CONTROL
+#define PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT137_ADDR_LO
+#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT137_ADDR_HI
+#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT137_MSG_DATA
+#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT137_CONTROL
+#define PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT138_ADDR_LO
+#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT138_ADDR_HI
+#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT138_MSG_DATA
+#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT138_CONTROL
+#define PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT139_ADDR_LO
+#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT139_ADDR_HI
+#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT139_MSG_DATA
+#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT139_CONTROL
+#define PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT140_ADDR_LO
+#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT140_ADDR_HI
+#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT140_MSG_DATA
+#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT140_CONTROL
+#define PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT141_ADDR_LO
+#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT141_ADDR_HI
+#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT141_MSG_DATA
+#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT141_CONTROL
+#define PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT142_ADDR_LO
+#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT142_ADDR_HI
+#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT142_MSG_DATA
+#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT142_CONTROL
+#define PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT143_ADDR_LO
+#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT143_ADDR_HI
+#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT143_MSG_DATA
+#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT143_CONTROL
+#define PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT144_ADDR_LO
+#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT144_ADDR_HI
+#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT144_MSG_DATA
+#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT144_CONTROL
+#define PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT145_ADDR_LO
+#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT145_ADDR_HI
+#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT145_MSG_DATA
+#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT145_CONTROL
+#define PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT146_ADDR_LO
+#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT146_ADDR_HI
+#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT146_MSG_DATA
+#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT146_CONTROL
+#define PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT147_ADDR_LO
+#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT147_ADDR_HI
+#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT147_MSG_DATA
+#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT147_CONTROL
+#define PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT148_ADDR_LO
+#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT148_ADDR_HI
+#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT148_MSG_DATA
+#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT148_CONTROL
+#define PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT149_ADDR_LO
+#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT149_ADDR_HI
+#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT149_MSG_DATA
+#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT149_CONTROL
+#define PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT150_ADDR_LO
+#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT150_ADDR_HI
+#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT150_MSG_DATA
+#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT150_CONTROL
+#define PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT151_ADDR_LO
+#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT151_ADDR_HI
+#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT151_MSG_DATA
+#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT151_CONTROL
+#define PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT152_ADDR_LO
+#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT152_ADDR_HI
+#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT152_MSG_DATA
+#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT152_CONTROL
+#define PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT153_ADDR_LO
+#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT153_ADDR_HI
+#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT153_MSG_DATA
+#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT153_CONTROL
+#define PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT154_ADDR_LO
+#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT154_ADDR_HI
+#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT154_MSG_DATA
+#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT154_CONTROL
+#define PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT155_ADDR_LO
+#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT155_ADDR_HI
+#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT155_MSG_DATA
+#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT155_CONTROL
+#define PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT156_ADDR_LO
+#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT156_ADDR_HI
+#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT156_MSG_DATA
+#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT156_CONTROL
+#define PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT157_ADDR_LO
+#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT157_ADDR_HI
+#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT157_MSG_DATA
+#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT157_CONTROL
+#define PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT158_ADDR_LO
+#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT158_ADDR_HI
+#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT158_MSG_DATA
+#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT158_CONTROL
+#define PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT159_ADDR_LO
+#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT159_ADDR_HI
+#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT159_MSG_DATA
+#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT159_CONTROL
+#define PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT160_ADDR_LO
+#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT160_ADDR_HI
+#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT160_MSG_DATA
+#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT160_CONTROL
+#define PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT161_ADDR_LO
+#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT161_ADDR_HI
+#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT161_MSG_DATA
+#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT161_CONTROL
+#define PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT162_ADDR_LO
+#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT162_ADDR_HI
+#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT162_MSG_DATA
+#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT162_CONTROL
+#define PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT163_ADDR_LO
+#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT163_ADDR_HI
+#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT163_MSG_DATA
+#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT163_CONTROL
+#define PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT164_ADDR_LO
+#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT164_ADDR_HI
+#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT164_MSG_DATA
+#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT164_CONTROL
+#define PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT165_ADDR_LO
+#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT165_ADDR_HI
+#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT165_MSG_DATA
+#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT165_CONTROL
+#define PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT166_ADDR_LO
+#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT166_ADDR_HI
+#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT166_MSG_DATA
+#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT166_CONTROL
+#define PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT167_ADDR_LO
+#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT167_ADDR_HI
+#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT167_MSG_DATA
+#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT167_CONTROL
+#define PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT168_ADDR_LO
+#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT168_ADDR_HI
+#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT168_MSG_DATA
+#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT168_CONTROL
+#define PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT169_ADDR_LO
+#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT169_ADDR_HI
+#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT169_MSG_DATA
+#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT169_CONTROL
+#define PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT170_ADDR_LO
+#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT170_ADDR_HI
+#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT170_MSG_DATA
+#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT170_CONTROL
+#define PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT171_ADDR_LO
+#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT171_ADDR_HI
+#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT171_MSG_DATA
+#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT171_CONTROL
+#define PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT172_ADDR_LO
+#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT172_ADDR_HI
+#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT172_MSG_DATA
+#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT172_CONTROL
+#define PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT173_ADDR_LO
+#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT173_ADDR_HI
+#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT173_MSG_DATA
+#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT173_CONTROL
+#define PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT174_ADDR_LO
+#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT174_ADDR_HI
+#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT174_MSG_DATA
+#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT174_CONTROL
+#define PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT175_ADDR_LO
+#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT175_ADDR_HI
+#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT175_MSG_DATA
+#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT175_CONTROL
+#define PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT176_ADDR_LO
+#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT176_ADDR_HI
+#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT176_MSG_DATA
+#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT176_CONTROL
+#define PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT177_ADDR_LO
+#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT177_ADDR_HI
+#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT177_MSG_DATA
+#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT177_CONTROL
+#define PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT178_ADDR_LO
+#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT178_ADDR_HI
+#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT178_MSG_DATA
+#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT178_CONTROL
+#define PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT179_ADDR_LO
+#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT179_ADDR_HI
+#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT179_MSG_DATA
+#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT179_CONTROL
+#define PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT180_ADDR_LO
+#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT180_ADDR_HI
+#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT180_MSG_DATA
+#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT180_CONTROL
+#define PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT181_ADDR_LO
+#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT181_ADDR_HI
+#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT181_MSG_DATA
+#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT181_CONTROL
+#define PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT182_ADDR_LO
+#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT182_ADDR_HI
+#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT182_MSG_DATA
+#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT182_CONTROL
+#define PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT183_ADDR_LO
+#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT183_ADDR_HI
+#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT183_MSG_DATA
+#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT183_CONTROL
+#define PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT184_ADDR_LO
+#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT184_ADDR_HI
+#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT184_MSG_DATA
+#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT184_CONTROL
+#define PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT185_ADDR_LO
+#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT185_ADDR_HI
+#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT185_MSG_DATA
+#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT185_CONTROL
+#define PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT186_ADDR_LO
+#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT186_ADDR_HI
+#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT186_MSG_DATA
+#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT186_CONTROL
+#define PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT187_ADDR_LO
+#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT187_ADDR_HI
+#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT187_MSG_DATA
+#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT187_CONTROL
+#define PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT188_ADDR_LO
+#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT188_ADDR_HI
+#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT188_MSG_DATA
+#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT188_CONTROL
+#define PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT189_ADDR_LO
+#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT189_ADDR_HI
+#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT189_MSG_DATA
+#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT189_CONTROL
+#define PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT190_ADDR_LO
+#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT190_ADDR_HI
+#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT190_MSG_DATA
+#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT190_CONTROL
+#define PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT191_ADDR_LO
+#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT191_ADDR_HI
+#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT191_MSG_DATA
+#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT191_CONTROL
+#define PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT192_ADDR_LO
+#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT192_ADDR_HI
+#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT192_MSG_DATA
+#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT192_CONTROL
+#define PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT193_ADDR_LO
+#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT193_ADDR_HI
+#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT193_MSG_DATA
+#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT193_CONTROL
+#define PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT194_ADDR_LO
+#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT194_ADDR_HI
+#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT194_MSG_DATA
+#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT194_CONTROL
+#define PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT195_ADDR_LO
+#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT195_ADDR_HI
+#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT195_MSG_DATA
+#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT195_CONTROL
+#define PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT196_ADDR_LO
+#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT196_ADDR_HI
+#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT196_MSG_DATA
+#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT196_CONTROL
+#define PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT197_ADDR_LO
+#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT197_ADDR_HI
+#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT197_MSG_DATA
+#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT197_CONTROL
+#define PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT198_ADDR_LO
+#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT198_ADDR_HI
+#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT198_MSG_DATA
+#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT198_CONTROL
+#define PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT199_ADDR_LO
+#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT199_ADDR_HI
+#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT199_MSG_DATA
+#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT199_CONTROL
+#define PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT200_ADDR_LO
+#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT200_ADDR_HI
+#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT200_MSG_DATA
+#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT200_CONTROL
+#define PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT201_ADDR_LO
+#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT201_ADDR_HI
+#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT201_MSG_DATA
+#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT201_CONTROL
+#define PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT202_ADDR_LO
+#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT202_ADDR_HI
+#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT202_MSG_DATA
+#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT202_CONTROL
+#define PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT203_ADDR_LO
+#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT203_ADDR_HI
+#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT203_MSG_DATA
+#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT203_CONTROL
+#define PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT204_ADDR_LO
+#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT204_ADDR_HI
+#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT204_MSG_DATA
+#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT204_CONTROL
+#define PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT205_ADDR_LO
+#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT205_ADDR_HI
+#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT205_MSG_DATA
+#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT205_CONTROL
+#define PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT206_ADDR_LO
+#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT206_ADDR_HI
+#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT206_MSG_DATA
+#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT206_CONTROL
+#define PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT207_ADDR_LO
+#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT207_ADDR_HI
+#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT207_MSG_DATA
+#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT207_CONTROL
+#define PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT208_ADDR_LO
+#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT208_ADDR_HI
+#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT208_MSG_DATA
+#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT208_CONTROL
+#define PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT209_ADDR_LO
+#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT209_ADDR_HI
+#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT209_MSG_DATA
+#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT209_CONTROL
+#define PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT210_ADDR_LO
+#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT210_ADDR_HI
+#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT210_MSG_DATA
+#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT210_CONTROL
+#define PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT211_ADDR_LO
+#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT211_ADDR_HI
+#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT211_MSG_DATA
+#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT211_CONTROL
+#define PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT212_ADDR_LO
+#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT212_ADDR_HI
+#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT212_MSG_DATA
+#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT212_CONTROL
+#define PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT213_ADDR_LO
+#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT213_ADDR_HI
+#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT213_MSG_DATA
+#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT213_CONTROL
+#define PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT214_ADDR_LO
+#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT214_ADDR_HI
+#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT214_MSG_DATA
+#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT214_CONTROL
+#define PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT215_ADDR_LO
+#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT215_ADDR_HI
+#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT215_MSG_DATA
+#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT215_CONTROL
+#define PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT216_ADDR_LO
+#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT216_ADDR_HI
+#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT216_MSG_DATA
+#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT216_CONTROL
+#define PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT217_ADDR_LO
+#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT217_ADDR_HI
+#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT217_MSG_DATA
+#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT217_CONTROL
+#define PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT218_ADDR_LO
+#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT218_ADDR_HI
+#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT218_MSG_DATA
+#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT218_CONTROL
+#define PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT219_ADDR_LO
+#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT219_ADDR_HI
+#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT219_MSG_DATA
+#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT219_CONTROL
+#define PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT220_ADDR_LO
+#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT220_ADDR_HI
+#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT220_MSG_DATA
+#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT220_CONTROL
+#define PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT221_ADDR_LO
+#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT221_ADDR_HI
+#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT221_MSG_DATA
+#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT221_CONTROL
+#define PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT222_ADDR_LO
+#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT222_ADDR_HI
+#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT222_MSG_DATA
+#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT222_CONTROL
+#define PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT223_ADDR_LO
+#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT223_ADDR_HI
+#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT223_MSG_DATA
+#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT223_CONTROL
+#define PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT224_ADDR_LO
+#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT224_ADDR_HI
+#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT224_MSG_DATA
+#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT224_CONTROL
+#define PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT225_ADDR_LO
+#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT225_ADDR_HI
+#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT225_MSG_DATA
+#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT225_CONTROL
+#define PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT226_ADDR_LO
+#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT226_ADDR_HI
+#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT226_MSG_DATA
+#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT226_CONTROL
+#define PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT227_ADDR_LO
+#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT227_ADDR_HI
+#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT227_MSG_DATA
+#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT227_CONTROL
+#define PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT228_ADDR_LO
+#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT228_ADDR_HI
+#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT228_MSG_DATA
+#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT228_CONTROL
+#define PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT229_ADDR_LO
+#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT229_ADDR_HI
+#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT229_MSG_DATA
+#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT229_CONTROL
+#define PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT230_ADDR_LO
+#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT230_ADDR_HI
+#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT230_MSG_DATA
+#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT230_CONTROL
+#define PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT231_ADDR_LO
+#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT231_ADDR_HI
+#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT231_MSG_DATA
+#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT231_CONTROL
+#define PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT232_ADDR_LO
+#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT232_ADDR_HI
+#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT232_MSG_DATA
+#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT232_CONTROL
+#define PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT233_ADDR_LO
+#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT233_ADDR_HI
+#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT233_MSG_DATA
+#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT233_CONTROL
+#define PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT234_ADDR_LO
+#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT234_ADDR_HI
+#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT234_MSG_DATA
+#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT234_CONTROL
+#define PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT235_ADDR_LO
+#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT235_ADDR_HI
+#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT235_MSG_DATA
+#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT235_CONTROL
+#define PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT236_ADDR_LO
+#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT236_ADDR_HI
+#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT236_MSG_DATA
+#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT236_CONTROL
+#define PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT237_ADDR_LO
+#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT237_ADDR_HI
+#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT237_MSG_DATA
+#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT237_CONTROL
+#define PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT238_ADDR_LO
+#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT238_ADDR_HI
+#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT238_MSG_DATA
+#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT238_CONTROL
+#define PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT239_ADDR_LO
+#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT239_ADDR_HI
+#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT239_MSG_DATA
+#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT239_CONTROL
+#define PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT240_ADDR_LO
+#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT240_ADDR_HI
+#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT240_MSG_DATA
+#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT240_CONTROL
+#define PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT241_ADDR_LO
+#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT241_ADDR_HI
+#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT241_MSG_DATA
+#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT241_CONTROL
+#define PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT242_ADDR_LO
+#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT242_ADDR_HI
+#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT242_MSG_DATA
+#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT242_CONTROL
+#define PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT243_ADDR_LO
+#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT243_ADDR_HI
+#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT243_MSG_DATA
+#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT243_CONTROL
+#define PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT244_ADDR_LO
+#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT244_ADDR_HI
+#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT244_MSG_DATA
+#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT244_CONTROL
+#define PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT245_ADDR_LO
+#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT245_ADDR_HI
+#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT245_MSG_DATA
+#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT245_CONTROL
+#define PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT246_ADDR_LO
+#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT246_ADDR_HI
+#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT246_MSG_DATA
+#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT246_CONTROL
+#define PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT247_ADDR_LO
+#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT247_ADDR_HI
+#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT247_MSG_DATA
+#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT247_CONTROL
+#define PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT248_ADDR_LO
+#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT248_ADDR_HI
+#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT248_MSG_DATA
+#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT248_CONTROL
+#define PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT249_ADDR_LO
+#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT249_ADDR_HI
+#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT249_MSG_DATA
+#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT249_CONTROL
+#define PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT250_ADDR_LO
+#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT250_ADDR_HI
+#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT250_MSG_DATA
+#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT250_CONTROL
+#define PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT251_ADDR_LO
+#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT251_ADDR_HI
+#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT251_MSG_DATA
+#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT251_CONTROL
+#define PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT252_ADDR_LO
+#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT252_ADDR_HI
+#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT252_MSG_DATA
+#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT252_CONTROL
+#define PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT253_ADDR_LO
+#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT253_ADDR_HI
+#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT253_MSG_DATA
+#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT253_CONTROL
+#define PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT254_ADDR_LO
+#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT254_ADDR_HI
+#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT254_MSG_DATA
+#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT254_CONTROL
+#define PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK 0x00000001L
+//PCIEMSIX_VECT255_ADDR_LO
+#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIEMSIX_VECT255_ADDR_HI
+#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT255_MSG_DATA
+#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//PCIEMSIX_VECT255_CONTROL
+#define PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_pciemsix_0_usb_MSIXPDEC
+//PCIEMSIX_PBA_0
+#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_1
+#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_2
+#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_3
+#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_4
+#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_5
+#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_6
+#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+//PCIEMSIX_PBA_7
+#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT 0x0
+#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_pcie0_pswusp0_pciedir_p
+//PCIEP_RESERVED
+#define PCIEP_RESERVED__RESERVED__SHIFT 0x0
+#define PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//PCIEP_SCRATCH
+#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//PCIEP_PORT_CNTL
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L
+//PCIE_TX_CNTL
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT 0x1b
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+#define PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK 0x08000000L
+//PCIE_TX_REQUESTER_ID
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//PCIE_TX_VENDOR_SPECIFIC
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L
+//PCIE_TX_REQUEST_NUM_CNTL
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//PCIE_TX_SEQ
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//PCIE_TX_REPLAY
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//PCIE_TX_ACK_LATENCY_LIMIT
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//PCIE_TX_NOP_DLLP
+#define PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0
+#define PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18
+#define PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL
+#define PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L
+//PCIE_TX_CNTL_2
+#define PCIE_TX_CNTL_2__TX_SKID_CREDIT_LIMIT__SHIFT 0x0
+#define PCIE_TX_CNTL_2__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT 0x4
+#define PCIE_TX_CNTL_2__TX_SKID_CREDIT_LIMIT_MASK 0x0000000FL
+#define PCIE_TX_CNTL_2__TX_SKID_CREDIT_OVERRIDE_EN_MASK 0x00000010L
+//PCIE_TX_CREDITS_ADVT_P
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L
+//PCIE_TX_CREDITS_ADVT_NP
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L
+//PCIE_TX_CREDITS_ADVT_CPL
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L
+//PCIE_TX_CREDITS_INIT_P
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//PCIE_TX_CREDITS_INIT_NP
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//PCIE_TX_CREDITS_INIT_CPL
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//PCIE_TX_CREDITS_STATUS
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//PCIE_TX_CREDITS_FCU_THRESHOLD
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//PCIE_P_PORT_LANE_STATUS
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//PCIE_FC_P
+#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define PCIE_FC_P__PH_CREDITS__SHIFT 0x10
+#define PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL
+#define PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L
+//PCIE_FC_NP
+#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10
+#define PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL
+#define PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L
+//PCIE_FC_CPL
+#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10
+#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL
+#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L
+//PCIE_FC_P_VC1
+#define PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0
+#define PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10
+#define PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL
+#define PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L
+//PCIE_FC_NP_VC1
+#define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0
+#define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10
+#define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL
+#define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L
+//PCIE_FC_CPL_VC1
+#define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0
+#define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10
+#define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL
+#define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L
+//PSWUSP0_PCIE_ERR_CNTL
+#define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd
+#define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13
+#define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14
+#define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x00001000L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x00002000L
+#define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L
+#define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L
+//PSWUSP0_PCIE_RX_CNTL
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+#define PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L
+//PCIE_RX_EXPECTED_SEQNUM
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//PCIE_RX_VENDOR_SPECIFIC
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//PCIE_RX_CNTL3
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//PCIE_RX_CREDITS_ALLOCATED_P
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//PCIE_RX_CREDITS_ALLOCATED_NP
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//PCIE_RX_CREDITS_ALLOCATED_CPL
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//PCIEP_ERROR_INJECT_PHYSICAL
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//PCIEP_ERROR_INJECT_TRANSACTION
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//PCIEP_SRIOV_PRIV_CTRL
+#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT 0x0
+#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x2
+#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK 0x00000003L
+#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x0000000CL
+//PCIEP_NAK_COUNTER
+#define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//PCIE_LC_CNTL
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//PCIE_LC_TRAINING_CNTL
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//PCIE_LC_LINK_WIDTH_CNTL
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//PCIE_LC_N_FTS_CNTL
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xe
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xf
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00004000L
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00008000L
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//PSWUSP0_PCIE_LC_SPEED_CNTL
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x3
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x4
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x6
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x7
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x8
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x9
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0xa
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xb
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xd
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xe
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x10
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x11
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x12
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x13
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x14
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x15
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x16
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x17
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x18
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x19
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x1a
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1c
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1d
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1e
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1f
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000008L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000030L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000040L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000080L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000100L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000200L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000400L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00001800L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00002000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x0000C000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00010000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00020000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00040000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00080000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00100000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00200000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00400000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x00800000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x01000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x02000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x0C000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x10000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x20000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x40000000L
+#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x80000000L
+//PCIE_LC_STATE0
+#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//PCIE_LC_STATE1
+#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//PCIE_LC_STATE2
+#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//PCIE_LC_STATE3
+#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//PCIE_LC_STATE4
+#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//PCIE_LC_STATE5
+#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//PCIE_LINK_MANAGEMENT_CNTL2
+#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT 0x17
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT 0x1b
+#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK 0x07800000L
+#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK 0x78000000L
+//PSWUSP0_PCIE_LC_CNTL2
+#define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13
+#define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//PCIE_LC_BW_CHANGE_CNTL
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//PCIE_LC_CDR_CNTL
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//PCIE_LC_LANE_CNTL
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+//PCIE_LC_CNTL3
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc
+#define PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd
+#define PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe
+#define PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT 0xf
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L
+#define PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L
+#define PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L
+#define PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK 0x00008000L
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L
+//PCIE_LC_CNTL4
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT 0x4
+#define PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT 0x5
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT 0x8
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT 0xb
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT 0xc
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT 0xf
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT 0x10
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT 0x11
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT 0x12
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK 0x00000010L
+#define PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK 0x00000020L
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK 0x00000300L
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK 0x00000800L
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK 0x00001000L
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK 0x00008000L
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK 0x00010000L
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK 0x00020000L
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK 0x003C0000L
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//PCIE_LC_CNTL5
+#define PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0
+#define PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2
+#define PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6
+#define PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa
+#define PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10
+#define PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT 0x15
+#define PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16
+#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L
+#define PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL
+#define PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L
+#define PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L
+#define PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L
+#define PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK 0x00200000L
+#define PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L
+#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//PCIE_LC_FORCE_COEFF
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13
+#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L
+#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//PCIE_LC_BEST_EQ_SETTINGS
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0x40000000L
+//PCIE_LC_FORCE_EQ_REQ_COEFF
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L
+//PCIE_LC_CNTL6
+#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6
+#define PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L
+#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL
+#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L
+#define PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L
+#define PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//PCIE_LC_CNTL7
+#define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18
+#define PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19
+#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f
+#define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L
+#define PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L
+#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L
+//PCIE_LINK_MANAGEMENT_STATUS
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//PCIE_LINK_MANAGEMENT_MASK
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//PCIE_LINK_MANAGEMENT_CNTL
+#define PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT 0x1e
+#define PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT 0x1f
+#define PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+#define PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK 0x40000000L
+#define PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK 0x80000000L
+//PCIEP_STRAP_LC
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13
+#define PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14
+#define PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+#define PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L
+#define PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L
+#define PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L
+//PSWUSP0_PCIEP_STRAP_MISC
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L
+#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L
+//PCIEP_STRAP_LC2
+#define PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0
+#define PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1
+#define PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3
+#define PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4
+#define PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7
+#define PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L
+#define PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L
+#define PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L
+#define PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L
+#define PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L
+//PCIE_LC_L1_PM_SUBSTATE
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5
+#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1a
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x04000000L
+//PCIE_LC_L1_PM_SUBSTATE2
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//PCIE_LC_PORT_ORDER
+#define PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//PCIEP_BCH_ECC_CNTL
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//PCIE_LC_CNTL8
+#define PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT 0x0
+#define PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT 0x2
+#define PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT 0x3
+#define PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT 0x7
+#define PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT 0x8
+#define PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT 0x9
+#define PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT 0xa
+#define PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT 0xb
+#define PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT 0xc
+#define PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT 0xd
+#define PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT 0x11
+#define PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT 0x12
+#define PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT 0x16
+#define PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x17
+#define PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT 0x19
+#define PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1a
+#define PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1b
+#define PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT 0x1c
+#define PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x1d
+#define PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x1e
+#define PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK 0x00000003L
+#define PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK 0x00000004L
+#define PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK 0x00000078L
+#define PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK 0x00000080L
+#define PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK 0x00000100L
+#define PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK 0x00000200L
+#define PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK 0x00000400L
+#define PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK 0x00000800L
+#define PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK 0x00001000L
+#define PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK 0x0001E000L
+#define PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK 0x00020000L
+#define PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK 0x003C0000L
+#define PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK 0x00400000L
+#define PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x01800000L
+#define PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK 0x02000000L
+#define PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x04000000L
+#define PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x08000000L
+#define PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK 0x10000000L
+#define PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x20000000L
+#define PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0xC0000000L
+//PCIE_LC_CNTL9
+#define PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x0
+#define PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1
+#define PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x3
+#define PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT 0x4
+#define PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x6
+#define PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x8
+#define PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0xa
+#define PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT 0xb
+#define PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0xc
+#define PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0xd
+#define PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xe
+#define PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT 0x18
+#define PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT 0x19
+#define PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT 0x1a
+#define PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT 0x1b
+#define PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x1c
+#define PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0x1d
+#define PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT 0x1f
+#define PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x00000001L
+#define PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x00000006L
+#define PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK 0x00000008L
+#define PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK 0x00000030L
+#define PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x000000C0L
+#define PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x00000300L
+#define PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000400L
+#define PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK 0x00000800L
+#define PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00001000L
+#define PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00002000L
+#define PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK 0x00FFC000L
+#define PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK 0x01000000L
+#define PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK 0x02000000L
+#define PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK 0x04000000L
+#define PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK 0x08000000L
+#define PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x10000000L
+#define PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x20000000L
+#define PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK 0x80000000L
+//PCIE_LC_FORCE_COEFF2
+#define PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0
+#define PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1
+#define PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7
+#define PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd
+#define PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13
+#define PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L
+#define PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL
+#define PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L
+#define PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L
+#define PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L
+//PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L
+#define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L
+//PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0
+#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1
+#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L
+#define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L
+//PCIE_LC_CNTL10
+#define PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x0
+#define PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT 0x1
+#define PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT 0x2
+#define PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT 0x4
+#define PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT 0x6
+#define PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT 0x10
+#define PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x1a
+#define PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT 0x1b
+#define PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x1d
+#define PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT 0x1e
+#define PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT 0x1f
+#define PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000001L
+#define PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK 0x00000002L
+#define PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK 0x0000000CL
+#define PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK 0x00000030L
+#define PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK 0x0000FFC0L
+#define PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK 0x03FF0000L
+#define PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x04000000L
+#define PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK 0x18000000L
+#define PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x20000000L
+#define PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK 0x40000000L
+#define PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK 0x80000000L
+//PCIE_LC_CNTL11
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9
+#define PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0xd
+#define PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT 0xe
+#define PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT 0xf
+#define PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT 0x10
+#define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT 0x11
+#define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT 0x12
+#define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT 0x13
+#define PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT 0x14
+#define PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x15
+#define PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x16
+#define PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT 0x17
+#define PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT 0x18
+#define PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT 0x1a
+#define PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT 0x1b
+#define PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c
+#define PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT 0x1e
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L
+#define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L
+#define PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00002000L
+#define PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK 0x00004000L
+#define PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK 0x00008000L
+#define PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK 0x00010000L
+#define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK 0x00020000L
+#define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK 0x00040000L
+#define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK 0x00080000L
+#define PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK 0x00100000L
+#define PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00200000L
+#define PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x00400000L
+#define PCIE_LC_CNTL11__LC_LSLD_EN_MASK 0x00800000L
+#define PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK 0x03000000L
+#define PCIE_LC_CNTL11__LC_LSLD_MODE_MASK 0x04000000L
+#define PCIE_LC_CNTL11__LC_LSLD_DONE_MASK 0x08000000L
+#define PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L
+#define PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L
+//PCIE_LC_CNTL12
+#define PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x0
+#define PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0x1
+#define PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x2
+#define PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x3
+#define PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0x4
+#define PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000001L
+#define PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000002L
+#define PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x00000004L
+#define PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000008L
+#define PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000010L
+//PCIE_LC_SAVE_RESTORE_1
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT 0xd
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK 0x00002000L
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L
+#define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L
+//PCIE_LC_SAVE_RESTORE_2
+#define PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0
+#define PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_pcie0_pciedir
+//PCIE_RESERVED
+#define PCIE_RESERVED__RESERVED__SHIFT 0x0
+#define PCIE_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//PCIE_SCRATCH
+#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//PCIE_RX_NUM_NAK
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xFFFFFFFFL
+//PCIE_RX_NUM_NAK_GENERATED
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xFFFFFFFFL
+//PCIE_CNTL
+#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
+#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
+#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
+#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
+#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000EL
+#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001C00L
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L
+#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x00100000L
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L
+#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3F000000L
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L
+//PCIE_CONFIG_CNTL
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9
+#define PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE__SHIFT 0xb
+#define PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT 0xd
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000FL
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L
+#define PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE_MASK 0x00001800L
+#define PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK 0x00006000L
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L
+//PCIE_DEBUG_CNTL
+#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
+#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
+#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0x000000FFL
+#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x00000100L
+//PCIE_TX_TRACKING_ADDR_LO
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT 0x2
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIE_TX_TRACKING_ADDR_HI
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT 0x0
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIE_TX_TRACKING_CTRL_STATUS
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT 0x0
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT 0x1
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT 0x8
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT 0xf
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK 0x00000001L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK 0x0000000EL
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK 0x00007F00L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK 0x00008000L
+//PCIE_BW_BY_UNITID
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN__SHIFT 0x0
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID__SHIFT 0x8
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN_MASK 0x00000001L
+#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_MASK 0x00007F00L
+//PCIE_CNTL2
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
+#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
+#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
+#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
+#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
+#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
+#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003EL
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007C0L
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x00000800L
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x00001000L
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x00002000L
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x00004000L
+#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L
+#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L
+#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L
+#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1F000000L
+#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000L
+#define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000L
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000L
+//PCIE_RX_CNTL2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x00000100L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0x00000E00L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x00001000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x00002000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x00004000L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x03FF0000L
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//PCIE_TX_F0_ATTR_CNTL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x00000003L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0x0000000CL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x00000030L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0x000000C0L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x00000300L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0x00000C00L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x00003000L
+//PCIE_TX_SWUS_ATTR_CNTL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK 0x00000003L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK 0x0000000CL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK 0x00000030L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK 0x000000C0L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK 0x00000300L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK 0x00000C00L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK 0x00003000L
+//PCIE_CI_CNTL
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT 0x10
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT 0x11
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT 0x12
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT 0x13
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT 0x14
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT 0x15
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT 0x16
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT 0x17
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT 0x18
+#define PCIE_CI_CNTL__CI_MSTSPLIT_DIS__SHIFT 0x19
+#define PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS__SHIFT 0x1a
+#define PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE__SHIFT 0x1b
+#define PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS__SHIFT 0x1c
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN__SHIFT 0x1d
+#define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN__SHIFT 0x1e
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN__SHIFT 0x1f
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000C0L
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK 0x00010000L
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK 0x00020000L
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK 0x00040000L
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK 0x00080000L
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK 0x00100000L
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK 0x00200000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK 0x00400000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK 0x00800000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK 0x01000000L
+#define PCIE_CI_CNTL__CI_MSTSPLIT_DIS_MASK 0x02000000L
+#define PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS_MASK 0x04000000L
+#define PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE_MASK 0x08000000L
+#define PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS_MASK 0x10000000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN_MASK 0x20000000L
+#define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN_MASK 0x40000000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN_MASK 0x80000000L
+//PCIE_BUS_CNTL
+#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
+#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x00001000L
+//PCIE_LC_STATE6
+#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
+#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
+#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
+#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
+#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003FL
+#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003F00L
+#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003F0000L
+#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3F000000L
+//PCIE_LC_STATE7
+#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
+#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
+#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
+#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
+#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003FL
+#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003F00L
+#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003F0000L
+#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3F000000L
+//PCIE_LC_STATE8
+#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
+#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
+#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
+#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
+#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003FL
+#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003F00L
+#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003F0000L
+#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3F000000L
+//PCIE_LC_STATE9
+#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
+#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
+#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
+#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
+#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003FL
+#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003F00L
+#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003F0000L
+#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3F000000L
+//PCIE_LC_STATE10
+#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
+#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
+#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
+#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
+#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003FL
+#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003F00L
+#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003F0000L
+#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3F000000L
+//PCIE_LC_STATE11
+#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
+#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
+#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
+#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
+#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003FL
+#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003F00L
+#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003F0000L
+#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3F000000L
+//PCIE_LC_STATUS1
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001CL
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
+//PCIE_LC_STATUS2
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000FFFFL
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xFFFF0000L
+//PCIE_TX_CNTL3
+#define PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS__SHIFT 0x0
+#define PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE__SHIFT 0x1
+#define PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS__SHIFT 0x4
+#define PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS__SHIFT 0x5
+#define PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN__SHIFT 0x6
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN__SHIFT 0x7
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE__SHIFT 0x8
+#define PCIE_TX_CNTL3__TX_ATOMIC_ORD_HASH_MODE__SHIFT 0x10
+#define PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN__SHIFT 0x13
+#define PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN__SHIFT 0x14
+#define PCIE_TX_CNTL3__MCA_CLKGATE_DIS__SHIFT 0x15
+#define PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS_MASK 0x00000001L
+#define PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE_MASK 0x0000000EL
+#define PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS_MASK 0x00000010L
+#define PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS_MASK 0x00000020L
+#define PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN_MASK 0x00000040L
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN_MASK 0x00000080L
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE_MASK 0x0000FF00L
+#define PCIE_TX_CNTL3__TX_ATOMIC_ORD_HASH_MODE_MASK 0x00070000L
+#define PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN_MASK 0x00080000L
+#define PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN_MASK 0x00100000L
+#define PCIE_TX_CNTL3__MCA_CLKGATE_DIS_MASK 0x00200000L
+//PCIE_TX_STATUS
+#define PCIE_TX_STATUS__TX_MST_MEM_READY__SHIFT 0x0
+#define PCIE_TX_STATUS__CI_MST_REQ_IDLE__SHIFT 0x1
+#define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD__SHIFT 0x2
+#define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE__SHIFT 0x3
+#define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE__SHIFT 0x4
+#define PCIE_TX_STATUS__CI_MST_TX_IDLE__SHIFT 0x5
+#define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE__SHIFT 0x6
+#define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE__SHIFT 0x7
+#define PCIE_TX_STATUS__TX_P_HDR_EMPTY__SHIFT 0x8
+#define PCIE_TX_STATUS__TX_NP_HDR_EMPTY__SHIFT 0x9
+#define PCIE_TX_STATUS__TX_P_DAT_EMPTY__SHIFT 0xa
+#define PCIE_TX_STATUS__TX_NP_DAT_EMPTY__SHIFT 0xb
+#define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS__SHIFT 0xc
+#define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS__SHIFT 0xd
+#define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS__SHIFT 0xe
+#define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS__SHIFT 0xf
+#define PCIE_TX_STATUS__TX_MST_MEM_READY_MASK 0x00000001L
+#define PCIE_TX_STATUS__CI_MST_REQ_IDLE_MASK 0x00000002L
+#define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD_MASK 0x00000004L
+#define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE_MASK 0x00000008L
+#define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE_MASK 0x00000010L
+#define PCIE_TX_STATUS__CI_MST_TX_IDLE_MASK 0x00000020L
+#define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE_MASK 0x00000040L
+#define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE_MASK 0x00000080L
+#define PCIE_TX_STATUS__TX_P_HDR_EMPTY_MASK 0x00000100L
+#define PCIE_TX_STATUS__TX_NP_HDR_EMPTY_MASK 0x00000200L
+#define PCIE_TX_STATUS__TX_P_DAT_EMPTY_MASK 0x00000400L
+#define PCIE_TX_STATUS__TX_NP_DAT_EMPTY_MASK 0x00000800L
+#define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS_MASK 0x00001000L
+#define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS_MASK 0x00002000L
+#define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS_MASK 0x00004000L
+#define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS_MASK 0x00008000L
+//PCIE_WPR_CNTL
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L
+//PCIE_RX_LAST_TLP0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP1
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP2
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP3
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP1
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP2
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP3
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xFFFFFFFFL
+//PCIE_I2C_REG_ADDR_EXPAND
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001FFFFL
+//PCIE_I2C_REG_DATA
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xFFFFFFFFL
+//PCIE_CFG_CNTL
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//PCIE_LC_PM_CNTL
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT 0x0
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT 0x4
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT 0x8
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT 0xc
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT 0x10
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT 0x14
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT 0x18
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT 0x1c
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK 0x0000000FL
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK 0x000000F0L
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK 0x00000F00L
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK 0x0000F000L
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK 0x000F0000L
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK 0x00F00000L
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK 0x0F000000L
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK 0xF0000000L
+//PCIE_LC_PORT_ORDER_CNTL
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT 0x0
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK 0x00000001L
+//PCIE_P_CNTL
+#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
+#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT 0x11
+#define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT__SHIFT 0x12
+#define PCIE_P_CNTL__MASTER_PLL_LANE_NUM__SHIFT 0x13
+#define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN__SHIFT 0x17
+#define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL__SHIFT 0x18
+#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L
+#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x00010000L
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK 0x00020000L
+#define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT_MASK 0x00040000L
+#define PCIE_P_CNTL__MASTER_PLL_LANE_NUM_MASK 0x00780000L
+#define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN_MASK 0x00800000L
+#define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL_MASK 0x01000000L
+//PCIE_P_BUF_STATUS
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000FFFFL
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xFFFF0000L
+//PCIE_P_DECODER_STATUS
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000FFFFL
+//PCIE_P_MISC_STATUS
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000FFL
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xFFFF0000L
+//PCIE_P_RCV_L0S_FTS_DET
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000FFL
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000FF00L
+//PCIE_RX_AD
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT 0x0
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT 0x1
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT 0x2
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT 0x3
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT 0x4
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT 0x5
+#define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT 0x8
+#define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT 0x9
+#define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT 0xa
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT 0xb
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT 0xc
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT 0xd
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT 0xe
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT 0xf
+#define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN__SHIFT 0x10
+#define PCIE_RX_AD__RX_RC_UR_POIS_ATOP__SHIFT 0x11
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK 0x00000001L
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK 0x00000002L
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK 0x00000004L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK 0x00000008L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK 0x00000010L
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK 0x00000020L
+#define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK 0x00000100L
+#define PCIE_RX_AD__RX_RC_UR_VDM0_MASK 0x00000200L
+#define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK 0x00000400L
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK 0x00000800L
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK 0x00001000L
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK 0x00002000L
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK 0x00004000L
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK 0x00008000L
+#define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN_MASK 0x00010000L
+#define PCIE_RX_AD__RX_RC_UR_POIS_ATOP_MASK 0x00020000L
+//PCIE_SDP_CTRL
+#define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT 0x0
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT 0x4
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT 0x5
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT 0x6
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT 0x7
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT 0x8
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT 0x9
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT 0xa
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT 0xb
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT 0xc
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT 0xd
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT 0xe
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT 0xf
+#define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN__SHIFT 0x10
+#define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN__SHIFT 0x11
+#define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN__SHIFT 0x12
+#define PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS__SHIFT 0x13
+#define PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN__SHIFT 0x14
+#define PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS__SHIFT 0x15
+#define PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS__SHIFT 0x16
+#define PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS__SHIFT 0x17
+#define PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS__SHIFT 0x18
+#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE__SHIFT 0x19
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER__SHIFT 0x1a
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK 0x0000000FL
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK 0x00000010L
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK 0x00000020L
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK 0x00000040L
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK 0x00000080L
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK 0x00000100L
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK 0x00000200L
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK 0x00000400L
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK 0x00000800L
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK 0x00001000L
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK 0x00002000L
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK 0x00004000L
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK 0x00008000L
+#define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN_MASK 0x00010000L
+#define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN_MASK 0x00020000L
+#define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN_MASK 0x00040000L
+#define PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS_MASK 0x00080000L
+#define PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN_MASK 0x00100000L
+#define PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS_MASK 0x00200000L
+#define PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS_MASK 0x00400000L
+#define PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS_MASK 0x00800000L
+#define PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS_MASK 0x01000000L
+#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE_MASK 0x02000000L
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER_MASK 0x1C000000L
+//PCIE_SDP_SWUS_SLV_ATTR_CTRL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L
+//PCIE_PERF_COUNT_CNTL
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L
+//PCIE_PERF_CNTL_TXCLK1
+#define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK1
+#define PCIE_PERF_COUNT0_TXCLK1__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK1__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK1
+#define PCIE_PERF_COUNT1_TXCLK1__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK1__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK2
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK2
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK2
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK3
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK3
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK3
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK4
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK4
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK4
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SCLK1
+#define PCIE_PERF_CNTL_SCLK1__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SCLK1__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SCLK1__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SCLK1__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SCLK1
+#define PCIE_PERF_COUNT0_SCLK1__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SCLK1__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SCLK1
+#define PCIE_PERF_COUNT1_SCLK1__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SCLK1__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SCLK2
+#define PCIE_PERF_CNTL_SCLK2__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SCLK2__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SCLK2__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SCLK2__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SCLK2
+#define PCIE_PERF_COUNT0_SCLK2__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SCLK2__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SCLK2
+#define PCIE_PERF_COUNT1_SCLK2__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SCLK2__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_EVENT_LC_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1_MASK 0x0000000FL
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1_MASK 0x000000F0L
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x00000F00L
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0000F000L
+//PCIE_PERF_CNTL_EVENT_CI_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2__SHIFT 0x1c
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3_MASK 0x0000000FL
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3_MASK 0x000000F0L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4_MASK 0x00000F00L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4_MASK 0x0000F000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1_MASK 0x000F0000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1_MASK 0x00F00000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2_MASK 0x0F000000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2_MASK 0xF0000000L
+//PCIE_HIP_REG0
+#define PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI__SHIFT 0x0
+#define PCIE_HIP_REG0__CI_HIP_APT0_ENABLE__SHIFT 0x18
+#define PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE__SHIFT 0x19
+#define PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE__SHIFT 0x1a
+#define PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE__SHIFT 0x1d
+#define PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI_MASK 0x000FFFFFL
+#define PCIE_HIP_REG0__CI_HIP_APT0_ENABLE_MASK 0x01000000L
+#define PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE_MASK 0x02000000L
+#define PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE_MASK 0x1C000000L
+#define PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE_MASK 0x60000000L
+//PCIE_HIP_REG1
+#define PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO__SHIFT 0x0
+#define PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO_MASK 0xFFFFFFFFL
+//PCIE_HIP_REG2
+#define PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI__SHIFT 0x0
+#define PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI_MASK 0x000FFFFFL
+//PCIE_HIP_REG3
+#define PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO__SHIFT 0x0
+#define PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO_MASK 0xFFFFFFFFL
+//PCIE_HIP_REG4
+#define PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI__SHIFT 0x0
+#define PCIE_HIP_REG4__CI_HIP_APT1_ENABLE__SHIFT 0x18
+#define PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE__SHIFT 0x19
+#define PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE__SHIFT 0x1a
+#define PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE__SHIFT 0x1d
+#define PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI_MASK 0x000FFFFFL
+#define PCIE_HIP_REG4__CI_HIP_APT1_ENABLE_MASK 0x01000000L
+#define PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE_MASK 0x02000000L
+#define PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE_MASK 0x1C000000L
+#define PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE_MASK 0x60000000L
+//PCIE_HIP_REG5
+#define PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO__SHIFT 0x0
+#define PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO_MASK 0xFFFFFFFFL
+//PCIE_HIP_REG6
+#define PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI__SHIFT 0x0
+#define PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI_MASK 0x000FFFFFL
+//PCIE_HIP_REG7
+#define PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO__SHIFT 0x0
+#define PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO_MASK 0xFFFFFFFFL
+//PCIE_HIP_REG8
+#define PCIE_HIP_REG8__CI_HIP_MASK__SHIFT 0x0
+#define PCIE_HIP_REG8__CI_HIP_MASK_MASK 0x000FFFFFL
+//PCIE_STRAP_F0
+#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
+#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
+#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
+#define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN__SHIFT 0x1d
+#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN__SHIFT 0x1f
+#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x00000004L
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x00000008L
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x00000010L
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x00000020L
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x00000040L
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x00000080L
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x00000100L
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x00000200L
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x00000400L
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x00000800L
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x00001000L
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x00002000L
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x00004000L
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x00008000L
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x00010000L
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x00040000L
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x00080000L
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x00100000L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x07000000L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x08000000L
+#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000L
+#define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN_MASK 0x20000000L
+#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN_MASK 0x80000000L
+//PCIE_STRAP_MISC
+#define PCIE_STRAP_MISC__STRAP_DLF_EN__SHIFT 0x0
+#define PCIE_STRAP_MISC__STRAP_16GT_EN__SHIFT 0x1
+#define PCIE_STRAP_MISC__STRAP_MARGINING_EN__SHIFT 0x2
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
+#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER__SHIFT 0x6
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
+#define PCIE_STRAP_MISC__STRAP_DLF_EN_MASK 0x00000001L
+#define PCIE_STRAP_MISC__STRAP_16GT_EN_MASK 0x00000002L
+#define PCIE_STRAP_MISC__STRAP_MARGINING_EN_MASK 0x00000004L
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x00000010L
+#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER_MASK 0x00000040L
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x04000000L
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000L
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000L
+//PCIE_STRAP_MISC2
+#define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE__SHIFT 0x5
+#define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x00000001L
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x00000002L
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x00000008L
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+#define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE_MASK 0x00000020L
+//PCIE_STRAP_PI
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x00000001L
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000L
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000L
+//PCIE_STRAP_I2C_BD
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x0000007FL
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x00000080L
+//PCIE_PRBS_CLR
+#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
+#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
+#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000FFFFL
+#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0x000F0000L
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x01000000L
+//PCIE_PRBS_STATUS1
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000FFFFL
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xFFFF0000L
+//PCIE_PRBS_STATUS2
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000FFFFL
+//PCIE_PRBS_FREERUN
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000FFFFL
+//PCIE_PRBS_MISC
+#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
+#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x0000000EL
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000010L
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000020L
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x000000C0L
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00001F00L
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000C000L
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xFFFF0000L
+//PCIE_PRBS_USER_PATTERN
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3FFFFFFFL
+//PCIE_PRBS_LO_BITCNT
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xFFFFFFFFL
+//PCIE_PRBS_HI_BITCNT
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000FFL
+//PCIE_PRBS_ERRCNT_0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_1
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_2
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_3
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_4
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_5
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_6
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_7
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_8
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_9
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_10
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_11
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_12
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_13
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_14
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_15
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xFFFFFFFFL
+//SWRST_COMMAND_STATUS
+#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
+#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT 0x18
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT 0x19
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT 0x1a
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT 0x1b
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT 0x1c
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT 0x1d
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT 0x1e
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT 0x1f
+#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x00000001L
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x00000002L
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x00010000L
+#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x00020000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK 0x01000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK 0x02000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK 0x04000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK 0x08000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK 0x10000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK 0x20000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK 0x40000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK 0x80000000L
+//SWRST_GENERAL_CONTROL
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x18
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT 0x19
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x00000001L
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x00000002L
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x0000001CL
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x00000100L
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x00000200L
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x00000400L
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x00001000L
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x01000000L
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK 0x02000000L
+//SWRST_COMMAND_0
+#define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT 0x0
+#define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT 0x8
+#define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT 0x9
+#define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT 0xa
+#define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT 0xb
+#define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT 0xc
+#define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT 0xd
+#define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT 0xe
+#define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT 0xf
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x18
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x19
+#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x1a
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x1b
+#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x1c
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x1d
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x1e
+#define SWRST_COMMAND_0__PORT0_COR_RESET_MASK 0x00000001L
+#define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK 0x00000100L
+#define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK 0x00000200L
+#define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK 0x00000400L
+#define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK 0x00000800L
+#define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK 0x00001000L
+#define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK 0x00002000L
+#define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK 0x00004000L
+#define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK 0x00008000L
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x01000000L
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x02000000L
+#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x04000000L
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x08000000L
+#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x10000000L
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x20000000L
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x40000000L
+//SWRST_COMMAND_1
+#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x15
+#define SWRST_COMMAND_1__RESETAXIMST__SHIFT 0x16
+#define SWRST_COMMAND_1__RESETAXISLV__SHIFT 0x17
+#define SWRST_COMMAND_1__RESETAXIINT__SHIFT 0x18
+#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x19
+#define SWRST_COMMAND_1__RESETLNCT__SHIFT 0x1a
+#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0x1b
+#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0x1c
+#define SWRST_COMMAND_1__RESETCPM__SHIFT 0x1d
+#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x1e
+#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1f
+#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x00200000L
+#define SWRST_COMMAND_1__RESETAXIMST_MASK 0x00400000L
+#define SWRST_COMMAND_1__RESETAXISLV_MASK 0x00800000L
+#define SWRST_COMMAND_1__RESETAXIINT_MASK 0x01000000L
+#define SWRST_COMMAND_1__RESETPCFG_MASK 0x02000000L
+#define SWRST_COMMAND_1__RESETLNCT_MASK 0x04000000L
+#define SWRST_COMMAND_1__RESETMNTR_MASK 0x08000000L
+#define SWRST_COMMAND_1__RESETHLTR_MASK 0x10000000L
+#define SWRST_COMMAND_1__RESETCPM_MASK 0x20000000L
+#define SWRST_COMMAND_1__RESETPHY0_MASK 0x40000000L
+#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x80000000L
+//SWRST_CONTROL_0
+#define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT 0x0
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT 0x8
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT 0x9
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT 0xa
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT 0xb
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT 0xc
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT 0xd
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT 0xe
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT 0xf
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x18
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x19
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x1a
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x1b
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x1c
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x1d
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x1e
+#define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK 0x00000001L
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK 0x00000100L
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK 0x00000200L
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK 0x00000400L
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK 0x00000800L
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK 0x00001000L
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK 0x00002000L
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK 0x00004000L
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK 0x00008000L
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x01000000L
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x02000000L
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x04000000L
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x08000000L
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x10000000L
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x20000000L
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x40000000L
+//SWRST_CONTROL_1
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x15
+#define SWRST_CONTROL_1__RESETAXIMST_RCEN__SHIFT 0x16
+#define SWRST_CONTROL_1__RESETAXISLV_RCEN__SHIFT 0x17
+#define SWRST_CONTROL_1__RESETAXIINT_RCEN__SHIFT 0x18
+#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x19
+#define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT 0x1a
+#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0x1b
+#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0x1c
+#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0x1d
+#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x1e
+#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1f
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x00200000L
+#define SWRST_CONTROL_1__RESETAXIMST_RCEN_MASK 0x00400000L
+#define SWRST_CONTROL_1__RESETAXISLV_RCEN_MASK 0x00800000L
+#define SWRST_CONTROL_1__RESETAXIINT_RCEN_MASK 0x01000000L
+#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x02000000L
+#define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK 0x04000000L
+#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x08000000L
+#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x10000000L
+#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x20000000L
+#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x40000000L
+#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x80000000L
+//SWRST_CONTROL_2
+#define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT 0x0
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT 0x8
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT 0x9
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT 0xa
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT 0xb
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT 0xc
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT 0xd
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT 0xe
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT 0xf
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x18
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x19
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x1a
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x1b
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x1c
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x1d
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x1e
+#define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK 0x00000001L
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK 0x00000100L
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK 0x00000200L
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK 0x00000400L
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK 0x00000800L
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK 0x00001000L
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK 0x00002000L
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK 0x00004000L
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK 0x00008000L
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x01000000L
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x02000000L
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x04000000L
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x08000000L
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x10000000L
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x20000000L
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x40000000L
+//SWRST_CONTROL_3
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x15
+#define SWRST_CONTROL_3__RESETAXIMST_ATEN__SHIFT 0x16
+#define SWRST_CONTROL_3__RESETAXISLV_ATEN__SHIFT 0x17
+#define SWRST_CONTROL_3__RESETAXIINT_ATEN__SHIFT 0x18
+#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x19
+#define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT 0x1a
+#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0x1b
+#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0x1c
+#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0x1d
+#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x1e
+#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1f
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x00200000L
+#define SWRST_CONTROL_3__RESETAXIMST_ATEN_MASK 0x00400000L
+#define SWRST_CONTROL_3__RESETAXISLV_ATEN_MASK 0x00800000L
+#define SWRST_CONTROL_3__RESETAXIINT_ATEN_MASK 0x01000000L
+#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x02000000L
+#define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK 0x04000000L
+#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x08000000L
+#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x10000000L
+#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x20000000L
+#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x40000000L
+#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x80000000L
+//SWRST_CONTROL_4
+#define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT 0x0
+#define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT 0x8
+#define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT 0x9
+#define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT 0xa
+#define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT 0xb
+#define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT 0xc
+#define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT 0xd
+#define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT 0xe
+#define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT 0xf
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x18
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x19
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x1a
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x1b
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x1c
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x1d
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x1e
+#define SWRST_CONTROL_4__PORT0_COR_WREN_MASK 0x00000001L
+#define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK 0x00000100L
+#define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK 0x00000200L
+#define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK 0x00000400L
+#define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK 0x00000800L
+#define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK 0x00001000L
+#define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK 0x00002000L
+#define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK 0x00004000L
+#define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK 0x00008000L
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x01000000L
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x02000000L
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x04000000L
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x08000000L
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x10000000L
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x20000000L
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x40000000L
+//SWRST_CONTROL_5
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x15
+#define SWRST_CONTROL_5__WRRESETAXIMST_EN__SHIFT 0x16
+#define SWRST_CONTROL_5__WRRESETAXISLV_EN__SHIFT 0x17
+#define SWRST_CONTROL_5__WRRESETAXIINT_EN__SHIFT 0x18
+#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x19
+#define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT 0x1a
+#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0x1b
+#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0x1c
+#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0x1d
+#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x1e
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1f
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x00200000L
+#define SWRST_CONTROL_5__WRRESETAXIMST_EN_MASK 0x00400000L
+#define SWRST_CONTROL_5__WRRESETAXISLV_EN_MASK 0x00800000L
+#define SWRST_CONTROL_5__WRRESETAXIINT_EN_MASK 0x01000000L
+#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x02000000L
+#define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK 0x04000000L
+#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x08000000L
+#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x10000000L
+#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x20000000L
+#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x40000000L
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x80000000L
+//SWRST_CONTROL_6
+#define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT 0x0
+#define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT 0x1
+#define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT 0x2
+#define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT 0x3
+#define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT 0x4
+#define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT 0x5
+#define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT 0x6
+#define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT 0x7
+#define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT 0x8
+#define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT 0x9
+#define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT 0xa
+#define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK 0x00000001L
+#define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK 0x00000002L
+#define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK 0x00000004L
+#define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK 0x00000008L
+#define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK 0x00000010L
+#define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK 0x00000020L
+#define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK 0x00000040L
+#define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK 0x00000080L
+#define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK 0x00000100L
+#define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK 0x00000200L
+#define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK 0x00000400L
+//SWRST_EP_COMMAND_0
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x00000001L
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x00000100L
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x00000200L
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x00000400L
+//SWRST_EP_CONTROL_0
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x00000001L
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x00000100L
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x00000200L
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x00000400L
+//CPM_CONTROL
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
+#define CPM_CONTROL__L1_PWR_GATE_ENABLE__SHIFT 0x2
+#define CPM_CONTROL__L1_1_PWR_GATE_ENABLE__SHIFT 0x3
+#define CPM_CONTROL__L1_2_PWR_GATE_ENABLE__SHIFT 0x4
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xb
+#define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE__SHIFT 0xd
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xe
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xf
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0x10
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0x11
+#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x12
+#define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG__SHIFT 0x15
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT 0x18
+#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT 0x19
+#define CPM_CONTROL__PG_EARLY_WAKE_ENABLE__SHIFT 0x1a
+#define CPM_CONTROL__PCIE_CORE_IDLE__SHIFT 0x1b
+#define CPM_CONTROL__PCIE_LINK_IDLE__SHIFT 0x1c
+#define CPM_CONTROL__PCIE_BUFFER_EMPTY__SHIFT 0x1d
+#define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY__SHIFT 0x1e
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L
+#define CPM_CONTROL__L1_PWR_GATE_ENABLE_MASK 0x00000004L
+#define CPM_CONTROL__L1_1_PWR_GATE_ENABLE_MASK 0x00000008L
+#define CPM_CONTROL__L1_2_PWR_GATE_ENABLE_MASK 0x00000010L
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x00000600L
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x00001800L
+#define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE_MASK 0x00002000L
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x00004000L
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x00008000L
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x00010000L
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x00020000L
+#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0x001C0000L
+#define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG_MASK 0x00200000L
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x00800000L
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L
+#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK 0x02000000L
+#define CPM_CONTROL__PG_EARLY_WAKE_ENABLE_MASK 0x04000000L
+#define CPM_CONTROL__PCIE_CORE_IDLE_MASK 0x08000000L
+#define CPM_CONTROL__PCIE_LINK_IDLE_MASK 0x10000000L
+#define CPM_CONTROL__PCIE_BUFFER_EMPTY_MASK 0x20000000L
+#define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY_MASK 0xC0000000L
+//CPM_SPLIT_CONTROL
+#define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE__SHIFT 0x0
+#define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE_MASK 0x00000001L
+//SMN_APERTURE_ID_A
+#define SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT 0x0
+#define SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK 0x00000FFFL
+//SMN_APERTURE_ID_B
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT 0x0
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT 0xc
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK 0x00000FFFL
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK 0x00FFF000L
+//LNCNT_CONTROL
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN__SHIFT 0x0
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT 0x1
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT 0x2
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN__SHIFT 0x3
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL__SHIFT 0x4
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN_MASK 0x00000001L
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK 0x00000002L
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK 0x00000004L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN_MASK 0x00000008L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL_MASK 0x00000010L
+//LNCNT_QUAN_THRD
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD__SHIFT 0x0
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD__SHIFT 0x4
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD_MASK 0x00000007L
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD_MASK 0x00000070L
+//LNCNT_WEIGHT
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT__SHIFT 0x0
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT__SHIFT 0x10
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT_MASK 0x0000FFFFL
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT_MASK 0xFFFF0000L
+//SMU_INT_PIN_SHARING_PORT_INDICATOR
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT 0x0
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT 0x8
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS__SHIFT 0x10
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK 0x000000FFL
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK 0x0000FF00L
+#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS_MASK 0x00FF0000L
+//PCIE_PGMST_CNTL
+#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0
+#define PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8
+#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT 0xe
+#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define PCIE_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L
+#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK 0x0000C000L
+//PCIE_PGSLV_CNTL
+#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+//LC_CPM_CONTROL_0
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE__SHIFT 0x0
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE__SHIFT 0x1
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE__SHIFT 0x2
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE__SHIFT 0x3
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE__SHIFT 0x4
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE__SHIFT 0x5
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE__SHIFT 0x6
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE__SHIFT 0x7
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE__SHIFT 0x8
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE__SHIFT 0x9
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE__SHIFT 0xa
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE__SHIFT 0xb
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE__SHIFT 0xc
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE__SHIFT 0xd
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE__SHIFT 0xe
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE__SHIFT 0xf
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE__SHIFT 0x10
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE__SHIFT 0x11
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE__SHIFT 0x12
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE__SHIFT 0x13
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE__SHIFT 0x14
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE__SHIFT 0x15
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE__SHIFT 0x16
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE__SHIFT 0x17
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE__SHIFT 0x18
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE__SHIFT 0x19
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE__SHIFT 0x1a
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE__SHIFT 0x1b
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE__SHIFT 0x1c
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE__SHIFT 0x1d
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE__SHIFT 0x1e
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE__SHIFT 0x1f
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE_MASK 0x00000001L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE_MASK 0x00000002L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE_MASK 0x00000004L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE_MASK 0x00000008L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE_MASK 0x00000010L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE_MASK 0x00000020L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE_MASK 0x00000040L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE_MASK 0x00000080L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE_MASK 0x00000100L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE_MASK 0x00000200L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE_MASK 0x00000400L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE_MASK 0x00000800L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE_MASK 0x00001000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE_MASK 0x00002000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE_MASK 0x00004000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE_MASK 0x00008000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE_MASK 0x00010000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE_MASK 0x00020000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE_MASK 0x00040000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE_MASK 0x00080000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE_MASK 0x00100000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE_MASK 0x00200000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE_MASK 0x00400000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE_MASK 0x00800000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE_MASK 0x01000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE_MASK 0x02000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE_MASK 0x04000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE_MASK 0x08000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE_MASK 0x10000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE_MASK 0x20000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE_MASK 0x40000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE_MASK 0x80000000L
+//LC_CPM_CONTROL_1
+#define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY__SHIFT 0x0
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE__SHIFT 0x10
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE__SHIFT 0x11
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE__SHIFT 0x12
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE__SHIFT 0x13
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE__SHIFT 0x14
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE__SHIFT 0x15
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE__SHIFT 0x16
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE__SHIFT 0x17
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE__SHIFT 0x18
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE__SHIFT 0x19
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE__SHIFT 0x1a
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE__SHIFT 0x1b
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE__SHIFT 0x1c
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE__SHIFT 0x1d
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE__SHIFT 0x1e
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE__SHIFT 0x1f
+#define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY_MASK 0x00000007L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE_MASK 0x00010000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE_MASK 0x00020000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE_MASK 0x00040000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE_MASK 0x00080000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE_MASK 0x00100000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE_MASK 0x00200000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE_MASK 0x00400000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE_MASK 0x00800000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE_MASK 0x01000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE_MASK 0x02000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE_MASK 0x04000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE_MASK 0x08000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE_MASK 0x10000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE_MASK 0x20000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE_MASK 0x40000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE_MASK 0x80000000L
+//PCIE_RXMARGIN_CONTROL_CAPABILITIES
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED__SHIFT 0x0
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE__SHIFT 0x1
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING__SHIFT 0x2
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD__SHIFT 0x3
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER__SHIFT 0x4
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED_MASK 0x00000001L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE_MASK 0x00000002L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING_MASK 0x00000004L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD_MASK 0x00000008L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER_MASK 0x00000010L
+//PCIE_RXMARGIN_1_SETTINGS
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS__SHIFT 0x0
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS__SHIFT 0x7
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET__SHIFT 0xd
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET__SHIFT 0x14
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS_MASK 0x0000007FL
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS_MASK 0x00001F80L
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET_MASK 0x000FE000L
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET_MASK 0x07F00000L
+//PCIE_RXMARGIN_2_SETTINGS
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE__SHIFT 0x0
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING__SHIFT 0x6
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT__SHIFT 0xc
+#define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES__SHIFT 0x13
+#define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT__SHIFT 0x18
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE_MASK 0x0000003FL
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING_MASK 0x00000FC0L
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT_MASK 0x0007F000L
+#define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES_MASK 0x00F80000L
+#define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT_MASK 0x3F000000L
+//PCIE_PRESENCE_DETECT_SELECT
+#define PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT__SHIFT 0x0
+#define PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT_MASK 0x00000001L
+//PCIE_LC_DEBUG_CNTL
+#define PCIE_LC_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
+#define PCIE_LC_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xFFFF0000L
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+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
+//BIF_CFG_DEV0_SWDS0_VENDOR_ID
+#define BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_DEVICE_ID
+#define BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_COMMAND
+#define BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_SWDS0_STATUS
+#define BIF_CFG_DEV0_SWDS0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_REVISION_ID
+#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_PROG_INTERFACE
+#define BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_SUB_CLASS
+#define BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_BASE_CLASS
+#define BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_CACHE_LINE
+#define BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_LATENCY
+#define BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_HEADER
+#define BIF_CFG_DEV0_SWDS0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_SWDS0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_SWDS0_BIST
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_SWDS0_BASE_ADDR_1
+#define BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_BASE_ADDR_2
+#define BIF_CFG_DEV0_SWDS0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS0_CAP_PTR
+#define BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_PMI_CAP
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_PCIE_CAP
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_SWDS0_DEVICE_CAP
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_SWDS0_DEVICE_CNTL
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_DEVICE_STATUS
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_SWDS0_LINK_CAP
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_LINK_CNTL
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_SWDS0_LINK_STATUS
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_SLOT_CAP
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_SWDS0_SLOT_CNTL
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV0_SWDS0_SLOT_STATUS
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS0_DEVICE_CAP2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_LINK_CAP2
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS0_LINK_CNTL2
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_SWDS0_LINK_STATUS2
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_SLOT_CAP2
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_SLOT_CNTL2
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_SLOT_STATUS2
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_SSID_CAP
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF0_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF1_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF2_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF3_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF4_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF5_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF6_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF7_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF8_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF9_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF10_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF11_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF12_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF13_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF14_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF15_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF16_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF16_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF16_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF16_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF17_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF17_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF17_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF17_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF18_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF18_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF18_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF18_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF19_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF19_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF19_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF19_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF20_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF20_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF20_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF20_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF21_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF21_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF21_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF21_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF22_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF22_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF22_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF22_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF23_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF23_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF23_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF23_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF24_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF24_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF24_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF24_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF25_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF25_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF25_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF25_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF26_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF26_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF26_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF26_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF27_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF27_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF27_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF27_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF28_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF28_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF28_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF28_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF29_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF29_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF29_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF29_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF30_0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF30_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF30_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF30_0_BIST
+#define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF0_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF1_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF2_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF2_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF3_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF3_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF4_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF4_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF5_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF5_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF6_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF6_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF7_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF7_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF8_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF8_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF8_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF8_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF9_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF9_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF9_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF9_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF10_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF10_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF10_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF10_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF11_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF11_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF11_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF11_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF12_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF12_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF12_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF12_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF13_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF13_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF13_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF13_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF14_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF14_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF14_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF14_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF15_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF15_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF15_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF15_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF16_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF16_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF16_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF16_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF16_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF17_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF17_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF17_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF17_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF17_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF18_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF18_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF18_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF18_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF18_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF19_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF19_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF19_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF19_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF19_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF20_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF20_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF20_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF20_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF20_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF21_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF21_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF21_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF21_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF21_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF22_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF22_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF22_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF22_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF22_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF23_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF23_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF23_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF23_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF23_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF24_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF24_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF24_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF24_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF24_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF25_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF25_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF25_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF25_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF25_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF26_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF26_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF26_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF26_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF26_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF27_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF27_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF27_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF27_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF27_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF28_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF28_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF28_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF28_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF28_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF29_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF29_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF29_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF29_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF29_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF30_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_DEV0_EPF0_VF30_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF30_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF30_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+//BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_VF30_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_pcie0_pswuscfg0_cfgdecp
+//PSWUSCFG0_1_VENDOR_ID
+#define PSWUSCFG0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//PSWUSCFG0_1_DEVICE_ID
+#define PSWUSCFG0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define PSWUSCFG0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//PSWUSCFG0_1_COMMAND
+#define PSWUSCFG0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define PSWUSCFG0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define PSWUSCFG0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define PSWUSCFG0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define PSWUSCFG0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define PSWUSCFG0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define PSWUSCFG0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define PSWUSCFG0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define PSWUSCFG0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define PSWUSCFG0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define PSWUSCFG0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define PSWUSCFG0_1_COMMAND__INT_DIS_MASK 0x0400L
+//PSWUSCFG0_1_STATUS
+#define PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define PSWUSCFG0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define PSWUSCFG0_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define PSWUSCFG0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define PSWUSCFG0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define PSWUSCFG0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define PSWUSCFG0_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define PSWUSCFG0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//PSWUSCFG0_1_REVISION_ID
+#define PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//PSWUSCFG0_1_PROG_INTERFACE
+#define PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//PSWUSCFG0_1_SUB_CLASS
+#define PSWUSCFG0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define PSWUSCFG0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//PSWUSCFG0_1_BASE_CLASS
+#define PSWUSCFG0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define PSWUSCFG0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//PSWUSCFG0_1_CACHE_LINE
+#define PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//PSWUSCFG0_1_LATENCY
+#define PSWUSCFG0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define PSWUSCFG0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//PSWUSCFG0_1_HEADER
+#define PSWUSCFG0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define PSWUSCFG0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define PSWUSCFG0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define PSWUSCFG0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//PSWUSCFG0_1_BIST
+#define PSWUSCFG0_1_BIST__BIST_COMP__SHIFT 0x0
+#define PSWUSCFG0_1_BIST__BIST_STRT__SHIFT 0x6
+#define PSWUSCFG0_1_BIST__BIST_CAP__SHIFT 0x7
+#define PSWUSCFG0_1_BIST__BIST_COMP_MASK 0x0FL
+#define PSWUSCFG0_1_BIST__BIST_STRT_MASK 0x40L
+#define PSWUSCFG0_1_BIST__BIST_CAP_MASK 0x80L
+//PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY
+#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//PSWUSCFG0_1_IO_BASE_LIMIT
+#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//PSWUSCFG0_1_SECONDARY_STATUS
+#define PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//PSWUSCFG0_1_MEM_BASE_LIMIT
+#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//PSWUSCFG0_1_PREF_BASE_LIMIT
+#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//PSWUSCFG0_1_PREF_BASE_UPPER
+#define PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PREF_LIMIT_UPPER
+#define PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_IO_BASE_LIMIT_HI
+#define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//PSWUSCFG0_1_CAP_PTR
+#define PSWUSCFG0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define PSWUSCFG0_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//PSWUSCFG0_1_ROM_BASE_ADDR
+#define PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_INTERRUPT_LINE
+#define PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//PSWUSCFG0_1_INTERRUPT_PIN
+#define PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//PSWUSCFG0_1_IRQ_BRIDGE_CNTL
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//PSWUSCFG0_1_EXT_BRIDGE_CNTL
+#define PSWUSCFG0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define PSWUSCFG0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//PSWUSCFG0_1_VENDOR_CAP_LIST
+#define PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//PSWUSCFG0_1_ADAPTER_ID_W
+#define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//PSWUSCFG0_1_PMI_CAP_LIST
+#define PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_1_PMI_CAP
+#define PSWUSCFG0_1_PMI_CAP__VERSION__SHIFT 0x0
+#define PSWUSCFG0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define PSWUSCFG0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define PSWUSCFG0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define PSWUSCFG0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define PSWUSCFG0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define PSWUSCFG0_1_PMI_CAP__VERSION_MASK 0x0007L
+#define PSWUSCFG0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define PSWUSCFG0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define PSWUSCFG0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define PSWUSCFG0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define PSWUSCFG0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//PSWUSCFG0_1_PMI_STATUS_CNTL
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//PSWUSCFG0_1_PCIE_CAP_LIST
+#define PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_1_PCIE_CAP
+#define PSWUSCFG0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//PSWUSCFG0_1_DEVICE_CAP
+#define PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//PSWUSCFG0_1_DEVICE_CNTL
+#define PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//PSWUSCFG0_1_DEVICE_STATUS
+#define PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+//PSWUSCFG0_1_LINK_CAP
+#define PSWUSCFG0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define PSWUSCFG0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define PSWUSCFG0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define PSWUSCFG0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define PSWUSCFG0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define PSWUSCFG0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define PSWUSCFG0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define PSWUSCFG0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//PSWUSCFG0_1_LINK_CNTL
+#define PSWUSCFG0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define PSWUSCFG0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define PSWUSCFG0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define PSWUSCFG0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//PSWUSCFG0_1_LINK_STATUS
+#define PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//PSWUSCFG0_1_DEVICE_CAP2
+#define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//PSWUSCFG0_1_DEVICE_CNTL2
+#define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//PSWUSCFG0_1_DEVICE_STATUS2
+#define PSWUSCFG0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define PSWUSCFG0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//PSWUSCFG0_1_LINK_CAP2
+#define PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//PSWUSCFG0_1_LINK_CNTL2
+#define PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//PSWUSCFG0_1_LINK_STATUS2
+#define PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//PSWUSCFG0_1_MSI_CAP_LIST
+#define PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_1_MSI_MSG_CNTL
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//PSWUSCFG0_1_MSI_MSG_ADDR_LO
+#define PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//PSWUSCFG0_1_MSI_MSG_ADDR_HI
+#define PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_MSI_MSG_DATA
+#define PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//PSWUSCFG0_1_MSI_MSG_DATA_64
+#define PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//PSWUSCFG0_1_SSID_CAP_LIST
+#define PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_1_SSID_CAP
+#define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//PSWUSCFG0_1_MSI_MAP_CAP_LIST
+#define PSWUSCFG0_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PSWUSCFG0_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define PSWUSCFG0_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//PSWUSCFG0_1_MSI_MAP_CAP
+#define PSWUSCFG0_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define PSWUSCFG0_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define PSWUSCFG0_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define PSWUSCFG0_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define PSWUSCFG0_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define PSWUSCFG0_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PSWUSCFG0_1_PCIE_PORT_VC_CNTL
+#define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//PSWUSCFG0_1_PCIE_PORT_VC_STATUS
+#define PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//PSWUSCFG0_1_PCIE_CORR_ERR_STATUS
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//PSWUSCFG0_1_PCIE_CORR_ERR_MASK
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//PSWUSCFG0_1_PCIE_HDR_LOG0
+#define PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_HDR_LOG1
+#define PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_HDR_LOG2
+#define PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_HDR_LOG3
+#define PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0
+#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1
+#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2
+#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3
+#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_LINK_CNTL3
+#define PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS
+#define PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_ACS_CAP
+#define PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//PSWUSCFG0_1_PCIE_ACS_CNTL
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_MC_CAP
+#define PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//PSWUSCFG0_1_PCIE_MC_CNTL
+#define PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//PSWUSCFG0_1_PCIE_MC_ADDR0
+#define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//PSWUSCFG0_1_PCIE_MC_ADDR1
+#define PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_MC_RCV0
+#define PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_MC_RCV1
+#define PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0
+#define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1
+#define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0
+#define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1
+#define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_LTR_CAP
+#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_ARI_CAP
+#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//PSWUSCFG0_1_PCIE_ARI_CNTL
+#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//PSWUSCFG0_1_PCIE_ESM_CAP_LIST
+#define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_ESM_HEADER_1
+#define PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_ESM_HEADER_2
+#define PSWUSCFG0_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//PSWUSCFG0_1_PCIE_ESM_STATUS
+#define PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//PSWUSCFG0_1_PCIE_ESM_CTRL
+#define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL
+#define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L
+#define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//PSWUSCFG0_1_PCIE_ESM_CAP_1
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//PSWUSCFG0_1_PCIE_ESM_CAP_2
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//PSWUSCFG0_1_PCIE_ESM_CAP_3
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//PSWUSCFG0_1_PCIE_ESM_CAP_4
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//PSWUSCFG0_1_PCIE_ESM_CAP_5
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//PSWUSCFG0_1_PCIE_ESM_CAP_6
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//PSWUSCFG0_1_PCIE_ESM_CAP_7
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_DATA_LINK_FEATURE_CAP
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_LINK_CAP_16GT
+#define PSWUSCFG0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define PSWUSCFG0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_LINK_CNTL_16GT
+#define PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_LINK_STATUS_16GT
+#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_MARGINING_PORT_CAP
+#define PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//PSWUSCFG0_1_MARGINING_PORT_STATUS
+#define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//PSWUSCFG0_1_PCIE_CCIX_CAP_LIST
+#define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_CCIX_HEADER_1
+#define PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//PSWUSCFG0_1_PCIE_CCIX_HEADER_2
+#define PSWUSCFG0_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//PSWUSCFG0_1_PCIE_CCIX_CAP
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//PSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//PSWUSCFG0_1_PCIE_CCIX_TRANS_CAP
+#define PSWUSCFG0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL
+#define PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE__SHIFT 0x1
+#define PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+#define PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1
+//BIF_BX_PF0_MM_INDEX
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF0_MM_DATA
+#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MM_INDEX_HI
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
+//BIF_CFG_DEV0_SWDS1_VENDOR_ID
+#define BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_DEVICE_ID
+#define BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_COMMAND
+#define BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_SWDS1_STATUS
+#define BIF_CFG_DEV0_SWDS1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_REVISION_ID
+#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_PROG_INTERFACE
+#define BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_SUB_CLASS
+#define BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_BASE_CLASS
+#define BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_CACHE_LINE
+#define BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_LATENCY
+#define BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_HEADER
+#define BIF_CFG_DEV0_SWDS1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_SWDS1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_SWDS1_BIST
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_SWDS1_BASE_ADDR_1
+#define BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_BASE_ADDR_2
+#define BIF_CFG_DEV0_SWDS1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS1_CAP_PTR
+#define BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_PMI_CAP
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_PCIE_CAP
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_SWDS1_DEVICE_CAP
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_SWDS1_DEVICE_CNTL
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_DEVICE_STATUS
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_SWDS1_LINK_CAP
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_LINK_CNTL
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_SWDS1_LINK_STATUS
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_SLOT_CAP
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_SWDS1_SLOT_CNTL
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV0_SWDS1_SLOT_STATUS
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS1_DEVICE_CAP2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_LINK_CAP2
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS1_LINK_CNTL2
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_SWDS1_LINK_STATUS2
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_SLOT_CAP2
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_SLOT_CNTL2
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_SLOT_STATUS2
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_SSID_CAP
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_1_STATUS
+#define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_HEADER
+#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_1_BIST
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_COMMAND
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_1_STATUS
+#define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_HEADER
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_1_BIST
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_COMMAND
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_1_STATUS
+#define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_LATENCY
+#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_HEADER
+#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_1_BIST
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_SBRN
+#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_FLADJ
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF2_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_1_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_COMMAND
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_1_STATUS
+#define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_LATENCY
+#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_HEADER
+#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_1_BIST
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_SBRN
+#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_FLADJ
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF3_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_1_SATA_CAP_0
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_SATA_CAP_1
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L
+#define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF0_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF1_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF2_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF3_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF4_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF5_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF6_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF7_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF8_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF9_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF10_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF11_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF12_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF13_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF14_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF15_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF16_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF16_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF16_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF16_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF17_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF17_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF17_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF17_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF18_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF18_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF18_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF18_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF19_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF19_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF19_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF19_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF20_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF20_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF20_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF20_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF21_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF21_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF21_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF21_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF22_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF22_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF22_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF22_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF23_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF23_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF23_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF23_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF24_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF24_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF24_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF24_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF25_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF25_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF25_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF25_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF26_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF26_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF26_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF26_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF27_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF27_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF27_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF27_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF28_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF28_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF28_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF28_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF29_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF29_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF29_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF29_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_VF30_1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF30_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF30_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF30_1_BIST
+#define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF1_MM_INDEX
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF1_MM_DATA
+#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MM_INDEX_HI
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
index 8c75669eb500..9470ec5e0f42 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
@@ -54,5 +54,8 @@
#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258
#define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c
+#define smnPCIE_RX_NUM_NAK 0x11180038
+#define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c
+
#endif // _nbio_6_1_SMN_HEADER
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
index 5563f0715896..caf5ffdc130a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
@@ -51,4 +51,7 @@
#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258
#define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c
+#define smnPCIE_RX_NUM_NAK 0x11180038
+#define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c
+
#endif // _nbio_7_0_SMN_HEADER
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
index c1457d880c4d..4bcacf529852 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
@@ -50,4 +50,7 @@
#define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x1118024c
#define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x11180250
+#define smnPCIE_RX_NUM_NAK 0x11180038
+#define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c
+
#endif // _nbio_7_4_0_SMN_HEADER
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h
new file mode 100644
index 000000000000..408500fc882a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h
@@ -0,0 +1,353 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _osssys_5_0_0_OFFSET_HEADER
+#define _osssys_5_0_0_OFFSET_HEADER
+
+
+
+// addressBlock: osssys_osssysdec
+// base address: 0x4280
+#define mmIH_VMID_0_LUT 0x0000
+#define mmIH_VMID_0_LUT_BASE_IDX 0
+#define mmIH_VMID_1_LUT 0x0001
+#define mmIH_VMID_1_LUT_BASE_IDX 0
+#define mmIH_VMID_2_LUT 0x0002
+#define mmIH_VMID_2_LUT_BASE_IDX 0
+#define mmIH_VMID_3_LUT 0x0003
+#define mmIH_VMID_3_LUT_BASE_IDX 0
+#define mmIH_VMID_4_LUT 0x0004
+#define mmIH_VMID_4_LUT_BASE_IDX 0
+#define mmIH_VMID_5_LUT 0x0005
+#define mmIH_VMID_5_LUT_BASE_IDX 0
+#define mmIH_VMID_6_LUT 0x0006
+#define mmIH_VMID_6_LUT_BASE_IDX 0
+#define mmIH_VMID_7_LUT 0x0007
+#define mmIH_VMID_7_LUT_BASE_IDX 0
+#define mmIH_VMID_8_LUT 0x0008
+#define mmIH_VMID_8_LUT_BASE_IDX 0
+#define mmIH_VMID_9_LUT 0x0009
+#define mmIH_VMID_9_LUT_BASE_IDX 0
+#define mmIH_VMID_10_LUT 0x000a
+#define mmIH_VMID_10_LUT_BASE_IDX 0
+#define mmIH_VMID_11_LUT 0x000b
+#define mmIH_VMID_11_LUT_BASE_IDX 0
+#define mmIH_VMID_12_LUT 0x000c
+#define mmIH_VMID_12_LUT_BASE_IDX 0
+#define mmIH_VMID_13_LUT 0x000d
+#define mmIH_VMID_13_LUT_BASE_IDX 0
+#define mmIH_VMID_14_LUT 0x000e
+#define mmIH_VMID_14_LUT_BASE_IDX 0
+#define mmIH_VMID_15_LUT 0x000f
+#define mmIH_VMID_15_LUT_BASE_IDX 0
+#define mmIH_VMID_0_LUT_MM 0x0010
+#define mmIH_VMID_0_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_1_LUT_MM 0x0011
+#define mmIH_VMID_1_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_2_LUT_MM 0x0012
+#define mmIH_VMID_2_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_3_LUT_MM 0x0013
+#define mmIH_VMID_3_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_4_LUT_MM 0x0014
+#define mmIH_VMID_4_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_5_LUT_MM 0x0015
+#define mmIH_VMID_5_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_6_LUT_MM 0x0016
+#define mmIH_VMID_6_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_7_LUT_MM 0x0017
+#define mmIH_VMID_7_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_8_LUT_MM 0x0018
+#define mmIH_VMID_8_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_9_LUT_MM 0x0019
+#define mmIH_VMID_9_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_10_LUT_MM 0x001a
+#define mmIH_VMID_10_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_11_LUT_MM 0x001b
+#define mmIH_VMID_11_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_12_LUT_MM 0x001c
+#define mmIH_VMID_12_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_13_LUT_MM 0x001d
+#define mmIH_VMID_13_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_14_LUT_MM 0x001e
+#define mmIH_VMID_14_LUT_MM_BASE_IDX 0
+#define mmIH_VMID_15_LUT_MM 0x001f
+#define mmIH_VMID_15_LUT_MM_BASE_IDX 0
+#define mmIH_COOKIE_0 0x0020
+#define mmIH_COOKIE_0_BASE_IDX 0
+#define mmIH_COOKIE_1 0x0021
+#define mmIH_COOKIE_1_BASE_IDX 0
+#define mmIH_COOKIE_2 0x0022
+#define mmIH_COOKIE_2_BASE_IDX 0
+#define mmIH_COOKIE_3 0x0023
+#define mmIH_COOKIE_3_BASE_IDX 0
+#define mmIH_COOKIE_4 0x0024
+#define mmIH_COOKIE_4_BASE_IDX 0
+#define mmIH_COOKIE_5 0x0025
+#define mmIH_COOKIE_5_BASE_IDX 0
+#define mmIH_COOKIE_6 0x0026
+#define mmIH_COOKIE_6_BASE_IDX 0
+#define mmIH_COOKIE_7 0x0027
+#define mmIH_COOKIE_7_BASE_IDX 0
+#define mmIH_REGISTER_LAST_PART0 0x003f
+#define mmIH_REGISTER_LAST_PART0_BASE_IDX 0
+#define mmSEM_REQ_INPUT_0 0x0040
+#define mmSEM_REQ_INPUT_0_BASE_IDX 0
+#define mmSEM_REQ_INPUT_1 0x0041
+#define mmSEM_REQ_INPUT_1_BASE_IDX 0
+#define mmSEM_REQ_INPUT_2 0x0042
+#define mmSEM_REQ_INPUT_2_BASE_IDX 0
+#define mmSEM_REQ_INPUT_3 0x0043
+#define mmSEM_REQ_INPUT_3_BASE_IDX 0
+#define mmSEM_REGISTER_LAST_PART0 0x007f
+#define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0
+#define mmIH_RB_CNTL 0x0080
+#define mmIH_RB_CNTL_BASE_IDX 0
+#define mmIH_RB_BASE 0x0081
+#define mmIH_RB_BASE_BASE_IDX 0
+#define mmIH_RB_BASE_HI 0x0082
+#define mmIH_RB_BASE_HI_BASE_IDX 0
+#define mmIH_RB_RPTR 0x0083
+#define mmIH_RB_RPTR_BASE_IDX 0
+#define mmIH_RB_WPTR 0x0084
+#define mmIH_RB_WPTR_BASE_IDX 0
+#define mmIH_RB_WPTR_ADDR_HI 0x0085
+#define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0
+#define mmIH_RB_WPTR_ADDR_LO 0x0086
+#define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0
+#define mmIH_DOORBELL_RPTR 0x0087
+#define mmIH_DOORBELL_RPTR_BASE_IDX 0
+#define mmIH_RB_CNTL_RING1 0x008c
+#define mmIH_RB_CNTL_RING1_BASE_IDX 0
+#define mmIH_RB_BASE_RING1 0x008d
+#define mmIH_RB_BASE_RING1_BASE_IDX 0
+#define mmIH_RB_BASE_HI_RING1 0x008e
+#define mmIH_RB_BASE_HI_RING1_BASE_IDX 0
+#define mmIH_RB_RPTR_RING1 0x008f
+#define mmIH_RB_RPTR_RING1_BASE_IDX 0
+#define mmIH_RB_WPTR_RING1 0x0090
+#define mmIH_RB_WPTR_RING1_BASE_IDX 0
+#define mmIH_DOORBELL_RPTR_RING1 0x0093
+#define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0
+#define mmIH_RB_CNTL_RING2 0x0098
+#define mmIH_RB_CNTL_RING2_BASE_IDX 0
+#define mmIH_RB_BASE_RING2 0x0099
+#define mmIH_RB_BASE_RING2_BASE_IDX 0
+#define mmIH_RB_BASE_HI_RING2 0x009a
+#define mmIH_RB_BASE_HI_RING2_BASE_IDX 0
+#define mmIH_RB_RPTR_RING2 0x009b
+#define mmIH_RB_RPTR_RING2_BASE_IDX 0
+#define mmIH_RB_WPTR_RING2 0x009c
+#define mmIH_RB_WPTR_RING2_BASE_IDX 0
+#define mmIH_DOORBELL_RPTR_RING2 0x009f
+#define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0
+#define mmIH_VERSION 0x00a5
+#define mmIH_VERSION_BASE_IDX 0
+#define mmIH_CNTL 0x00c0
+#define mmIH_CNTL_BASE_IDX 0
+#define mmIH_CNTL2 0x00c1
+#define mmIH_CNTL2_BASE_IDX 0
+#define mmIH_STATUS 0x00c2
+#define mmIH_STATUS_BASE_IDX 0
+#define mmIH_PERFMON_CNTL 0x00c3
+#define mmIH_PERFMON_CNTL_BASE_IDX 0
+#define mmIH_PERFCOUNTER0_RESULT 0x00c4
+#define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmIH_PERFCOUNTER1_RESULT 0x00c5
+#define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7
+#define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0
+#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8
+#define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0
+#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9
+#define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0
+#define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca
+#define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0
+#define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb
+#define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0
+#define mmIH_DSM_MATCH_FCN_ID 0x00cc
+#define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0
+#define mmIH_LIMIT_INT_RATE_CNTL 0x00cd
+#define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0
+#define mmIH_VF_RB_STATUS 0x00ce
+#define mmIH_VF_RB_STATUS_BASE_IDX 0
+#define mmIH_VF_RB_STATUS2 0x00cf
+#define mmIH_VF_RB_STATUS2_BASE_IDX 0
+#define mmIH_VF_RB1_STATUS 0x00d0
+#define mmIH_VF_RB1_STATUS_BASE_IDX 0
+#define mmIH_VF_RB1_STATUS2 0x00d1
+#define mmIH_VF_RB1_STATUS2_BASE_IDX 0
+#define mmIH_VF_RB2_STATUS 0x00d2
+#define mmIH_VF_RB2_STATUS_BASE_IDX 0
+#define mmIH_VF_RB2_STATUS2 0x00d3
+#define mmIH_VF_RB2_STATUS2_BASE_IDX 0
+#define mmIH_INT_FLOOD_CNTL 0x00d5
+#define mmIH_INT_FLOOD_CNTL_BASE_IDX 0
+#define mmIH_RB0_INT_FLOOD_STATUS 0x00d6
+#define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0
+#define mmIH_RB1_INT_FLOOD_STATUS 0x00d7
+#define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0
+#define mmIH_RB2_INT_FLOOD_STATUS 0x00d8
+#define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0
+#define mmIH_INT_FLOOD_STATUS 0x00d9
+#define mmIH_INT_FLOOD_STATUS_BASE_IDX 0
+#define mmIH_STORM_CLIENT_LIST_CNTL 0x00da
+#define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0
+#define mmIH_CLK_CTRL 0x00db
+#define mmIH_CLK_CTRL_BASE_IDX 0
+#define mmIH_INT_FLAGS 0x00dc
+#define mmIH_INT_FLAGS_BASE_IDX 0
+#define mmIH_LAST_INT_INFO0 0x00dd
+#define mmIH_LAST_INT_INFO0_BASE_IDX 0
+#define mmIH_LAST_INT_INFO1 0x00de
+#define mmIH_LAST_INT_INFO1_BASE_IDX 0
+#define mmIH_LAST_INT_INFO2 0x00df
+#define mmIH_LAST_INT_INFO2_BASE_IDX 0
+#define mmIH_SCRATCH 0x00e0
+#define mmIH_SCRATCH_BASE_IDX 0
+#define mmIH_CLIENT_CREDIT_ERROR 0x00e1
+#define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0
+#define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2
+#define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmIH_GPU_IOV_VIOLATION_LOG2 0x00e3
+#define mmIH_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0
+#define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e4
+#define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0
+#define mmIH_CREDIT_STATUS 0x00e5
+#define mmIH_CREDIT_STATUS_BASE_IDX 0
+#define mmIH_MMHUB_ERROR 0x00e6
+#define mmIH_MMHUB_ERROR_BASE_IDX 0
+#define mmIH_MEM_POWER_CTRL 0x00e9
+#define mmIH_MEM_POWER_CTRL_BASE_IDX 0
+#define mmIH_VF_RB_STATUS3 0x00ea
+#define mmIH_VF_RB_STATUS3_BASE_IDX 0
+#define mmIH_VF_RB_STATUS4 0x00eb
+#define mmIH_VF_RB_STATUS4_BASE_IDX 0
+#define mmIH_VF_RB1_STATUS3 0x00ec
+#define mmIH_VF_RB1_STATUS3_BASE_IDX 0
+#define mmIH_VF_RB2_STATUS3 0x00ee
+#define mmIH_VF_RB2_STATUS3_BASE_IDX 0
+#define mmIH_REGISTER_LAST_PART2 0x00ff
+#define mmIH_REGISTER_LAST_PART2_BASE_IDX 0
+#define mmSEM_CLK_CTRL 0x0100
+#define mmSEM_CLK_CTRL_BASE_IDX 0
+#define mmSEM_UTC_CREDIT 0x0101
+#define mmSEM_UTC_CREDIT_BASE_IDX 0
+#define mmSEM_UTC_CONFIG 0x0102
+#define mmSEM_UTC_CONFIG_BASE_IDX 0
+#define mmSEM_UTCL2_TRAN_EN_LUT 0x0103
+#define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0
+#define mmSEM_MCIF_CONFIG 0x0104
+#define mmSEM_MCIF_CONFIG_BASE_IDX 0
+#define mmSEM_PERFMON_CNTL 0x0105
+#define mmSEM_PERFMON_CNTL_BASE_IDX 0
+#define mmSEM_PERFCOUNTER0_RESULT 0x0106
+#define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0
+#define mmSEM_PERFCOUNTER1_RESULT 0x0107
+#define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0
+#define mmSEM_STATUS 0x0108
+#define mmSEM_STATUS_BASE_IDX 0
+#define mmSEM_MAILBOX_CLIENTCONFIG 0x0109
+#define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0
+#define mmSEM_MAILBOX 0x010a
+#define mmSEM_MAILBOX_BASE_IDX 0
+#define mmSEM_MAILBOX_CONTROL 0x010b
+#define mmSEM_MAILBOX_CONTROL_BASE_IDX 0
+#define mmSEM_CHICKEN_BITS 0x010c
+#define mmSEM_CHICKEN_BITS_BASE_IDX 0
+#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d
+#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0
+#define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e
+#define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
+#define mmSEM_OUTSTANDING_THRESHOLD 0x010f
+#define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0
+#define mmSEM_MEM_POWER_CTRL 0x0110
+#define mmSEM_MEM_POWER_CTRL_BASE_IDX 0
+#define mmSEM_GPU_IOV_VIOLATION_LOG2 0x0111
+#define mmSEM_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0
+#define mmSEM_REGISTER_LAST_PART2 0x017f
+#define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0
+#define mmIH_ACTIVE_FCN_ID 0x0180
+#define mmIH_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmIH_VIRT_RESET_REQ 0x0181
+#define mmIH_VIRT_RESET_REQ_BASE_IDX 0
+#define mmIH_CLIENT_CFG 0x0184
+#define mmIH_CLIENT_CFG_BASE_IDX 0
+#define mmIH_CLIENT_CFG_INDEX 0x0188
+#define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0
+#define mmIH_CLIENT_CFG_DATA 0x0189
+#define mmIH_CLIENT_CFG_DATA_BASE_IDX 0
+#define mmIH_CID_REMAP_INDEX 0x018a
+#define mmIH_CID_REMAP_INDEX_BASE_IDX 0
+#define mmIH_CID_REMAP_DATA 0x018b
+#define mmIH_CID_REMAP_DATA_BASE_IDX 0
+#define mmIH_CHICKEN 0x018c
+#define mmIH_CHICKEN_BASE_IDX 0
+#define mmIH_MMHUB_CNTL 0x018d
+#define mmIH_MMHUB_CNTL_BASE_IDX 0
+#define mmIH_INT_DROP_CNTL 0x018e
+#define mmIH_INT_DROP_CNTL_BASE_IDX 0
+#define mmIH_INT_DROP_MATCH_VALUE0 0x018f
+#define mmIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0
+#define mmIH_INT_DROP_MATCH_VALUE1 0x0190
+#define mmIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0
+#define mmIH_INT_DROP_MATCH_MASK0 0x0191
+#define mmIH_INT_DROP_MATCH_MASK0_BASE_IDX 0
+#define mmIH_INT_DROP_MATCH_MASK1 0x0192
+#define mmIH_INT_DROP_MATCH_MASK1_BASE_IDX 0
+#define mmIH_REGISTER_LAST_PART1 0x019f
+#define mmIH_REGISTER_LAST_PART1_BASE_IDX 0
+#define mmSEM_ACTIVE_FCN_ID 0x01a0
+#define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmSEM_VIRT_RESET_REQ 0x01a1
+#define mmSEM_VIRT_RESET_REQ_BASE_IDX 0
+#define mmSEM_RESP_SDMA0 0x01a4
+#define mmSEM_RESP_SDMA0_BASE_IDX 0
+#define mmSEM_RESP_SDMA1 0x01a5
+#define mmSEM_RESP_SDMA1_BASE_IDX 0
+#define mmSEM_RESP_UVD 0x01a6
+#define mmSEM_RESP_UVD_BASE_IDX 0
+#define mmSEM_RESP_VCE_0 0x01a7
+#define mmSEM_RESP_VCE_0_BASE_IDX 0
+#define mmSEM_RESP_ACP 0x01a8
+#define mmSEM_RESP_ACP_BASE_IDX 0
+#define mmSEM_RESP_ISP 0x01a9
+#define mmSEM_RESP_ISP_BASE_IDX 0
+#define mmSEM_RESP_VCE_1 0x01aa
+#define mmSEM_RESP_VCE_1_BASE_IDX 0
+#define mmSEM_RESP_VP8 0x01ab
+#define mmSEM_RESP_VP8_BASE_IDX 0
+#define mmSEM_RESP_GC 0x01ac
+#define mmSEM_RESP_GC_BASE_IDX 0
+#define mmSEM_CID_REMAP_INDEX 0x01b0
+#define mmSEM_CID_REMAP_INDEX_BASE_IDX 0
+#define mmSEM_CID_REMAP_DATA 0x01b1
+#define mmSEM_CID_REMAP_DATA_BASE_IDX 0
+#define mmSEM_ATOMIC_OP_LUT 0x01b2
+#define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0
+#define mmSEM_EDC_CONFIG 0x01b3
+#define mmSEM_EDC_CONFIG_BASE_IDX 0
+#define mmSEM_CHICKEN_BITS2 0x01b4
+#define mmSEM_CHICKEN_BITS2_BASE_IDX 0
+#define mmSEM_MMHUB_CNTL 0x01b5
+#define mmSEM_MMHUB_CNTL_BASE_IDX 0
+#define mmSEM_REGISTER_LAST_PART1 0x01bf
+#define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h
new file mode 100644
index 000000000000..05543bde3444
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h
@@ -0,0 +1,1305 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _osssys_5_0_0_SH_MASK_HEADER
+#define _osssys_5_0_0_SH_MASK_HEADER
+
+
+// addressBlock: osssys_osssysdec
+//IH_VMID_0_LUT
+#define IH_VMID_0_LUT__PASID__SHIFT 0x0
+#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_1_LUT
+#define IH_VMID_1_LUT__PASID__SHIFT 0x0
+#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_2_LUT
+#define IH_VMID_2_LUT__PASID__SHIFT 0x0
+#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_3_LUT
+#define IH_VMID_3_LUT__PASID__SHIFT 0x0
+#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_4_LUT
+#define IH_VMID_4_LUT__PASID__SHIFT 0x0
+#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_5_LUT
+#define IH_VMID_5_LUT__PASID__SHIFT 0x0
+#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_6_LUT
+#define IH_VMID_6_LUT__PASID__SHIFT 0x0
+#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_7_LUT
+#define IH_VMID_7_LUT__PASID__SHIFT 0x0
+#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_8_LUT
+#define IH_VMID_8_LUT__PASID__SHIFT 0x0
+#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_9_LUT
+#define IH_VMID_9_LUT__PASID__SHIFT 0x0
+#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_10_LUT
+#define IH_VMID_10_LUT__PASID__SHIFT 0x0
+#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_11_LUT
+#define IH_VMID_11_LUT__PASID__SHIFT 0x0
+#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_12_LUT
+#define IH_VMID_12_LUT__PASID__SHIFT 0x0
+#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_13_LUT
+#define IH_VMID_13_LUT__PASID__SHIFT 0x0
+#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_14_LUT
+#define IH_VMID_14_LUT__PASID__SHIFT 0x0
+#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_15_LUT
+#define IH_VMID_15_LUT__PASID__SHIFT 0x0
+#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL
+//IH_VMID_0_LUT_MM
+#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_1_LUT_MM
+#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_2_LUT_MM
+#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_3_LUT_MM
+#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_4_LUT_MM
+#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_5_LUT_MM
+#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_6_LUT_MM
+#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_7_LUT_MM
+#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_8_LUT_MM
+#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_9_LUT_MM
+#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_10_LUT_MM
+#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_11_LUT_MM
+#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_12_LUT_MM
+#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_13_LUT_MM
+#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_14_LUT_MM
+#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_VMID_15_LUT_MM
+#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0
+#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL
+//IH_COOKIE_0
+#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0
+#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8
+#define IH_COOKIE_0__RING_ID__SHIFT 0x10
+#define IH_COOKIE_0__VM_ID__SHIFT 0x18
+#define IH_COOKIE_0__RESERVED__SHIFT 0x1c
+#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f
+#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL
+#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L
+#define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L
+#define IH_COOKIE_0__VM_ID_MASK 0x0F000000L
+#define IH_COOKIE_0__RESERVED_MASK 0x70000000L
+#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L
+//IH_COOKIE_1
+#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0
+#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL
+//IH_COOKIE_2
+#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0
+#define IH_COOKIE_2__RESERVED__SHIFT 0x10
+#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f
+#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL
+#define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L
+#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L
+//IH_COOKIE_3
+#define IH_COOKIE_3__PAS_ID__SHIFT 0x0
+#define IH_COOKIE_3__RESERVED__SHIFT 0x10
+#define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f
+#define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL
+#define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L
+#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L
+//IH_COOKIE_4
+#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0
+#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL
+//IH_COOKIE_5
+#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0
+#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL
+//IH_COOKIE_6
+#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0
+#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL
+//IH_COOKIE_7
+#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0
+#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL
+//IH_REGISTER_LAST_PART0
+#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0
+#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL
+//SEM_REQ_INPUT_0
+#define SEM_REQ_INPUT_0__DATA__SHIFT 0x0
+#define SEM_REQ_INPUT_0__DATA_MASK 0xFFFFFFFFL
+//SEM_REQ_INPUT_1
+#define SEM_REQ_INPUT_1__DATA__SHIFT 0x0
+#define SEM_REQ_INPUT_1__DATA_MASK 0xFFFFFFFFL
+//SEM_REQ_INPUT_2
+#define SEM_REQ_INPUT_2__DATA__SHIFT 0x0
+#define SEM_REQ_INPUT_2__DATA_MASK 0xFFFFFFFFL
+//SEM_REQ_INPUT_3
+#define SEM_REQ_INPUT_3__DATA__SHIFT 0x0
+#define SEM_REQ_INPUT_3__DATA_MASK 0xFFFFFFFFL
+//SEM_REGISTER_LAST_PART0
+#define SEM_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0
+#define SEM_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL
+//IH_RB_CNTL
+#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
+#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa
+#define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb
+#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
+#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11
+#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12
+#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14
+#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15
+#define IH_RB_CNTL__MC_RO__SHIFT 0x16
+#define IH_RB_CNTL__MC_VMID__SHIFT 0x18
+#define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
+#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L
+#define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L
+#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
+#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L
+#define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L
+#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L
+#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L
+#define IH_RB_CNTL__MC_RO_MASK 0x00400000L
+#define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L
+#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//IH_RB_BASE
+#define IH_RB_BASE__ADDR__SHIFT 0x0
+#define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//IH_RB_BASE_HI
+#define IH_RB_BASE_HI__ADDR__SHIFT 0x0
+#define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL
+//IH_RB_RPTR
+#define IH_RB_RPTR__OFFSET__SHIFT 0x2
+#define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//IH_RB_WPTR
+#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
+#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
+#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L
+#define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L
+#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L
+//IH_RB_WPTR_ADDR_HI
+#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL
+//IH_RB_WPTR_ADDR_LO
+#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//IH_DOORBELL_RPTR
+#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0
+#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c
+#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL
+#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L
+//IH_RB_CNTL_RING1
+#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
+#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa
+#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb
+#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc
+#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
+#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12
+#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14
+#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16
+#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18
+#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c
+#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L
+#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL
+#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L
+#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
+#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L
+#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L
+#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
+#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
+#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L
+#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L
+#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L
+#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L
+#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L
+#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//IH_RB_BASE_RING1
+#define IH_RB_BASE_RING1__ADDR__SHIFT 0x0
+#define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL
+//IH_RB_BASE_HI_RING1
+#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0
+#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL
+//IH_RB_RPTR_RING1
+#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2
+#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL
+//IH_RB_WPTR_RING1
+#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12
+#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13
+#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L
+#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL
+#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L
+#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L
+//IH_DOORBELL_RPTR_RING1
+#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0
+#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c
+#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL
+#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L
+//IH_RB_CNTL_RING2
+#define IH_RB_CNTL_RING2__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL_RING2__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
+#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT 0xa
+#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR__SHIFT 0xb
+#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT 0xc
+#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
+#define IH_RB_CNTL_RING2__MC_SWAP__SHIFT 0x12
+#define IH_RB_CNTL_RING2__MC_SNOOP__SHIFT 0x14
+#define IH_RB_CNTL_RING2__MC_RO__SHIFT 0x16
+#define IH_RB_CNTL_RING2__MC_VMID__SHIFT 0x18
+#define IH_RB_CNTL_RING2__MC_SPACE__SHIFT 0x1c
+#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_CNTL_RING2__RB_ENABLE_MASK 0x00000001L
+#define IH_RB_CNTL_RING2__RB_SIZE_MASK 0x0000003EL
+#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK 0x00000080L
+#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
+#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK 0x00000400L
+#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR_MASK 0x00000800L
+#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
+#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
+#define IH_RB_CNTL_RING2__MC_SWAP_MASK 0x000C0000L
+#define IH_RB_CNTL_RING2__MC_SNOOP_MASK 0x00100000L
+#define IH_RB_CNTL_RING2__MC_RO_MASK 0x00400000L
+#define IH_RB_CNTL_RING2__MC_VMID_MASK 0x0F000000L
+#define IH_RB_CNTL_RING2__MC_SPACE_MASK 0x70000000L
+#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//IH_RB_BASE_RING2
+#define IH_RB_BASE_RING2__ADDR__SHIFT 0x0
+#define IH_RB_BASE_RING2__ADDR_MASK 0xFFFFFFFFL
+//IH_RB_BASE_HI_RING2
+#define IH_RB_BASE_HI_RING2__ADDR__SHIFT 0x0
+#define IH_RB_BASE_HI_RING2__ADDR_MASK 0x000000FFL
+//IH_RB_RPTR_RING2
+#define IH_RB_RPTR_RING2__OFFSET__SHIFT 0x2
+#define IH_RB_RPTR_RING2__OFFSET_MASK 0x0003FFFCL
+//IH_RB_WPTR_RING2
+#define IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR_RING2__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT 0x12
+#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT 0x13
+#define IH_RB_WPTR_RING2__RB_OVERFLOW_MASK 0x00000001L
+#define IH_RB_WPTR_RING2__OFFSET_MASK 0x0003FFFCL
+#define IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK 0x00040000L
+#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK 0x00080000L
+//IH_DOORBELL_RPTR_RING2
+#define IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT 0x0
+#define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x1c
+#define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03FFFFFFL
+#define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L
+//IH_VERSION
+#define IH_VERSION__MINVER__SHIFT 0x0
+#define IH_VERSION__MAJVER__SHIFT 0x8
+#define IH_VERSION__REV__SHIFT 0x10
+#define IH_VERSION__MINVER_MASK 0x0000007FL
+#define IH_VERSION__MAJVER_MASK 0x00007F00L
+#define IH_VERSION__REV_MASK 0x003F0000L
+//IH_CNTL
+#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0
+#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6
+#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8
+#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
+#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL
+#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L
+#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L
+#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L
+//IH_CNTL2
+#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0
+#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8
+#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL
+#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L
+//IH_STATUS
+#define IH_STATUS__IDLE__SHIFT 0x0
+#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
+#define IH_STATUS__BUFFER_IDLE__SHIFT 0x2
+#define IH_STATUS__RB_FULL__SHIFT 0x3
+#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
+#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
+#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
+#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
+#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
+#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
+#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
+#define IH_STATUS__SWITCH_READY__SHIFT 0xb
+#define IH_STATUS__RB1_FULL__SHIFT 0xc
+#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd
+#define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe
+#define IH_STATUS__RB2_FULL__SHIFT 0xf
+#define IH_STATUS__RB2_FULL_DRAIN__SHIFT 0x10
+#define IH_STATUS__RB2_OVERFLOW__SHIFT 0x11
+#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12
+#define IH_STATUS__IDLE_MASK 0x00000001L
+#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L
+#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L
+#define IH_STATUS__RB_FULL_MASK 0x00000008L
+#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L
+#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L
+#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L
+#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L
+#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L
+#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L
+#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L
+#define IH_STATUS__SWITCH_READY_MASK 0x00000800L
+#define IH_STATUS__RB1_FULL_MASK 0x00001000L
+#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L
+#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L
+#define IH_STATUS__RB2_FULL_MASK 0x00008000L
+#define IH_STATUS__RB2_FULL_DRAIN_MASK 0x00010000L
+#define IH_STATUS__RB2_OVERFLOW_MASK 0x00020000L
+#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L
+//IH_PERFMON_CNTL
+#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
+#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
+#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10
+#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11
+#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12
+#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L
+#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L
+#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x00000FFCL
+#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L
+#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L
+#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0FFC0000L
+//IH_PERFCOUNTER0_RESULT
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//IH_PERFCOUNTER1_RESULT
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//IH_DSM_MATCH_VALUE_BIT_31_0
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL
+//IH_DSM_MATCH_VALUE_BIT_63_32
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL
+//IH_DSM_MATCH_VALUE_BIT_95_64
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL
+//IH_DSM_MATCH_FIELD_CONTROL
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
+#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
+#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L
+#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L
+#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L
+//IH_DSM_MATCH_DATA_CONTROL
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL
+//IH_DSM_MATCH_FCN_ID
+#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x0
+#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x7
+#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001FL
+#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000080L
+//IH_LIMIT_INT_RATE_CNTL
+#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0
+#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1
+#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5
+#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11
+#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15
+#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L
+#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL
+#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L
+#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L
+#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L
+//IH_VF_RB_STATUS
+#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
+#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x7FFFFFFFL
+//IH_VF_RB_STATUS2
+#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0
+#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x7FFFFFFFL
+//IH_VF_RB1_STATUS
+#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
+#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x7FFFFFFFL
+//IH_VF_RB1_STATUS2
+#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0
+#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x7FFFFFFFL
+//IH_VF_RB2_STATUS
+#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
+#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK 0x7FFFFFFFL
+//IH_VF_RB2_STATUS2
+#define IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT 0x0
+#define IH_VF_RB2_STATUS2__RB_FULL_VF_MASK 0x7FFFFFFFL
+//IH_INT_FLOOD_CNTL
+#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0
+#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3
+#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4
+#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L
+#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L
+#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L
+//IH_RB0_INT_FLOOD_STATUS
+#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
+#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
+#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x7FFFFFFFL
+#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
+//IH_RB1_INT_FLOOD_STATUS
+#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
+#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
+#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x7FFFFFFFL
+#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
+//IH_RB2_INT_FLOOD_STATUS
+#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
+#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
+#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x7FFFFFFFL
+#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
+//IH_INT_FLOOD_STATUS
+#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1d
+#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e
+#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x1F000000L
+#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x20000000L
+#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L
+//IH_STORM_CLIENT_LIST_CNTL
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L
+#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L
+//IH_CLK_CTRL
+#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a
+#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b
+#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c
+#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
+#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e
+#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
+#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L
+#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L
+#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L
+#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
+#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L
+#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
+//IH_INT_FLAGS
+#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0
+#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1
+#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2
+#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3
+#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4
+#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5
+#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6
+#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7
+#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8
+#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9
+#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa
+#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb
+#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc
+#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd
+#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe
+#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf
+#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10
+#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11
+#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12
+#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13
+#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14
+#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15
+#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16
+#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17
+#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18
+#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19
+#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a
+#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b
+#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c
+#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d
+#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e
+#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f
+#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L
+#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L
+#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L
+#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L
+#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L
+#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L
+#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L
+#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L
+#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L
+#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L
+#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L
+#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L
+#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L
+#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L
+#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L
+#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L
+#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L
+#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L
+#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L
+#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L
+#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L
+#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L
+#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L
+#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L
+#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L
+#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L
+#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L
+#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L
+#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L
+#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L
+#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L
+#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L
+//IH_LAST_INT_INFO0
+#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0
+#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8
+#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10
+#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18
+#define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f
+#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL
+#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L
+#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L
+#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L
+#define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L
+//IH_LAST_INT_INFO1
+#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0
+#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL
+//IH_LAST_INT_INFO2
+#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0
+#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10
+#define IH_LAST_INT_INFO2__VF__SHIFT 0x17
+#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL
+#define IH_LAST_INT_INFO2__VF_ID_MASK 0x001F0000L
+#define IH_LAST_INT_INFO2__VF_MASK 0x00800000L
+//IH_SCRATCH
+#define IH_SCRATCH__DATA__SHIFT 0x0
+#define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL
+//IH_CLIENT_CREDIT_ERROR
+#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f
+#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L
+#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L
+//IH_GPU_IOV_VIOLATION_LOG
+#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
+#define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14
+#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
+#define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x01F00000L
+//IH_GPU_IOV_VIOLATION_LOG2
+#define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
+#define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
+//IH_COOKIE_REC_VIOLATION_LOG
+#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x8
+#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x10
+#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x0000FF00L
+#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0x03FF0000L
+//IH_CREDIT_STATUS
+#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1
+#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2
+#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3
+#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4
+#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5
+#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6
+#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7
+#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8
+#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9
+#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa
+#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb
+#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc
+#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd
+#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe
+#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf
+#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10
+#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11
+#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12
+#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13
+#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14
+#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15
+#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16
+#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17
+#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18
+#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19
+#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a
+#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b
+#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c
+#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d
+#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e
+#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f
+#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L
+#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L
+#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L
+#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L
+#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L
+#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L
+#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L
+#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L
+#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L
+#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L
+#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L
+#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L
+#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L
+#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L
+#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L
+#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L
+#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L
+#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L
+#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L
+#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L
+#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L
+#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L
+#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L
+#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L
+#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L
+#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L
+#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L
+#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L
+#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L
+#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L
+#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L
+//IH_MMHUB_ERROR
+#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1
+#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2
+#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7
+#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L
+#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L
+#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L
+#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L
+//IH_MEM_POWER_CTRL
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT 0x0
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT 0x1
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT 0x2
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT 0x3
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT 0x4
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK 0x00000001L
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK 0x00000002L
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK 0x00000004L
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK 0x00000008L
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK 0x00000070L
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L
+#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L
+//IH_VF_RB_STATUS3
+#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0
+#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK 0x7FFFFFFFL
+//IH_VF_RB_STATUS4
+#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT 0x0
+#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK 0x7FFFFFFFL
+//IH_VF_RB1_STATUS3
+#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0
+#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK 0x7FFFFFFFL
+//IH_VF_RB2_STATUS3
+#define IH_VF_RB2_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0
+#define IH_VF_RB2_STATUS3__RB_OVERFLOW_VF_MASK 0x7FFFFFFFL
+//IH_REGISTER_LAST_PART2
+#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0
+#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL
+//SEM_CLK_CTRL
+#define SEM_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SEM_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SEM_CLK_CTRL__RESERVED__SHIFT 0xc
+#define SEM_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SEM_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SEM_CLK_CTRL__MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a
+#define SEM_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SEM_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SEM_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SEM_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e
+#define SEM_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
+#define SEM_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
+#define SEM_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define SEM_CLK_CTRL__RESERVED_MASK 0x00FFF000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
+#define SEM_CLK_CTRL__MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
+#define SEM_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
+#define SEM_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L
+#define SEM_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
+//SEM_UTC_CREDIT
+#define SEM_UTC_CREDIT__UTCL2_CREDIT__SHIFT 0x0
+#define SEM_UTC_CREDIT__WATERMARK__SHIFT 0x8
+#define SEM_UTC_CREDIT__UTCL2_CREDIT_MASK 0x0000001FL
+#define SEM_UTC_CREDIT__WATERMARK_MASK 0x00000F00L
+//SEM_UTC_CONFIG
+#define SEM_UTC_CONFIG__USE_MTYPE__SHIFT 0x0
+#define SEM_UTC_CONFIG__FORCE_SNOOP__SHIFT 0x3
+#define SEM_UTC_CONFIG__FORCE_GCC__SHIFT 0x4
+#define SEM_UTC_CONFIG__USE_PT_SNOOP__SHIFT 0x5
+#define SEM_UTC_CONFIG__USE_MTYPE_MASK 0x00000007L
+#define SEM_UTC_CONFIG__FORCE_SNOOP_MASK 0x00000008L
+#define SEM_UTC_CONFIG__FORCE_GCC_MASK 0x00000010L
+#define SEM_UTC_CONFIG__USE_PT_SNOOP_MASK 0x00000020L
+//SEM_UTCL2_TRAN_EN_LUT
+#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN__SHIFT 0x0
+#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN__SHIFT 0x1
+#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN__SHIFT 0x2
+#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN__SHIFT 0x3
+#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN__SHIFT 0x4
+#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN__SHIFT 0x5
+#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN__SHIFT 0x6
+#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN__SHIFT 0x7
+#define SEM_UTCL2_TRAN_EN_LUT__RESERVED__SHIFT 0x8
+#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN__SHIFT 0x1f
+#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN_MASK 0x00000001L
+#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN_MASK 0x00000002L
+#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN_MASK 0x00000004L
+#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN_MASK 0x00000008L
+#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN_MASK 0x00000010L
+#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN_MASK 0x00000020L
+#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN_MASK 0x00000040L
+#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN_MASK 0x00000080L
+#define SEM_UTCL2_TRAN_EN_LUT__RESERVED_MASK 0x7FFFFF00L
+#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN_MASK 0x80000000L
+//SEM_MCIF_CONFIG
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0x000000FCL
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x00003F00L
+//SEM_PERFMON_CNTL
+#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
+#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
+#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
+#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
+#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
+#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
+//SEM_PERFCOUNTER0_RESULT
+#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SEM_PERFCOUNTER1_RESULT
+#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
+//SEM_STATUS
+#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
+#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
+#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
+#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
+#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
+#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
+#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
+#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
+#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
+#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
+#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
+#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf
+#define SEM_STATUS__OUTSTANDING_CLEAN__SHIFT 0x10
+#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH__SHIFT 0x11
+#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH__SHIFT 0x12
+#define SEM_STATUS__INVREQ_CNT_IDLE__SHIFT 0x13
+#define SEM_STATUS__ENTRYLIST_IDLE__SHIFT 0x14
+#define SEM_STATUS__MIF_IDLE__SHIFT 0x15
+#define SEM_STATUS__REGISTER_IDLE__SHIFT 0x16
+#define SEM_STATUS__ATCL2_INVREQ_IDLE__SHIFT 0x17
+#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f
+#define SEM_STATUS__SEM_IDLE_MASK 0x00000001L
+#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x00000002L
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x00000004L
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x00000008L
+#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x00000010L
+#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x00000020L
+#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x00000040L
+#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x00000080L
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x00000100L
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x00000200L
+#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x00000400L
+#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x00000800L
+#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x00001000L
+#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x00002000L
+#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x00004000L
+#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x00008000L
+#define SEM_STATUS__OUTSTANDING_CLEAN_MASK 0x00010000L
+#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH_MASK 0x00020000L
+#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH_MASK 0x00040000L
+#define SEM_STATUS__INVREQ_CNT_IDLE_MASK 0x00080000L
+#define SEM_STATUS__ENTRYLIST_IDLE_MASK 0x00100000L
+#define SEM_STATUS__MIF_IDLE_MASK 0x00200000L
+#define SEM_STATUS__REGISTER_IDLE_MASK 0x00400000L
+#define SEM_STATUS__ATCL2_INVREQ_IDLE_MASK 0x00800000L
+#define SEM_STATUS__SWITCH_READY_MASK 0x80000000L
+//SEM_MAILBOX_CLIENTCONFIG
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001C0L
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000E00L
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x00007000L
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x001C0000L
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00E00000L
+//SEM_MAILBOX
+#define SEM_MAILBOX__HOSTPORT__SHIFT 0x0
+#define SEM_MAILBOX__RESERVED__SHIFT 0x10
+#define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL
+#define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L
+//SEM_MAILBOX_CONTROL
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x0
+#define SEM_MAILBOX_CONTROL__RESERVED__SHIFT 0x10
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000FFFFL
+#define SEM_MAILBOX_CONTROL__RESERVED_MASK 0xFFFF0000L
+//SEM_CHICKEN_BITS
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
+#define SEM_CHICKEN_BITS__CLIENT_REQ_FCNID_CHECK__SHIFT 0x5
+#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6
+#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
+#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX__SHIFT 0xa
+#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc
+#define SEM_CHICKEN_BITS__ATOMIC_EN__SHIFT 0xe
+#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK__SHIFT 0xf
+#define SEM_CHICKEN_BITS__CLEAR_MAILBOX__SHIFT 0x10
+#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN__SHIFT 0x12
+#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK__SHIFT 0x13
+#define SEM_CHICKEN_BITS__VM_INV_FLUSH__SHIFT 0x14
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x00000001L
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x00000002L
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x00000004L
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x00000018L
+#define SEM_CHICKEN_BITS__CLIENT_REQ_FCNID_CHECK_MASK 0x00000020L
+#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x00000040L
+#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x00000080L
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0x00000300L
+#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX_MASK 0x00000C00L
+#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x00003000L
+#define SEM_CHICKEN_BITS__ATOMIC_EN_MASK 0x00004000L
+#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK_MASK 0x00008000L
+#define SEM_CHICKEN_BITS__CLEAR_MAILBOX_MASK 0x00030000L
+#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN_MASK 0x00040000L
+#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK_MASK 0x00080000L
+#define SEM_CHICKEN_BITS__VM_INV_FLUSH_MASK 0x00100000L
+//SEM_MAILBOX_CLIENTCONFIG_EXTRA
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x0000000FL
+//SEM_GPU_IOV_VIOLATION_LOG
+#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
+#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
+#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
+#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
+#define SEM_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
+#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14
+#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
+#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
+#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
+#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
+#define SEM_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
+#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x01F00000L
+//SEM_OUTSTANDING_THRESHOLD
+#define SEM_OUTSTANDING_THRESHOLD__VALUE__SHIFT 0x0
+#define SEM_OUTSTANDING_THRESHOLD__VALUE_MASK 0x000000FFL
+//SEM_MEM_POWER_CTRL
+#define SEM_MEM_POWER_CTRL__MEM_POWER_CTRL_EN__SHIFT 0x0
+#define SEM_MEM_POWER_CTRL__MEM_POWER_LS_EN__SHIFT 0x1
+#define SEM_MEM_POWER_CTRL__MEM_POWER_DS_EN__SHIFT 0x2
+#define SEM_MEM_POWER_CTRL__MEM_POWER_SD_EN__SHIFT 0x3
+#define SEM_MEM_POWER_CTRL__MEM_IDLE_HYSTERESIS__SHIFT 0x4
+#define SEM_MEM_POWER_CTRL__MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8
+#define SEM_MEM_POWER_CTRL__MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe
+#define SEM_MEM_POWER_CTRL__MEM_POWER_CTRL_EN_MASK 0x00000001L
+#define SEM_MEM_POWER_CTRL__MEM_POWER_LS_EN_MASK 0x00000002L
+#define SEM_MEM_POWER_CTRL__MEM_POWER_DS_EN_MASK 0x00000004L
+#define SEM_MEM_POWER_CTRL__MEM_POWER_SD_EN_MASK 0x00000008L
+#define SEM_MEM_POWER_CTRL__MEM_IDLE_HYSTERESIS_MASK 0x00000070L
+#define SEM_MEM_POWER_CTRL__MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L
+#define SEM_MEM_POWER_CTRL__MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L
+//SEM_GPU_IOV_VIOLATION_LOG2
+#define SEM_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
+#define SEM_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
+//SEM_REGISTER_LAST_PART2
+#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0
+#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL
+//IH_ACTIVE_FCN_ID
+#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
+#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5
+#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
+#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000001FL
+#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L
+#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
+//IH_VIRT_RESET_REQ
+#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define IH_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
+#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//IH_CLIENT_CFG
+#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0
+#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001FL
+//IH_CLIENT_CFG_INDEX
+#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0
+#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL
+//IH_CLIENT_CFG_DATA
+#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT 0x0
+#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12
+#define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x14
+#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16
+#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18
+#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT 0x19
+#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK 0x0003FFFFL
+#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L
+#define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L
+#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L
+#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L
+#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK 0x02000000L
+//IH_CID_REMAP_INDEX
+#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0
+#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L
+//IH_CID_REMAP_DATA
+#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0
+#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8
+#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18
+#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL
+#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L
+#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L
+//IH_CHICKEN
+#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0
+#define IH_CHICKEN__DBGU_TRIGGER_ENABLE__SHIFT 0x1
+#define IH_CHICKEN__CROSS_TRIGGER_ENABLE__SHIFT 0x2
+#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3
+#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4
+#define IH_CHICKEN__REG_FIREWALL_ENABLE__SHIFT 0x5
+#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L
+#define IH_CHICKEN__DBGU_TRIGGER_ENABLE_MASK 0x00000002L
+#define IH_CHICKEN__CROSS_TRIGGER_ENABLE_MASK 0x00000004L
+#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L
+#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L
+#define IH_CHICKEN__REG_FIREWALL_ENABLE_MASK 0x00000020L
+//IH_MMHUB_CNTL
+#define IH_MMHUB_CNTL__UNITID__SHIFT 0x0
+#define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8
+#define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc
+#define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL
+#define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000700L
+#define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x00007000L
+//IH_INT_DROP_CNTL
+#define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0
+#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1
+#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2
+#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3
+#define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4
+#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5
+#define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6
+#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8
+#define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10
+#define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L
+#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L
+#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L
+#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L
+#define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L
+#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L
+#define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L
+#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L
+#define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L
+//IH_INT_DROP_MATCH_VALUE0
+#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0
+#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8
+#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10
+#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17
+#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18
+#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL
+#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L
+#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x001F0000L
+#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L
+#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L
+//IH_INT_DROP_MATCH_VALUE1
+#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0
+#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL
+//IH_INT_DROP_MATCH_MASK0
+#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0
+#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8
+#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10
+#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17
+#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18
+#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL
+#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L
+#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x001F0000L
+#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L
+#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L
+//IH_INT_DROP_MATCH_MASK1
+#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0
+#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL
+//IH_REGISTER_LAST_PART1
+#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0
+#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL
+//SEM_ACTIVE_FCN_ID
+#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SEM_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
+#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000L
+//SEM_VIRT_RESET_REQ
+#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SEM_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
+#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000L
+//SEM_RESP_SDMA0
+#define SEM_RESP_SDMA0__ADDR__SHIFT 0x0
+#define SEM_RESP_SDMA0__ADDR_MASK 0x0FFFFFFFL
+//SEM_RESP_SDMA1
+#define SEM_RESP_SDMA1__ADDR__SHIFT 0x0
+#define SEM_RESP_SDMA1__ADDR_MASK 0x0FFFFFFFL
+//SEM_RESP_UVD
+#define SEM_RESP_UVD__ADDR__SHIFT 0x0
+#define SEM_RESP_UVD__ADDR_MASK 0x0FFFFFFFL
+//SEM_RESP_VCE_0
+#define SEM_RESP_VCE_0__ADDR__SHIFT 0x0
+#define SEM_RESP_VCE_0__ADDR_MASK 0x0FFFFFFFL
+//SEM_RESP_ACP
+#define SEM_RESP_ACP__ADDR__SHIFT 0x0
+#define SEM_RESP_ACP__ADDR_MASK 0x0FFFFFFFL
+//SEM_RESP_ISP
+#define SEM_RESP_ISP__ADDR__SHIFT 0x0
+#define SEM_RESP_ISP__ADDR_MASK 0x0FFFFFFFL
+//SEM_RESP_VCE_1
+#define SEM_RESP_VCE_1__ADDR__SHIFT 0x0
+#define SEM_RESP_VCE_1__ADDR_MASK 0x0FFFFFFFL
+//SEM_RESP_VP8
+#define SEM_RESP_VP8__ADDR__SHIFT 0x0
+#define SEM_RESP_VP8__ADDR_MASK 0x0FFFFFFFL
+//SEM_RESP_GC
+#define SEM_RESP_GC__ADDR__SHIFT 0x0
+#define SEM_RESP_GC__ADDR_MASK 0x0FFFFFFFL
+//SEM_CID_REMAP_INDEX
+#define SEM_CID_REMAP_INDEX__INDEX__SHIFT 0x0
+#define SEM_CID_REMAP_INDEX__INDEX_MASK 0x00000003L
+//SEM_CID_REMAP_DATA
+#define SEM_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0
+#define SEM_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8
+#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18
+#define SEM_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL
+#define SEM_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L
+#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L
+//SEM_ATOMIC_OP_LUT
+#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL__SHIFT 0x0
+#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1__SHIFT 0x7
+#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL__SHIFT 0xe
+#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0__SHIFT 0x15
+#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL_MASK 0x0000007FL
+#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1_MASK 0x00003F80L
+#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL_MASK 0x001FC000L
+#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0_MASK 0x0FE00000L
+//SEM_EDC_CONFIG
+#define SEM_EDC_CONFIG__WRITE_DIS__SHIFT 0x0
+#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SEM_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L
+#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
+//SEM_CHICKEN_BITS2
+#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0
+#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID__SHIFT 0x1
+#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L
+#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID_MASK 0x00000002L
+//SEM_MMHUB_CNTL
+#define SEM_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
+#define SEM_MMHUB_CNTL__TLVL_VALUE__SHIFT 0x8
+#define SEM_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
+#define SEM_MMHUB_CNTL__TLVL_VALUE_MASK 0x00000700L
+//SEM_REGISTER_LAST_PART1
+#define SEM_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0
+#define SEM_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
new file mode 100644
index 000000000000..5df70484bc7d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_11_0_0_OFFSET_HEADER
+#define _smuio_11_0_0_OFFSET_HEADER
+
+
+
+// addressBlock: smuio_smuio_SmuSmuioDec
+// base address: 0x5a000
+#define mmSMUSVI0_TEL_PLANE0 0x0004
+#define mmSMUSVI0_TEL_PLANE0_BASE_IDX 0
+#define mmSMUIO_MCM_CONFIG 0x0024
+#define mmSMUIO_MCM_CONFIG_BASE_IDX 0
+#define mmSMUIO_MP_RESET_INTR 0x00c1
+#define mmSMUIO_MP_RESET_INTR_BASE_IDX 0
+#define mmSMUIO_SOC_HALT 0x00c2
+#define mmSMUIO_SOC_HALT_BASE_IDX 0
+#define mmSMUIO_PWRMGT 0x00c8
+#define mmSMUIO_PWRMGT_BASE_IDX 0
+#define mmROM_CNTL 0x00e0
+#define mmROM_CNTL_BASE_IDX 0
+#define mmPAGE_MIRROR_CNTL 0x00e1
+#define mmPAGE_MIRROR_CNTL_BASE_IDX 0
+#define mmROM_STATUS 0x00e2
+#define mmROM_STATUS_BASE_IDX 0
+#define mmCGTT_ROM_CLK_CTRL0 0x00e3
+#define mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0
+#define mmROM_INDEX 0x00e4
+#define mmROM_INDEX_BASE_IDX 0
+#define mmROM_DATA 0x00e5
+#define mmROM_DATA_BASE_IDX 0
+#define mmROM_START 0x00e6
+#define mmROM_START_BASE_IDX 0
+#define mmROM_SW_CNTL 0x00e7
+#define mmROM_SW_CNTL_BASE_IDX 0
+#define mmROM_SW_STATUS 0x00e8
+#define mmROM_SW_STATUS_BASE_IDX 0
+#define mmROM_SW_COMMAND 0x00e9
+#define mmROM_SW_COMMAND_BASE_IDX 0
+#define mmROM_SW_DATA_1 0x00ea
+#define mmROM_SW_DATA_1_BASE_IDX 0
+#define mmROM_SW_DATA_2 0x00eb
+#define mmROM_SW_DATA_2_BASE_IDX 0
+#define mmROM_SW_DATA_3 0x00ec
+#define mmROM_SW_DATA_3_BASE_IDX 0
+#define mmROM_SW_DATA_4 0x00ed
+#define mmROM_SW_DATA_4_BASE_IDX 0
+#define mmROM_SW_DATA_5 0x00ee
+#define mmROM_SW_DATA_5_BASE_IDX 0
+#define mmROM_SW_DATA_6 0x00ef
+#define mmROM_SW_DATA_6_BASE_IDX 0
+#define mmROM_SW_DATA_7 0x00f0
+#define mmROM_SW_DATA_7_BASE_IDX 0
+#define mmROM_SW_DATA_8 0x00f1
+#define mmROM_SW_DATA_8_BASE_IDX 0
+#define mmROM_SW_DATA_9 0x00f2
+#define mmROM_SW_DATA_9_BASE_IDX 0
+#define mmROM_SW_DATA_10 0x00f3
+#define mmROM_SW_DATA_10_BASE_IDX 0
+#define mmROM_SW_DATA_11 0x00f4
+#define mmROM_SW_DATA_11_BASE_IDX 0
+#define mmROM_SW_DATA_12 0x00f5
+#define mmROM_SW_DATA_12_BASE_IDX 0
+#define mmROM_SW_DATA_13 0x00f6
+#define mmROM_SW_DATA_13_BASE_IDX 0
+#define mmROM_SW_DATA_14 0x00f7
+#define mmROM_SW_DATA_14_BASE_IDX 0
+#define mmROM_SW_DATA_15 0x00f8
+#define mmROM_SW_DATA_15_BASE_IDX 0
+#define mmROM_SW_DATA_16 0x00f9
+#define mmROM_SW_DATA_16_BASE_IDX 0
+#define mmROM_SW_DATA_17 0x00fa
+#define mmROM_SW_DATA_17_BASE_IDX 0
+#define mmROM_SW_DATA_18 0x00fb
+#define mmROM_SW_DATA_18_BASE_IDX 0
+#define mmROM_SW_DATA_19 0x00fc
+#define mmROM_SW_DATA_19_BASE_IDX 0
+#define mmROM_SW_DATA_20 0x00fd
+#define mmROM_SW_DATA_20_BASE_IDX 0
+#define mmROM_SW_DATA_21 0x00fe
+#define mmROM_SW_DATA_21_BASE_IDX 0
+#define mmROM_SW_DATA_22 0x00ff
+#define mmROM_SW_DATA_22_BASE_IDX 0
+#define mmROM_SW_DATA_23 0x0100
+#define mmROM_SW_DATA_23_BASE_IDX 0
+#define mmROM_SW_DATA_24 0x0101
+#define mmROM_SW_DATA_24_BASE_IDX 0
+#define mmROM_SW_DATA_25 0x0102
+#define mmROM_SW_DATA_25_BASE_IDX 0
+#define mmROM_SW_DATA_26 0x0103
+#define mmROM_SW_DATA_26_BASE_IDX 0
+#define mmROM_SW_DATA_27 0x0104
+#define mmROM_SW_DATA_27_BASE_IDX 0
+#define mmROM_SW_DATA_28 0x0105
+#define mmROM_SW_DATA_28_BASE_IDX 0
+#define mmROM_SW_DATA_29 0x0106
+#define mmROM_SW_DATA_29_BASE_IDX 0
+#define mmROM_SW_DATA_30 0x0107
+#define mmROM_SW_DATA_30_BASE_IDX 0
+#define mmROM_SW_DATA_31 0x0108
+#define mmROM_SW_DATA_31_BASE_IDX 0
+#define mmROM_SW_DATA_32 0x0109
+#define mmROM_SW_DATA_32_BASE_IDX 0
+#define mmROM_SW_DATA_33 0x010a
+#define mmROM_SW_DATA_33_BASE_IDX 0
+#define mmROM_SW_DATA_34 0x010b
+#define mmROM_SW_DATA_34_BASE_IDX 0
+#define mmROM_SW_DATA_35 0x010c
+#define mmROM_SW_DATA_35_BASE_IDX 0
+#define mmROM_SW_DATA_36 0x010d
+#define mmROM_SW_DATA_36_BASE_IDX 0
+#define mmROM_SW_DATA_37 0x010e
+#define mmROM_SW_DATA_37_BASE_IDX 0
+#define mmROM_SW_DATA_38 0x010f
+#define mmROM_SW_DATA_38_BASE_IDX 0
+#define mmROM_SW_DATA_39 0x0110
+#define mmROM_SW_DATA_39_BASE_IDX 0
+#define mmROM_SW_DATA_40 0x0111
+#define mmROM_SW_DATA_40_BASE_IDX 0
+#define mmROM_SW_DATA_41 0x0112
+#define mmROM_SW_DATA_41_BASE_IDX 0
+#define mmROM_SW_DATA_42 0x0113
+#define mmROM_SW_DATA_42_BASE_IDX 0
+#define mmROM_SW_DATA_43 0x0114
+#define mmROM_SW_DATA_43_BASE_IDX 0
+#define mmROM_SW_DATA_44 0x0115
+#define mmROM_SW_DATA_44_BASE_IDX 0
+#define mmROM_SW_DATA_45 0x0116
+#define mmROM_SW_DATA_45_BASE_IDX 0
+#define mmROM_SW_DATA_46 0x0117
+#define mmROM_SW_DATA_46_BASE_IDX 0
+#define mmROM_SW_DATA_47 0x0118
+#define mmROM_SW_DATA_47_BASE_IDX 0
+#define mmROM_SW_DATA_48 0x0119
+#define mmROM_SW_DATA_48_BASE_IDX 0
+#define mmROM_SW_DATA_49 0x011a
+#define mmROM_SW_DATA_49_BASE_IDX 0
+#define mmROM_SW_DATA_50 0x011b
+#define mmROM_SW_DATA_50_BASE_IDX 0
+#define mmROM_SW_DATA_51 0x011c
+#define mmROM_SW_DATA_51_BASE_IDX 0
+#define mmROM_SW_DATA_52 0x011d
+#define mmROM_SW_DATA_52_BASE_IDX 0
+#define mmROM_SW_DATA_53 0x011e
+#define mmROM_SW_DATA_53_BASE_IDX 0
+#define mmROM_SW_DATA_54 0x011f
+#define mmROM_SW_DATA_54_BASE_IDX 0
+#define mmROM_SW_DATA_55 0x0120
+#define mmROM_SW_DATA_55_BASE_IDX 0
+#define mmROM_SW_DATA_56 0x0121
+#define mmROM_SW_DATA_56_BASE_IDX 0
+#define mmROM_SW_DATA_57 0x0122
+#define mmROM_SW_DATA_57_BASE_IDX 0
+#define mmROM_SW_DATA_58 0x0123
+#define mmROM_SW_DATA_58_BASE_IDX 0
+#define mmROM_SW_DATA_59 0x0124
+#define mmROM_SW_DATA_59_BASE_IDX 0
+#define mmROM_SW_DATA_60 0x0125
+#define mmROM_SW_DATA_60_BASE_IDX 0
+#define mmROM_SW_DATA_61 0x0126
+#define mmROM_SW_DATA_61_BASE_IDX 0
+#define mmROM_SW_DATA_62 0x0127
+#define mmROM_SW_DATA_62_BASE_IDX 0
+#define mmROM_SW_DATA_63 0x0128
+#define mmROM_SW_DATA_63_BASE_IDX 0
+#define mmROM_SW_DATA_64 0x0129
+#define mmROM_SW_DATA_64_BASE_IDX 0
+#define mmSMU_GPIOPAD_SW_INT_STAT 0x0140
+#define mmSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0
+#define mmSMU_GPIOPAD_MASK 0x0141
+#define mmSMU_GPIOPAD_MASK_BASE_IDX 0
+#define mmSMU_GPIOPAD_A 0x0142
+#define mmSMU_GPIOPAD_A_BASE_IDX 0
+#define mmSMU_GPIOPAD_TXIMPSEL 0x0143
+#define mmSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0
+#define mmSMU_GPIOPAD_EN 0x0144
+#define mmSMU_GPIOPAD_EN_BASE_IDX 0
+#define mmSMU_GPIOPAD_Y 0x0145
+#define mmSMU_GPIOPAD_Y_BASE_IDX 0
+#define mmSMU_GPIOPAD_RXEN 0x0146
+#define mmSMU_GPIOPAD_RXEN_BASE_IDX 0
+#define mmSMU_GPIOPAD_RCVR_SEL0 0x0147
+#define mmSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0
+#define mmSMU_GPIOPAD_RCVR_SEL1 0x0148
+#define mmSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0
+#define mmSMU_GPIOPAD_PU_EN 0x0149
+#define mmSMU_GPIOPAD_PU_EN_BASE_IDX 0
+#define mmSMU_GPIOPAD_PD_EN 0x014a
+#define mmSMU_GPIOPAD_PD_EN_BASE_IDX 0
+#define mmSMU_GPIOPAD_PINSTRAPS 0x014b
+#define mmSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0
+#define mmDFT_PINSTRAPS 0x014c
+#define mmDFT_PINSTRAPS_BASE_IDX 0
+#define mmSMU_GPIOPAD_INT_STAT_EN 0x014d
+#define mmSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0
+#define mmSMU_GPIOPAD_INT_STAT 0x014e
+#define mmSMU_GPIOPAD_INT_STAT_BASE_IDX 0
+#define mmSMU_GPIOPAD_INT_STAT_AK 0x014f
+#define mmSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0
+#define mmSMU_GPIOPAD_INT_EN 0x0150
+#define mmSMU_GPIOPAD_INT_EN_BASE_IDX 0
+#define mmSMU_GPIOPAD_INT_TYPE 0x0151
+#define mmSMU_GPIOPAD_INT_TYPE_BASE_IDX 0
+#define mmSMU_GPIOPAD_INT_POLARITY 0x0152
+#define mmSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0
+#define mmROM_CC_BIF_PINSTRAP 0x0153
+#define mmROM_CC_BIF_PINSTRAP_BASE_IDX 0
+#define mmIO_SMUIO_PINSTRAP 0x0154
+#define mmIO_SMUIO_PINSTRAP_BASE_IDX 0
+#define mmSMUIO_PCC_CONTROL 0x0155
+#define mmSMUIO_PCC_CONTROL_BASE_IDX 0
+#define mmSMUIO_PCC_GPIO_SELECT 0x0156
+#define mmSMUIO_PCC_GPIO_SELECT_BASE_IDX 0
+#define mmSMUIO_GPIO_INT0_SELECT 0x0157
+#define mmSMUIO_GPIO_INT0_SELECT_BASE_IDX 0
+#define mmSMUIO_GPIO_INT1_SELECT 0x0158
+#define mmSMUIO_GPIO_INT1_SELECT_BASE_IDX 0
+#define mmSMUIO_GPIO_INT2_SELECT 0x0159
+#define mmSMUIO_GPIO_INT2_SELECT_BASE_IDX 0
+#define mmSMUIO_GPIO_INT3_SELECT 0x015a
+#define mmSMUIO_GPIO_INT3_SELECT_BASE_IDX 0
+#define mmSMU_GPIOPAD_MP_INT0_STAT 0x015b
+#define mmSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0
+#define mmSMU_GPIOPAD_MP_INT1_STAT 0x015c
+#define mmSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0
+#define mmSMU_GPIOPAD_MP_INT2_STAT 0x015d
+#define mmSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0
+#define mmSMU_GPIOPAD_MP_INT3_STAT 0x015e
+#define mmSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0
+#define mmSMIO_INDEX 0x015f
+#define mmSMIO_INDEX_BASE_IDX 0
+#define mmS0_VID_SMIO_CNTL 0x0160
+#define mmS0_VID_SMIO_CNTL_BASE_IDX 0
+#define mmS1_VID_SMIO_CNTL 0x0161
+#define mmS1_VID_SMIO_CNTL_BASE_IDX 0
+#define mmOPEN_DRAIN_SELECT 0x0162
+#define mmOPEN_DRAIN_SELECT_BASE_IDX 0
+#define mmSMIO_ENABLE 0x0163
+#define mmSMIO_ENABLE_BASE_IDX 0
+#define mmSMU_GPIOPAD_S0 0x0166
+#define mmSMU_GPIOPAD_S0_BASE_IDX 0
+#define mmSMU_GPIOPAD_S1 0x0167
+#define mmSMU_GPIOPAD_S1_BASE_IDX 0
+#define mmSMU_GPIOPAD_SCL_EN 0x0168
+#define mmSMU_GPIOPAD_SCL_EN_BASE_IDX 0
+#define mmSMU_GPIOPAD_SDA_EN 0x0169
+#define mmSMU_GPIOPAD_SDA_EN_BASE_IDX 0
+#define mmSMU_GPIOPAD_SCHMEN 0x016a
+#define mmSMU_GPIOPAD_SCHMEN_BASE_IDX 0
+
+
+// addressBlock: smuio_smuio_pwr_SmuSmuioDec
+// base address: 0x5a800
+#define mmIP_DISCOVERY_VERSION 0x0000
+#define mmIP_DISCOVERY_VERSION_BASE_IDX 1
+#define mmSOC_GAP_PWROK 0x00f8
+#define mmSOC_GAP_PWROK_BASE_IDX 1
+#define mmGFX_GAP_PWROK 0x00f9
+#define mmGFX_GAP_PWROK_BASE_IDX 1
+#define mmPWROK_REFCLK_GAP_CYCLES 0x00fa
+#define mmPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1
+#define mmGOLDEN_TSC_INCREMENT_UPPER 0x0100
+#define mmGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1
+#define mmGOLDEN_TSC_INCREMENT_LOWER 0x0101
+#define mmGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1
+#define mmGOLDEN_TSC_COUNT_UPPER 0x0102
+#define mmGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1
+#define mmGOLDEN_TSC_COUNT_LOWER 0x0103
+#define mmGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1
+#define mmSOC_GOLDEN_TSC_SHADOW_UPPER 0x0104
+#define mmSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
+#define mmSOC_GOLDEN_TSC_SHADOW_LOWER 0x0105
+#define mmSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
+#define mmGFX_GOLDEN_TSC_SHADOW_UPPER 0x0106
+#define mmGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
+#define mmGFX_GOLDEN_TSC_SHADOW_LOWER 0x0107
+#define mmGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
+#define mmPWR_VIRT_RESET_REQ 0x0108
+#define mmPWR_VIRT_RESET_REQ_BASE_IDX 1
+#define mmSCRATCH_REGISTER0 0x0110
+#define mmSCRATCH_REGISTER0_BASE_IDX 1
+#define mmSCRATCH_REGISTER1 0x0111
+#define mmSCRATCH_REGISTER1_BASE_IDX 1
+#define mmSCRATCH_REGISTER2 0x0112
+#define mmSCRATCH_REGISTER2_BASE_IDX 1
+#define mmSCRATCH_REGISTER3 0x0113
+#define mmSCRATCH_REGISTER3_BASE_IDX 1
+#define mmSCRATCH_REGISTER4 0x0114
+#define mmSCRATCH_REGISTER4_BASE_IDX 1
+#define mmSCRATCH_REGISTER5 0x0115
+#define mmSCRATCH_REGISTER5_BASE_IDX 1
+#define mmSCRATCH_REGISTER6 0x0116
+#define mmSCRATCH_REGISTER6_BASE_IDX 1
+#define mmSCRATCH_REGISTER7 0x0117
+#define mmSCRATCH_REGISTER7_BASE_IDX 1
+#define mmPWR_DISP_TIMER_CONTROL 0x012c
+#define mmPWR_DISP_TIMER_CONTROL_BASE_IDX 1
+#define mmPWR_DISP_TIMER2_CONTROL 0x012e
+#define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX 1
+#define mmPWR_DISP_TIMER_GLOBAL_CONTROL 0x0130
+#define mmPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1
+#define mmPWR_IH_CONTROL 0x0131
+#define mmPWR_IH_CONTROL_BASE_IDX 1
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
new file mode 100644
index 000000000000..237961558e89
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
@@ -0,0 +1,689 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_11_0_0_SH_MASK_HEADER
+#define _smuio_11_0_0_SH_MASK_HEADER
+
+
+// addressBlock: smuio_smuio_SmuSmuioDec
+//SMUSVI0_TEL_PLANE0
+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0
+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10
+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL
+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L
+//SMUIO_MCM_CONFIG
+#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0
+#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2
+#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x5
+#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x6
+#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L
+#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL
+#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L
+#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x000000C0L
+//SMUIO_MP_RESET_INTR
+#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0
+#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L
+//SMUIO_SOC_HALT
+#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2
+#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3
+#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L
+#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L
+//SMUIO_PWRMGT
+#define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0
+#define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4
+#define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L
+#define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L
+//ROM_CNTL
+#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0
+#define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14
+#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15
+#define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16
+#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17
+#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c
+#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L
+#define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L
+#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L
+#define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L
+#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L
+//PAGE_MIRROR_CNTL
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x00FFFFFFL
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x01000000L
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L
+//ROM_STATUS
+#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
+#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L
+//CGTT_ROM_CLK_CTRL0
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
+//ROM_INDEX
+#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
+#define ROM_INDEX__ROM_INDEX_MASK 0x00FFFFFFL
+//ROM_DATA
+#define ROM_DATA__ROM_DATA__SHIFT 0x0
+#define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL
+//ROM_START
+#define ROM_START__ROM_START__SHIFT 0x0
+#define ROM_START__ROM_START_MASK 0x00FFFFFFL
+//ROM_SW_CNTL
+#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
+#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
+#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL
+#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L
+//ROM_SW_STATUS
+#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
+#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L
+//ROM_SW_COMMAND
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L
+//ROM_SW_DATA_1
+#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_2
+#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_3
+#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_4
+#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_5
+#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_6
+#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_7
+#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_8
+#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_9
+#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_10
+#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_11
+#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_12
+#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_13
+#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_14
+#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_15
+#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_16
+#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_17
+#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_18
+#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_19
+#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_20
+#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_21
+#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_22
+#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_23
+#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_24
+#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_25
+#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_26
+#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_27
+#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_28
+#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_29
+#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_30
+#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_31
+#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_32
+#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_33
+#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_34
+#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_35
+#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_36
+#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_37
+#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_38
+#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_39
+#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_40
+#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_41
+#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_42
+#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_43
+#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_44
+#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_45
+#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_46
+#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_47
+#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_48
+#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_49
+#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_50
+#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_51
+#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_52
+#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_53
+#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_54
+#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_55
+#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_56
+#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_57
+#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_58
+#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_59
+#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_60
+#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_61
+#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_62
+#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_63
+#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//ROM_SW_DATA_64
+#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL
+//SMU_GPIOPAD_SW_INT_STAT
+#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L
+//SMU_GPIOPAD_MASK
+#define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
+#define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_A
+#define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0
+#define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_TXIMPSEL
+#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0
+#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_EN
+#define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0
+#define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_Y
+#define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0
+#define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_RXEN
+#define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0
+#define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_RCVR_SEL0
+#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0
+#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_RCVR_SEL1
+#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0
+#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_PU_EN
+#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
+#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_PD_EN
+#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
+#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_PINSTRAPS
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L
+#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L
+//DFT_PINSTRAPS
+#define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0
+#define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000000FFL
+//SMU_GPIOPAD_INT_STAT_EN
+#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
+#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L
+//SMU_GPIOPAD_INT_STAT
+#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L
+//SMU_GPIOPAD_INT_STAT_AK
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
+#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L
+#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L
+#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L
+//SMU_GPIOPAD_INT_EN
+#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
+#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L
+//SMU_GPIOPAD_INT_TYPE
+#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
+#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L
+//SMU_GPIOPAD_INT_POLARITY
+#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
+#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
+#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL
+#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L
+//ROM_CC_BIF_PINSTRAP
+#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x0
+#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT 0x1
+#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x4
+#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x7
+#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x8
+#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x9
+#define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT 0xa
+#define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L
+#define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK 0x0000000EL
+#define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L
+#define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L
+#define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L
+#define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L
+#define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK 0x00000400L
+//IO_SMUIO_PINSTRAP
+#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0
+#define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3
+#define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x5
+#define IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT 0x8
+#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L
+#define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L
+#define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000E0L
+#define IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK 0x00000100L
+//SMUIO_PCC_CONTROL
+#define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
+#define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L
+//SMUIO_PCC_GPIO_SELECT
+#define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
+#define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL
+//SMUIO_GPIO_INT0_SELECT
+#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0
+#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL
+//SMUIO_GPIO_INT1_SELECT
+#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0
+#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL
+//SMUIO_GPIO_INT2_SELECT
+#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0
+#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL
+//SMUIO_GPIO_INT3_SELECT
+#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0
+#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL
+//SMU_GPIOPAD_MP_INT0_STAT
+#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL
+//SMU_GPIOPAD_MP_INT1_STAT
+#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL
+//SMU_GPIOPAD_MP_INT2_STAT
+#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL
+//SMU_GPIOPAD_MP_INT3_STAT
+#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0
+#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL
+//SMIO_INDEX
+#define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0
+#define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L
+//S0_VID_SMIO_CNTL
+#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0
+#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL
+//S1_VID_SMIO_CNTL
+#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0
+#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL
+//OPEN_DRAIN_SELECT
+#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0
+#define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f
+#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL
+#define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L
+//SMIO_ENABLE
+#define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0
+#define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL
+//SMU_GPIOPAD_S0
+#define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0
+#define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_S1
+#define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0
+#define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_SCL_EN
+#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0
+#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_SDA_EN
+#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0
+#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL
+//SMU_GPIOPAD_SCHMEN
+#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0
+#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL
+
+
+// addressBlock: smuio_smuio_pwr_SmuSmuioDec
+//IP_DISCOVERY_VERSION
+#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0
+#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL
+//SOC_GAP_PWROK
+#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0
+#define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L
+//GFX_GAP_PWROK
+#define GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT 0x0
+#define GFX_GAP_PWROK__gfx_gap_pwrok_MASK 0x00000001L
+//PWROK_REFCLK_GAP_CYCLES
+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0
+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8
+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL
+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L
+//GOLDEN_TSC_INCREMENT_UPPER
+#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0
+#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL
+//GOLDEN_TSC_INCREMENT_LOWER
+#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0
+#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL
+//GOLDEN_TSC_COUNT_UPPER
+#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0
+#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL
+//GOLDEN_TSC_COUNT_LOWER
+#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0
+#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL
+//SOC_GOLDEN_TSC_SHADOW_UPPER
+#define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper__SHIFT 0x0
+#define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper_MASK 0x00FFFFFFL
+//SOC_GOLDEN_TSC_SHADOW_LOWER
+#define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower__SHIFT 0x0
+#define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower_MASK 0xFFFFFFFFL
+//GFX_GOLDEN_TSC_SHADOW_UPPER
+#define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT 0x0
+#define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK 0x00FFFFFFL
+//GFX_GOLDEN_TSC_SHADOW_LOWER
+#define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT 0x0
+#define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK 0xFFFFFFFFL
+//PWR_VIRT_RESET_REQ
+#define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
+#define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f
+#define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL
+#define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L
+//SCRATCH_REGISTER0
+#define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0
+#define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER1
+#define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0
+#define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER2
+#define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0
+#define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER3
+#define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0
+#define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER4
+#define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0
+#define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER5
+#define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0
+#define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER6
+#define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0
+#define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL
+//SCRATCH_REGISTER7
+#define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0
+#define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL
+//PWR_DISP_TIMER_CONTROL
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
+//PWR_DISP_TIMER2_CONTROL
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
+//PWR_DISP_TIMER_GLOBAL_CONTROL
+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa
+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL
+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L
+//PWR_IH_CONTROL
+#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0
+#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5
+#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6
+#define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL
+#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L
+#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h
new file mode 100644
index 000000000000..b089af613990
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h
@@ -0,0 +1,1008 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _vcn_2_0_0_OFFSET_HEADER
+#define _vcn_2_0_0_OFFSET_HEADER
+
+
+
+// addressBlock: uvd0_jpegnpdec
+// base address: 0x1e200
+#define mmUVD_JPEG_CNTL 0x0080
+#define mmUVD_JPEG_CNTL_BASE_IDX 0
+#define mmUVD_JPEG_RB_BASE 0x0081
+#define mmUVD_JPEG_RB_BASE_BASE_IDX 0
+#define mmUVD_JPEG_RB_WPTR 0x0082
+#define mmUVD_JPEG_RB_WPTR_BASE_IDX 0
+#define mmUVD_JPEG_RB_RPTR 0x0083
+#define mmUVD_JPEG_RB_RPTR_BASE_IDX 0
+#define mmUVD_JPEG_RB_SIZE 0x0084
+#define mmUVD_JPEG_RB_SIZE_BASE_IDX 0
+#define mmUVD_JPEG_DEC_SCRATCH0 0x0089
+#define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0
+#define mmUVD_JPEG_INT_EN 0x008a
+#define mmUVD_JPEG_INT_EN_BASE_IDX 0
+#define mmUVD_JPEG_INT_STAT 0x008b
+#define mmUVD_JPEG_INT_STAT_BASE_IDX 0
+#define mmUVD_JPEG_PITCH 0x009f
+#define mmUVD_JPEG_PITCH_BASE_IDX 0
+#define mmUVD_JPEG_UV_PITCH 0x00a0
+#define mmUVD_JPEG_UV_PITCH_BASE_IDX 0
+#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1
+#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0
+#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2
+#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0
+#define mmJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3
+#define mmJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0
+#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4
+#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0
+#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5
+#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0
+#define mmJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6
+#define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0
+#define mmJPEG_DEC_ADDR_MODE 0x00a7
+#define mmJPEG_DEC_ADDR_MODE_BASE_IDX 0
+#define mmUVD_JPEG_GPCOM_CMD 0x00a9
+#define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 0
+#define mmUVD_JPEG_GPCOM_DATA0 0x00aa
+#define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX 0
+#define mmUVD_JPEG_GPCOM_DATA1 0x00ab
+#define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX 0
+#define mmUVD_JPEG_SCRATCH1 0x00ae
+#define mmUVD_JPEG_SCRATCH1_BASE_IDX 0
+#define mmUVD_JPEG_DEC_SOFT_RST 0x00af
+#define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jpeg_enc_dec
+// base address: 0x1e300
+#define mmUVD_JPEG_ENC_INT_EN 0x00c1
+#define mmUVD_JPEG_ENC_INT_EN_BASE_IDX 0
+#define mmUVD_JPEG_ENC_INT_STATUS 0x00c2
+#define mmUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0
+#define mmUVD_JPEG_ENC_ENGINE_CNTL 0x00c5
+#define mmUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0
+#define mmUVD_JPEG_ENC_SCRATCH1 0x00ce
+#define mmUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
+// base address: 0x1e380
+#define mmUVD_JPEG_ENC_STATUS 0x00e5
+#define mmUVD_JPEG_ENC_STATUS_BASE_IDX 0
+#define mmUVD_JPEG_ENC_PITCH 0x00e6
+#define mmUVD_JPEG_ENC_PITCH_BASE_IDX 0
+#define mmUVD_JPEG_ENC_LUMA_BASE 0x00e7
+#define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0
+#define mmUVD_JPEG_ENC_CHROMAU_BASE 0x00e8
+#define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0
+#define mmUVD_JPEG_ENC_CHROMAV_BASE 0x00e9
+#define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0
+#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea
+#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0
+#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb
+#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0
+#define mmJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec
+#define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0
+#define mmJPEG_ENC_ADDR_MODE 0x00ed
+#define mmJPEG_ENC_ADDR_MODE_BASE_IDX 0
+#define mmUVD_JPEG_ENC_GPCOM_CMD 0x00ee
+#define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0
+#define mmUVD_JPEG_ENC_GPCOM_DATA0 0x00ef
+#define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0
+#define mmUVD_JPEG_ENC_GPCOM_DATA1 0x00f0
+#define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0
+#define mmUVD_JPEG_ENC_CGC_CNTL 0x00f5
+#define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0
+#define mmUVD_JPEG_ENC_SCRATCH0 0x00f6
+#define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0
+#define mmUVD_JPEG_ENC_SOFT_RST 0x00f7
+#define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jrbc_dec
+// base address: 0x1e400
+#define mmUVD_JRBC_RB_WPTR 0x0100
+#define mmUVD_JRBC_RB_WPTR_BASE_IDX 0
+#define mmUVD_JRBC_RB_CNTL 0x0101
+#define mmUVD_JRBC_RB_CNTL_BASE_IDX 0
+#define mmUVD_JRBC_IB_SIZE 0x0102
+#define mmUVD_JRBC_IB_SIZE_BASE_IDX 0
+#define mmUVD_JRBC_URGENT_CNTL 0x0103
+#define mmUVD_JRBC_URGENT_CNTL_BASE_IDX 0
+#define mmUVD_JRBC_RB_REF_DATA 0x0104
+#define mmUVD_JRBC_RB_REF_DATA_BASE_IDX 0
+#define mmUVD_JRBC_RB_COND_RD_TIMER 0x0105
+#define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0
+#define mmUVD_JRBC_SOFT_RESET 0x0108
+#define mmUVD_JRBC_SOFT_RESET_BASE_IDX 0
+#define mmUVD_JRBC_STATUS 0x0109
+#define mmUVD_JRBC_STATUS_BASE_IDX 0
+#define mmUVD_JRBC_RB_RPTR 0x010a
+#define mmUVD_JRBC_RB_RPTR_BASE_IDX 0
+#define mmUVD_JRBC_RB_BUF_STATUS 0x010b
+#define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0
+#define mmUVD_JRBC_IB_BUF_STATUS 0x010c
+#define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0
+#define mmUVD_JRBC_IB_SIZE_UPDATE 0x010d
+#define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0
+#define mmUVD_JRBC_IB_COND_RD_TIMER 0x010e
+#define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0
+#define mmUVD_JRBC_IB_REF_DATA 0x010f
+#define mmUVD_JRBC_IB_REF_DATA_BASE_IDX 0
+#define mmUVD_JPEG_PREEMPT_CMD 0x0110
+#define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX 0
+#define mmUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111
+#define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0
+#define mmUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112
+#define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0
+#define mmUVD_JRBC_RB_SIZE 0x0113
+#define mmUVD_JRBC_RB_SIZE_BASE_IDX 0
+#define mmUVD_JRBC_SCRATCH0 0x0114
+#define mmUVD_JRBC_SCRATCH0_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jrbc_enc_dec
+// base address: 0x1e480
+#define mmUVD_JRBC_ENC_RB_WPTR 0x0120
+#define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0
+#define mmUVD_JRBC_ENC_RB_CNTL 0x0121
+#define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0
+#define mmUVD_JRBC_ENC_IB_SIZE 0x0122
+#define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0
+#define mmUVD_JRBC_ENC_URGENT_CNTL 0x0123
+#define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0
+#define mmUVD_JRBC_ENC_RB_REF_DATA 0x0124
+#define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0
+#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125
+#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0
+#define mmUVD_JRBC_ENC_SOFT_RESET 0x0128
+#define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0
+#define mmUVD_JRBC_ENC_STATUS 0x0129
+#define mmUVD_JRBC_ENC_STATUS_BASE_IDX 0
+#define mmUVD_JRBC_ENC_RB_RPTR 0x012a
+#define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0
+#define mmUVD_JRBC_ENC_RB_BUF_STATUS 0x012b
+#define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0
+#define mmUVD_JRBC_ENC_IB_BUF_STATUS 0x012c
+#define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0
+#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d
+#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0
+#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e
+#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0
+#define mmUVD_JRBC_ENC_IB_REF_DATA 0x012f
+#define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0
+#define mmUVD_JPEG_ENC_PREEMPT_CMD 0x0130
+#define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0
+#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131
+#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0
+#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132
+#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0
+#define mmUVD_JRBC_ENC_RB_SIZE 0x0133
+#define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0
+#define mmUVD_JRBC_ENC_SCRATCH0 0x0134
+#define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jmi_dec
+// base address: 0x1e500
+#define mmUVD_JMI_CTRL 0x0145
+#define mmUVD_JMI_CTRL_BASE_IDX 0
+#define mmUVD_LMI_JRBC_CTRL 0x0146
+#define mmUVD_LMI_JRBC_CTRL_BASE_IDX 0
+#define mmUVD_LMI_JPEG_CTRL 0x0147
+#define mmUVD_LMI_JPEG_CTRL_BASE_IDX 0
+#define mmUVD_JMI_EJRBC_CTRL 0x0148
+#define mmUVD_JMI_EJRBC_CTRL_BASE_IDX 0
+#define mmUVD_LMI_EJPEG_CTRL 0x0149
+#define mmUVD_LMI_EJPEG_CTRL_BASE_IDX 0
+#define mmUVD_LMI_JRBC_IB_VMID 0x014f
+#define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 0
+#define mmUVD_LMI_JRBC_RB_VMID 0x0150
+#define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX 0
+#define mmUVD_LMI_JPEG_VMID 0x0151
+#define mmUVD_LMI_JPEG_VMID_BASE_IDX 0
+#define mmUVD_JMI_ENC_JRBC_IB_VMID 0x0152
+#define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0
+#define mmUVD_JMI_ENC_JRBC_RB_VMID 0x0153
+#define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0
+#define mmUVD_JMI_ENC_JPEG_VMID 0x0154
+#define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0
+#define mmUVD_JMI_PERFMON_CTRL 0x015c
+#define mmUVD_JMI_PERFMON_CTRL_BASE_IDX 0
+#define mmUVD_JMI_PERFMON_COUNT_LO 0x015d
+#define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0
+#define mmUVD_JMI_PERFMON_COUNT_HI 0x015e
+#define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161
+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163
+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164
+#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165
+#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166
+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167
+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168
+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169
+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e
+#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f
+#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170
+#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171
+#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a
+#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b
+#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c
+#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d
+#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e
+#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f
+#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180
+#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181
+#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182
+#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183
+#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184
+#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185
+#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186
+#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187
+#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JPEG_PREEMPT_VMID 0x0188
+#define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0
+#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189
+#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0
+#define mmUVD_LMI_JPEG2_VMID 0x018a
+#define mmUVD_LMI_JPEG2_VMID_BASE_IDX 0
+#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b
+#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c
+#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d
+#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e
+#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_LMI_JPEG_CTRL2 0x018f
+#define mmUVD_LMI_JPEG_CTRL2_BASE_IDX 0
+#define mmUVD_JMI_DEC_SWAP_CNTL 0x0190
+#define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0
+#define mmUVD_JMI_ENC_SWAP_CNTL 0x0191
+#define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0
+#define mmUVD_JMI_CNTL 0x0192
+#define mmUVD_JMI_CNTL_BASE_IDX 0
+#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a
+#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0
+#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b
+#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0
+#define mmUVD_JMI_DEC_SWAP_CNTL2 0x019c
+#define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jpeg_common_dec
+// base address: 0x1e700
+#define mmJPEG_SOFT_RESET_STATUS 0x01c0
+#define mmJPEG_SOFT_RESET_STATUS_BASE_IDX 0
+#define mmJPEG_SYS_INT_EN 0x01c1
+#define mmJPEG_SYS_INT_EN_BASE_IDX 0
+#define mmJPEG_SYS_INT_STATUS 0x01c2
+#define mmJPEG_SYS_INT_STATUS_BASE_IDX 0
+#define mmJPEG_SYS_INT_ACK 0x01c3
+#define mmJPEG_SYS_INT_ACK_BASE_IDX 0
+#define mmJPEG_MASTINT_EN 0x01c8
+#define mmJPEG_MASTINT_EN_BASE_IDX 0
+#define mmJPEG_IH_CTRL 0x01c9
+#define mmJPEG_IH_CTRL_BASE_IDX 0
+#define mmJRBBM_ARB_CTRL 0x01cb
+#define mmJRBBM_ARB_CTRL_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_jpeg_common_sclk_dec
+// base address: 0x1e780
+#define mmJPEG_CGC_GATE 0x01e0
+#define mmJPEG_CGC_GATE_BASE_IDX 0
+#define mmJPEG_CGC_CTRL 0x01e1
+#define mmJPEG_CGC_CTRL_BASE_IDX 0
+#define mmJPEG_CGC_STATUS 0x01e2
+#define mmJPEG_CGC_STATUS_BASE_IDX 0
+#define mmJPEG_COMN_CGC_MEM_CTRL 0x01e3
+#define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0
+#define mmJPEG_DEC_CGC_MEM_CTRL 0x01e4
+#define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0
+#define mmJPEG2_DEC_CGC_MEM_CTRL 0x01e5
+#define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0
+#define mmJPEG_ENC_CGC_MEM_CTRL 0x01e6
+#define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0
+#define mmJPEG_SOFT_RESET2 0x01e7
+#define mmJPEG_SOFT_RESET2_BASE_IDX 0
+#define mmJPEG_PERF_BANK_CONF 0x01e8
+#define mmJPEG_PERF_BANK_CONF_BASE_IDX 0
+#define mmJPEG_PERF_BANK_EVENT_SEL 0x01e9
+#define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0
+#define mmJPEG_PERF_BANK_COUNT0 0x01ea
+#define mmJPEG_PERF_BANK_COUNT0_BASE_IDX 0
+#define mmJPEG_PERF_BANK_COUNT1 0x01eb
+#define mmJPEG_PERF_BANK_COUNT1_BASE_IDX 0
+#define mmJPEG_PERF_BANK_COUNT2 0x01ec
+#define mmJPEG_PERF_BANK_COUNT2_BASE_IDX 0
+#define mmJPEG_PERF_BANK_COUNT3 0x01ed
+#define mmJPEG_PERF_BANK_COUNT3_BASE_IDX 0
+
+
+// addressBlock: uvd0_uvd_pg_dec
+// base address: 0x1f800
+#define mmUVD_PGFSM_CONFIG 0x0000
+#define mmUVD_PGFSM_CONFIG_BASE_IDX 1
+#define mmUVD_PGFSM_STATUS 0x0001
+#define mmUVD_PGFSM_STATUS_BASE_IDX 1
+#define mmUVD_POWER_STATUS 0x0004
+#define mmUVD_POWER_STATUS_BASE_IDX 1
+#define mmUVD_PG_IND_INDEX 0x0005
+#define mmUVD_PG_IND_INDEX_BASE_IDX 1
+#define mmUVD_PG_IND_DATA 0x0006
+#define mmUVD_PG_IND_DATA_BASE_IDX 1
+#define mmCC_UVD_HARVESTING 0x0007
+#define mmCC_UVD_HARVESTING_BASE_IDX 1
+#define mmUVD_JPEG_POWER_STATUS 0x000a
+#define mmUVD_JPEG_POWER_STATUS_BASE_IDX 1
+#define mmUVD_DPG_LMA_CTL 0x0011
+#define mmUVD_DPG_LMA_CTL_BASE_IDX 1
+#define mmUVD_DPG_LMA_DATA 0x0012
+#define mmUVD_DPG_LMA_DATA_BASE_IDX 1
+#define mmUVD_DPG_LMA_MASK 0x0013
+#define mmUVD_DPG_LMA_MASK_BASE_IDX 1
+#define mmUVD_DPG_PAUSE 0x0014
+#define mmUVD_DPG_PAUSE_BASE_IDX 1
+#define mmUVD_SCRATCH1 0x0015
+#define mmUVD_SCRATCH1_BASE_IDX 1
+#define mmUVD_SCRATCH2 0x0016
+#define mmUVD_SCRATCH2_BASE_IDX 1
+#define mmUVD_SCRATCH3 0x0017
+#define mmUVD_SCRATCH3_BASE_IDX 1
+#define mmUVD_SCRATCH4 0x0018
+#define mmUVD_SCRATCH4_BASE_IDX 1
+#define mmUVD_SCRATCH5 0x0019
+#define mmUVD_SCRATCH5_BASE_IDX 1
+#define mmUVD_SCRATCH6 0x001a
+#define mmUVD_SCRATCH6_BASE_IDX 1
+#define mmUVD_SCRATCH7 0x001b
+#define mmUVD_SCRATCH7_BASE_IDX 1
+#define mmUVD_SCRATCH8 0x001c
+#define mmUVD_SCRATCH8_BASE_IDX 1
+#define mmUVD_SCRATCH9 0x001d
+#define mmUVD_SCRATCH9_BASE_IDX 1
+#define mmUVD_SCRATCH10 0x001e
+#define mmUVD_SCRATCH10_BASE_IDX 1
+#define mmUVD_SCRATCH11 0x001f
+#define mmUVD_SCRATCH11_BASE_IDX 1
+#define mmUVD_SCRATCH12 0x0020
+#define mmUVD_SCRATCH12_BASE_IDX 1
+#define mmUVD_SCRATCH13 0x0021
+#define mmUVD_SCRATCH13_BASE_IDX 1
+#define mmUVD_SCRATCH14 0x0022
+#define mmUVD_SCRATCH14_BASE_IDX 1
+#define mmUVD_FREE_COUNTER_REG 0x0024
+#define mmUVD_FREE_COUNTER_REG_BASE_IDX 1
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026
+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x0027
+#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1
+#define mmUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028
+#define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1
+#define mmUVD_PF_STATUS 0x0039
+#define mmUVD_PF_STATUS_BASE_IDX 1
+#define mmUVD_DPG_CLK_EN_VCPU_REPORT 0x003c
+#define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1
+#define mmUVD_GFX8_ADDR_CONFIG 0x0049
+#define mmUVD_GFX8_ADDR_CONFIG_BASE_IDX 1
+#define mmUVD_GFX10_ADDR_CONFIG 0x004a
+#define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX 1
+#define mmUVD_GPCNT2_CNTL 0x004b
+#define mmUVD_GPCNT2_CNTL_BASE_IDX 1
+#define mmUVD_GPCNT2_TARGET_LOWER 0x004c
+#define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1
+#define mmUVD_GPCNT2_STATUS_LOWER 0x004d
+#define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1
+#define mmUVD_GPCNT2_TARGET_UPPER 0x004e
+#define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1
+#define mmUVD_GPCNT2_STATUS_UPPER 0x004f
+#define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1
+#define mmUVD_GPCNT3_CNTL 0x0050
+#define mmUVD_GPCNT3_CNTL_BASE_IDX 1
+#define mmUVD_GPCNT3_TARGET_LOWER 0x0051
+#define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1
+#define mmUVD_GPCNT3_STATUS_LOWER 0x0052
+#define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1
+#define mmUVD_GPCNT3_TARGET_UPPER 0x0053
+#define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1
+#define mmUVD_GPCNT3_STATUS_UPPER 0x0054
+#define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1
+#define mmUVD_TSC_LOWER 0x0057
+#define mmUVD_TSC_LOWER_BASE_IDX 1
+#define mmUVD_TSC_UPPER 0x0058
+#define mmUVD_TSC_UPPER_BASE_IDX 1
+
+
+// addressBlock: uvd0_uvddec
+// base address: 0x1ff00
+#define mmUVD_SEMA_CNTL 0x01c0
+#define mmUVD_SEMA_CNTL_BASE_IDX 1
+#define mmUVD_RB_RPTR3 0x01db
+#define mmUVD_RB_RPTR3_BASE_IDX 1
+#define mmUVD_RB_WPTR3 0x01dc
+#define mmUVD_RB_WPTR3_BASE_IDX 1
+#define mmUVD_RB_BASE_LO3 0x01dd
+#define mmUVD_RB_BASE_LO3_BASE_IDX 1
+#define mmUVD_RB_BASE_HI3 0x01de
+#define mmUVD_RB_BASE_HI3_BASE_IDX 1
+#define mmUVD_RB_SIZE3 0x01df
+#define mmUVD_RB_SIZE3_BASE_IDX 1
+#define mmUVD_RB_ARB_CTRL 0x01e0
+#define mmUVD_RB_ARB_CTRL_BASE_IDX 1
+#define mmUVD_LMI_LAT_CTRL 0x01e2
+#define mmUVD_LMI_LAT_CTRL_BASE_IDX 1
+#define mmUVD_LMI_LAT_CNTR 0x01e3
+#define mmUVD_LMI_LAT_CNTR_BASE_IDX 1
+#define mmUVD_LMI_AVG_LAT_CNTR 0x01e4
+#define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1
+#define mmUVD_SOFT_RESET2 0x01e6
+#define mmUVD_SOFT_RESET2_BASE_IDX 1
+#define mmUVD_LMI_SPH 0x01e7
+#define mmUVD_LMI_SPH_BASE_IDX 1
+#define mmUVD_CTX_INDEX 0x01e8
+#define mmUVD_CTX_INDEX_BASE_IDX 1
+#define mmUVD_CTX_DATA 0x01e9
+#define mmUVD_CTX_DATA_BASE_IDX 1
+#define mmUVD_CGC_GATE 0x01ea
+#define mmUVD_CGC_GATE_BASE_IDX 1
+#define mmUVD_CGC_STATUS 0x01eb
+#define mmUVD_CGC_STATUS_BASE_IDX 1
+#define mmUVD_CGC_CTRL 0x01ec
+#define mmUVD_CGC_CTRL_BASE_IDX 1
+#define mmUVD_CGC_UDEC_STATUS 0x01ed
+#define mmUVD_CGC_UDEC_STATUS_BASE_IDX 1
+#define mmUVD_CXW_WR_INT_ID 0x01ee
+#define mmUVD_CXW_WR_INT_ID_BASE_IDX 1
+#define mmUVD_CXW_WR_INT_CTX_ID 0x01ef
+#define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1
+#define mmUVD_VCPU_INT_ROUTE 0x01f3
+#define mmUVD_VCPU_INT_ROUTE_BASE_IDX 1
+#define mmUVD_GP_SCRATCH0 0x01f4
+#define mmUVD_GP_SCRATCH0_BASE_IDX 1
+#define mmUVD_GP_SCRATCH1 0x01f5
+#define mmUVD_GP_SCRATCH1_BASE_IDX 1
+#define mmUVD_GP_SCRATCH2 0x01f6
+#define mmUVD_GP_SCRATCH2_BASE_IDX 1
+#define mmUVD_GP_SCRATCH3 0x01f7
+#define mmUVD_GP_SCRATCH3_BASE_IDX 1
+#define mmUVD_GP_SCRATCH4 0x01f8
+#define mmUVD_GP_SCRATCH4_BASE_IDX 1
+#define mmUVD_GP_SCRATCH5 0x01f9
+#define mmUVD_GP_SCRATCH5_BASE_IDX 1
+#define mmUVD_GP_SCRATCH6 0x01fa
+#define mmUVD_GP_SCRATCH6_BASE_IDX 1
+#define mmUVD_GP_SCRATCH7 0x01fb
+#define mmUVD_GP_SCRATCH7_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE_VMID 0x01fc
+#define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1
+#define mmUVD_LMI_CTRL2 0x01fd
+#define mmUVD_LMI_CTRL2_BASE_IDX 1
+#define mmUVD_MASTINT_EN 0x0200
+#define mmUVD_MASTINT_EN_BASE_IDX 1
+#define mmUVD_SYS_INT_EN 0x0201
+#define mmUVD_SYS_INT_EN_BASE_IDX 1
+#define mmUVD_SYS_INT_STATUS 0x0202
+#define mmUVD_SYS_INT_STATUS_BASE_IDX 1
+#define mmUVD_SYS_INT_ACK 0x0203
+#define mmUVD_SYS_INT_ACK_BASE_IDX 1
+#define mmUVD_VCPU_INT_EN 0x0204
+#define mmUVD_VCPU_INT_EN_BASE_IDX 1
+#define mmUVD_VCPU_INT_ACK 0x0206
+#define mmUVD_VCPU_INT_ACK_BASE_IDX 1
+#define mmUVD_TOP_CTRL 0x0207
+#define mmUVD_TOP_CTRL_BASE_IDX 1
+#define mmUVD_ENC_VCPU_INT_EN 0x021f
+#define mmUVD_ENC_VCPU_INT_EN_BASE_IDX 1
+#define mmUVD_ENC_VCPU_INT_ACK 0x0221
+#define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x0222
+#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1
+#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI 0x0223
+#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1
+#define mmUVD_LMI_URGENT_CTRL 0x0224
+#define mmUVD_LMI_URGENT_CTRL_BASE_IDX 1
+#define mmUVD_LMI_CTRL 0x0226
+#define mmUVD_LMI_CTRL_BASE_IDX 1
+#define mmUVD_LMI_STATUS 0x0227
+#define mmUVD_LMI_STATUS_BASE_IDX 1
+#define mmUVD_LMI_VM_CTRL 0x0228
+#define mmUVD_LMI_VM_CTRL_BASE_IDX 1
+#define mmUVD_LMI_PERFMON_CTRL 0x022a
+#define mmUVD_LMI_PERFMON_CTRL_BASE_IDX 1
+#define mmUVD_LMI_PERFMON_COUNT_LO 0x022b
+#define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1
+#define mmUVD_LMI_PERFMON_COUNT_HI 0x022c
+#define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1
+#define mmUVD_LMI_SWAP_CNTL 0x022d
+#define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1
+#define mmUVD_UDEC_ADR 0x022e
+#define mmUVD_UDEC_ADR_BASE_IDX 1
+#define mmUVD_MP_SWAP_CNTL 0x022f
+#define mmUVD_MP_SWAP_CNTL_BASE_IDX 1
+#define mmUVD_MPC_LUMA_SRCH 0x0231
+#define mmUVD_MPC_LUMA_SRCH_BASE_IDX 1
+#define mmUVD_MPC_LUMA_HIT 0x0232
+#define mmUVD_MPC_LUMA_HIT_BASE_IDX 1
+#define mmUVD_MPC_LUMA_HITPEND 0x0233
+#define mmUVD_MPC_LUMA_HITPEND_BASE_IDX 1
+#define mmUVD_MPC_CHROMA_SRCH 0x0234
+#define mmUVD_MPC_CHROMA_SRCH_BASE_IDX 1
+#define mmUVD_MPC_CHROMA_HIT 0x0235
+#define mmUVD_MPC_CHROMA_HIT_BASE_IDX 1
+#define mmUVD_MPC_CHROMA_HITPEND 0x0236
+#define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX 1
+#define mmUVD_MPC_CNTL 0x0237
+#define mmUVD_MPC_CNTL_BASE_IDX 1
+#define mmUVD_MPC_PITCH 0x0238
+#define mmUVD_MPC_PITCH_BASE_IDX 1
+#define mmUVD_MPC_SET_MUXA0 0x0239
+#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1
+#define mmUVD_MPC_SET_MUXA1 0x023a
+#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1
+#define mmUVD_MPC_SET_MUXB0 0x023b
+#define mmUVD_MPC_SET_MUXB0_BASE_IDX 1
+#define mmUVD_MPC_SET_MUXB1 0x023c
+#define mmUVD_MPC_SET_MUXB1_BASE_IDX 1
+#define mmUVD_MPC_SET_MUX 0x023d
+#define mmUVD_MPC_SET_MUX_BASE_IDX 1
+#define mmUVD_MPC_SET_ALU 0x023e
+#define mmUVD_MPC_SET_ALU_BASE_IDX 1
+#define mmUVD_GPCOM_SYS_CMD 0x023f
+#define mmUVD_GPCOM_SYS_CMD_BASE_IDX 1
+#define mmUVD_GPCOM_SYS_DATA0 0x0240
+#define mmUVD_GPCOM_SYS_DATA0_BASE_IDX 1
+#define mmUVD_GPCOM_SYS_DATA1 0x0241
+#define mmUVD_GPCOM_SYS_DATA1_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET0 0x0242
+#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE0 0x0243
+#define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET1 0x0244
+#define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE1 0x0245
+#define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET2 0x0246
+#define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE2 0x0247
+#define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET3 0x0248
+#define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE3 0x0249
+#define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET4 0x024a
+#define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE4 0x024b
+#define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET5 0x024c
+#define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE5 0x024d
+#define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET6 0x024e
+#define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE6 0x024f
+#define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET7 0x0250
+#define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE7 0x0251
+#define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_OFFSET8 0x0252
+#define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1
+#define mmUVD_VCPU_CACHE_SIZE8 0x0253
+#define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX 1
+#define mmUVD_VCPU_NONCACHE_OFFSET0 0x0254
+#define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1
+#define mmUVD_VCPU_NONCACHE_SIZE0 0x0255
+#define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1
+#define mmUVD_VCPU_NONCACHE_OFFSET1 0x0256
+#define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1
+#define mmUVD_VCPU_NONCACHE_SIZE1 0x0257
+#define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1
+#define mmUVD_VCPU_CNTL 0x0258
+#define mmUVD_VCPU_CNTL_BASE_IDX 1
+#define mmUVD_VCPU_PRID 0x0259
+#define mmUVD_VCPU_PRID_BASE_IDX 1
+#define mmUVD_VCPU_TRCE 0x025a
+#define mmUVD_VCPU_TRCE_BASE_IDX 1
+#define mmUVD_VCPU_TRCE_RD 0x025b
+#define mmUVD_VCPU_TRCE_RD_BASE_IDX 1
+#define mmUVD_MPC_PERF0 0x025c
+#define mmUVD_MPC_PERF0_BASE_IDX 1
+#define mmUVD_MPC_PERF1 0x025d
+#define mmUVD_MPC_PERF1_BASE_IDX 1
+#define mmUVD_CXW_WR 0x025f
+#define mmUVD_CXW_WR_BASE_IDX 1
+#define mmUVD_SOFT_RESET 0x0260
+#define mmUVD_SOFT_RESET_BASE_IDX 1
+#define mmUVD_LMI_RBC_IB_VMID 0x0261
+#define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1
+#define mmUVD_RBC_IB_SIZE 0x0262
+#define mmUVD_RBC_IB_SIZE_BASE_IDX 1
+#define mmUVD_LMI_RBC_RB_VMID 0x0263
+#define mmUVD_LMI_RBC_RB_VMID_BASE_IDX 1
+#define mmUVD_RBC_RB_RPTR 0x0264
+#define mmUVD_RBC_RB_RPTR_BASE_IDX 1
+#define mmUVD_RBC_RB_WPTR 0x0265
+#define mmUVD_RBC_RB_WPTR_BASE_IDX 1
+#define mmUVD_RBC_RB_WPTR_CNTL 0x0266
+#define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1
+#define mmUVD_RBC_READ_REQ_URGENT_CNTL 0x0267
+#define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1
+#define mmUVD_RBC_WPTR_STATUS 0x0268
+#define mmUVD_RBC_WPTR_STATUS_BASE_IDX 1
+#define mmUVD_RBC_RB_CNTL 0x0269
+#define mmUVD_RBC_RB_CNTL_BASE_IDX 1
+#define mmUVD_RBC_RB_RPTR_ADDR 0x026a
+#define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1
+#define mmUVD_JOB_START 0x026d
+#define mmUVD_JOB_START_BASE_IDX 1
+#define mmUVD_JOB_DONE 0x026e
+#define mmUVD_JOB_DONE_BASE_IDX 1
+#define mmUVD_STATUS 0x026f
+#define mmUVD_STATUS_BASE_IDX 1
+#define mmUVD_SEMA_TIMEOUT_STATUS 0x0270
+#define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1
+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x0271
+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1
+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x0272
+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1
+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x0273
+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1
+#define mmUVD_CXW_EN 0x0274
+#define mmUVD_CXW_EN_BASE_IDX 1
+#define mmUVD_CXW_SE 0x0275
+#define mmUVD_CXW_SE_BASE_IDX 1
+#define mmUVD_CXW_FINISHED 0x0276
+#define mmUVD_CXW_FINISHED_BASE_IDX 1
+#define mmUVD_CXW_SHIFT_FINISHED 0x0277
+#define mmUVD_CXW_SHIFT_FINISHED_BASE_IDX 1
+#define mmUVD_CXW_START 0x0278
+#define mmUVD_CXW_START_BASE_IDX 1
+#define mmUVD_CXW_BLOCK_STATUS 0x0279
+#define mmUVD_CXW_BLOCK_STATUS_BASE_IDX 1
+#define mmUVD_STOP_CONTEXT 0x027a
+#define mmUVD_STOP_CONTEXT_BASE_IDX 1
+#define mmUVD_CXW_SAVE_AREA_ADDR 0x027b
+#define mmUVD_CXW_SAVE_AREA_ADDR_BASE_IDX 1
+#define mmUVD_CBUF_ID 0x027c
+#define mmUVD_CBUF_ID_BASE_IDX 1
+#define mmUVD_CONTEXT_ID 0x027d
+#define mmUVD_CONTEXT_ID_BASE_IDX 1
+#define mmUVD_CXW_SAVE_AREA_SIZE 0x027e
+#define mmUVD_CXW_SAVE_AREA_SIZE_BASE_IDX 1
+#define mmUVD_CONTEXT_ID2 0x027f
+#define mmUVD_CONTEXT_ID2_BASE_IDX 1
+#define mmUVD_CXW_CNTL 0x0280
+#define mmUVD_CXW_CNTL_BASE_IDX 1
+#define mmUVD_CXW_EVENT 0x0281
+#define mmUVD_CXW_EVENT_BASE_IDX 1
+#define mmUVD_CXW_SCAN_AREA_OFFSET 0x0282
+#define mmUVD_CXW_SCAN_AREA_OFFSET_BASE_IDX 1
+#define mmUVD_CXW_SHIFT_CNTL 0x0283
+#define mmUVD_CXW_SHIFT_CNTL_BASE_IDX 1
+#define mmUVD_RBC_CAM_EN 0x0286
+#define mmUVD_RBC_CAM_EN_BASE_IDX 1
+#define mmUVD_RBC_CAM_INDEX 0x0287
+#define mmUVD_RBC_CAM_INDEX_BASE_IDX 1
+#define mmUVD_RBC_CAM_DATA 0x0288
+#define mmUVD_RBC_CAM_DATA_BASE_IDX 1
+#define mmUVD_RBC_VCPU_ACCESS 0x0289
+#define mmUVD_RBC_VCPU_ACCESS_BASE_IDX 1
+#define mmUVD_CXW_INT_ID 0x0293
+#define mmUVD_CXW_INT_ID_BASE_IDX 1
+#define mmUVD_LMI_CRC0 0x0294
+#define mmUVD_LMI_CRC0_BASE_IDX 1
+#define mmUVD_LMI_CRC1 0x0295
+#define mmUVD_LMI_CRC1_BASE_IDX 1
+#define mmUVD_LMI_CRC2 0x0296
+#define mmUVD_LMI_CRC2_BASE_IDX 1
+#define mmUVD_LMI_CRC3 0x0297
+#define mmUVD_LMI_CRC3_BASE_IDX 1
+#define mmUVD_RBC_WPTR_POLL_CNTL 0x0298
+#define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1
+#define mmUVD_RBC_WPTR_POLL_ADDR 0x0299
+#define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1
+#define mmUVD_RB_BASE_LO4 0x029f
+#define mmUVD_RB_BASE_LO4_BASE_IDX 1
+#define mmUVD_RB_BASE_HI4 0x02a0
+#define mmUVD_RB_BASE_HI4_BASE_IDX 1
+#define mmUVD_RB_SIZE4 0x02a1
+#define mmUVD_RB_SIZE4_BASE_IDX 1
+#define mmUVD_RB_RPTR4 0x02a2
+#define mmUVD_RB_RPTR4_BASE_IDX 1
+#define mmUVD_LMI_MC_CREDITS 0x02a3
+#define mmUVD_LMI_MC_CREDITS_BASE_IDX 1
+#define mmUVD_RBC_BUF_STATUS 0x02b0
+#define mmUVD_RBC_BUF_STATUS_BASE_IDX 1
+#define mmUVD_RBC_IB_SIZE_UPDATE 0x02b1
+#define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1
+#define mmUVD_RBC_BDM_PRE 0x02b2
+#define mmUVD_RBC_BDM_PRE_BASE_IDX 1
+#define mmCG_TIMESTAMP_LOW 0x02b5
+#define mmCG_TIMESTAMP_LOW_BASE_IDX 1
+#define mmCG_TIMESTAMP_HIGH 0x02b6
+#define mmCG_TIMESTAMP_HIGH_BASE_IDX 1
+#define mmUVD_UMC_UVD_CTL_CMD 0x02b7
+#define mmUVD_UMC_UVD_CTL_CMD_BASE_IDX 1
+#define mmUVD_UMC_UVD_BLOCK_REQ 0x02b8
+#define mmUVD_UMC_UVD_BLOCK_REQ_BASE_IDX 1
+#define mmUVD_RBC_CXW_RELEASE 0x02b9
+#define mmUVD_RBC_CXW_RELEASE_BASE_IDX 1
+#define mmUVD_YBASE 0x02ba
+#define mmUVD_YBASE_BASE_IDX 1
+#define mmUVD_UVBASE 0x02bb
+#define mmUVD_UVBASE_BASE_IDX 1
+#define mmUVD_PITCH 0x02bc
+#define mmUVD_PITCH_BASE_IDX 1
+#define mmUVD_WIDTH 0x02bd
+#define mmUVD_WIDTH_BASE_IDX 1
+#define mmUVD_HEIGHT 0x02be
+#define mmUVD_HEIGHT_BASE_IDX 1
+#define mmUVD_PICCOUNT 0x02bf
+#define mmUVD_PICCOUNT_BASE_IDX 1
+
+
+// addressBlock: uvd0_uvdnpdec
+// base address: 0x20700
+#define mmUVD_SEMA_ADDR_LOW 0x0580
+#define mmUVD_SEMA_ADDR_LOW_BASE_IDX 1
+#define mmUVD_SEMA_ADDR_HIGH 0x0581
+#define mmUVD_SEMA_ADDR_HIGH_BASE_IDX 1
+#define mmUVD_SEMA_CMD 0x0582
+#define mmUVD_SEMA_CMD_BASE_IDX 1
+#define mmUVD_GPCOM_VCPU_CMD 0x0583
+#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1
+#define mmUVD_GPCOM_VCPU_DATA0 0x0584
+#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1
+#define mmUVD_GPCOM_VCPU_DATA1 0x0585
+#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1
+#define mmUVD_ENGINE_CNTL 0x0586
+#define mmUVD_ENGINE_CNTL_BASE_IDX 1
+#define mmUVD_SUVD_CGC_GATE 0x05a4
+#define mmUVD_SUVD_CGC_GATE_BASE_IDX 1
+#define mmUVD_SUVD_CGC_STATUS 0x05a5
+#define mmUVD_SUVD_CGC_STATUS_BASE_IDX 1
+#define mmUVD_SUVD_CGC_CTRL 0x05a6
+#define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x05ac
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x05ad
+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x05ae
+#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x05af
+#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x05b0
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x05b1
+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x05b2
+#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x05b3
+#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x05b4
+#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x05b5
+#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x05b6
+#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x05b7
+#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x05b8
+#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x05b9
+#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x05ba
+#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x05bb
+#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_SCRATCH_NP 0x05bc
+#define mmUVD_SCRATCH_NP_BASE_IDX 1
+#define mmUVD_NO_OP 0x05bf
+#define mmUVD_NO_OP_BASE_IDX 1
+#define mmMDM_DMA_CMD 0x05c0
+#define mmMDM_DMA_CMD_BASE_IDX 1
+#define mmMDM_DMA_STATUS 0x05c1
+#define mmMDM_DMA_STATUS_BASE_IDX 1
+#define mmMDM_DMA_CTL 0x05c2
+#define mmMDM_DMA_CTL_BASE_IDX 1
+#define mmMDM_ENC_PIPE_BUSY 0x05c3
+#define mmMDM_ENC_PIPE_BUSY_BASE_IDX 1
+#define mmMDM_WIG_PIPE_BUSY 0x05c5
+#define mmMDM_WIG_PIPE_BUSY_BASE_IDX 1
+#define mmUVD_VERSION 0x05c9
+#define mmUVD_VERSION_BASE_IDX 1
+#define mmUVD_GP_SCRATCH8 0x05ca
+#define mmUVD_GP_SCRATCH8_BASE_IDX 1
+#define mmUVD_GP_SCRATCH9 0x05cb
+#define mmUVD_GP_SCRATCH9_BASE_IDX 1
+#define mmUVD_GP_SCRATCH10 0x05cc
+#define mmUVD_GP_SCRATCH10_BASE_IDX 1
+#define mmUVD_GP_SCRATCH11 0x05cd
+#define mmUVD_GP_SCRATCH11_BASE_IDX 1
+#define mmUVD_GP_SCRATCH12 0x05ce
+#define mmUVD_GP_SCRATCH12_BASE_IDX 1
+#define mmUVD_GP_SCRATCH13 0x05cf
+#define mmUVD_GP_SCRATCH13_BASE_IDX 1
+#define mmUVD_GP_SCRATCH14 0x05d0
+#define mmUVD_GP_SCRATCH14_BASE_IDX 1
+#define mmUVD_GP_SCRATCH15 0x05d1
+#define mmUVD_GP_SCRATCH15_BASE_IDX 1
+#define mmUVD_GP_SCRATCH16 0x05d2
+#define mmUVD_GP_SCRATCH16_BASE_IDX 1
+#define mmUVD_GP_SCRATCH17 0x05d3
+#define mmUVD_GP_SCRATCH17_BASE_IDX 1
+#define mmUVD_GP_SCRATCH18 0x05d4
+#define mmUVD_GP_SCRATCH18_BASE_IDX 1
+#define mmUVD_GP_SCRATCH19 0x05d5
+#define mmUVD_GP_SCRATCH19_BASE_IDX 1
+#define mmUVD_GP_SCRATCH20 0x05d6
+#define mmUVD_GP_SCRATCH20_BASE_IDX 1
+#define mmUVD_GP_SCRATCH21 0x05d7
+#define mmUVD_GP_SCRATCH21_BASE_IDX 1
+#define mmUVD_GP_SCRATCH22 0x05d8
+#define mmUVD_GP_SCRATCH22_BASE_IDX 1
+#define mmUVD_GP_SCRATCH23 0x05d9
+#define mmUVD_GP_SCRATCH23_BASE_IDX 1
+#define mmUVD_ENC_REG_INDEX 0x05da
+#define mmUVD_ENC_REG_INDEX_BASE_IDX 1
+#define mmUVD_ENC_REG_DATA 0x05db
+#define mmUVD_ENC_REG_DATA_BASE_IDX 1
+#define mmUVD_OUT_RB_BASE_LO 0x05dc
+#define mmUVD_OUT_RB_BASE_LO_BASE_IDX 1
+#define mmUVD_OUT_RB_BASE_HI 0x05dd
+#define mmUVD_OUT_RB_BASE_HI_BASE_IDX 1
+#define mmUVD_OUT_RB_SIZE 0x05de
+#define mmUVD_OUT_RB_SIZE_BASE_IDX 1
+#define mmUVD_OUT_RB_RPTR 0x05df
+#define mmUVD_OUT_RB_RPTR_BASE_IDX 1
+#define mmUVD_OUT_RB_WPTR 0x05e0
+#define mmUVD_OUT_RB_WPTR_BASE_IDX 1
+#define mmUVD_RB_BASE_LO2 0x05e1
+#define mmUVD_RB_BASE_LO2_BASE_IDX 1
+#define mmUVD_RB_BASE_HI2 0x05e2
+#define mmUVD_RB_BASE_HI2_BASE_IDX 1
+#define mmUVD_RB_SIZE2 0x05e3
+#define mmUVD_RB_SIZE2_BASE_IDX 1
+#define mmUVD_RB_RPTR2 0x05e4
+#define mmUVD_RB_RPTR2_BASE_IDX 1
+#define mmUVD_RB_WPTR2 0x05e5
+#define mmUVD_RB_WPTR2_BASE_IDX 1
+#define mmUVD_RB_BASE_LO 0x05e6
+#define mmUVD_RB_BASE_LO_BASE_IDX 1
+#define mmUVD_RB_BASE_HI 0x05e7
+#define mmUVD_RB_BASE_HI_BASE_IDX 1
+#define mmUVD_RB_SIZE 0x05e8
+#define mmUVD_RB_SIZE_BASE_IDX 1
+#define mmUVD_RB_RPTR 0x05e9
+#define mmUVD_RB_RPTR_BASE_IDX 1
+#define mmUVD_RB_WPTR 0x05ea
+#define mmUVD_RB_WPTR_BASE_IDX 1
+#define mmUVD_ENC_PIPE_BUSY 0x05eb
+#define mmUVD_ENC_PIPE_BUSY_BASE_IDX 1
+#define mmUVD_RB_WPTR4 0x0616
+#define mmUVD_RB_WPTR4_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x061e
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x061f
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x0620
+#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x0621
+#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0622
+#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0623
+#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0626
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0627
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0628
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0629
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1
+
+
+// addressBlock: uvd0_uvdnp2dec
+// base address: 0x21100
+#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x0640
+#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x0641
+#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x0642
+#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0643
+#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0644
+#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0645
+#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0646
+#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0647
+#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0648
+#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0649
+#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x064a
+#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x064b
+#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x064c
+#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x064d
+#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x064e
+#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x064f
+#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_NC_VMID 0x0651
+#define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1
+#define mmUVD_LMI_MMSCH_CTRL 0x0652
+#define mmUVD_LMI_MMSCH_CTRL_BASE_IDX 1
+#define mmUVD_MMSCH_SOFT_RESET 0x0654
+#define mmUVD_MMSCH_SOFT_RESET_BASE_IDX 1
+#define mmUVD_LMI_ARB_CTRL2 0x0662
+#define mmUVD_LMI_ARB_CTRL2_BASE_IDX 1
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
new file mode 100644
index 000000000000..bb9f8b60b146
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
@@ -0,0 +1,3815 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _vcn_2_0_0_SH_MASK_HEADER
+#define _vcn_2_0_0_SH_MASK_HEADER
+
+
+// addressBlock: uvd0_mmsch_dec
+//MMSCH_UCODE_ADDR
+#define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2
+#define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f
+#define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL
+#define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L
+//MMSCH_UCODE_DATA
+#define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
+//MMSCH_SRAM_ADDR
+#define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2
+#define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f
+#define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL
+#define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L
+//MMSCH_SRAM_DATA
+#define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0
+#define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_SRAM_OFFSET
+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2
+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10
+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL
+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L
+//MMSCH_DB_SRAM_OFFSET
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L
+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L
+//MMSCH_CTX_SRAM_OFFSET
+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2
+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10
+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL
+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L
+//MMSCH_CTL
+#define MMSCH_CTL__P_RUNSTALL__SHIFT 0x0
+#define MMSCH_CTL__P_RESET__SHIFT 0x1
+#define MMSCH_CTL__VFID_FIFO_EN__SHIFT 0x4
+#define MMSCH_CTL__P_LOCK__SHIFT 0x1f
+#define MMSCH_CTL__P_RUNSTALL_MASK 0x00000001L
+#define MMSCH_CTL__P_RESET_MASK 0x00000002L
+#define MMSCH_CTL__VFID_FIFO_EN_MASK 0x00000010L
+#define MMSCH_CTL__P_LOCK_MASK 0x80000000L
+//MMSCH_INTR
+#define MMSCH_INTR__INTR__SHIFT 0x0
+#define MMSCH_INTR__INTR_MASK 0x00001FFFL
+//MMSCH_INTR_ACK
+#define MMSCH_INTR_ACK__INTR__SHIFT 0x0
+#define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL
+//MMSCH_INTR_STATUS
+#define MMSCH_INTR_STATUS__INTR__SHIFT 0x0
+#define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL
+//MMSCH_VF_VMID
+#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0
+#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5
+#define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL
+#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L
+//MMSCH_VF_CTX_ADDR_LO
+#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6
+#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L
+//MMSCH_VF_CTX_ADDR_HI
+#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0
+#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL
+//MMSCH_VF_CTX_SIZE
+#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0
+#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL
+//MMSCH_VF_GPCOM_ADDR_LO
+#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6
+#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L
+//MMSCH_VF_GPCOM_ADDR_HI
+#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0
+#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL
+//MMSCH_VF_GPCOM_SIZE
+#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0
+#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_HOST
+#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_RESP
+#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_0
+#define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_0_RESP
+#define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_1
+#define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX_1_RESP
+#define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0
+#define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL
+//MMSCH_CNTL
+#define MMSCH_CNTL__CLK_EN__SHIFT 0x0
+#define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1
+#define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5
+#define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9
+#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa
+#define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
+#define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c
+#define MMSCH_CNTL__CLK_EN_MASK 0x00000001L
+#define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L
+#define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L
+#define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L
+#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L
+#define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L
+#define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L
+//MMSCH_NONCACHE_OFFSET0
+#define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0
+#define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL
+//MMSCH_NONCACHE_SIZE0
+#define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0
+#define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL
+//MMSCH_NONCACHE_OFFSET1
+#define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0
+#define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL
+//MMSCH_NONCACHE_SIZE1
+#define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0
+#define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL
+//MMSCH_PROC_STATE1
+#define MMSCH_PROC_STATE1__PC__SHIFT 0x0
+#define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL
+//MMSCH_LAST_MC_ADDR
+#define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0
+#define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f
+#define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL
+#define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L
+//MMSCH_LAST_MEM_ACCESS_HI
+#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0
+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8
+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc
+#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L
+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L
+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L
+//MMSCH_LAST_MEM_ACCESS_LO
+#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0
+#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL
+//MMSCH_IOV_ACTIVE_FCN_ID
+#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0
+#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f
+#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000001FL
+#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L
+//MMSCH_SCRATCH_0
+#define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_1
+#define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_SCH_BLOCK_0
+#define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_CONTROL_0
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6
+#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8
+#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L
+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
+#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L
+#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L
+#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L
+//MMSCH_GPUIOV_CMD_STATUS_0
+#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_VM_BUSY_STATUS_0
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCNS_0
+#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_DW6_0
+#define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW7_0
+#define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW8_0
+#define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_SCH_BLOCK_1
+#define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_CONTROL_1
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6
+#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8
+#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L
+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
+#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L
+#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L
+#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L
+//MMSCH_GPUIOV_CMD_STATUS_1
+#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_VM_BUSY_STATUS_1
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCNS_1
+#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_1
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_DW6_1
+#define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW7_1
+#define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW8_1
+#define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_CNTXT
+#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0
+#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7
+#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa
+#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL
+#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L
+#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L
+//MMSCH_SCRATCH_2
+#define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0
+#define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_3
+#define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0
+#define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_4
+#define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0
+#define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_5
+#define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0
+#define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_6
+#define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0
+#define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL
+//MMSCH_SCRATCH_7
+#define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0
+#define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL
+//MMSCH_VFID_FIFO_HEAD_0
+#define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0
+#define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL
+//MMSCH_VFID_FIFO_TAIL_0
+#define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0
+#define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL
+//MMSCH_VFID_FIFO_HEAD_1
+#define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0
+#define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL
+//MMSCH_VFID_FIFO_TAIL_1
+#define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0
+#define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL
+//MMSCH_NACK_STATUS
+#define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0
+#define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2
+#define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L
+#define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL
+//MMSCH_VF_MAILBOX0_DATA
+#define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL
+//MMSCH_VF_MAILBOX1_DATA
+#define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0
+#define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_SCH_BLOCK_IP_0
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_STATUS_IP_0
+#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_SCH_BLOCK_IP_1
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_STATUS_IP_1
+#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_CNTXT_IP
+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0
+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7
+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL
+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L
+//MMSCH_GPUIOV_SCH_BLOCK_2
+#define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_CONTROL_2
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6
+#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8
+#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L
+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
+#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L
+#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L
+#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L
+//MMSCH_GPUIOV_CMD_STATUS_2
+#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_VM_BUSY_STATUS_2
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0
+#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCNS_2
+#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_2
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L
+//MMSCH_GPUIOV_DW6_2
+#define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW7_2
+#define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_DW8_2
+#define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0
+#define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL
+//MMSCH_GPUIOV_SCH_BLOCK_IP_2
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L
+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L
+//MMSCH_GPUIOV_CMD_STATUS_IP_2
+#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0
+#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL
+//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL
+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L
+//MMSCH_VFID_FIFO_HEAD_2
+#define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0
+#define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL
+//MMSCH_VFID_FIFO_TAIL_2
+#define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0
+#define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL
+//MMSCH_VM_BUSY_STATUS_0
+#define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0
+#define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_VM_BUSY_STATUS_1
+#define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0
+#define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL
+//MMSCH_VM_BUSY_STATUS_2
+#define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0
+#define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_jpegnpdec
+//UVD_JPEG_CNTL
+#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1
+#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2
+#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3
+#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4
+#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L
+#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L
+#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L
+#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L
+//UVD_JPEG_RB_BASE
+#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0
+#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6
+#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL
+#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L
+//UVD_JPEG_RB_WPTR
+#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L
+//UVD_JPEG_RB_RPTR
+#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L
+//UVD_JPEG_RB_SIZE
+#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L
+//UVD_JPEG_DEC_SCRATCH0
+#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0
+#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
+//UVD_JPEG_INT_EN
+#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0
+#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1
+#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2
+#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6
+#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7
+#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8
+#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9
+#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa
+#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb
+#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc
+#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd
+#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe
+#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf
+#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L
+#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L
+#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L
+#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L
+#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L
+#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L
+#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L
+#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L
+#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L
+#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L
+#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L
+#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L
+#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L
+//UVD_JPEG_INT_STAT
+#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0
+#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1
+#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2
+#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6
+#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7
+#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8
+#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9
+#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa
+#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb
+#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc
+#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd
+#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe
+#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf
+#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L
+#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L
+#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L
+#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L
+#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L
+#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L
+#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L
+#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L
+#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L
+#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L
+#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L
+#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L
+#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L
+//UVD_JPEG_PITCH
+#define UVD_JPEG_PITCH__PITCH__SHIFT 0x0
+#define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL
+//UVD_JPEG_UV_PITCH
+#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0
+#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL
+//JPEG_DEC_Y_GFX8_TILING_SURFACE
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L
+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L
+//JPEG_DEC_UV_GFX8_TILING_SURFACE
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L
+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L
+//JPEG_DEC_GFX8_ADDR_CONFIG
+#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
+//JPEG_DEC_Y_GFX10_TILING_SURFACE
+#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
+#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
+//JPEG_DEC_UV_GFX10_TILING_SURFACE
+#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
+#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
+//JPEG_DEC_GFX10_ADDR_CONFIG
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//JPEG_DEC_ADDR_MODE
+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0
+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2
+#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc
+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L
+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL
+#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L
+//UVD_JPEG_GPCOM_CMD
+#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1
+#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL
+//UVD_JPEG_GPCOM_DATA0
+#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0
+#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL
+//UVD_JPEG_GPCOM_DATA1
+#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0
+#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL
+//UVD_JPEG_SCRATCH1
+#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0
+#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL
+//UVD_JPEG_DEC_SOFT_RST
+#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0
+#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10
+#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L
+#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L
+
+
+// addressBlock: uvd0_uvd_jpeg_enc_dec
+//UVD_JPEG_ENC_INT_EN
+#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0
+#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1
+#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2
+#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3
+#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4
+#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5
+#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6
+#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L
+#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L
+#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L
+#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L
+#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L
+#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L
+#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L
+//UVD_JPEG_ENC_INT_STATUS
+#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0
+#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1
+#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2
+#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3
+#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4
+#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5
+#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6
+#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L
+#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L
+#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L
+#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L
+#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L
+#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L
+#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L
+//UVD_JPEG_ENC_ENGINE_CNTL
+#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0
+#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1
+#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2
+#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3
+#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4
+#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9
+#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L
+#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L
+#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L
+#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L
+#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L
+#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L
+//UVD_JPEG_ENC_SCRATCH1
+#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0
+#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
+//UVD_JPEG_ENC_STATUS
+#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0
+#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1
+#define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2
+#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3
+#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L
+#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L
+#define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L
+#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L
+//UVD_JPEG_ENC_PITCH
+#define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0
+#define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10
+#define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL
+#define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L
+//UVD_JPEG_ENC_LUMA_BASE
+#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0
+#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_CHROMAU_BASE
+#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0
+#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_CHROMAV_BASE
+#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0
+#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL
+//JPEG_ENC_Y_GFX10_TILING_SURFACE
+#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
+#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
+//JPEG_ENC_UV_GFX10_TILING_SURFACE
+#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
+#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
+//JPEG_ENC_GFX10_ADDR_CONFIG
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//JPEG_ENC_ADDR_MODE
+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0
+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2
+#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc
+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L
+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL
+#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L
+//UVD_JPEG_ENC_GPCOM_CMD
+#define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1
+#define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL
+//UVD_JPEG_ENC_GPCOM_DATA0
+#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0
+#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_GPCOM_DATA1
+#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0
+#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_CGC_CNTL
+#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0
+#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L
+//UVD_JPEG_ENC_SCRATCH0
+#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0
+#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_SOFT_RST
+#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0
+#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10
+#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L
+#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L
+
+
+// addressBlock: uvd0_uvd_jrbc_dec
+//UVD_JRBC_RB_WPTR
+#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_JRBC_RB_CNTL
+#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0
+#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1
+#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4
+#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L
+#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L
+#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L
+//UVD_JRBC_IB_SIZE
+#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
+//UVD_JRBC_URGENT_CNTL
+#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0
+#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L
+//UVD_JRBC_RB_REF_DATA
+#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0
+#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
+//UVD_JRBC_RB_COND_RD_TIMER
+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
+#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
+#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
+#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
+#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
+//UVD_JRBC_SOFT_RESET
+#define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0
+#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11
+#define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L
+#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L
+//UVD_JRBC_STATUS
+#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0
+#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1
+#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2
+#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3
+#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4
+#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5
+#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6
+#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7
+#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8
+#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9
+#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
+#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb
+#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc
+#define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10
+#define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11
+#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L
+#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L
+#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L
+#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L
+#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L
+#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L
+#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L
+#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L
+#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L
+#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L
+#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L
+#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L
+#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L
+#define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L
+#define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L
+//UVD_JRBC_RB_RPTR
+#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_JRBC_RB_BUF_STATUS
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L
+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L
+//UVD_JRBC_IB_BUF_STATUS
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L
+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L
+//UVD_JRBC_IB_SIZE_UPDATE
+#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4
+#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L
+//UVD_JRBC_IB_COND_RD_TIMER
+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
+#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
+#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
+#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
+#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
+//UVD_JRBC_IB_REF_DATA
+#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0
+#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
+//UVD_JPEG_PREEMPT_CMD
+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0
+#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1
+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2
+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L
+#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L
+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L
+//UVD_JPEG_PREEMPT_FENCE_DATA0
+#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0
+#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL
+//UVD_JPEG_PREEMPT_FENCE_DATA1
+#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0
+#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL
+//UVD_JRBC_RB_SIZE
+#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L
+//UVD_JRBC_SCRATCH0
+#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0
+#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_jrbc_enc_dec
+//UVD_JRBC_ENC_RB_WPTR
+#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_JRBC_ENC_RB_CNTL
+#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0
+#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1
+#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4
+#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L
+#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L
+#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L
+//UVD_JRBC_ENC_IB_SIZE
+#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
+//UVD_JRBC_ENC_URGENT_CNTL
+#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0
+#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L
+//UVD_JRBC_ENC_RB_REF_DATA
+#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0
+#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
+//UVD_JRBC_ENC_RB_COND_RD_TIMER
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
+//UVD_JRBC_ENC_SOFT_RESET
+#define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0
+#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11
+#define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L
+#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L
+//UVD_JRBC_ENC_STATUS
+#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0
+#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1
+#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2
+#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3
+#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4
+#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5
+#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6
+#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7
+#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8
+#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9
+#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
+#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb
+#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc
+#define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10
+#define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11
+#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L
+#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L
+#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L
+#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L
+#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L
+#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L
+#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L
+#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L
+#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L
+#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L
+#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L
+#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L
+#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L
+#define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L
+#define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L
+//UVD_JRBC_ENC_RB_RPTR
+#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_JRBC_ENC_RB_BUF_STATUS
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L
+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L
+//UVD_JRBC_ENC_IB_BUF_STATUS
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L
+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L
+//UVD_JRBC_ENC_IB_SIZE_UPDATE
+#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4
+#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L
+//UVD_JRBC_ENC_IB_COND_RD_TIMER
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
+//UVD_JRBC_ENC_IB_REF_DATA
+#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0
+#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_PREEMPT_CMD
+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0
+#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1
+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2
+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L
+#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L
+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L
+//UVD_JPEG_ENC_PREEMPT_FENCE_DATA0
+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0
+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL
+//UVD_JPEG_ENC_PREEMPT_FENCE_DATA1
+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0
+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL
+//UVD_JRBC_ENC_RB_SIZE
+#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L
+//UVD_JRBC_ENC_SCRATCH0
+#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0
+#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_jmi_dec
+//UVD_JMI_CTRL
+#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0
+#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1
+#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2
+#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8
+#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10
+#define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18
+#define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19
+#define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L
+#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L
+#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L
+#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L
+#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L
+#define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L
+#define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L
+//UVD_LMI_JRBC_CTRL
+#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4
+#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8
+#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14
+#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16
+#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L
+#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L
+//UVD_LMI_JPEG_CTRL
+#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4
+#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8
+#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14
+#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16
+#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L
+#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L
+//UVD_JMI_EJRBC_CTRL
+#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4
+#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8
+#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14
+#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16
+#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L
+#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L
+//UVD_LMI_EJPEG_CTRL
+#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4
+#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8
+#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14
+#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16
+#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L
+#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L
+//UVD_LMI_JRBC_IB_VMID
+#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4
+#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8
+#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL
+#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L
+#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L
+//UVD_LMI_JRBC_RB_VMID
+#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4
+#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8
+#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL
+#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L
+#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L
+//UVD_LMI_JPEG_VMID
+#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0
+#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4
+#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8
+#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL
+#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L
+#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L
+//UVD_JMI_ENC_JRBC_IB_VMID
+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0
+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4
+#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8
+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL
+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L
+#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L
+//UVD_JMI_ENC_JRBC_RB_VMID
+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0
+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4
+#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8
+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL
+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L
+#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L
+//UVD_JMI_ENC_JPEG_VMID
+#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0
+#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5
+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa
+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf
+#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13
+#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17
+#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL
+#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L
+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L
+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L
+#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L
+#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L
+//UVD_JMI_PERFMON_CTRL
+#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0
+#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8
+#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L
+#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L
+//UVD_JMI_PERFMON_COUNT_LO
+#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0
+#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL
+//UVD_JMI_PERFMON_COUNT_HI
+#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0
+#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL
+//UVD_LMI_JPEG_READ_64BIT_BAR_LOW
+#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW
+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW
+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW
+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH
+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW
+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW
+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH
+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_PREEMPT_VMID
+#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0
+#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL
+//UVD_LMI_ENC_JPEG_PREEMPT_VMID
+#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0
+#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL
+//UVD_LMI_JPEG2_VMID
+#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0
+#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4
+#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL
+#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L
+//UVD_LMI_JPEG2_READ_64BIT_BAR_LOW
+#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW
+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH
+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_JPEG_CTRL2
+#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4
+#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8
+#define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14
+#define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16
+#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L
+#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L
+#define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L
+#define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L
+//UVD_JMI_DEC_SWAP_CNTL
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
+#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc
+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe
+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L
+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L
+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L
+#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L
+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L
+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L
+//UVD_JMI_ENC_SWAP_CNTL
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
+#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc
+#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe
+#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10
+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12
+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14
+#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L
+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L
+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L
+#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L
+#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L
+#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L
+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L
+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L
+#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L
+//UVD_JMI_CNTL
+#define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0
+#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8
+#define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L
+#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L
+//UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW
+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH
+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_JMI_DEC_SWAP_CNTL2
+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0
+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2
+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L
+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL
+
+
+// addressBlock: uvd0_uvd_jpeg_common_dec
+//JPEG_SOFT_RESET_STATUS
+#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0
+#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1
+#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2
+#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3
+#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4
+#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5
+#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L
+#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L
+#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L
+#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L
+#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L
+#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L
+//JPEG_SYS_INT_EN
+#define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0
+#define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1
+#define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2
+#define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3
+#define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4
+#define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5
+#define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6
+#define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L
+#define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L
+#define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L
+#define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L
+#define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L
+#define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L
+#define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L
+//JPEG_SYS_INT_STATUS
+#define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0
+#define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1
+#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2
+#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3
+#define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4
+#define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5
+#define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6
+#define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L
+#define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L
+#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L
+#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L
+#define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L
+#define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L
+#define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L
+//JPEG_SYS_INT_ACK
+#define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0
+#define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1
+#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2
+#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3
+#define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4
+#define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5
+#define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6
+#define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L
+#define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L
+#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L
+#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L
+#define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L
+#define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L
+#define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L
+//JPEG_MASTINT_EN
+#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
+#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
+#define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
+#define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L
+//JPEG_IH_CTRL
+#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0
+#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1
+#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2
+#define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3
+#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7
+#define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13
+#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L
+#define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L
+#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L
+#define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L
+#define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L
+#define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L
+//JRBBM_ARB_CTRL
+#define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0
+#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1
+#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2
+#define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L
+#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L
+#define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L
+
+
+// addressBlock: uvd0_uvd_jpeg_common_sclk_dec
+//JPEG_CGC_GATE
+#define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0
+#define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1
+#define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2
+#define JPEG_CGC_GATE__JMCIF__SHIFT 0x3
+#define JPEG_CGC_GATE__JRBBM__SHIFT 0x4
+#define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L
+#define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L
+#define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L
+#define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L
+#define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L
+//JPEG_CGC_CTRL
+#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
+#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1
+#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5
+#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa
+#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb
+#define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc
+#define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10
+#define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11
+#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12
+#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13
+#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14
+#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
+#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL
+#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L
+#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L
+#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L
+#define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L
+#define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L
+#define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L
+#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L
+#define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L
+#define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L
+//JPEG_CGC_STATUS
+#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0
+#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1
+#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2
+#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3
+#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4
+#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5
+#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6
+#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7
+#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8
+#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L
+#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L
+#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L
+#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L
+#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L
+#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L
+#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L
+#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L
+#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L
+//JPEG_COMN_CGC_MEM_CTRL
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2
+#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
+#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L
+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L
+#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L
+#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L
+//JPEG_DEC_CGC_MEM_CTRL
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L
+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L
+//JPEG2_DEC_CGC_MEM_CTRL
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L
+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L
+//JPEG_ENC_CGC_MEM_CTRL
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L
+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L
+//JPEG_SOFT_RESET2
+#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0
+#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L
+//JPEG_PERF_BANK_CONF
+#define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0
+#define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8
+#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10
+#define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL
+#define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L
+#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L
+//JPEG_PERF_BANK_EVENT_SEL
+#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0
+#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8
+#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10
+#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18
+#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL
+#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L
+#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L
+#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L
+//JPEG_PERF_BANK_COUNT0
+#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0
+#define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL
+//JPEG_PERF_BANK_COUNT1
+#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0
+#define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL
+//JPEG_PERF_BANK_COUNT2
+#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0
+#define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL
+//JPEG_PERF_BANK_COUNT3
+#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0
+#define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvd_pg_dec
+//UVD_PGFSM_CONFIG
+#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0
+#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2
+#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4
+#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6
+#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8
+#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa
+#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc
+#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe
+#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10
+#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12
+#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14
+#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16
+#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L
+#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL
+#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L
+#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L
+#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L
+#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L
+#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L
+#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L
+#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L
+#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L
+#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L
+#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L
+//UVD_PGFSM_STATUS
+#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0
+#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2
+#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4
+#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6
+#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8
+#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa
+#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc
+#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe
+#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10
+#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12
+#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14
+#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16
+#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L
+#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL
+#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L
+#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L
+#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L
+#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L
+#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L
+#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L
+#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L
+#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L
+#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L
+#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L
+//UVD_POWER_STATUS
+#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
+#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
+#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4
+#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
+#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9
+#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb
+#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f
+#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L
+#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L
+#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L
+#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L
+#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L
+#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L
+#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L
+//UVD_PG_IND_INDEX
+#define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0
+#define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL
+//UVD_PG_IND_DATA
+#define UVD_PG_IND_DATA__DATA__SHIFT 0x0
+#define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL
+//CC_UVD_HARVESTING
+#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0
+#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1
+#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L
+#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L
+//UVD_JPEG_POWER_STATUS
+#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0
+#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4
+#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8
+#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9
+#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f
+#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L
+#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L
+#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L
+#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L
+#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L
+//UVD_DPG_LMA_CTL
+#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0
+#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1
+#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2
+#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4
+#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10
+#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L
+#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L
+#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L
+#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L
+#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L
+//UVD_DPG_LMA_DATA
+#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0
+#define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL
+//UVD_DPG_LMA_MASK
+#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0
+#define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL
+//UVD_DPG_PAUSE
+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0
+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1
+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2
+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3
+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L
+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L
+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L
+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L
+//UVD_SCRATCH1
+#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0
+#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH2
+#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0
+#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH3
+#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0
+#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH4
+#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0
+#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH5
+#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0
+#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH6
+#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0
+#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH7
+#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0
+#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH8
+#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0
+#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH9
+#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0
+#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH10
+#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0
+#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH11
+#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0
+#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH12
+#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0
+#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH13
+#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0
+#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL
+//UVD_SCRATCH14
+#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0
+#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL
+//UVD_FREE_COUNTER_REG
+#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0
+#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL
+//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_DPG_VCPU_CACHE_OFFSET0
+#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
+#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL
+//UVD_DPG_LMI_VCPU_CACHE_VMID
+#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0
+#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL
+//UVD_PF_STATUS
+#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0
+#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1
+#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2
+#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3
+#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4
+#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5
+#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6
+#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7
+#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8
+#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9
+#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa
+#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb
+#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc
+#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd
+#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe
+#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf
+#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10
+#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11
+#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12
+#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L
+#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L
+#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L
+#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L
+#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L
+#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L
+#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L
+#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L
+#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L
+#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L
+#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L
+#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L
+#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L
+#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L
+#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L
+#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L
+#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L
+#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L
+#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L
+//UVD_DPG_CLK_EN_VCPU_REPORT
+#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0
+#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1
+#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L
+#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL
+//UVD_GFX8_ADDR_CONFIG
+#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
+//UVD_GFX10_ADDR_CONFIG
+#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
+#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
+#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
+#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
+#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
+#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
+#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
+//UVD_GPCNT2_CNTL
+#define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0
+#define UVD_GPCNT2_CNTL__START__SHIFT 0x1
+#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2
+#define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L
+#define UVD_GPCNT2_CNTL__START_MASK 0x00000002L
+#define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L
+//UVD_GPCNT2_TARGET_LOWER
+#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0
+#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL
+//UVD_GPCNT2_STATUS_LOWER
+#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0
+#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL
+//UVD_GPCNT2_TARGET_UPPER
+#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0
+#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL
+//UVD_GPCNT2_STATUS_UPPER
+#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0
+#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL
+//UVD_GPCNT3_CNTL
+#define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0
+#define UVD_GPCNT3_CNTL__START__SHIFT 0x1
+#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2
+#define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3
+#define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa
+#define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L
+#define UVD_GPCNT3_CNTL__START_MASK 0x00000002L
+#define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L
+#define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L
+#define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L
+//UVD_GPCNT3_TARGET_LOWER
+#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0
+#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL
+//UVD_GPCNT3_STATUS_LOWER
+#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0
+#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL
+//UVD_GPCNT3_TARGET_UPPER
+#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0
+#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL
+//UVD_GPCNT3_STATUS_UPPER
+#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0
+#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL
+//UVD_TSC_LOWER
+#define UVD_TSC_LOWER__COUNT__SHIFT 0x0
+#define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL
+//UVD_TSC_UPPER
+#define UVD_TSC_UPPER__COUNT__SHIFT 0x0
+#define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL
+
+
+// addressBlock: uvd0_uvddec
+//UVD_SEMA_CNTL
+#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
+#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L
+//UVD_RB_RPTR3
+#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR3
+#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RB_BASE_LO3
+#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI3
+#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE3
+#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_ARB_CTRL
+#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0
+#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1
+#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2
+#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3
+#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4
+#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5
+#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6
+#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7
+#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8
+#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L
+#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L
+#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L
+#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L
+#define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L
+#define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L
+#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L
+#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L
+#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L
+//UVD_LMI_LAT_CTRL
+#define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0
+#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8
+#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9
+#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa
+#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb
+#define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10
+#define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL
+#define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L
+#define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L
+#define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L
+#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L
+#define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L
+//UVD_LMI_LAT_CNTR
+#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0
+#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8
+#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL
+#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L
+//UVD_LMI_AVG_LAT_CNTR
+#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0
+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8
+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10
+#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL
+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L
+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L
+//UVD_SOFT_RESET2
+#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0
+#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10
+#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11
+#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L
+#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L
+#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L
+//UVD_LMI_SPH
+#define UVD_LMI_SPH__ADDR__SHIFT 0x0
+#define UVD_LMI_SPH__STS__SHIFT 0x1c
+#define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e
+#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f
+#define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL
+#define UVD_LMI_SPH__STS_MASK 0x30000000L
+#define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L
+#define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L
+//UVD_CTX_INDEX
+#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
+#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL
+//UVD_CTX_DATA
+#define UVD_CTX_DATA__DATA__SHIFT 0x0
+#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL
+//UVD_CGC_GATE
+#define UVD_CGC_GATE__SYS__SHIFT 0x0
+#define UVD_CGC_GATE__UDEC__SHIFT 0x1
+#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
+#define UVD_CGC_GATE__REGS__SHIFT 0x3
+#define UVD_CGC_GATE__RBC__SHIFT 0x4
+#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
+#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
+#define UVD_CGC_GATE__IDCT__SHIFT 0x7
+#define UVD_CGC_GATE__MPRD__SHIFT 0x8
+#define UVD_CGC_GATE__MPC__SHIFT 0x9
+#define UVD_CGC_GATE__LBSI__SHIFT 0xa
+#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
+#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
+#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
+#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
+#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
+#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
+#define UVD_CGC_GATE__WCB__SHIFT 0x11
+#define UVD_CGC_GATE__VCPU__SHIFT 0x12
+#define UVD_CGC_GATE__SCPU__SHIFT 0x13
+#define UVD_CGC_GATE__MMSCH__SHIFT 0x14
+#define UVD_CGC_GATE__SYS_MASK 0x00000001L
+#define UVD_CGC_GATE__UDEC_MASK 0x00000002L
+#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L
+#define UVD_CGC_GATE__REGS_MASK 0x00000008L
+#define UVD_CGC_GATE__RBC_MASK 0x00000010L
+#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L
+#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L
+#define UVD_CGC_GATE__IDCT_MASK 0x00000080L
+#define UVD_CGC_GATE__MPRD_MASK 0x00000100L
+#define UVD_CGC_GATE__MPC_MASK 0x00000200L
+#define UVD_CGC_GATE__LBSI_MASK 0x00000400L
+#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L
+#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L
+#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L
+#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L
+#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L
+#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L
+#define UVD_CGC_GATE__WCB_MASK 0x00020000L
+#define UVD_CGC_GATE__VCPU_MASK 0x00040000L
+#define UVD_CGC_GATE__SCPU_MASK 0x00080000L
+#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L
+//UVD_CGC_STATUS
+#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
+#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
+#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
+#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
+#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
+#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
+#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
+#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
+#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
+#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
+#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
+#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
+#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
+#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
+#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
+#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
+#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
+#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
+#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
+#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
+#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
+#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
+#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
+#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
+#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
+#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
+#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
+#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b
+#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c
+#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d
+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
+#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L
+#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L
+#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L
+#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L
+#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L
+#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L
+#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L
+#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L
+#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L
+#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L
+#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L
+#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L
+#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L
+#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L
+#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L
+#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L
+#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L
+#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L
+#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L
+#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
+#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L
+#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L
+#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L
+#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L
+#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L
+#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L
+#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L
+#define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L
+#define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L
+#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L
+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L
+//UVD_CGC_CTRL
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
+#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
+#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
+#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
+#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
+#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
+#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
+#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
+#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
+#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
+#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
+#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
+#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
+#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
+#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
+#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
+#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
+#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
+#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
+#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
+#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
+#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
+#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
+#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L
+#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L
+#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
+#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L
+#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
+#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
+#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L
+#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L
+#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L
+#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
+#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L
+#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L
+#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L
+#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L
+#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L
+#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
+#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L
+#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L
+#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
+#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L
+#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L
+#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L
+//UVD_CGC_UDEC_STATUS
+#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
+#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
+#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
+#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
+#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
+#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
+#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
+#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
+#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
+#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
+#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
+#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
+#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
+#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
+#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
+#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L
+#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L
+#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L
+#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L
+#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L
+#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L
+#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L
+#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L
+#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L
+#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L
+#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L
+#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L
+#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L
+#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L
+#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L
+//UVD_CXW_WR_INT_ID
+#define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0
+#define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL
+//UVD_CXW_WR_INT_CTX_ID
+#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0
+#define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL
+//UVD_VCPU_INT_ROUTE
+#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0
+#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1
+#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2
+#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L
+#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L
+#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L
+//UVD_GP_SCRATCH0
+#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH1
+#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH2
+#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH3
+#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH4
+#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH5
+#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH6
+#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH7
+#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE_VMID
+#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL
+//UVD_LMI_CTRL2
+#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
+#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
+#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
+#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
+#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19
+#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a
+#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b
+#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
+#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
+#define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L
+#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L
+#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L
+#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L
+#define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L
+//UVD_MASTINT_EN
+#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
+#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
+#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
+#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
+#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
+#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L
+#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L
+#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L
+//UVD_SYS_INT_EN
+#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0
+#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1
+#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2
+#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3
+#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6
+#define UVD_SYS_INT_EN__UVD_HOST_CXW_EN__SHIFT 0x8
+#define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb
+#define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc
+#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10
+#define UVD_SYS_INT_EN__WPTR_IDLE_EN__SHIFT 0x15
+#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT 0x16
+#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17
+#define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18
+#define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19
+#define UVD_SYS_INT_EN__FCS_EN__SHIFT 0x1a
+#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b
+#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c
+#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d
+#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f
+#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L
+#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L
+#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L
+#define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L
+#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L
+#define UVD_SYS_INT_EN__UVD_HOST_CXW_EN_MASK 0x00000100L
+#define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L
+#define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L
+#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L
+#define UVD_SYS_INT_EN__WPTR_IDLE_EN_MASK 0x00200000L
+#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK 0x00400000L
+#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L
+#define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L
+#define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L
+#define UVD_SYS_INT_EN__FCS_EN_MASK 0x04000000L
+#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L
+#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L
+#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L
+#define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L
+//UVD_SYS_INT_STATUS
+#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0
+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1
+#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2
+#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3
+#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6
+#define UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT__SHIFT 0x8
+#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb
+#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc
+#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10
+#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12
+#define UVD_SYS_INT_STATUS__WPTR_IDLE_INT__SHIFT 0x15
+#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT__SHIFT 0x16
+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17
+#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18
+#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19
+#define UVD_SYS_INT_STATUS__FCS_INT__SHIFT 0x1a
+#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b
+#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c
+#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d
+#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f
+#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L
+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L
+#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L
+#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L
+#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L
+#define UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT_MASK 0x00000100L
+#define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L
+#define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L
+#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L
+#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L
+#define UVD_SYS_INT_STATUS__WPTR_IDLE_INT_MASK 0x00200000L
+#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT_MASK 0x00400000L
+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L
+#define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L
+#define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L
+#define UVD_SYS_INT_STATUS__FCS_INT_MASK 0x04000000L
+#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L
+#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L
+#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L
+#define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L
+//UVD_SYS_INT_ACK
+#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0
+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1
+#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2
+#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3
+#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6
+#define UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK__SHIFT 0x8
+#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb
+#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc
+#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10
+#define UVD_SYS_INT_ACK__WPTR_IDLE_ACK__SHIFT 0x15
+#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT 0x16
+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17
+#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18
+#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19
+#define UVD_SYS_INT_ACK__FCS_ACK__SHIFT 0x1a
+#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b
+#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c
+#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d
+#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f
+#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L
+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L
+#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L
+#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L
+#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L
+#define UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK_MASK 0x00000100L
+#define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L
+#define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L
+#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L
+#define UVD_SYS_INT_ACK__WPTR_IDLE_ACK_MASK 0x00200000L
+#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK 0x00400000L
+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L
+#define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L
+#define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L
+#define UVD_SYS_INT_ACK__FCS_ACK_MASK 0x04000000L
+#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L
+#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L
+#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L
+#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L
+//UVD_VCPU_INT_EN
+#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0
+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1
+#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2
+#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3
+#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4
+#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5
+#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6
+#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7
+#define UVD_VCPU_INT_EN__UVD_HOST_CXW_EN__SHIFT 0x8
+#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9
+#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa
+#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb
+#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc
+#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10
+#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11
+#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12
+#define UVD_VCPU_INT_EN__WPTR_IDLE_EN__SHIFT 0x15
+#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT 0x16
+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17
+#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18
+#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19
+#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a
+#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b
+#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c
+#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d
+#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e
+#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f
+#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L
+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L
+#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L
+#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L
+#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L
+#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L
+#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L
+#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L
+#define UVD_VCPU_INT_EN__UVD_HOST_CXW_EN_MASK 0x00000100L
+#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L
+#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L
+#define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L
+#define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L
+#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L
+#define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L
+#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L
+#define UVD_VCPU_INT_EN__WPTR_IDLE_EN_MASK 0x00200000L
+#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK 0x00400000L
+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L
+#define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L
+#define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L
+#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L
+#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L
+#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L
+#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L
+#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L
+#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L
+//UVD_VCPU_INT_ACK
+#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0
+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1
+#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2
+#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3
+#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4
+#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5
+#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6
+#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7
+#define UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK__SHIFT 0x8
+#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9
+#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa
+#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb
+#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc
+#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10
+#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11
+#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12
+#define UVD_VCPU_INT_ACK__WPTR_IDLE_ACK__SHIFT 0x15
+#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT 0x16
+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17
+#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18
+#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19
+#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a
+#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b
+#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c
+#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d
+#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e
+#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f
+#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L
+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L
+#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L
+#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L
+#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L
+#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L
+#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L
+#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L
+#define UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK_MASK 0x00000100L
+#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L
+#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L
+#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L
+#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L
+#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L
+#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L
+#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L
+#define UVD_VCPU_INT_ACK__WPTR_IDLE_ACK_MASK 0x00200000L
+#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK 0x00400000L
+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L
+#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L
+#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L
+#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L
+#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L
+#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L
+#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L
+#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L
+#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L
+//UVD_TOP_CTRL
+#define UVD_TOP_CTRL__STANDARD__SHIFT 0x0
+#define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4
+#define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL
+#define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L
+//UVD_ENC_VCPU_INT_EN
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L
+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L
+//UVD_ENC_VCPU_INT_ACK
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L
+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L
+//UVD_LMI_VCPU_CACHE_VMIDS_MULTI
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L
+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L
+//UVD_LMI_VCPU_NC_VMIDS_MULTI
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L
+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L
+//UVD_LMI_URGENT_CTRL
+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2
+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa
+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12
+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a
+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL
+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L
+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L
+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L
+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L
+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L
+//UVD_LMI_CTRL
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
+#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
+#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
+#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
+#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
+#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b
+#define UVD_LMI_CTRL__RFU__SHIFT 0x1c
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L
+#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
+#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
+#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L
+#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L
+#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L
+#define UVD_LMI_CTRL__RFU_MASK 0xF0000000L
+//UVD_LMI_STATUS
+#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
+#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
+#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
+#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
+#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
+#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
+#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12
+#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13
+#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14
+#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15
+#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16
+#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
+#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L
+#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
+#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L
+#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L
+#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L
+#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L
+#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L
+#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L
+#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L
+//UVD_LMI_VM_CTRL
+#define UVD_LMI_VM_CTRL__VCPU_VM__SHIFT 0x0
+#define UVD_LMI_VM_CTRL__CM_VM__SHIFT 0x1
+#define UVD_LMI_VM_CTRL__IT_VM__SHIFT 0x2
+#define UVD_LMI_VM_CTRL__MP_VM__SHIFT 0x3
+#define UVD_LMI_VM_CTRL__DB_VM__SHIFT 0x4
+#define UVD_LMI_VM_CTRL__RB_VM__SHIFT 0x5
+#define UVD_LMI_VM_CTRL__IB_VM__SHIFT 0x6
+#define UVD_LMI_VM_CTRL__CSM_VM__SHIFT 0x7
+#define UVD_LMI_VM_CTRL__RB_WR_VM__SHIFT 0x8
+#define UVD_LMI_VM_CTRL__DBW_VM__SHIFT 0xa
+#define UVD_LMI_VM_CTRL__RB_RPTR_VM__SHIFT 0xb
+#define UVD_LMI_VM_CTRL__RE_VM__SHIFT 0xc
+#define UVD_LMI_VM_CTRL__SCPU_VM__SHIFT 0xd
+#define UVD_LMI_VM_CTRL__ACAP_VM__SHIFT 0xe
+#define UVD_LMI_VM_CTRL__VCPU_VM_MASK 0x00000001L
+#define UVD_LMI_VM_CTRL__CM_VM_MASK 0x00000002L
+#define UVD_LMI_VM_CTRL__IT_VM_MASK 0x00000004L
+#define UVD_LMI_VM_CTRL__MP_VM_MASK 0x00000008L
+#define UVD_LMI_VM_CTRL__DB_VM_MASK 0x00000010L
+#define UVD_LMI_VM_CTRL__RB_VM_MASK 0x00000020L
+#define UVD_LMI_VM_CTRL__IB_VM_MASK 0x00000040L
+#define UVD_LMI_VM_CTRL__CSM_VM_MASK 0x00000080L
+#define UVD_LMI_VM_CTRL__RB_WR_VM_MASK 0x00000100L
+#define UVD_LMI_VM_CTRL__DBW_VM_MASK 0x00000400L
+#define UVD_LMI_VM_CTRL__RB_RPTR_VM_MASK 0x00000800L
+#define UVD_LMI_VM_CTRL__RE_VM_MASK 0x00001000L
+#define UVD_LMI_VM_CTRL__SCPU_VM_MASK 0x00002000L
+#define UVD_LMI_VM_CTRL__ACAP_VM_MASK 0x00004000L
+//UVD_LMI_PERFMON_CTRL
+#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0
+#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8
+#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L
+#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L
+//UVD_LMI_PERFMON_COUNT_LO
+#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0
+#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL
+//UVD_LMI_PERFMON_COUNT_HI
+#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0
+#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL
+//UVD_LMI_SWAP_CNTL
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
+#define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L
+#define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00C00000L
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L
+//UVD_UDEC_ADR
+#define UVD_UDEC_ADR__SYNC_RE__SHIFT 0x7
+#define UVD_UDEC_ADR__SYNC_RE_MASK 0x00000080L
+//UVD_MP_SWAP_CNTL
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L
+//UVD_MPC_LUMA_SRCH
+#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0
+#define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_LUMA_HIT
+#define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0
+#define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_LUMA_HITPEND
+#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0
+#define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_CHROMA_SRCH
+#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0
+#define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_CHROMA_HIT
+#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0
+#define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_CHROMA_HITPEND
+#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0
+#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL
+//UVD_MPC_CNTL
+#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
+#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
+#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
+#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
+#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13
+#define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14
+#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
+#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L
+#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L
+#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L
+#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L
+#define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L
+//UVD_MPC_PITCH
+#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0
+#define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL
+//UVD_MPC_SET_MUXA0
+#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L
+#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L
+#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L
+//UVD_MPC_SET_MUXA1
+#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
+#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L
+//UVD_MPC_SET_MUXB0
+#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L
+#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L
+#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L
+//UVD_MPC_SET_MUXB1
+#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
+#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL
+#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L
+#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L
+//UVD_MPC_SET_MUX
+#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
+#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
+#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
+#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L
+#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L
+#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L
+//UVD_MPC_SET_ALU
+#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
+#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
+#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L
+#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L
+//UVD_GPCOM_SYS_CMD
+#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0
+#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1
+#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f
+#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L
+#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL
+#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L
+//UVD_GPCOM_SYS_DATA0
+#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0
+#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL
+//UVD_GPCOM_SYS_DATA1
+#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0
+#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL
+//UVD_VCPU_CACHE_OFFSET0
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE0
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET1
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE1
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET2
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE2
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET3
+#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE3
+#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET4
+#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE4
+#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET5
+#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE5
+#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET6
+#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE6
+#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET7
+#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE7
+#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_OFFSET8
+#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL
+//UVD_VCPU_CACHE_SIZE8
+#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL
+//UVD_VCPU_NONCACHE_OFFSET0
+#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0
+#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL
+//UVD_VCPU_NONCACHE_SIZE0
+#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0
+#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL
+//UVD_VCPU_NONCACHE_OFFSET1
+#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0
+#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL
+//UVD_VCPU_NONCACHE_SIZE1
+#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0
+#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL
+//UVD_VCPU_CNTL
+#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
+#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
+#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
+#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
+#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
+#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
+#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
+#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
+#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
+#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c
+#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e
+#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f
+#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L
+#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L
+#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L
+#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L
+#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L
+#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L
+#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L
+#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L
+#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x00080000L
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L
+#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000L
+#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000L
+#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000L
+//UVD_VCPU_PRID
+#define UVD_VCPU_PRID__PRID__SHIFT 0x0
+#define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL
+//UVD_VCPU_TRCE
+#define UVD_VCPU_TRCE__PC__SHIFT 0x0
+#define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL
+//UVD_VCPU_TRCE_RD
+#define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0
+#define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL
+//UVD_MPC_PERF0
+#define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0
+#define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL
+//UVD_MPC_PERF1
+#define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0
+#define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL
+//UVD_CXW_WR
+#define UVD_CXW_WR__DAT__SHIFT 0x0
+#define UVD_CXW_WR__STAT__SHIFT 0x1f
+#define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL
+#define UVD_CXW_WR__STAT_MASK 0x80000000L
+//UVD_SOFT_RESET
+#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
+#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
+#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
+#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
+#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
+#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
+#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9
+#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
+#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
+#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
+#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17
+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18
+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
+#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L
+#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L
+#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L
+#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L
+#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L
+#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L
+#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L
+#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L
+#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L
+#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L
+#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L
+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L
+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L
+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L
+//UVD_LMI_RBC_IB_VMID
+#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
+#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL
+//UVD_RBC_IB_SIZE
+#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
+//UVD_LMI_RBC_RB_VMID
+#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0
+#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL
+//UVD_RBC_RB_RPTR
+#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RBC_RB_WPTR
+#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RBC_RB_WPTR_CNTL
+#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0
+#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL
+//UVD_RBC_READ_REQ_URGENT_CNTL
+#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0
+#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L
+//UVD_RBC_WPTR_STATUS
+#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4
+#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L
+//UVD_RBC_RB_CNTL
+#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
+#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL
+#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
+//UVD_RBC_RB_RPTR_ADDR
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL
+//UVD_JOB_START
+#define UVD_JOB_START__JOB_START__SHIFT 0x0
+#define UVD_JOB_START__JOB_START_MASK 0x00000001L
+//UVD_JOB_DONE
+#define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0
+#define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L
+//UVD_STATUS
+#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
+#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
+#define UVD_STATUS__AVP_BUSY__SHIFT 0x8
+#define UVD_STATUS__IDCT_BUSY__SHIFT 0x9
+#define UVD_STATUS__IDCT_CTL_ACK__SHIFT 0xb
+#define UVD_STATUS__UVD_CTL_ACK__SHIFT 0xc
+#define UVD_STATUS__AVP_BLOCK_ACK__SHIFT 0xd
+#define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT 0xe
+#define UVD_STATUS__UVD_BLOCK_ACK__SHIFT 0xf
+#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10
+#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f
+#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L
+#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL
+#define UVD_STATUS__AVP_BUSY_MASK 0x00000100L
+#define UVD_STATUS__IDCT_BUSY_MASK 0x00000200L
+#define UVD_STATUS__IDCT_CTL_ACK_MASK 0x00000800L
+#define UVD_STATUS__UVD_CTL_ACK_MASK 0x00001000L
+#define UVD_STATUS__AVP_BLOCK_ACK_MASK 0x00002000L
+#define UVD_STATUS__IDCT_BLOCK_ACK_MASK 0x00004000L
+#define UVD_STATUS__UVD_BLOCK_ACK_MASK 0x00008000L
+#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L
+#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L
+//UVD_SEMA_TIMEOUT_STATUS
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L
+//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
+//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
+//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
+//UVD_CXW_EN
+#define UVD_CXW_EN__CXW_ENABLE__SHIFT 0x0
+#define UVD_CXW_EN__CXW_ENABLE_MASK 0x00000001L
+//UVD_CXW_SE
+#define UVD_CXW_SE__CXW_SCAN_ENABLE__SHIFT 0x0
+#define UVD_CXW_SE__CXW_SCAN_ENABLE_MASK 0x00000001L
+//UVD_CXW_FINISHED
+#define UVD_CXW_FINISHED__CXW_FINISHED__SHIFT 0x0
+#define UVD_CXW_FINISHED__CXW_FINISHED_MASK 0x00000001L
+//UVD_CXW_SHIFT_FINISHED
+#define UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED__SHIFT 0x0
+#define UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED_MASK 0x00000001L
+//UVD_CXW_START
+#define UVD_CXW_START__START_CXW__SHIFT 0x0
+#define UVD_CXW_START__START_CXW_MASK 0x00000001L
+//UVD_CXW_BLOCK_STATUS
+#define UVD_CXW_BLOCK_STATUS__VCPU_IDLE__SHIFT 0x0
+#define UVD_CXW_BLOCK_STATUS__LBSI_IDLE__SHIFT 0x1
+#define UVD_CXW_BLOCK_STATUS__LMI_IDLE__SHIFT 0x2
+#define UVD_CXW_BLOCK_STATUS__VCPU_IDLE_MASK 0x00000001L
+#define UVD_CXW_BLOCK_STATUS__LBSI_IDLE_MASK 0x00000002L
+#define UVD_CXW_BLOCK_STATUS__LMI_IDLE_MASK 0x00000004L
+//UVD_STOP_CONTEXT
+#define UVD_STOP_CONTEXT__STOP_CONTEXT__SHIFT 0x0
+#define UVD_STOP_CONTEXT__CONTEXT_MODE__SHIFT 0x1
+#define UVD_STOP_CONTEXT__STOP_CONTEXT_MASK 0x00000001L
+#define UVD_STOP_CONTEXT__CONTEXT_MODE_MASK 0x00000002L
+//UVD_CXW_SAVE_AREA_ADDR
+#define UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR__SHIFT 0x6
+#define UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR_MASK 0xFFFFFFC0L
+//UVD_CBUF_ID
+#define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0
+#define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL
+//UVD_CONTEXT_ID
+#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
+#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL
+//UVD_CXW_SAVE_AREA_SIZE
+#define UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE__SHIFT 0x0
+#define UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE_MASK 0xFFFFFFFFL
+//UVD_CONTEXT_ID2
+#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0
+#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL
+//UVD_CXW_CNTL
+#define UVD_CXW_CNTL__HOST_CXW_EN__SHIFT 0x0
+#define UVD_CXW_CNTL__EXTERNAL_CXW_EN__SHIFT 0x1
+#define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN__SHIFT 0x3
+#define UVD_CXW_CNTL__HOST_CXW_INT_EN__SHIFT 0x4
+#define UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN__SHIFT 0x5
+#define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN__SHIFT 0x7
+#define UVD_CXW_CNTL__HOST_CXW_EN_MASK 0x00000001L
+#define UVD_CXW_CNTL__EXTERNAL_CXW_EN_MASK 0x00000002L
+#define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN_MASK 0x00000008L
+#define UVD_CXW_CNTL__HOST_CXW_INT_EN_MASK 0x00000010L
+#define UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN_MASK 0x00000020L
+#define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN_MASK 0x00000080L
+//UVD_CXW_EVENT
+#define UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED__SHIFT 0x0
+#define UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED__SHIFT 0x1
+#define UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT 0x3
+#define UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED__SHIFT 0x4
+#define UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT 0x5
+#define UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED_MASK 0x00000001L
+#define UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED_MASK 0x00000002L
+#define UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK 0x00000008L
+#define UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED_MASK 0x00000010L
+#define UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK 0x00000020L
+//UVD_CXW_SCAN_AREA_OFFSET
+#define UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET__SHIFT 0x0
+#define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE__SHIFT 0x1a
+#define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE__SHIFT 0x1b
+#define UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET_MASK 0x03FFFFFFL
+#define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE_MASK 0x04000000L
+#define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE_MASK 0x08000000L
+//UVD_CXW_SHIFT_CNTL
+#define UVD_CXW_SHIFT_CNTL__SHIFT_CNTL__SHIFT 0x0
+#define UVD_CXW_SHIFT_CNTL__SHIFT_COUNT__SHIFT 0x1
+#define UVD_CXW_SHIFT_CNTL__SHIFT_CNTL_MASK 0x00000001L
+#define UVD_CXW_SHIFT_CNTL__SHIFT_COUNT_MASK 0x00000FFEL
+//UVD_RBC_CAM_EN
+#define UVD_RBC_CAM_EN__RBC_CAM_EN__SHIFT 0x0
+#define UVD_RBC_CAM_EN__RBC_CAM_EN_MASK 0x00000001L
+//UVD_RBC_CAM_INDEX
+#define UVD_RBC_CAM_INDEX__RBC_CAM_INDEX__SHIFT 0x0
+#define UVD_RBC_CAM_INDEX__RBC_CAM_INDEX_MASK 0xFFFFFFFFL
+//UVD_RBC_CAM_DATA
+#define UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG__SHIFT 0x0
+#define UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP__SHIFT 0x10
+#define UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG_MASK 0x0000FFFFL
+#define UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP_MASK 0xFFFF0000L
+//UVD_RBC_VCPU_ACCESS
+#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0
+#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L
+//UVD_CXW_INT_ID
+#define UVD_CXW_INT_ID__ID__SHIFT 0x0
+#define UVD_CXW_INT_ID__ID_MASK 0x000000FFL
+//UVD_LMI_CRC0
+#define UVD_LMI_CRC0__CRC32__SHIFT 0x0
+#define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL
+//UVD_LMI_CRC1
+#define UVD_LMI_CRC1__CRC32__SHIFT 0x0
+#define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL
+//UVD_LMI_CRC2
+#define UVD_LMI_CRC2__CRC32__SHIFT 0x0
+#define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL
+//UVD_LMI_CRC3
+#define UVD_LMI_CRC3__CRC32__SHIFT 0x0
+#define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL
+//UVD_RBC_WPTR_POLL_CNTL
+#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0
+#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL
+#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
+//UVD_RBC_WPTR_POLL_ADDR
+#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2
+#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL
+//UVD_RB_BASE_LO4
+#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI4
+#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE4
+#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_RPTR4
+#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L
+//UVD_LMI_MC_CREDITS
+#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0
+#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8
+#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10
+#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18
+#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL
+#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L
+#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L
+#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L
+//UVD_RBC_BUF_STATUS
+#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0
+#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8
+#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10
+#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13
+#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16
+#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19
+#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL
+#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L
+#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L
+#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L
+#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L
+#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L
+//UVD_RBC_IB_SIZE_UPDATE
+#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4
+#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L
+//UVD_RBC_BDM_PRE
+#define UVD_RBC_BDM_PRE__BDM_ENABLE__SHIFT 0x0
+#define UVD_RBC_BDM_PRE__BDM_ENABLE_MASK 0x00000001L
+//CG_TIMESTAMP_LOW
+#define CG_TIMESTAMP_LOW__CG_LOW__SHIFT 0x0
+#define CG_TIMESTAMP_LOW__CG_LOW_MASK 0xFFFFFFFFL
+//CG_TIMESTAMP_HIGH
+#define CG_TIMESTAMP_HIGH__CG_HIGH__SHIFT 0x0
+#define CG_TIMESTAMP_HIGH__CG_HIGH_MASK 0xFFFFFFFFL
+//UVD_UMC_UVD_CTL_CMD
+#define UVD_UMC_UVD_CTL_CMD__CMC_REQ__SHIFT 0x0
+#define UVD_UMC_UVD_CTL_CMD__CMC_REQ_MASK 0x00000001L
+//UVD_UMC_UVD_BLOCK_REQ
+#define UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ__SHIFT 0x0
+#define UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ_MASK 0x00000001L
+//UVD_RBC_CXW_RELEASE
+#define UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC__SHIFT 0x0
+#define UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC_MASK 0x00000001L
+//UVD_YBASE
+#define UVD_YBASE__DUM__SHIFT 0x0
+#define UVD_YBASE__DUM_MASK 0xFFFFFFFFL
+//UVD_UVBASE
+#define UVD_UVBASE__DUM__SHIFT 0x0
+#define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL
+//UVD_PITCH
+#define UVD_PITCH__DUM__SHIFT 0x0
+#define UVD_PITCH__DUM_MASK 0xFFFFFFFFL
+//UVD_WIDTH
+#define UVD_WIDTH__DUM__SHIFT 0x0
+#define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL
+//UVD_HEIGHT
+#define UVD_HEIGHT__DUM__SHIFT 0x0
+#define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL
+//UVD_PICCOUNT
+#define UVD_PICCOUNT__DUM__SHIFT 0x0
+#define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvdnpdec
+//UVD_SEMA_ADDR_LOW
+#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0
+#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL
+//UVD_SEMA_ADDR_HIGH
+#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0
+#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL
+//UVD_SEMA_CMD
+#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
+#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
+#define UVD_SEMA_CMD__MODE__SHIFT 0x6
+#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
+#define UVD_SEMA_CMD__VMID__SHIFT 0x8
+#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL
+#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L
+#define UVD_SEMA_CMD__MODE_MASK 0x00000040L
+#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L
+#define UVD_SEMA_CMD__VMID_MASK 0x00000F00L
+//UVD_GPCOM_VCPU_CMD
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
+#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L
+#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L
+//UVD_GPCOM_VCPU_DATA0
+#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
+#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL
+//UVD_GPCOM_VCPU_DATA1
+#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
+#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL
+//UVD_ENGINE_CNTL
+#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
+#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2
+#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L
+#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L
+//UVD_SUVD_CGC_GATE
+#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
+#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
+#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
+#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
+#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
+#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
+#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
+#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
+#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
+#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
+#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
+#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
+#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
+#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd
+#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
+#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf
+#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12
+#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13
+#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14
+#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15
+#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16
+#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17
+#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18
+#define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19
+#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L
+#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L
+#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L
+#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L
+#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L
+#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L
+#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L
+#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L
+#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L
+#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L
+#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L
+#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L
+#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L
+#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L
+#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L
+#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L
+#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L
+#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L
+#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L
+#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L
+#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L
+#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L
+#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L
+//UVD_SUVD_CGC_STATUS
+#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
+#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
+#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
+#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
+#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
+#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
+#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe
+#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf
+#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10
+#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13
+#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14
+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15
+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16
+#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17
+#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18
+#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19
+#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a
+#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b
+#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c
+#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L
+#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L
+#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L
+#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L
+#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L
+#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L
+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L
+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L
+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L
+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L
+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L
+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L
+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L
+#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L
+#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L
+#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L
+#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L
+#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L
+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L
+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L
+#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L
+#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L
+#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L
+#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L
+#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L
+#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L
+//UVD_SUVD_CGC_CTRL
+#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
+#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
+#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
+#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
+#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
+#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6
+#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7
+#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8
+#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9
+#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
+#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L
+#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L
+#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L
+#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L
+#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L
+#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L
+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L
+#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L
+#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L
+#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L
+#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L
+//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_SCRATCH_NP
+#define UVD_SCRATCH_NP__DATA__SHIFT 0x0
+#define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL
+//UVD_NO_OP
+#define UVD_NO_OP__NO_OP__SHIFT 0x0
+#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL
+//MDM_DMA_CMD
+#define MDM_DMA_CMD__MDM_DMA_CMD__SHIFT 0x0
+#define MDM_DMA_CMD__MDM_DMA_CMD_MASK 0xFFFFFFFFL
+//MDM_DMA_STATUS
+#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY__SHIFT 0x0
+#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY__SHIFT 0x1
+#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY__SHIFT 0x2
+#define MDM_DMA_STATUS__RB_DMA_WR_BUSY__SHIFT 0x3
+#define MDM_DMA_STATUS__RB_DMA_RD_BUSY__SHIFT 0x4
+#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY__SHIFT 0x5
+#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY__SHIFT 0x6
+#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY_MASK 0x00000001L
+#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY_MASK 0x00000002L
+#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY_MASK 0x00000004L
+#define MDM_DMA_STATUS__RB_DMA_WR_BUSY_MASK 0x00000008L
+#define MDM_DMA_STATUS__RB_DMA_RD_BUSY_MASK 0x00000010L
+#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY_MASK 0x00000020L
+#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY_MASK 0x00000040L
+//MDM_DMA_CTL
+#define MDM_DMA_CTL__MDM_BYPASS__SHIFT 0x0
+#define MDM_DMA_CTL__FOUR_CMD__SHIFT 0x1
+#define MDM_DMA_CTL__ENCODE_MODE__SHIFT 0x2
+#define MDM_DMA_CTL__VP9_DEC_MODE__SHIFT 0x3
+#define MDM_DMA_CTL__SW_DRST__SHIFT 0x1f
+#define MDM_DMA_CTL__MDM_BYPASS_MASK 0x00000001L
+#define MDM_DMA_CTL__FOUR_CMD_MASK 0x00000002L
+#define MDM_DMA_CTL__ENCODE_MODE_MASK 0x00000004L
+#define MDM_DMA_CTL__VP9_DEC_MODE_MASK 0x00000008L
+#define MDM_DMA_CTL__SW_DRST_MASK 0x80000000L
+//MDM_ENC_PIPE_BUSY
+#define MDM_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0
+#define MDM_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1
+#define MDM_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2
+#define MDM_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3
+#define MDM_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4
+#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5
+#define MDM_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6
+#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7
+#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8
+#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9
+#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa
+#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb
+#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY__SHIFT 0xc
+#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY__SHIFT 0xd
+#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10
+#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11
+#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12
+#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13
+#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14
+#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15
+#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16
+#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c
+#define MDM_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L
+#define MDM_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L
+#define MDM_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L
+#define MDM_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L
+#define MDM_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L
+#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L
+#define MDM_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L
+#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L
+#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L
+#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L
+#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L
+#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L
+#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY_MASK 0x00001000L
+#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY_MASK 0x00002000L
+#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L
+#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L
+#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L
+#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L
+#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L
+#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L
+#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L
+#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L
+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L
+//MDM_WIG_PIPE_BUSY
+#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY__SHIFT 0x0
+#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY__SHIFT 0x1
+#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY__SHIFT 0x2
+#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL__SHIFT 0x3
+#define MDM_WIG_PIPE_BUSY__LCM_BUSY__SHIFT 0x4
+#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x5
+#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x6
+#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x7
+#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0x8
+#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0x9
+#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0xa
+#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0xb
+#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0xc
+#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0xd
+#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0xe
+#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0xf
+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x10
+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x11
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x12
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x13
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x14
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x15
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x16
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY__SHIFT 0x17
+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x18
+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x19
+#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY__SHIFT 0x1a
+#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY__SHIFT 0x1b
+#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY__SHIFT 0x1c
+#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY__SHIFT 0x1d
+#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY_MASK 0x00000001L
+#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY_MASK 0x00000002L
+#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY_MASK 0x00000004L
+#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL_MASK 0x00000008L
+#define MDM_WIG_PIPE_BUSY__LCM_BUSY_MASK 0x00000010L
+#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000020L
+#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000040L
+#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000080L
+#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000100L
+#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000200L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00000400L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00000800L
+#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00001000L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00002000L
+#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00004000L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00008000L
+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00010000L
+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00020000L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x00040000L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x00080000L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x00100000L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x00200000L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x00400000L
+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY_MASK 0x00800000L
+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x01000000L
+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x02000000L
+#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY_MASK 0x04000000L
+#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY_MASK 0x08000000L
+#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY_MASK 0x10000000L
+#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY_MASK 0x20000000L
+//UVD_VERSION
+#define UVD_VERSION__MINOR_VERSION__SHIFT 0x0
+#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10
+#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL
+#define UVD_VERSION__MAJOR_VERSION_MASK 0xFFFF0000L
+//UVD_GP_SCRATCH8
+#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH9
+#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH10
+#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH11
+#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH12
+#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH13
+#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH14
+#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH15
+#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH16
+#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH17
+#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH18
+#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH19
+#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH20
+#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH21
+#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH22
+#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL
+//UVD_GP_SCRATCH23
+#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0
+#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL
+//UVD_ENC_REG_INDEX
+#define UVD_ENC_REG_INDEX__INDEX__SHIFT 0x0
+#define UVD_ENC_REG_INDEX__INDEX_MASK 0x00001FFFL
+//UVD_ENC_REG_DATA
+#define UVD_ENC_REG_DATA__DATA__SHIFT 0x0
+#define UVD_ENC_REG_DATA__DATA_MASK 0xFFFFFFFFL
+//UVD_OUT_RB_BASE_LO
+#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
+#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_OUT_RB_BASE_HI
+#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_OUT_RB_SIZE
+#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
+//UVD_OUT_RB_RPTR
+#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_OUT_RB_WPTR
+#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RB_BASE_LO2
+#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI2
+#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE2
+#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_RPTR2
+#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR2
+#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L
+//UVD_RB_BASE_LO
+#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
+#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
+//UVD_RB_BASE_HI
+#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
+//UVD_RB_SIZE
+#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
+//UVD_RB_RPTR
+#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+//UVD_RB_WPTR
+#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+//UVD_ENC_PIPE_BUSY
+#define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0
+#define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1
+#define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2
+#define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3
+#define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4
+#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5
+#define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6
+#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7
+#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8
+#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9
+#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa
+#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb
+#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10
+#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11
+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12
+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13
+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14
+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e
+#define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L
+#define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L
+#define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L
+#define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L
+#define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L
+#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L
+#define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L
+#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L
+#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L
+#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L
+#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L
+#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L
+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L
+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L
+//UVD_RB_WPTR4
+#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4
+#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L
+//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
+#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW
+#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_IB_64BIT_BAR_HIGH
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_IB_64BIT_BAR_LOW
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_RB_64BIT_BAR_HIGH
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_RBC_RB_64BIT_BAR_LOW
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+
+
+// addressBlock: uvd0_uvdnp2dec
+//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW
+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH
+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
+//UVD_LMI_MMSCH_NC_VMID
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L
+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L
+//UVD_LMI_MMSCH_CTRL
+#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0
+#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1
+#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3
+#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5
+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7
+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9
+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb
+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc
+#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L
+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L
+//UVD_MMSCH_SOFT_RESET
+#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0
+#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1
+#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f
+#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L
+#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L
+#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L
+//UVD_LMI_ARB_CTRL2
+#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0
+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1
+#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2
+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6
+#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa
+#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14
+#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L
+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L
+#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL
+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L
+#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L
+#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L
+
+
+#endif
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